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Fabrication Steps....
Dr. S. Moorthi
AP/ EEE, NIT-T
• Wafer formation
• Photolithography
• Well and channel formation
• Oxidation
• Isolation
• Gate and source/ drain formation
• Contacts and Metallisation
• Electrical Testing
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Wafer Formation:
-Czochralski Method
PhotoLithography:
•Carving pictures in stone using light.
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Oxidation:
Oxidation of silicon is achieved by heating the silicon
wafer in an oxidising atmosphere.
- Wet Oxidation
- dry oxidation
- Atomic layer oxidation (ALD)
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Isolation:
Isolation from neighbouring transistors can be effectively
made using field oxide.
Gate oxide will be thin and available below the gate of
the transistor.
Thermal Oxidation
Silicon is the dominant semiconductor used in integrated circuit processing,
in large part due to its ability to form a robust (tough) native oxide.
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Thermal Oxidation
After cleaning with the RCA clean, silicon wafers
are placed into a high temperature furnace
(900ºC < T < 1200ºC) in the presence of
oxygen or water where the following reaction
occurs:
Si + O2 → SiO2
or
In order to create integrated circuits, the silicon wafer must be doped with
impurities (boron and phosphorus are the most common) selectively – this is
accomplished by removing the oxide in specific areas so the dopants are
allowed to diffuse (movement due to high temperature) into the exposed
silicon.
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But photolithography is binary – either the film is exposed or not exposed; there
are no shades of gray.
Photolithography
Mask or Reticle:
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Photolithography
PR Application:
Photolithography
Alignment and Exposure:
The PR coated wafer is placed into a
system (mask aligner or ‘stepper’)
which allows the mask to be aligned
to the wafer. After alignment, the
system opens a shutter to allow UV
light to illuminate the PR through the
mask for a controlled period of time.
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Photolithography
Development:
After the wafer is exposed to UV light through the mask, the acidic regions of
PR are removed by dipping the wafer into an alkaline (base) developing
solution. The acidic PR reacts chemically with the basic developer to
form water soluble salts that dissolve in the developer.
At this point the mask image can be seen in the PR (remember that the PR
was illuminated with UV light through the mask, so only light in the shape
of the circuit reaches the PR – the rest of the PR did not change!).
Note: the image from the mask has only been transferred to the PR. The
PR will be used as a mask for etching the underlying oxide in an acid
bath.
Etching
The previous steps produced a pattern in the PR
layer coating the oxidized wafer. This patterned
PR will now be used for selectively etching the
oxide areas that are exposed.
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In order for current to flow in a material there must be ‘loose’ electrons. But all
the electrons in silicon are working at holding the atoms together, which
means it is not a good conductor of current.
So what can be done to allow the silicon to conduct current more easily? Free
‘carriers’ of current must be added. The goal is to find an element about the
same size as a silicon atom so that it fits together well with the silicon, but
with more electrons in its outer shell.
If phosphorus is inserted into the silicon wafer in a certain way, it will take the
place of a silicon atom and bond with its four neighbor silicon atoms. After
bonding, phosphorus has an electron left over that is not bonded to a silicon
atom. It turns out this extra electron is not strongly held by the phosphorus
atom any more, so it can be removed easily. This electron then becomes a
‘carrier’ for current – it is free to move around the wafer. So the conductivity
of the silicon wafer increases. This type of silicon ‘doped’ with phosphorus
is called an n-type semiconductor.
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Think of carriers as being able to only move across a flat surface or down a
slope. The built in potential is a hill that the carrier can not go up. So in
order for the carrier to keep moving, the low part must be pushed up to be
level or higher than the top of the hill. In the case of an n-type / p-type
junction, the energy to push up the low side comes in the form of a voltage
applied to the wafer. The voltage is used to ‘push up’ the ‘ground’ on the low
side of the hill before current flows from n-type to p-type regions.
But if the voltage is reversed, the energy is used to push the low side lower
while keeping the high side at the same height! That means the carrier
probably won’t ever make it up the higher hill, so it is stuck (no current
flows).
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Some modern processes may require more than 20 iterations of this sequence!
Oxidation
Photo-
lithography
Etching
Diffusion (Ion
Implantation)
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Process
Phosphorus Diffusion
• Photolithography Mask 2
• Etch
• Phosphorus Predeposition
Process
Electrical contact vias (holes) to silicon
• Photolithography Mask 4
• Etch
Metal definition
• Photolithography Mask 5
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Metallization
After all diffusion and oxidation steps are
completed, metal is deposited onto
the surface of the wafer. This metal is
used to ‘wire’ the devices fabricated in
the silicon together.
Metallization
After metallization, the wafer is completely covered by the aluminum.
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Completed wafer
Steps to create wafer:
1. Initial oxidation
2. Photolithography Mask 1
3. Oxide etch
4. Boron predep
5. Boron drive and re-oxidation
6. Photolithography Mask 2
7. Oxide etch
8. Phosphorus predeposition
9. Photolithography Mask 3
10. Gate oxidation
11. Photolithography Mask 4
12. Etch
13. Photolithography Mask 5
14. Metal evaporation
15. Metal definition
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