ECE 261: CMOS VLSI Design

Methodologies

Prof. Krishnendu (Krish) Chakrabarty

Dept. Electrical and Computer Engineering

Room 2513 CIEMAS

Ph: 660-5244

E-mail: krish@ee.duke.edu

URL: http://www.ee.duke.edu/~krish

Course URL:

http://people.ee.duke.edu/~krish/teaching/261.html

Google group: ECE261_Fall2011

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Course Objectives

•
Introduction to CMOS VLSI design methodologies

–
Emphasis on full-custom design

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Circuit and system levels

•
Extensive use of Mentor Graphics CAD tools for IC design,
simulation, and layout verification

•
Specific techniques for designing high-speed, low-power, and
easily-testable circuits

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 Introduction

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Integrated circuits: many transistors on one chip.

•
Very Large Scale Integration (VLSI): bucketloads!

•
Complementary Metal Oxide Semiconductor

–
Fast, cheap, low power transistors

•
Today: How to build your own simple CMOS chip

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CMOS transistors

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Building logic gates from transistors

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Transistor layout and fabrication

•
Rest of the course: How to build a good CMOS chip

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 Designing for VLSI

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Designing a system on a chip

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Craft components from silicon rather than selecting catalog parts

•
ICs (chips) are batch fabricated

–
Inexpensive unit cost

•
Bugs are hard to fix!

–
Extensive design verification needed

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VLSI Design: Overview

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VLSI design is system design

–
Designing fast inverters is fun, but need knowledge of all aspects
of digital design: algorithms, systems, circuits, fabrication, and
packaging

–
Need to bridge gap between abstract vision of digital design and
the underlying digital circuit and its peculiarities

–
Circuit-level optimization, verification, and testing techniques are
important

•
Tall thin approach does not always work

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Today’s designer is “fatter”, but well-versed in both high-level and
low-level design skills

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 VLSI: Enabling Technology

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Automotive electronic systems

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A typical car has over 100 ICs (stereo systems, display panels, fuel
injection systems, smart suspensions, antilock brakes, airbags)

•
Signal Processing (DSP chips, data acquisition systems)

•
Transaction processing (bank ATMs)

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PCs, workstations, servers, consumer electronics

•
Medical electronics (artificial eye, implants)

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Avionics, space applications

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Networking hardware: Routers and switches

•
…..

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The Semiconductor Industry

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53% compound annual growth rate over 50 years

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No other technology has grown so fast so long

•
Driven by miniaturization of transistors

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Smaller is cheaper, faster, lower in power!

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Revolutionary effects on society

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4

 Design Complexity

•
Transistor counts and IC densities continue to
grow!

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Moore’s Law-The number of transistors on an IC doubles every
1.5 years

–
Intel x486: 1 million transistors (1989), PowerPC: 2-3 million
transistors (1994), Pentium: 3.1 million transistors (1994), DEC
Alpha: 10 million transistors (1995)-9 million in SRAM, Pentium
IV (2001): 42 million transistors, Xeon (8 cores): 2.3 billion
transistors

•
Memory (DRAM) is the “technology driver”

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256 Mbits DRAM (1998), 512 Mb DRAM (2003), 1GB, 2 GB,…

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VLSI Technology

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CMOS: Complementary Metal Oxide Silicon

–
Based on voltage-controlled field-effect transistors (FETs)

•
Other technologies: bipolar junction transistors
(BJTs), BiCMOS, gallium arsenide (GaAs)

–
BJTs, BiCMOS, ECL circuits are faster but CMOS consumes
lower power and are easier to fabricate

–
GaAs carriers have higher mobility but high integration levels are
difficult to achieve in GaAs technology

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 Transistor Types

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Bipolar transistors

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npn or pnp silicon structure

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Small current into very thin base layer controls large
currents between emitter and collector

–
Base currents limit integration density

•
Metal Oxide Semiconductor Field Effect
Transistors

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nMOS and pMOS MOSFETS

–
Voltage applied to insulated gate controls current
between source and drain

–
Low power allows very high integration

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IC Manufacturing

•
Some manufacturing processes are tightly coupled to the
product, e.g. Buick/Chevy assembly line

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IC manufacturing technology is more versatile

•
CMOS manufacturing line can make circuits of any type
by changing some basic tools called masks

–
The same plant can manufacture both microprocessors and microwave
controllers by simply changing masks

•
Silicon wafers: raw materials of IC manufacturing

IC

Test

structure
Wafer

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 Chip Designer’s Lexicon

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Boston geometry: masks that use only curves

–
In contrast to Manhattan and Euclidean geometries

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Dog and pony show: A presentation to
management

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Hit by a truck: Losing a key technical person at a
crucial point in a project (especially common in
the IC design industry today!)

•
Infant mortality: failure of ICs during the first few
hours of operation

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Silicon Lattice

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Transistors are built on a silicon substrate

•
Silicon is a Group IV material

•
Forms crystal lattice with bonds to four neighbors

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 Dopants

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Silicon is a semiconductor

•
Pure silicon has no free carriers and conducts
poorly

•
Adding dopants increases the conductivity

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Group V: extra electron (n-type)

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Group III: missing electron, called hole (p-type)

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p-n Junctions

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A junction between p-type and n-type
semiconductor forms a diode.

•
Current flows only in one direction

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 nMOS Transistor

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Four terminals: gate, source, drain, body

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Gate – oxide – body stack looks like a capacitor

–
Gate and body are conductors

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SiO2 (oxide) is a very good insulator

–
Called metal – oxide – semiconductor (MOS) capacitor

–
Even though gate is


no longer made of metal

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nMOS Operation

•
Body is usually tied to ground (0 V)

•
When the gate is at a low voltage:

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P-type body is at low voltage

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Source-body and drain-body diodes are OFF

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No current flows, transistor is OFF

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 nMOS Operation (Contd.)

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When the gate is at a high voltage:

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Positive charge on gate of MOS capacitor

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Negative charge attracted to body

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Inverts a channel under gate to n-type

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Now current can flow through n-type silicon from
source through channel to drain, transistor is ON

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pMOS Transistor

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Similar, but doping and voltages reversed

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Body tied to high voltage (VDD)

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Gate low: transistor ON

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Gate high: transistor OFF

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Bubble indicates inverted behavior

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 Power Supply Voltage

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GND = 0 V

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In 1980’s, VDD = 5V

•
VDD has decreased in modern processes

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High VDD would damage modern tiny transistors

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Lower VDD saves power

•
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

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Annual Sales

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>1019 transistors manufactured in 2008

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1 billion for every human on the planet

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 MOS Integrated Circuits

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1970’s processes usually had only nMOS transistors

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Inexpensive, but consume power while idle

Intel
Museum.
[Vadasz69]
Reprinted
© 1969 IEEE. with
permission.

Intel 1101 256-bit SRAM Intel 4004 4-bit μProc

•
1980s-present: CMOS processes for low idle power

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Moore’s Law: Then

•
1965: Gordon Moore plotted transistor on each
chip

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Fit straight line on semilog scale

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Transistor counts have doubled every 26 months

Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
[Moore65]
Electronics Magazine

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And Now…

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 Feature Size

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Minimum feature size shrinking 30% every 2-3
years

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Corollaries

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Many other factors grow exponentially

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Ex: clock frequency, processor performance

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 Cost of Fabs

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Some History

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Basic principles of MOS: Lilienfield (1925), Heil
(1935)

–
Problem: Fabrication, materials processing

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BJT transistors were designed at Bell Labs in the late forties and
fifties (sixty years of the transistor!)

•
MOS planar process: 1960, Weiner (CMOS flip-
flops:1962), Wanlass (inverter, NOR, NAND
gates: 1963)

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 History

•
1958: First integrated circuit

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Flip-flop using two transistors

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Built by Jack Kilby at Texas
Instruments

•
2010
Courtesy Texas Instruments

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Intel Core i7 μprocessor

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2.3 billion transistors

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64 Gb Flash memory

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> 16 billion transistors

[Trinh09]
© 2009 IEEE.

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Invention of the Transistor

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Vacuum tubes ruled in first half of 20th century
Large, expensive, power-hungry, unreliable

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1947: first point contact transistor

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John Bardeen and Walter Brattain at Bell Labs

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See Crystal Fire


by Riordan, Hoddeson

AT&T Archives.
Reprinted with
permission.

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 The First Computer

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ENIAC - The first electronic computer

(1946)

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 Intel 4004 Micro-Processor

1971, 2300 transistors, 10 microns process

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Intel Pentium (II) microprocessor

1997, 7.5 M transistor, 0.35 micron processs

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 Newer Microprocessors

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Intel Pentium 4

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2000, 42 M transistors, 1.15 V, 0.18 micron process

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Core i7

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4 physical cores

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2008, 45 nm process, 781 M transistors, 3.6 GHz max

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Intel Xeon server chip

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8 cores

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2009, 2.3 billion transistors, 45 nm process

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Design Abstraction Levels

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 Coping with Complexity

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How to design System-on-Chip?

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Many millions (even billions!) of transistors

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Tens to hundreds of engineers

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Structured Design

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Design Partitioning

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Structured Design

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Hierarchy: Divide and Conquer

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Recursively system into modules

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Regularity

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Reuse modules wherever possible

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Ex: Standard cell library

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Modularity: well-formed interfaces

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Allows modules to be treated as black boxes

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Locality

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Physical and temporal

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 Design Partitioning

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Architecture: User’s perspective, what does it do?

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Instruction set, registers

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MIPS, x86, Alpha, PIC, ARM, …

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Microarchitecture

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Single cycle, multcycle, pipelined, superscalar?

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Logic: how are functional blocks constructed

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Ripple carry, carry lookahead, carry select adders

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Circuit: how are transistors used

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Complementary CMOS, pass transistors, domino

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Physical: chip layout

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Datapaths, memories, random logic

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Gajski Y-Chart

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 MIPS Architecture

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Example: subset of MIPS processor architecture

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Drawn from Patterson & Hennessy

•
MIPS is a 32-bit architecture with 32 registers

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Consider 8-bit subset using 8-bit datapath

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Only implement 8 registers ($0 - $7)

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$0 hardwired to 00000000

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8-bit program counter

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MIPS Microarchitecture

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Multicycle μarchitecture ( [Paterson04],
[Harris07] )

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 Multicycle Controller

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Logic Design

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Start at top level

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Hierarchically decompose MIPS into units

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Top-level interface

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 Block Diagram

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Hierarchical Design

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 HDLs

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Hardware Description Languages

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Widely used in logic design

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Verilog and VHDL

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Describe hardware using code

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Document logic functions

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Simulate logic before building

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Synthesize code into gates and layout

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Requires a library of standard cells

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Verilog Example

module fulladder(input a, b, c,

output s, cout);

sum s1(a, b, c, s);

carry c1(a, b, c, cout);

endmodule

module carry(input a, b, c,

output cout)

assign cout = (a&b) | (a&c) | (b&c);

endmodule

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 Circuit Design

•
How should logic be implemented?

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NANDs and NORs vs. ANDs and ORs?

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Fan-in and fan-out?

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How wide should transistors be?

•
These choices affect speed, area, power

•
Logic synthesis makes these choices for you

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Good enough for many applications

–
Hand-crafted circuits are still better

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Example: Carry Logic

•
assign cout = (a&b) | (a&c) | (b&c);

Transistors? Gate Delays?

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 Gate-level Netlist

module carry(input a, b, c,

output cout)

wire x, y, z;

and g1(x, a, b);

and g2(y, a, c);

and g3(z, b, c);

or g4(cout, x, y, z);

endmodule

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Transistor-Level Netlist

module carry(input a, b, c,

output cout)

wire i1, i2, i3, i4, cn;

tranif1 n1(i1, 0, a);

tranif1 n2(i1, 0, b);

tranif1 n3(cn, i1, c);

tranif1 n4(i2, 0, b);

tranif1 n5(cn, i2, a);

tranif0 p1(i3, 1, a);

tranif0 p2(i3, 1, b);

tranif0 p3(cn, i3, c);

tranif0 p4(i4, 1, b);

tranif0 p5(cn, i4, a);

tranif1 n6(cout, 0, cn);

tranif0 p6(cout, 1, cn);

endmodule

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 SPICE Netlist

.SUBCKT CARRY A B C COUT VDD GND
MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P
MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P
MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P
MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P
MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P
MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P
MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P
MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P
MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P
MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P
CI1 I1 GND 2FF
CI3 I3 GND 3FF
CA A GND 4FF
CB B GND 4FF
CC C GND 2FF
CCN CN GND 4FF
CCOUT COUT GND 2FF
.ENDS

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Physical Design

•
Floorplan

•
Standard cells

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Place & route

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Datapaths

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Slice planning

•
Area estimation

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MIPS Floorplan

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MIPS Layout

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 Standard Cells

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Uniform cell height

•
Uniform well height

•
M1 VDD and GND rails

•
M2 Access to I/Os

•
Well / substrate taps

•
Exploits regularity

59

Synthesized Controller

•
Synthesize HDL into gate-level netlist

•
Place & Route using standard cell library

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 Pitch Matching

•
Synthesized controller area is mostly wires

–
Design is smaller if wires run through/over cells

–
Smaller = faster, lower power as well!

•
Design snap-together cells for datapaths and
arrays

–
Plan wires into cells

–
Connect by abutment

•
Exploits locality

•
Takes lots of effort

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MIPS Datapath

•
8-bit datapath built from 8 bitslices (regularity)

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Zipper at top drives control signals to datapath

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 Slice Plans

•
Slice plan for bitslice

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Cell ordering, dimensions, wiring tracks

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Arrange cells for wiring locality

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Area Estimation

•
Need area estimates to make floorplan

–
Compare to another block you already designed

–
Or estimate from transistor counts

–
Budget room for large wiring tracks

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 Design Verification

•
Fabrication is slow & expensive

–
MOSIS 0.6μm: $1000, 3 months

–
65 nm: $3M, 1 month

•
Debugging chips is very hard

–
Limited visibility into operation

•
Prove design is right before building!

–
Logic simulation

–
Ckt. simulation / formal verification

–
Layout vs. schematic comparison

–
Design & electrical rule checks

•
Verification is > 50% of effort on most chips!

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Fabrication & Packaging

•
Tapeout final layout

•
Fabrication

–
6, 8, 12” wafers

–
Optimized for throughput,


not latency (10 weeks!)

–
Cut into individual dice

•
Packaging

–
Bond gold wires from die I/O pads to package

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 Testing

•
Test that chip operates

–
Design errors

–
Manufacturing errors

•
A single dust particle or wafer defect kills a die

–
Yields from 90% to < 10%

–
Depends on die size, maturity of process

–
Test each part before shipping to customer

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