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Dr Philip Leong
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Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 1)
Addressing modes
addr is address field of instruction
Immediate addr is operand
Register addr is register number in CPU
– operand := [ addr ]
Direct addr is address in primary (main) memory
– operand := [ addr ]
Indirect addr is register number (or memory address)
– operand_address := [ addr ]
operand [ operand_address ]
Indexed addr is base address, index is a register
– operand := [ addr + [ index ] ]
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 2)
Instructions
Two Operand Instructions
Label: OPCODE Destination, Source ; Comments
¾ Memory Operands
[ BaseReg + Scale * IndexReg + Displacement ]
e.g. [24], [BP], [ESI+2], [BP + 8 * DI + 16]
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 4)
Directives
¾ Most assemblers allow “global” variables to be allocated and defined
symbolically with a data definition directive, e.g.
Age EQU 22
MyPointer EQU 1000
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 5)
Examples
Label Instruction Comment
MOV AH, CL ; AH := CL
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 6)
More Examples
Label Instruction Comment
CMP EAX, ECX ; Compare operands and Set
; EFLAGS register
JE forlabel ; if FLAGS.ZF = 1 then
; EIP := forlabel
forlabel: NEG AX ; AX := -AX
CALL print ; Call procedure print
RET ; Return from procedure
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 7)
Register Operand
Register
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 9)
Memory Operands
Specify an address offset (effective address) using expressions of the
form (different parts of expression are optional):
1) Base Register (EAX, EBX, ECX, EDX, ESP, EBP, EDI, ESI)
(only BX or BP on 8086)
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 12)
Example 1: MOV AX, [22]
AX
-637
Data Segment
(e.g. DS * 16) 0
+22 2 ...
22
22 -637
Instruction
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 13)
Example 2: MOV AX, ES:[22]
AX
+738
Extra Segment
(e.g. ES * 16) 0
+22 2 ...
22
22 +738
Instruction
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 14)
Example 3: MOV BYTE PTR [22], 98
Instruction
98
Data Segment
(e.g. DS * 16) 0
+22 2 ...
22
22 98
Instruction
24 MOV WORD PTR [26], 99
26 99
99
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 15)
Base (Register Indirect)
[ Base ]
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 16)
Example 1: MOV AX, [BX]
AX
-100
Data Segment
0
2
+66 ...
BX 66 -100
66
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 17)
Example 2: MOV [BP], AL
AL
55
Stack Segment
(e.g. SS * 16) 0
2
+12 ...
BP 12 55
12
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 18)
Base + Displacement (Register Relative)
[ Base + Displacement ] or Displacement [ Base ]
AX
2244
Data Segment
0
BX 2
+12 ...
12 BX points to Start
of a Record with
+4 12 X fields X, Y & Z
Y
4 +4 selects field Z
16 2244
Instruction
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 20)
Example 2: MOV AX, [BX+4]
AX
Data Segment
-99
+4 0
2
Instruction
4 A[0]
+4 6 A[1]
+12 8 A[2] +4 points to start of
10 A[3] an Array
BX 12 A[4]
14 A[5] BX holds “index” to
12 array element
16 -99
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 21)
Base + Index (Based Indexed)
[ Base + Index ] or [ Base ] [ Index ]
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 22)
Example: MOV AX, [BX+DI]
AX
-27
Data Segment
0
BX +12 2 ...
12
Start of Array
12 A[0]
DI +6 14 A[1]
6 16 A[2]
DI is index to 18 -27
array element
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 23)
Base + Index + Displacement (Based Relative Index)
Stack Segment AX
0
BP +12 +67
...
12
12
+10
+10
Instruction 22 A[0] BP+10 points to start
+6 24 A[1] of array on stack
26 A[2]
6 28 +67 DI holds “position” of
array element
DI
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 25)
(Scale*Index) + Displacement (Scaled Index)
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 26)
Example: MOV AX, ES:[2*ECX+4]
AX
Extra Segment
-99
+4 0
2
Instruction
4 A[0]
+4 6 A[1]
8 A[2]
+(2*6) 10 +4 points to start of
A[3] a Array
ECX 12 A[4]
14 A[5] ECX holds position of
6 array element
16 -99
Elements = 2 bytes
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 27)
Base + (Scale * Index) + Displacement
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 28)
Example: MOV EAX, [EBX+4*EDX+10]
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 29)
Think about
1. Why zero, single and two operand instructions occur in the
8086 instruction set.
2. The difference between a directive and an assembly
language statement
3. The difference between all of the addressing modes
4. How high level language statements like a = b[5]+c are
translated to assembly language and what addressing modes
are used
5. The machine organisation required to handle the addressing
modes
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 30)