Class 5

Low Power Modes Block

Low Power Mode Control 0 Register
(LPMCR0)
 Automatic Wakeup in Low-power
Modes
• Wakeup from HALT: Set WDHALTI bit in CLKCTL
register to 1. When the device wakes up from
HALT, it will be through a CPU-watchdog reset.
The WDFLAG bit in the WDCR register can be
used to differentiate between a CPU-watchdog-
reset and a device reset.
• Wakeup from STANDBY: Set WDINTE bit in
LPMCR0 register to 1. When the device wakes up
from STANDBY, it will be through the WAKEINT
interrupt (Interrupt 1.8 in the PIE).
CPU Watchdog Block
 Watchdog
• The WDCNTR is reset when the proper
sequence is written to the WDKEY register
before the 8-bit watchdog counter (WDCNTR)
overflows.
WDKEY sequences
 Watchdog Reset or Watchdog
Interrupt Mode
• The watchdog can be configured in the SCSR register to either reset
the device (WDRST) or assert an interrupt (WDINT)
• Reset mode:
If the watchdog is configured to reset the device, then the WDRST
signal will pull the device reset (XRS) pin low for 512 OSCCLK cycles
when the watchdog counter reaches its maximum value.)
• Interrupt mode:
• If the watchdog is configured to assert an interrupt, then the
WDINT signal will be driven low for 512 OSCCLK cycles, causing the
WAKEINT interrupt in the PIE to be taken if it is enabled in the PIE
module. The watchdog interrupt is edge triggered on the falling
edge of WDINT. Thus, if the WAKEINT interrupt is re-enabled before
WDINT goes inactive, you will not immediately get another
interrupt. The next WAKEINT interrupt will occur at the next
watchdog timeout.
 Watchdog Operation in Low Power
Modes
• In STANDBY mode, all of the clocks to the peripherals are turned off
on the device. The only peripheral that remains functional is the
watchdog since the watchdog module runs off the oscillator clock
(OSCCLK). The WDINT signal is fed to the Low Power Modes (LPM)
block so that it can be used to wake the device from STANDBY low
power mode (if enabled). See the Low Power Modes Block section
of the device data manual for details.
• In IDLE mode, the watchdog interrupt (WDINT) signal can generate
an interrupt to the CPU to take the CPU out of IDLE mode. The
watchdog is connected to the WAKEINT interrupt in the PIE.
• In HALT mode, this feature cannot be used because the oscillator
(and PLL) are turned off and, therefore, so is the watchdog.
 Emulation Considerations
• CPU Suspended: When the CPU is suspended, the
watchdog clock (WDCLK) is suspended
• Run-Free Mode: When the CPU is placed in run-free
mode, then the watchdog module resumes operation
as normal.
• Real-Time Single-Step Mode: When the CPU is in real-
time single-step mode, the watchdog clock(WDCLK) is
suspended. The watchdog remains suspended even
within real time interrupts.
• Real-Time Run-Free Mode: When the CPU is in real-
time run-free mode, the watchdog operates as normal.
System Control and Status Register
(SCSR)
Watchdog Counter Register
(WDCNTR)
Watchdog Reset Key Register
(WDKEY)
Watchdog Control Register (WDCR)
 32-Bit CPU Timers 0/1/2
• The CPU Timer-0 and CPU-Timer 1 can be
used in user applications.
• Timer 2 is reserved for DSP/BIOS. If the
application is not using DSP/BIOS, then Timer
2 can be used in the application.
32-Bit CPU Timers 0/1/2
CPU-Timer Interrupts Signals and
Output Signal
 CPU-Timer Interrupts Signals and
Output Signal
• The 32-bit counter register TIMH:TIM is
loaded with the value in the period register
PRDH:PRD.
• The counter decrements once every
(TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles,
where TDDRH:TDDR is the timer divider. When
the counter reaches 0, a timer interrupt
output signal generates an interrupt pulse.
CPU-Timers 0, 1, 2 Configuration and
Control Registers
TIMERxTIM Register (x = 0, 1, 2)
TIMERxTIMH Register
TIMERxPRD Register (x = 0, 1, 2)