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2SJ553(L),2SJ553(S)

Silicon P Channel MOS FET


High Speed Power Switching

ADE-208-650B (Z)
3rd. Edition
Jun 1998

Features

• Low on-resistance
R DS(on) = 0.028Ω typ.
• Low drive current.
• 4V gate drive devices.
• High speed switching.

Outline

LDPAK

4 4

1
2
3
G 1
2
3 1. Gate
2. Drain
3. Source
4. Drain
S
2SJ553(L),2SJ553(S)

Absolute Maximum Ratings (Ta = 25°C)


Item Symbol Ratings Unit
Drain to source voltage VDSS –60 V
Gate to source voltage VGSS ±20 V
Drain current ID –30 A
Note1
Drain peak current I D(pulse) –120 A
Body-drain diode reverse drain current I DR –30 A
Note3
Avalanche current I AP –30 A
Note3
Avalanche energy EAR 77 mJ
Note2
Channel dissipation Pch 75 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Note: 1. PW ≤ 10µs, duty cycle ≤ 1 %
2. Value at Tc = 25°C
3. Value at Tch = 25°C, Rg ≥ 50 Ω

Electrical Characteristics (Ta = 25°C)


Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS –60 — — V I D = –10mA, VGS = 0
Gate to source breakdown voltage V(BR)GSS ±20 — — V I G = ±100µA, VDS = 0
Zero gate voltege drain current I DSS — — –10 µA VDS = –60 V, VGS = 0
Gate to source leak current I GSS — — ±10 µA VGS = ±16V, VDS = 0
Gate to source cutoff voltage VGS(off) –1.0 — –2.0 V I D = –1mA, VDS = –10V
Static drain to source on state RDS(on) — 0.028 0.037 Ω I D = –15A, VGS = –10V Note4
resistance RDS(on) — 0.038 0.055 Ω I D = –15A, VGS = –4V Note4
Forward transfer admittance |yfs| 15 25 — S I D = –15A, VDS = –10V Note4
Input capacitance Ciss — 2500 — pF VDS = –10V
Output capacitance Coss — 1300 — pF VGS = 0
Reverse transfer capacitance Crss — 300 — pF f = 1MHz
Turn-on delay time t d(on) — 25 — ns VGS = –10V, I D = –15A
Rise time tr — 150 — ns RL = 2Ω
Turn-off delay time t d(off) — 350 — ns
Fall time tf — 220 — ns
Body–drain diode forward voltage VDF — –0.95 — V I F = –30A, VGS = 0
Body–drain diode reverse t rr — 100 — ns I F = –30A, VGS = 0
recovery time diF/ dt =50A/µs
Note: 4. Pulse test

2
2SJ553(L),2SJ553(S)

Main Characteristics

Power vs. Temperature Derating Maximum Safe Operation Area


80 –1000
Pch (W)

10

I D (A)
–100
µs
60
10
0
PW µs
1
m
Channel Dissipation

= s

Drain Current
DC 10
40 –10 Op ms
er (1
sh
Operation in (T atio ot)
c= n
this area is 2 5
°C
20 –1 limited by R DS(on) )

Ta = 25 °C
–0.1
0 50 100 150 200 –0.1 –1 –10 –100
Case Temperature Tc (°C) Drain to Source Voltage V DS (V)

Typical Output Characteristics Typical Transfer Characteristics


–50 –50
V DS = –10 V
–8 V –3.5 V Pulse Test
–40 –40
I D (A)

I D (A)

–5 V Pulse Test
–4 V
–30 –30
VGS = –10 V
Drain Current

Drain Current

–3 V
–20 –20

Tc = 75 °C 25 °C
–10 –2.5 V –10
-25 °C
–2 V
0 –2 –4 –6 –8 –10 0 –1 –2 –3 –4 –5
Drain to Source Voltage V DS (V) Gate to Source Voltage V GS (V)

3
2SJ553(L),2SJ553(S)

Drain to Source Saturation Voltage vs. Static Drain to Source on State Resistance
Gate to Source Voltage vs. Drain Current
–5 1
Pulse Test

Drain to Source On State Resistance


R DS(on) ( Ω )
Drain to Source Saturation Voltage
V DS(on) (V)

0.5
–4

0.2
–3
0.1
–2
I D = –50 A 0.05 VGS = –4 V

–1 –10 V
–20 A 0.02
–10 A Pulse Test
0.01
0 –4 –8 –12 –16 –20 –1 –3 –10 –30 –100 –300 –1000
Gate to Source Voltage V GS (V) Drain Current I D (A)

Static Drain to Source on State Resistance Forward Transfer Admittance vs.


vs. Temperature Drain Current
100
Static Drain to Source on State Resistance

0.1
Forward Transfer Admittance |y fs | (S)
R DS(on) ( Ω)

Pulse Test
30
0.08 Tc = –25 °C
–20 A
10 25 °C
–10 A
0.06 I D = –50 A
–50 A
V GS = –4 V 3
75 °C
0.04 –10,–20A 1

0.02 V GS = –10 V 0.3 V DS = –10 V


Pulse Test
0 0.1
–40 0 40 80 120 160 –0.1 –0.3 –1 –3 –10 –30 –100
Case Temperature Tc (°C) Drain Current I D (A)

4
2SJ553(L),2SJ553(S)

Body–Drain Diode Reverse Typical Capacitance vs.


Recovery Time Drain to Source Voltage
1000 10000
VGS = 0
Reverse Recovery Time trr (ns)

500 f = 1 MHz
3000 Ciss

Capacitance C (pF)
200 1000
Coss
100 300

50 100 Crss

20 di / dt = 50 A / µs 30
VGS = 0, Ta = 25 °C
10 10
0.1 0.3 1 3 10 30 100 0 –10 –20 –30 –40 –50
Reverse Drain Current I DR (A) Drain to Source Voltage V DS (V)

Dynamic Input Characteristics Switching Characteristics


0 0 1000
V DS (V)

V GS (V)

V DD = –10 V V DS
–25 V t d(off)
500
Switching Time t (ns)

–20 –50 V –4
I D = –30 A
tf
Drain to Source Voltage

Gate to Source Voltage

200
–40 –8
100 tr
V GS
–60 –12
V DD = –10 V 50
–25 V
t d(on)
–80 –50 V –16
20
V GS = –10 V, V DD = –30 V
PW = 5 µs, duty <
=1%
–100 –20 10
0 40 80 120 160 200 –0.1 –0.3 –1 –3 –10 –30 –100
Gate Charge Qg (nc) Drain Current I D (A)

5
2SJ553(L),2SJ553(S)

Reverse Drain Current vs. Maximum Avalanche Energy vs.


Source to Drain Voltage Channel Temperature Derating
–50 100

Repetitive Avalanche Energy EAR (mJ)


Pulse Test I AP = –30 A
Reverse Drain Current I DR (A)

V DD = –25 V
–40 80
duty < 0.1 %
Rg > 50 Ω
–5 V
–30 60

–10 V V GS = 0
–20 40

–10 20

0
0 –0.4 –0.8 –1.2 –1.6 –2.0 25 50 75 100 125 150
Source to Drain Voltage V SD (V) Channel Temperature Tch (°C)

Avalanche Test Circuit Avalanche Waveform

1 VDSS
2
EAR = • L • I AP •
L 2 VDSS – V DD
V DS
Monitor
I AP V (BR)DSS
Monitor
I AP
Rg D. U. T VDD V DS
ID
Vin 50Ω
–15 V
VDD
0

6
2SJ553(L),2SJ553(S)

Normalized Transient Thermal Impedance vs. Pulse Width


3
Normalized Transient Thermao Impedance γ s (t)

Tc = 25°C
1
D=1

0.5
0.3

0.2
θ ch – c(t) = γ s (t) • θ ch – c
0.1 0.1 θ ch – c = 1.67 °C/W, Tc = 25 °C
0.05
PDM PW
D=
0.02 T
0.03 1 lse
0.0 t pu PW
h o
1s T

0.01
10 µ 100 µ 1m 10 m 100 m 1 10
Pulse Width PW (S)

Switching Time Test Circuit Waveform

Vin Monitor Vout Vin


Monitor
D.U.T. 10%
RL
90%

Vin V DD 90%
50Ω 90%
-10 V = –30 V

Vout 10% 10%

td(on) tr td(off) tf

7
2SJ553(L),2SJ553(S)

Package Dimensions

Unit: mm

(1.4)
10.2 ± 0.3 4.44 ± 0.2
1.3 ± 0.2
11.3 ± 0.5
8.6 ± 0.3
10.0 +0.3
–0.5

(1.4)
10.2 ± 0.3 4.44 ± 0.2
1.3 ± 0.2
(1.5)

2.59 ± 0.2
1.2 ± 0.2 1.27 ± 0.2

8.6 ± 0.3
10.0 +0.3
–0.5
0.86 +0.2
–0.1
11.0 ± 0.5

(1.5)
0.76 ± 0.1

(1.5)
0.1 +0.2
–0.1
2.59 ± 0.2

3.0 +0.3
–0.5
1.27 ± 0.2

0.4 ± 0.1
0.4 ± 0.1 1.2 ± 0.2 0.86 +0.2
–0.1
2.54 ± 0.5 2.54 ± 0.5 2.54 ± 0.5 2.54 ± 0.5

L type S type

Hitachi Code LDPAK


EIAJ —
JEDEC —

8
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