SEMICONDUCTOR TECHNICAL DATA

SEMICONDUCTOR TECHNICAL DATA

The MC14006B shift register is comprised of four separate shift register L SUFFIX
CERAMIC
sections sharing a common clock: two sections have four stages, and two
CASE 632
sections have five stages with an output tap on both the fourth and fifth
stages. This makes it possible to obtain a shift register of 4, 5, 8, 9, 10, 12,
13, 14, 16, 17, or 18 bits by appropriate selection of inputs and outputs. This
part is particularly useful in serial shift registers and time delay circuits. P SUFFIX
PLASTIC
• Output Transitions Occur on the Falling Edge of the Clock Pulse CASE 646
• Fully Static Operation
• Can be Cascaded to Provide Longer Shift Register Lengths
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
•
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Capable of Driving Two Low–power TTL Loads or One Low–power SOIC
Schottky TTL Load Over the Rated Temperature Range CASE 751A
• Pin–for–Pin Replacement for CD4006B
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to VSS)
MC14XXXBCP Plastic
Symbol Parameter Value Unit MC14XXXBCL Ceramic
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBD SOIC
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V TA = – 55° to 125°C for all packages.
lin, lout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package† 500 mW TRUTH TABLE
Dn C Qn+1
Tstg Storage Temperature – 65 to + 150 _C (Single Stage)
0 0
TL Lead Temperature (8–Second Soldering) 260 _C 1 1
* Maximum Ratings are those values beyond which damage to the device may occur. x Qn
X = Don’t Care
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
1 13 4 11 12 5 10 6 8 9
DP1 Q4 DP5 Q8 Q9 DP10 Q13 DP14 Q17 Q18
VDD = PIN 14 D D D D D D
VSS = PIN 7 4 4 1 4 4 1
NC = PIN 2 STAGES STAGES STAGE STAGES STAGES STAGE
C C C C C C
CLOCK 3
LOGIC DIAGRAM
(ONE REGISTER STAGE)
C C
#
*
DATA D+1
* Transmission Gate (C) #Inverter used only on the first stage of
1 C C each four–stage element.
Input to output is
IN OUT (A) A bidirectional low impedance when control input 1 is “low” and control input 2 is “high”.
(B) An open circuit when control input 1 is “high” and control input 2 is “low”.
2
(C)
REV 3
1/94
MOTOROLA CMOS LOGIC DATA

Motorola, Inc. 1995 MC14006B
25
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ – 55_C 25_C 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Vin = 0)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15 — 20 — 0.015 20 — 600
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**† IT 5.0 IT = (1.3 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.6 µA/kHz) f + IDD
Per Package) 15 IT = (3.9 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
PIN ASSIGNMENT
DP1 1 14 VDD
NC 2 13 Q4
C 3 12 Q9
DP5 4 11 Q8
DP10 5 10 Q13
DP14 6 9 Q18
VSS 7 8 Q17
NC = NO CONNECTION
MC14006B MOTOROLA CMOS LOGIC DATA

26
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH ns
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns tPHL 5.0 — 300 600
tPLH, tPHL = (0.66 ns/pF) CL + 77 ns 10 — 110 220
tPLH, tPHL = (0.5 ns/pF) CL + 55 ns 15 — 80 160
Clock Pulse Width tWH 5.0 200 100 — ns
10 120 60 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15 80 40 —
Clock Pulse Frequency fcl 5.0 — 5.0 2.5 MHz
10 — 8.3 4.2
15 — 12 6.0
µs
Clock Pulse Rise and Fall Time** tTLH 5.0 — — 15
tTHL 10 — — 5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15 — — 4
Setup Time tsu 5.0 0 – 50 — ns
10 0 – 15 —
15 0 – 8.0 —
Hold Time th 5.0 180 75 — ns
10 90 25 —
* The formulas given are for the typical characteristics only at 25_C.
15 75 20
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
—
** When shift register sections are cascaded, the maximum rise and fall times of the clock input should be equal to or less than the rise and fall times
** of the data outputs driving data inputs, plus the propagation delay of the output driving stage for the output capacitance load.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
VDD = – VGS Vout VDD = VGS Vout
14 14
CLOCK Q4 CLOCK Q4
DP1 Q8 DP1 Q8
Q9 Q9
DP5 Q13 DP5 Q13
DP10 Q17 IOH DP10 Q17 IOL
DP14 Q18 DP14 Q18
7 VSS EXTERNAL VSS EXTERNAL

POWER POWER
SUPPLY SUPPLY
Figure 1. Typical Output Source Current Figure 2. Typical Output Sink Current
Characteristics Test Circuit Characteristics Test Circuit
MOTOROLA CMOS LOGIC DATA MC14006B

27
VDD
14
PULSE
GENERATOR CLOCK Q4
DP1 Q8
Q9
DP5 Q13 CL CL
DP10 Q17 14
TEST 8 9
DP14 Q18
1/3 MC14000
PRESET 7
7 VSS CL CL CL CL OR EQUIV
50
ID
µF
1
f
CLOCK 50%
DATA
Figure 3. Power Dissipation Test Circuit and Waveforms
VDD
14
PULSE
CLOCK Q4
GENERATOR 1
DP1 Q8
Q9
DP5
Q13 CL
DP10 Q17 CL
PULSE CL
DP14 Q18
GENERATOR 2 CL
CL
7 VSS CL
20 ns 20 ns tWL tWH
90% VDD
CLOCK 50%
10% VSS
th “1” th “0”
tsu “1” tsu “0”
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
90% VDD
DATA 50%
10% VSS
4–STAGE 20 ns 20 ns tPLH tPHL
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
OUTPUT VOH
90%
Q4, Q8 50%
10% VOL
Q13, Q17 tTLH tTHL
ÉÉÉ
tPHL
5–STAGE VOH
ÉÉÉ
OUTPUT 90%
50%
Q9, Q18 10% VOL
ÉÉÉ
tTLH tTHL
ÉÉÉ
Output state can change since data previously clocked in might be in either state.
Figure 4. Switching Time Test Circuit and Waveforms
MC14006B MOTOROLA CMOS LOGIC DATA

28
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
14 9 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
–B– 3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
1 7 4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
–T– C 0.155 0.200 3.94 5.08
SEATING
K D 0.015 0.020 0.39 0.50
PLANE F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
F G N M J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
D 14 PL J 14 PL L 0.300 BSC 7.62 BSC
M 0_ 15_ 0_ 15_
0.25 (0.010) M T A S
0.25 (0.010) M T B S N 0.020 0.040 0.51 1.01
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06 NOTES:
ISSUE L 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
14 8 MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 7 FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J J 0.008 0.015 0.20 0.38
N K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
SEATING
PLANE K M 0_ 10_ 0_ 10_
H G D M N 0.015 0.039 0.39 1.01
MOTOROLA CMOS LOGIC DATA MC14006B

29
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
–A– Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
*MC14006B/D*
MC14006B ◊ MOTOROLA CMOS LOGIC DATA
MC14006B/D
30

SEMICONDUCTOR TECHNICAL DATA

Enviado por

Dados do documento

Título original

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

SEMICONDUCTOR TECHNICAL DATA

Enviado por

Direitos autorais:

Formatos disponíveis

MOTOROLA CMOS LOGIC DATA

MC14006B MOTOROLA CMOS LOGIC DATA

VDD = – VGS Vout VDD = VGS Vout

7 VSS EXTERNAL VSS EXTERNAL

MOTOROLA CMOS LOGIC DATA MC14006B

Figure 3. Power Dissipation Test Circuit and Waveforms

Figure 4. Switching Time Test Circuit and Waveforms

MC14006B MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA MC14006B

How to reach us:

Você também pode gostar

SEMICONDUCTOR TECHNICAL DATA

Enviado por

Dados do documento

Título original

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

SEMICONDUCTOR TECHNICAL DATA

Enviado por

Direitos autorais:

Formatos disponíveis

 

MOTOROLA CMOS LOGIC DATA

MC14006B MOTOROLA CMOS LOGIC DATA

VDD = – VGS Vout VDD = VGS Vout

7 VSS EXTERNAL VSS EXTERNAL

MOTOROLA CMOS LOGIC DATA MC14006B

Figure 3. Power Dissipation Test Circuit and Waveforms

Figure 4. Switching Time Test Circuit and Waveforms

MC14006B MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA MC14006B

How to reach us:

Você também pode gostar