Chapter Goals

• Describe operation of MOSFETs and JFETs.

• Define MOSFET characteristics in operation regions of cutoff,
triode and saturation.
Chapter 5 • Discuss mathematical models for i-v characteristics of MOSFETs
and JFETs.
Field-Effect Transistors • Introduce graphical representations for output and transfer
characteristic descriptions of electronic devices.
• Define and contrast characteristics of enhancement-mode and
depletion-mode MOFETs.
• Define symbols to represent MOSFETs in circuit schematics.
• Investigate circuits that bias transistors into different operating
regions.
• MOSFET and JFET DC circuit analysis
• Explore MOSFET modeling in SPICE

Channel-Length Modulation

• As vDS increases above

vDSAT, the length of the
depleted channel beyond
pinch-off point, DL,
increases and actual L
decreases.

• iD increases slightly with

vDS instead of being
constant.
'
Kn W  2
λ = channel length modulation iD =  v −VTN  1+ λv DS 
 GS
parameter 2 L

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 Enhancement-Mode PMOS Transistors:
Structure

• p-type source and drain regions in

n-type substrate.
• vGS < 0 required to create p-type
inversion layer in channel region
• For current flow, vGS < vTP
• To maintain reverse bias on
source-substrate and drain-
substrate junctions, vSB < 0 and
vDB < 0
• Positive bulk-source potential
causes VTP to become more
negative

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 Depletion-Mode MOSFETS

• NMOS transistors with VTN ≤ 0

• Ion implantation process is used to form a built-in
n-type channel in the device to connect source
and drain by a resistive channel
• Non-zero drain current for vGS = 0; negative vGS
required to turn device off.

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 Problem-solving Technique :MOSFET MOSFET Circuit Symbols
DC Analysis
• STep1: Requires knowing the bias
condition of the transistor such as • (g) and (i) are the
cutoff or saturation or nonsaturation. most commonly used
• Step2: If the bias condition is not symbols in VLSI logic
obvious, one must guess the bias design.
condition before analyzing the circuit.
• Step3 How can we Guess? • MOS devices are
(i) Assume that the transistor is biased in symmetric.
the saturation region, which implies • In NMOS, n+ region at
that: higher voltage is the
VGS>VTN, ID>0, and VDS≥VDS(sat) drain.
If all the above conditions are satisfied,
analyze the circuit using the saturation • In PMOS p+ region at
current voltage relations. lower voltage is the
(ii) If VGS<VTN, then transistor is probably drain
in cutoff mode.
(iii) If VDS<VDS(sat), the transistor is
likely biased in nonsaturation region,
analyze the circuit using nonsaturation
current voltage relations.

Summary of the MOSFET

Current-Voltage relationship MOSFET DC Analysis

• The DC circuit analysis is an important

part of the design of an amplifier.
Table 5.1

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 Common source circuit with coupling DC equivalent circuit.
capacitance Cc, which act an an open
circuit to the dc

Gate

PMOS common source circuit

If the device is biased in saturation

region

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 If ID=0 ⇒VDS=5V
If VDS=0 ⇒ ID=VDD/RD=0.25mA

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7
If VGS=0 and drain voltage (VDS) changes
Pinchoff at the drain terminal

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9
⇒

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