CCH LecturesF06

Introduction EE 40 Course Overview
• Instructor: Prof. Connie Chang-Hasnain • EECS 40:

– Office: 263M Cory Hall – One of five EECS core courses (with 20, 61A, 61B, and 61C)
– Office hour: M 3-4, W 12-1 • introduces “hardware” side of EECS
• prerequisite for EE105, EE130, EE141, EE150
– Email: cch@eecs.berkeley.edu
– Prerequisites: Math 1B, Physics 7B
– Secretary: Therese George, 253 Cory, therese@eecs.berkeley.edu
– Course involves three hours of lecture, one hour of discussion
• Background and three hours of lab work each week.
– 1987: Ph. D., EECS, UC Berkeley • Course content:
– Experiences: Bellcore; Assistant/Associate Prof. in EE, Stanford – Fundamental circuit concepts and analysis techniques
University; Founder, CEO, Bandwidth9 – First and second order circuits, impulse and frequency response
– 1996 - : Professor of EECS, Berkeley – Op Amps
– 2004 - : Director, Center for Optoelectronic Nano-SemiconductoR Tech. – Diode and FET: Device and Circuits
• Some Current Research Projects – Amplification, Logic, Filter
– Vertical cavity surface emitting lasers • Text Book
– Integrating VCSEL and MEMS – Electrical Engineering: Principles and Applications”, third edition,
Allan R. Hambley, Pearson Prentice Hall, 2005
– Synthesis of nanowires and quantum dots
– Supplementary Notes
– Slow down light in semiconductor to <200 m/sec.
EE40 Fall Slide 1 Prof. Chang-Hasnain EE40 Fall Slide 2 Prof. Chang-Hasnain
2006 2006
Important DATES Grading Policy

• Office hours, Discussion and Lab Sessions will • Weights:
start on week 2
– 11%: 11 HW sets
– Stay with ONE Discussion and Lab session you
registered. – 15%: 11 Labs
• Midterm and Final Dates: • 7 structured experiments (7%)
– Midterm: 10-11am on 9/27, 10/25, 11/29 (Location • one 4-week final project (8%)
TBD)
– 13% each: 3 midterm exams
– Final: 8-11am on 12/12 (Location TBD)
– 35%: Final exam
• Best Lecture Notes Contest
– Due at 263M Cory, 5pm, 12/15 • No late HW or Lab reports accepted
– Bonus points equivalent to 2% of final grade for one • No make-up exams unless Prof. Chang’s
winner
– If none of the submission contains complete information, no approval is obtained at least 24 hours before
winner will be selected. exam time; proofs of extraneous circumstances
• Best Final Project Contest are required.
– 12/8 3-5pm Location TBD
2006 2006
Grading Policy (Cont’d) Classroom Rules
• Weekly HW: • Please come to class on time.
– Assignment on the web by 5 pm Wednesdays,
starting 8/30/05. • Turn off cell phones, pagers, radio, CD,
– Due 5 pm the following Wednesday in HW box, 240 DVD, etc.
Cory.
• No food.
– On the top page, right top corner, write your name (in
the form: Last Name, First Name) with discussion • No pets.
session number.
• Do not come in and out of classroom.
– Graded homework will be returned one week later in
discussion sessions. • Lectures will be recorded and webcasted.
• Labs
– Complete the prelab section before going to the lab.
– Satisfactory completion of each lab is necessary to
pass class.
2006 2006
Week 1 Electric Charge

• Outline • Electrical effects are due to
– Electrical quantities – separation of charge electric force (voltage)
• Charge
– charges in motion electric flow (current)
• Current
• Voltage • Macroscopically, most matter is electrically
• Power neutral most of the time.
– The ideal basic circuit element – Exceptions: clouds in a thunderstorm, people on
– Sign conventions carpets in dry weather, plates of a charged capacitor,
– Circuit element I-V characteristics etc.
– Construction of a circuit model
• Microscopically, matter is full of electric charges
– Kirchhoff’s laws – a closer look
– Electric charge exists in discrete quantities, integral
• Reading multiples of the electronic charge -1.6 x 10-19
– Chapter 1 and beginning of Ch. 2 Coulomb
2006 2006
Classification of Materials
• Solids in which the outermost atomic electrons
are free to move around are metals.
– Metals typically have ~1 “free electron” per atom
– Examples:
• Solids in which all electrons are tightly bound to
atoms are insulators.
– Examples:
• Electrons in semiconductors are not tightly
bound and can be easily “promoted” to a free
state.
– Examples:
2006 2006
Electric Current Electric Current Examples

Definition: rate of positive charge flow 1. 105 positively charged particles (each with charge
1.6×10-19 C) flow to the right (+x direction) every
Symbol: i
nanosecond
Units: Coulombs per second ≡ Amperes (A)
Note: Current has polarity. Q 105 ×1.6 ×10−19
I = =+ −9
= 1.6 ×10−5 A
i = dq/dt where t 10
q = charge (Coulombs)
t = time (in seconds)
2. 105 electrons flow to the right (+x direction) every
microsecond
Q 105 ×1.6 ×10−19

I= =− −9
= −1.6 ×10−5 A
André-Marie Ampère's t 10
1775-1836
2006 2006
Current Density Current Density Example (cont’d)
Definition: rate of positive charge flow per unit area • Example 2:
Symbol: J Typical dimensions of integrated circuit
Units: A / cm2 components are in the range of 1 µm. What is
Example 1: Semiconductor with 1018 “free
the current density in a wire with 1 µm² area
Wire attached
electrons” per cm3 carrying 5 mA?
to end
2 cm
1 cm
C2
C1
10 cm
X
Suppose we force a current of 1 A to flow from C1 to C2:

• Electron flow is in -x direction:
1C / sec electrons
−19
= −6.25 × 1018
− 1.6 ×10 C / electron sec
2006 2006
Electric Potential (Voltage) Electric Power

• Definition: energy per unit charge • Definition: transfer of energy per unit time
• Symbol: v • Symbol: p
• Units: Joules/Coulomb ≡ Volts (V) • Units: Joules per second ≡ Watts (W)
Alessandro Volta
v = dw/dq (1745–1827) p = dw/dt = (dw/dq)(dq/dt) = vi
where w = energy (in Joules), q = charge (in Coulombs)
• Concept:
Note: Potential is always referenced to some point. As a positive charge q moves through a James Watt
1736 - 1819
a drop in voltage v, it loses energy
Subscript convention:
energy change = qv
vab means the potential at a
minus the potential at b. rate is proportional to # charges/sec
b vab ≡ va - vb
2006 2006
The Ideal Basic Circuit Element A Note about Reference Directions
i • A problem like “Find the current” or “Find the
voltage” is always accompanied by a definition
+ • Polarity reference for voltage can be of the direction:
v indicated by plus and minus signs - v +
i
_ • Reference direction for the current
is indicated by an arrow
Attributes: • In this case, if the current turns out to be 1 mA

• Two terminals (points of connection) flowing to the left, we would say i = -1 mA.
• Mathematically described in terms of current • In order to perform circuit analysis to determine
the voltages and currents in an electric circuit,
and/or voltage you need to specify reference directions.
• Cannot be subdivided into other elements • There is no need to guess the reference
direction so that the answers come out positive.
2006 2006
Sign Convention Example Another Example

Suppose you have an unlabelled battery and you measure Find vab, vca, vcb a
+ 2V −
c
its voltage with a digital voltmeter (DVM). It will tell you the + +
magnitude and sign of the voltage. −1 V vcd
− −
a With this circuit, you are b d
+ vbd −
measuring vab.
−1.401 The DVM indicates −1.401, so
DVM va is lower than vb by 1.401 V.
Which is the positive battery

b +
terminal?
Note that we have used the “ground” symbol ( ) for the reference Note that the labeling convention has nothing to do with
node on the DVM. Often it is labeled “C” for “common.”
whether or not v is positive or negative.
2006 2006
Sign Convention for Power Power
Passive sign convention If an element is absorbing power (i.e. if p > 0), positive
charge is flowing from higher potential to lower potential.
p = vi p = -vi
p = vi if the “passive sign convention” is used:
i i i i
i i
_ _ _
+ + +
v v v v v or v
_ + _ + _ +
How can a circuit element absorb power?
• If p > 0, power is being delivered to the box. By converting electrical energy into heat (resistors in toasters),
light (light bulbs), or acoustic energy (speakers); by storing
• If p < 0, power is being extracted from the box. energy (charging a battery).
2006 2006
Power Calculation Example Circuit Elements

Find the power absorbed by each element:
• 5 ideal basic circuit elements:
– voltage source active elements, capable of
Conservation of energy
– current source generating electric energy
total power delivered
equals – resistor
passive elements, incapable of
total power absorbed – inductor generating electric energy
Aside: For electronics these are unrealistically – capacitor
large currents – milliamperes or smaller is more
typical
vi (W) p (W) • Many practical systems can be modeled with
918 just sources and resistors
- 810
- 12
- 400
• The basic analytical techniques for solving
- 224 circuits with inductors and capacitors are
1116
similar to those for resistive circuits
2006 2006
Electrical Sources Ideal Voltage Source
• An electrical source is a device that is capable • Circuit element that maintains a prescribed
of converting non-electric energy to electric voltage across its terminals, regardless of the
energy and vice versa. current flowing in those terminals.
Examples: – Voltage is known, but current is determined by the
– battery: chemical electric circuit to which the source is connected.
– dynamo (generator/motor): mechanical electric • The voltage can be either independent or
(Ex. gasoline-powered generator, Bonneville dam) dependent on a voltage or current elsewhere in
the circuit, and can be constant or time-varying.
Electrical sources can either deliver or absorb power Device symbols:
vs +_ vs=µ vx +_ vs=ρ ix +_
independent voltage-controlled current-controlled

2006 2006
Ideal Current Source Electrical Resistance

• Circuit element that maintains a prescribed • Resistance: the ratio of voltage drop and
current through its terminals, regardless of the current. The circuit element used to model this
behavior is the resistor.
voltage across those terminals.
R
– Current is known, but voltage is determined by the Circuit symbol:
circuit to which the source is connected.
• The current can be either independent or Units: Volts per Ampere ≡ ohms (Ω
Ω)
dependent on a voltage or current elsewhere in
the circuit, and can be constant or time-varying. • The current flowing in the resistor
is proportional to the voltage
Device symbols:
across the resistor:
Georg Simon Ohm
is is=α vx is=β ix v = i R (Ohm’s Law) 1789-1854
where v = voltage (V), i = current (A), and R = resistance (Ω)

independent voltage-controlled current-controlled
2006 2006
Electrical Conductance Short Circuit and Open Circuit
• Conductance is the reciprocal of resistance. • Short circuit
Symbol: G – R = 0 no voltage difference exists
Ω – all points on the wire are at the same
Units: siemens (S) or mhos ( ) potential.
Example: – Current can flow, as determined by the circuit
Consider an 8 Ω resistor. What is its conductance? • Open circuit
– R = ∞ no current flows
– Voltage difference can exist, as determined
by the circuit
Werner von Siemens
1816-1892
2006 2006
Example: Power Absorbed by a Resistor More Examples

p = vi = ( iR )i = i2R • Are these interconnections permissible?
This circuit connection is
p = vi = v ( v/R ) = v2/R permissible. This is because
the current sources can
Note that p > 0 always, for a resistor a resistor sustain any voltage across;
Hence this is permissible.
dissipates electric energy
Example:
a) Calculate the voltage vg and current ia.
b) Determine the power dissipated in the 80Ω resistor. This circuit connection is
NOT permissible. It violates
the KCL.
2006 2006
Summary Summary (cont’d)
• Current = rate of charge flow i = dq/dt • Passive sign convention
• Voltage = energy per unit charge created by – For a passive device, the reference direction
charge separation
for current through the element is in the
• Power = energy per unit time direction of the reference voltage drop across
• Ideal Basic Circuit Elements the element
– two-terminal component that cannot be sub-divided
– described mathematically in terms of its terminal
voltage and current
– An ideal voltage source maintains a prescribed voltage
regardless of the current in the device.
– An ideal current source maintains a prescribed current
regardless of the voltage across the device.
– A resistor constrains its voltage and current to be
proportional to each other: v = iR (Ohm’s law)
2006 2006
Current vs. Voltage (I-V) Characteristic I-V Characteristic of Ideal Voltage Source
i
• Voltage sources, current sources, and a i
resistors can be described by plotting the +
current (i) as a function of the voltage (v) Vab _+ vs
_
i i=0
b v
+ Vs>0
v
_
1. Plot the I-V characteristic for vs > 0. For what
values of i does the source absorb power? For
what values of i does the source release power?
Passive? Active? 2. Repeat
Vs>0 (1)
i<0for vs < 0.power; i>0 absorb power
release
3. What is the I-V characteristic for an ideal wire?
2006 2006
I-V Characteristic of Ideal Voltage Source I-V Characteristic of Ideal Voltage Source
i i
a i a i
+ +
Vab +_ vs Vab +_ vs
_ _
b v b v
Vs<0
2. Plot the I-V characteristic for vs < 0. For what 3. What is the I-V characteristic for an ideal wire?
values of i does the source absorb power? For
what values of i does the source release power?
Vs<0 i>0 release power; i<0 absorb power Do not forget Vab=-Vba
2006 2006
I-V Characteristic of Ideal Current Source Short Circuit and Open Circuit
i i Wire (“short circuit”):
+ • R = 0 no voltage difference exists
v is (all points on the wire are at the same potential)
_ • Current can flow, as determined by the circuit
v
Air (“open circuit”):
• R = ∞ no current flows
• Voltage difference can exist,
1. Plot the I-V characteristic for is > 0. For what values as determined by the circuit
of v does the source absorb power? For what
values of v does the source release power?
V>0 absorb power; V<0 release power
2006 2006
I-V Characteristic of Ideal Resistor More Examples: Correction from last Lec.
i i • Are these interconnections permissible?
a
This circuit connection is
+ permissible. This is because
v R the current sources can
_ sustain any voltage across;
Hence this is permissible.
b v
1. Plot the I-V characteristic for R = 1 kΩ
Ω. What is the
slope?
a a This circuit connection is
+ NOT permissible. It violates
Vab Vab the KCL.
R R
_
b b
2006 2006
Construction of a Circuit Model Terminology: Nodes and Branches

• The electrical behavior of each physical Node: A point where two or more circuit elements
component is of primary interest. are connected
• We need to account for undesired as well

as desired electrical effects.
Branch: A path that connects two nodes
• Simplifying assumptions should be made
wherever reasonable.
2006 2006
Circuit Nodes and Loops Kirchhoff’s Laws
• A node is a point where two or more circuit • Kirchhoff’s Current Law (KCL):
elements are connected. – The algebraic sum of all the currents entering
• A loop is formed by tracing a closed path in a any node in a circuit equals zero.
circuit through selected basic circuit elements • Kirchhoff’s Voltage Law (KVL):
without passing through any intermediate node – The algebraic sum of all the voltages around
more than once any loop in a circuit equals zero.
Gustav Robert Kirchhoff

1824-1887
2006 2006
Notation: Node and Branch Voltages Using Kirchhoff’s Current Law (KCL)
• Use one node as the reference (the “common” Consider a node connecting several branches:
or “ground” node) – label it with a symbol
• The voltage drop from node x to the reference
i2
node is called the node voltage vx.
i3
• The voltage across a circuit element is defined
i1
as the difference between the node voltages at
its terminals
– v1 + i4
Example: a R1 b
+ +
va _+ vs
• Use reference directions to determine whether
R2 vb
_ _ currents are “entering” or “leaving” the node –
c  REFERENCE NODE with no concern about actual current directions
2006 2006
Formulations of Kirchhoff’s Current Law A Major Implication of KCL
(Charge stored in node is zero.)
• KCL tells us that all of the elements in a single
Formulation 1: branch carry the same current.
Sum of currents entering node • We say these elements are connected in series.
= sum of currents leaving node
Formulation 2:
Algebraic sum of currents entering node = 0
• Currents leaving are included with a minus sign.
Formulation 3: Current entering node = Current leaving node

Algebraic sum of currents leaving node = 0 i1 = i2
• Currents entering are included with a minus sign.
2006 2006
KCL Example Generalization of KCL

• The sum of currents entering/leaving a closed
Currents entering the node: surface is zero. Circuit branches can be inside
-10 mA
i this surface, i.e. the surface can enclose more
than one node!
5 mA Currents leaving the node:
i2
i3
15 mA
This could be a big
chunk of a circuit, i4
3 formulations of KCL: e.g. a “black box” i1
1.
2.
3.
2006 2006
Generalized KCL Examples Using Kirchhoff’s Voltage Law (KVL)
Consider a branch which forms part of a loop:
50 mA
5µA + –
loop v1 loop v2
_
+
2µA i
Moving from + to - Moving from - to +
i
We add V1 We subtract V1
• Use reference polarities to determine whether a

voltage is dropped
• No concern about actual voltage polarities
2006 2006
Formulations of Kirchhoff’s Voltage Law A Major Implication of KVL

(Conservation of energy) • KVL tells us that any set of elements which are
Formulation 1: connected at both ends carry the same voltage.
Sum of voltage drops around loop • We say these elements are connected in parallel.
= sum of voltage rises around loop
Formulation 2: + +
Algebraic sum of voltage drops around loop = 0 va vb
• Voltage rises are included with a minus sign. _ _
(Handy trick: Look at the first sign you encounter on each element when tracing the loop.)
Formulation 3: Applying KVL in the clockwise direction,

Algebraic sum of voltage rises around loop = 0 starting at the top:
• Voltage drops are included with a minus sign.
vb – va = 0 vb = va
2006 2006
KVL Example An Underlying Assumption of KVL
Three closed paths: • No time-varying magnetic flux through the loop
Otherwise, there would be an induced voltage (Faraday’s Law)
+ v2 − v3
b
− +
a c
1 2 • Note: Antennas are designed to “pick up”

+ + + v
electromagnetic waves; “regular circuits” B( t )
va vb vc often do so undesirably.
− - −
Avoid these loops! + −
3 v( t )
Path 1: How do we deal with antennas (EECS 117A)?
Path 2: Include a voltage source as the circuit representation

of the induced voltage or “noise”.
Path 3: (Use a lumped model rather than a distributed (wave) model.)
2006 2006
I-V Characteristic of Elements Resistors in Series

i Find the I-V characteristic. Consider a circuit with multiple resistors connected in series.
a
Find their “equivalent resistance”.
+ i
R + • KCL tells us that the same
Vab _ vs I
_ current (I) flows through
R1
every resistor
b R2
+ • KVL tells us
VSS
v − R3
R4
Equivalent resistance of resistors in series is the sum

2006 2006
Voltage Divider When can the Voltage Divider Formula be Used?
I I
I I = VSS / (R1 + R2 + R3 + R4)
+ R1 R1
R1
– V1 R2
+ R2
+
R2 + – V2 VSS + – V2
+
VSS
VSS + − R3 − R3
− R3
– V3
R4 R4 R5
R4
R R
V = 2 ⋅V V ≠ 2 ⋅V
2 SS 2 SS
R +R +R +R R +R +R +R
1 2 3 4 1 2 3 4
Correct, if nothing else Why? What is V2?
is connected to nodes
2006 2006
Resistors in Parallel General Formula for Parallel Resistors

Consider a circuit with two resistors connected in parallel. What single resistance Req is equivalent to three resistors in parallel?
Find their “equivalent resistance”. I I
x + +
• KVL tells us that the V R1 R2 R3 eq
≡ V Req
I1 I2 same voltage is dropped − −
across each resistor
ISS R1 R2
Vx = I1 R1 = I2 R2
• KCL tells us
Equivalent conductance of resistors in parallel is the sum

2006 2006
Current Divider Generalized Current Divider Formula
x Consider a current divider circuit with >2 resistors in parallel:
I1 I2 + I
I1 I2 I3 V V=
ISS R1 R2 Vx = I1 R1 = ISS Req I R1 R2 R3  1   1   1 
 +  +  
−  R1   R 2   R 3 
V  1/R 3 
I3 = = I 
R3 1/R 1 + 1/R 2 + 1/R 3 
2006 2006
Summary Summary (cont’d)

• An electrical system can be modeled by an electric circuit • Resistors in Series – Voltage Divider
(combination of paths, each containing 1 or more circuit
elements)
– Lumped model
• Conductances in Parallel – Current Divider
• The Current versus voltage characteristics (I-V plot) is
a universal means of describing a circuit element.
• Kirchhoff’s current law (KCL) states that the algebraic
sum of all currents at any node in a circuit equals zero.
– Comes from conservation of charge
• Kirchhoff’s voltage law (KVL) states that the algebraic
sum of all voltages around any closed path in a circuit
equals zero.
– Comes from conservation of potential energy
2006 2006
Week 2 Measuring Voltage
• Outline To measure the voltage drop across an element in a
real circuit, insert a voltmeter (digital multimeter in
– Node-Voltage Analysis voltage mode) in parallel with the element.
– Mesh-Current Analysis Voltmeters are characterized by their “voltmeter input
– Superposition resistance” (Rin). Ideally, this should be very high
– Thévenin equivalent circuits (typical value 10 MΩ)
– Norton equivalent circuits

Ideal
– Maximum Power Transfer
Voltmeter
• Reading
Rin
– Chapter 2
2006 2006
Effect of Voltmeter Measuring Current

undisturbed circuit circuit with voltmeter inserted To measure the current flowing through an element in a
real circuit, insert an ammeter (digital multimeter in
current mode) in series with the element.
R1 R1
+ + Ammeters are characterized by their “ammeter input
VSS +
_ V2
+
VSS _ resistance” (Rin). Ideally, this should be very low
R2 R2 Rin V2′
– – (typical value 1Ω).
Compare to R2 Ideal
Ammeter
 R2   R 2 || Rin 
V2 = VSS   V2′ = VSS  
R1 + R 2  R 2 || Rin + R1 
Rin
Example: VSS = 10 V , R 2 = 100 K , R1 = 900 K ⇒ V2 = 1V
Rin = 10 M , V2′ = ?
2006 2006
Effect of Ammeter Using Equivalent Resistances
Measurement error due to non-zero input resistance: Simplify a circuit before applying KCL and/or KVL:
undisturbed circuit circuit with ammeter inserted Example: Find I
I Imeas
ammeter I
R1 R1 R1 R1 = R2 = 3 kΩ
Rin R3 R3 = 6 kΩ
R2
V1 +
_ V1 +
_ +
R2 7V R4
−
R2 R4 = R5 = 5 kΩ
R6
R5 R6 = 10 kΩ
V1 V1
I= Imeas =
R1 + R 2 R1 + R 2 + Rin
Example: V1 = 1 V, R1= R2 = 500 Ω, Rin = 1Ω Compare to
1V R2 + R2
I= = 1mA, I meas = ?
500Ω + 500Ω
2006 2006
Node-Voltage Circuit Analysis Method Nodal Analysis: Example #1

R1 R
1. Choose a reference node (“ground”) 3
Look for the one with the most connections!
+
- V1 R2 R4 IS
2. Define unknown node voltages
those which are not fixed by voltage sources
1. Choose a reference node.
3. Write KCL at each unknown node, expressing
current in terms of the node voltages (using the 2. Define the node voltages (except reference node and
I-V relationships of branch elements) the one set by the voltage source).
Special cases: floating voltage sources 3. Apply KCL at the nodes with unknown voltage.
4. Solve the set of independent equations
N equations for N unknown node voltages
4. Solve for unknown node voltages.
2006 2006
Nodal Analysis: Example #2 Nodal Analysis w/ “Floating Voltage Source”
R1 A “floating” voltage source is one for which neither side is
Va R5 connected to the reference node, e.g. VLL in the circuit below:
Va VLL Vb
R3 I1 - +
V R2 R4 V2
1
I1 R2 R4 I2
Challenges:
Determine number of nodes needed Problem: We cannot write KCL at nodes a or b because
Deal with different types of sources there is no way to express the current through the voltage
source in terms of Va-Vb.
Solution: Define a “supernode” – that chunk of the circuit
containing nodes a and b. Express KCL for this supernode.
Incorporate voltage source constraint into KCL equation.
2006 2006
Nodal Analysis: Example #3 Formal Circuit Analysis Methods

supernode MESH ANALYSIS
NODAL ANALYSIS
(“Mesh-Current Method”)
Va VLL (“Node-Voltage Method”)
Vb 1) Select M independent mesh
- + 0) Choose a reference node currents such that at least one
1) Define unknown node voltages mesh current passes through each
branch*
I1 R2 R4 I2 2) Apply KCL to each unknown
M = #branches - #nodes + 1
node, expressing current in
terms of the node voltages 2) Apply KVL to each mesh,
=> N equations for expressing voltages in terms of
N unknown node voltages mesh currents
Eq’n 1: KCL at supernode
=> M equations for
3) Solve for node voltages
M unknown mesh currents
=> determine branch currents
3) Solve for mesh currents
=> determine node voltages
Substitute property of voltage source: *Simple method for planar circuits
A mesh current is not necessarily identified with a branch current.
2006 2006
Mesh Analysis: Example #1 Mesh Analysis with a Current Source
ia ib
1. Select M mesh currents.

Problem: We cannot write KVL for meshes a and b
2. Apply KVL to each mesh.
because there is no way to express the voltage drop
across the current source in terms of the mesh currents.
Solution: Define a “supermesh” – a mesh which avoids the
3. Solve for mesh currents.
branch containing the current source. Apply KVL for this
supermesh.
2006 2006
Mesh Analysis: Example #2 Mesh Analysis with Dependent Sources

• Exactly analogous to Node Analysis
• Dependent Voltage Source: (1) Formulate
ia ib and write KVL mesh eqns. (2) Include and
express dependency constraint in terms of
mesh currents
Eq’n 1: KVL for supermesh • Dependent Current Source: (1) Use
supermesh. (2) Include and express
dependency constraint in terms of mesh
currents
Eq’n 2: Constraint due to current source:
2006 2006
Circuit w/ Dependent Source Example Superposition
Find i2, i1 and io A linear circuit is one constructed only of linear
elements (linear resistors, and linear capacitors and
inductors, linear dependent sources) and
independent sources. Linear
means I-V charcteristic of elements/sources are
straight lines when plotted
Principle of Superposition:
• In any linear circuit containing multiple
independent sources, the current or voltage at
any point in the network may be calculated as
the algebraic sum of the individual contributions
of each source acting alone.
2006 2006
Source Combinations Superposition

• Voltage sources in series can be replaced by an Procedure:
equivalent voltage source: 1. Determine contribution due to one independent source
• Set all other sources to 0: Replace independent voltage
+ source by short circuit, independent current source by open
v1 – + circuit
v1+v2
+ ≡ – 2. Repeat for each independent source
v2 – 3. Sum individual contributions to obtain desired voltage
or current
• Current sources in parallel can be replaced by
an equivalent current source:
i1 i2 ≡ i1+i2
2006 2006
Open Circuit and Short Circuit Superposition Example
• Open circuit i=0 ; Cut off the branch • Find Vo 2Ω 4V
• Short circuit v=0 ; replace the element by wire +–
+
+
• Turn off an independent voltage source means 24 V – 4A 4 Ω Vo
– V=0
–
– Replace by wire
– Short circuit
• Turn off an independent current source means
– i=0
– Cut off the branch
– open circuit
2006 2006
Equivalent Circuit Concept Thévenin Equivalent Circuit

• A network of voltage sources, current sources, • Any* linear 2-terminal (1-port) network of indep. voltage
and resistors can be replaced by an sources, indep. current sources, and linear resistors can
be replaced by an equivalent circuit consisting of an
equivalent circuit which has identical terminal
independent voltage source in series with a resistor
properties (I-V characteristics) without without affecting the operation of the rest of the circuit.
affecting the operation of the rest of the circuit.
iA iB Thévenin equivalent circuit
network A network B a RTh a
+ +
of of
sources vA ≡ sources vB network + iL + iL
of
and _ and _ vL
+
vL
resistors resistors sources
and
RL ≡ VTh – RL
– –
resistors
iA(vA) = iB(vB) b b
“load” resistor
2006 2006
I-V Characteristic of Thévenin Equivalent Thévenin Equivalent Example
• The I-V characteristic for the series combination of Find the Thevenin equivalent with respect to the terminals a,b:
elements is obtained by adding their voltage drops:
For a given current i, the voltage drop
vab is equal to the sum of the voltages i
dropped across the source (VTh)
and across the resistor (iRTh)
vab = VTh- iR
RTh a
i + v
+
VTh – vab I-V characteristic
of resistor: v = iR
–
I-V characteristic of voltage source: v = VTh

2006 2006
RTh Calculation Example #1 Norton Equivalent Circuit

• Any* linear 2-terminal (1-port) network of indep. voltage
sources, indep. current sources, and linear resistors can
be replaced by an equivalent circuit consisting of an
independent current source in parallel with a resistor
without affecting the operation of the rest of the circuit.
Norton equivalent circuit

a a
Set all independent sources to 0: network + iL + iL
of
sources vL RL ≡ iN RN vL RL
and
– –
resistors
b b
2006 2006
I-V Characteristic of Norton Equivalent Finding IN and RN = RTh
• The I-V characteristic for the parallel combination of
elements is obtained by adding their currents:
For a given voltage vab, the current i is Analogous to calculation of Thevenin Eq. Ckt:
equal to the sum of the currents in i I-V
each of the two branches: characteristic 1) Find o.c voltage and s.c. current
of current
source: i = -IN IN ≡ isc = VTh/RTh
a i
+ i = IN-Gv
v
iN RN vab
– I-V characteristic 2) Or, find s.c. current and Norton (Thev) resistance
of resistor: i=Gv
b
2006 2006
Finding IN and RN Maximum Power Transfer Theorem

Thévenin equivalent circuit
• We can derive the Norton equivalent circuit from RTh Power absorbed by load resistor:
a Thévenin equivalent circuit simply by making a 2
source transformation: + iL  VTh 

+ p = i RL = 
2
L
 RL
RTh a a
VTh – vL RL  RTh + RL 
–
+ iL + iL
+
vTh – vL RL iN RN vL RL dp
To find the value of RL for which p is maximum, set to 0:
– – dRL
dp  (R + RL )2 − RL × 2(RTh + RL ) 
b b = VTh2  Th =0
dRL  ( R Th + RL )4

voc v
RN = RTh = ; iN = Th = isc
⇒ (RTh + RL ) − RL × 2(RTh + RL ) = 0
2
isc RTh
⇒ RTh = RL A resistive load receives maximum power from a circuit if the
load resistance equals the Thévenin resistance of the circuit.
2006 2006
Week 3 (Lec 3.1-3.2) The Wheatstone Bridge
• Outline • Circuit used to precisely measure resistances in
– Wheatstone Bridge the range from 1 Ω to 1 MΩ, with ±0.1% accuracy
R1 and R2 are resistors with known values
– Delta-Y Conversion
R3 is a variable resistor (typically 1 to 11,000Ω)
– Dependent Sources
Rx is the resistor whose value is to be measured
– Potential plots for resistive circuits
– The capacitor
battery R1 R2
– The inductor
+
• Reading V
current detector
–
– Chap. 2 and Chap. 3 R3 Rx
variable resistor
2006 2006
Finding the value of Rx Finding the value of Rx

• Adjust R3 until there is no current in the detector • Adjust R3 until there is no current in the detector
R2 R2
Then, Rx = R3 Then, Rx = R3
R1 Derivation: R1 Derivation:
KCL => i1 = i3 and i2 = ix
R1 R2 R1 R2 KVL => i3R3 = ixRx and i1R1 = i2R2

i1 i2 i1 i2
+ +
V i3 ix V i3 ix i1R3 = i2Rx
– –
R3 Rx R3 Rx
R3 Rx
Typically, R2 / R1 can be varied Typically, R2 / R1 can be varied
=
R1 R2
from 0.001 to 1000 in decimal steps from 0.001 to 1000 in decimal steps
2006 2006
Identifying Series and Parallel Combinations Y-Delta Conversion
Some circuits must be analyzed (not amenable to simple inspection) • These two resistive circuits are equivalent for
R1 voltages and currents external to the Y and ∆
R1 R2
+ R3 I circuits. Internally, the voltages and currents
V
−
+ R2 R3 are different.
a
V - Rc
b
R4 R5
a b
R4 R1 R2
Special cases: Rb Ra R3
R3 = 0 OR R3 = ∞
R5
c c
RbRc RaRc RaRb

R1 = R2 = R3 =
Ra + Rb + Rc Ra + Rb + Rc Ra + Rb + Rc
Brain Teaser Category: Important for motors and electrical utilities.
2006 2006
Delta-to-Wye (Pi-to-Tee) Equivalent Circuits ∆-Y and Y-∆

∆ Conversion Formulas
• In order for the Delta interconnection to be equivalent
to the Wye interconnection, the resistance between Delta-to-Wye conversion Wye-to-Delta conversion
corresponding terminal pairs must be the same
Rc Rc
a b
RbRc a b R1R2 + R2R3 + R3R1
Rc (Ra + Rb) R1 = Ra =
Rab = = R1 + R2 Ra + Rb + Rc R1
Rb Ra
Ra + Rb + Rc Rb Ra
RaRc c R1R2 + R2R3 + R3R1

a c Ra (Rb + Rc) R2 = Rb =
b Rbc = = R2 + R3 Ra + Rb + Rc R2
Ra + Rb + Rc a
R1 R2 b
RaRb R1R2 + R2R3 + R3R1
Rb (Ra + Rc) R3 = R1 R2
Rc =
Rca = = R1 + R3 Ra + Rb + Rc R3
R3 R3
Ra + Rb + Rc
c
c
2006 2006
Circuit Simplification Example Dependent Sources
Find the equivalent resistance Rab: • Node-Voltage Method
Ω
2Ω Ω
2Ω
– Dependent current source:
a a • treat as independent current source in organizing node eqns
• substitute constraining dependency in terms of defined node voltages.
Ω
18Ω Ω
12Ω – Dependent voltage source:
Ω
6Ω
≡ • treat as independent voltage source in organizing node eqns
• Substitute constraining dependency in terms of defined node voltages.
Ω
9Ω Ω
4Ω • Mesh Analysis
b
– Dependent Voltage Source:
• Formulate and write KVL mesh eqns.
Ω
9Ω Ω
4Ω • Include and express dependency constraint in terms of mesh currents
b – Dependent Current Source:
• Use supermesh.
• Include and express dependency constraint in terms of mesh currents
2006 2006
Comments on Dependent Sources Node-Voltage Method and Dependent Sources

A dependent source establishes a voltage or current • If a circuit contains dependent sources, what to do?
whose value depends on the value of a voltage or
current at a specified location in the circuit. Example:
(device model, used to model behavior of transistors & amplifiers) i∆
To specify a dependent source, we must identify: 20 Ω
1. the controlling voltage or current (must be calculated, in general)
2. the relationship between the controlling voltage or current
10 Ω
+
and the supplied voltage or current 2.4 A 200 Ω – 80 V
3. the reference direction for the supplied voltage or current –
+ 5i∆
The relationship between the dependent source
and its reference cannot be broken!
– Dependent sources cannot be turned off for various
purposes (e.g. to find the Thévenin resistance, or in
analysis using Superposition).
2006 2006
RTh Calculation Example #2 Circuit w/ Dependent Source Example
Find the Thevenin equivalent with respect to the terminals a,b: Find i2, i1 and io
2006 2006
Summary of Techniques for Circuit Analysis -1 Summary of Techniques for Circuit Analysis -2
(Chap 2) (Chap 2)
• Resistor network • Node Analysis
– Parallel resistors – Node voltage is the unknown
– Series resistors – Solve for KCL
– Y-delta conversion – Floating voltage source using super node
– “Add” current source and find voltage (or vice • Mesh Analysis
versa) – Loop current is the unknown
• Superposition – Solve for KVL
– Leave one independent source on at a time – Current source using super mesh
– Sum over all responses • Thevenin and Norton Equivalent Circuits
– Voltage off SC – Solve for OC voltage
– Current off OC – Solve for SC current
2006 2006
Potential Plots for a Single Resistor and Two
Open Circuit and Short Circuit
Resistors in Series (Potential is Plotted Vertically)
• Open circuit i=0 ; Cut off the branch
• Short circuit v=0 ; replace the element by wire
• Turn off an independent voltage source means
– V=0
– Replace by wire
– Short circuit
• Turn off an independent current source means
– i=0
– Cut off the branch
– open circuit
Arrows represent voltage drops

2006 2006
Potential Plot for Two Resistors in Parallel The Capacitor

V Two conductors (a,b) separated by an insulator:
R1 difference in potential = Vab
=> equal & opposite charge Q on conductors
R2 Q = CVab (stored charge in terms of voltage)
where C is the capacitance of the structure,

positive (+) charge is on the conductor at higher potential
Parallel-plate capacitor:
• area of the plates = A (m2)
• separation between plates = d (m)
• dielectric permittivity of insulator = ε
Arrows represent voltage drops (F/m)
Aε
C= F
(F)
=> capacitance d
2006 2006
Capacitor Voltage in Terms of Current
+
Symbol: or C t
C C Electrolytic (polarized) Q(t ) = ∫ ic (t )dt + Q(0)

capacitor
0
Units: Farads (Coulombs/Volt)
t t
(typical range of values: 1 pF to 1 µF; for “supercapa- 1 Q(0) 1
citors” up to a few F!) vc (t ) = ∫ ic (t )dt + = ∫ ic (t )dt + vc (0)
Current-Voltage relationship: C0 C C0
ic
dQ dv dC Uses: Capacitors are used to store energy for camera flashbulbs,
ic = = C c + vc +
in filters that separate various frequency signals, and
dt dt dt vc they appear as undesired “parasitic” elements in circuits where
If C (geometry) is unchanging, iC = C dvC/dt
– they usually degrade circuit performance
Note: Q (vc) must be a continuous function of time
2006 2006
Stored Energy A more rigorous derivation

CAPACITORS STORE ELECTRIC ENERGY
ic
You might think the energy stored on a capacitor is QV = +
CV2, which has the dimension of Joules. But during
This derivation holds
vc
charging, the average voltage across the capacitor was independent of the circuit! –
only half the final value of V for a linear capacitor.
Thus, energy is 1 QV = 1
CV 2 . t = t Final v = VFinal dQ v = VFinal
2 2
w= ∫ v c ⋅ i c dt = ∫ c
v dt = ∫ v c dQ
t = t Initial v = VInitial dt v = VInitial
Example: A 1 pF capacitance charged to 5 Volts
has ½(5V)2 (1pF) = 12.5 pJ v = VFinal 1
(A 5F supercapacitor charged to 5 2 1 2
volts stores 63 J; if it discharged at a
w= ∫ Cv c dv c = CVFinal − CVInitial
v = VInitial 2 2
constant rate in 1 ms energy is
discharged at a 63 kW rate!)
2006 2006
Example: Current, Power & Energy for a Capacitor
t
1 i(t) p (W) i(t)
C ∫0
v(t ) = i (τ )dτ + v(0)
v (V) v(t)
+
v(t)
+
– 10 µF – 10 µF
1
0 t (µs)
1 2 3 4 5
t (µs)
0 1 2 3 4 5
i (µA) vc and q must be continuous
dv functions of time; however, p = vi
i =C ic can be discontinuous.
dt
w (J) t
t (µs) 1
w = ∫ pdτ = Cv 2
0 1 2 3 4 5
Note: In “steady state”
(dc operation), time 0
2
derivatives are zero t (µs)
0 1 2 3 4 5
C is an open circuit
2006 2006
Capacitors in Series Capacitive Voltage Divider

+ v1(t) – + v2(t) – Q: Suppose the voltage applied across a series combination
of capacitors is changed by ∆v. How will this affect the
+ voltage across each individual capacitor?
C1 C2
i(t) i(t) v(t)=v1(t)+v2(t) ∆Q1=C1∆v1
Ceq ∆v = ∆v1 + ∆v2
– Note that no net charge can
∆Q1
Q1+∆ +
C1 can be introduced to this node.
∆v1
v1+∆
-Q1−∆Q1 – Therefore, −∆Q1+∆Q2=0
∆v
v+∆ +
–
∆Q2
Q2+∆ + ⇒ C1∆v1 = C2 ∆v2
C2 ∆v2
v2(t)+∆ C1
−Q2−∆Q2 – ∆v2 = ∆v
1 1 1 C1 + C2
= + ∆Q2=C2∆v2 Note: Capacitors in series have the same incremental
Ceq C1 C2
charge.
2006 2006
Practical Capacitors Inductor
• A capacitor can be constructed by interleaving the plates
with two dielectric layers and rolling them up, to achieve Symbol:
a compact size. L
Units: Henrys (Volts • second / Ampere)

(typical range of values: µH to 10 H)
Current in terms of voltage:

1 iL
• To achieve a small volume, a very thin dielectric with a diL = vL (t )dt +
high dielectric constant is desirable. However, dielectric L vL
materials break down and become conductors when the t
1 –
electric field (units: V/cm) is too high.
iL (t ) = ∫ vL (τ )dτ + i (t0 )
– Real capacitors have maximum voltage ratings L t0
– An engineering trade-off exists between compact size and
high voltage rating Note: iL must be a continuous function of time
2006 2006
Stored Energy Inductors in Series and Parallel

INDUCTORS STORE MAGNETIC ENERGY
Consider an inductor having an initial current i(t0) = i0
Common
p(t ) = v(t )i(t ) = Current
w(t ) = ∫ p(τ )dτ =

t0
Common
1 1 2
w(t ) = Li 2 − Li0 Voltage
2 2
2006 2006
Mutual Inductance Summary
i1 M i2 Capacitor Inductor
+ +
dv di
v1 L1 L2 v2 i =C v=L
dt dt
- -
1 2 1
w = Cv w = Li 2
di di 2 2
v1 = L1 1 + M 2
dt dt v cannot change instantaneously i cannot change instantaneously
di di i can change instantaneously v can change instantaneously
v2 = M 1 + L1 2 Do not short-circuit a charged Do not open-circuit an inductor with
dt dt capacitor (-> infinite current!) current (-> infinite voltage!)
n n
Example: Transformer – 100% flux linkage 1
=∑
1
n ind.’s in series: Leq = ∑ Li
n cap.’s in series: Ceq i =1 Ci i =1
N1 turns N2 turns |v2|/|v1| = N2/N1 1 n

1
∑
n
n cap.’s in parallel: Ceq = ∑C
i =1
i
n ind.’s in parallel: =
Leq i =1 Li
2006 2006
Summary 2 Chapter 4 (Lec. 3-3 to 5-1)

• Steady-state nothing is time varying. • OUTLINE
• In steady state, an inductor behaves like a short – First Order Circuits
circuit • RC and RL Examples
• General Procedure
• In steady state, a capacitor behaves like an – RC and RL Circuits with General Sources
open circuit • Particular and complementary solutions
• Time constant
– Second Order Circuits
• The differential equation
• Particular and complementary solutions
• The natural frequency and the damping ratio
• Reading
– Chapter 4
2006 2006
First-Order Circuits Response of a Circuit
• A circuit that contains only sources, resistors • Transient response of an RL or RC circuit is
and an inductor is called an RL circuit. – Behavior when voltage or current source are suddenly
• A circuit that contains only sources, resistors applied to or removed from the circuit due to switching.
and a capacitor is called an RC circuit. – Temporary behavior
• RL and RC circuits are called first-order circuits • Steady-state response (aka. forced response)
because their voltages and currents are – Response that persists long after transient has decayed
described by first-order differential equations. • Natural response of an RL or RC circuit is
R R – Behavior (i.e., current and voltage) when stored energy
in the inductor or capacitor is released to the resistive
part of the network (containing no independent
i i
vs
+
vs
+ sources).
– L – C
2006 2006
Natural Response Summary First Order Circuits

RL Circuit RC Circuit +
vr(t)
- iL(t)
ic(t)
i + +
R
+ +
L R C v R vs(t) C vc(t) is(t) R L vL(t)
- -
–
-
• Inductor current • Capacitor voltage KVL around the loop: KCL at the node:
cannot change cannot change t
vr(t) + vc(t) = vs(t) v(t ) 1
instantaneously instantaneously + ∫ v( x)dx = is (t )
• In steady state, an • In steady state, a R L −∞
dvc (t )
inductor behaves like capacitor behaves like RC + vc (t ) = vs (t ) L diL (t )
dt + iL (t ) = is (t )
a short circuit. an open circuit R dt
2006 2006
Procedure for Finding Transient Response Procedure (cont’d)
1. Identify the variable of interest 3. Calculate the final value of the variable
• For RL circuits, it is usually the inductor current iL(t) (its value as t ∞)
• For RC circuits, it is usually the capacitor voltage vc(t) • Again, make use of the fact that an inductor
behaves like a short circuit in steady state (t ∞)
2. Determine the initial value (at t = t0- and t0+) of or that a capacitor behaves like an open circuit in
the variable steady state (t ∞)
• Recall that iL(t) and vc(t) are continuous variables:
4. Calculate the time constant for the circuit
iL(t0+) = iL(t0−) and vc(t0+) = vc(t0−)
τ = L/R for an RL circuit, where R is the Thévenin
• Assuming that the circuit reached steady state before equivalent resistance “seen” by the inductor
t0 , use the fact that an inductor behaves like a short τ = RC for an RC circuit where R is the Thévenin
circuit in steady state or that a capacitor behaves like equivalent resistance “seen” by the capacitor
an open circuit in steady state
2006 2006
Natural Response of an RC Circuit Solving for the Voltage (t ≥ 0)

• Consider the following circuit, for which the switch is • For t > 0, the circuit reduces to
closed for t < 0, and then opened at t = 0: i
Ro +
t=0 Vo +
− C v R
Ro
+
Vo +
− R –
C v
– • Applying KCL to the RC circuit:
Notation:
0– is used to denote the time just prior to switching
0+ is used to denote the time immediately after switching
• The voltage on the capacitor at t = 0– is Vo
• Solution:
v(t ) = v(0)e−t / RC
2006 2006
Solving for the Current (t > 0) Solving for Power and Energy Delivered (t > 0)
i i
Ro + Ro +
Vo +
− C v R v(t ) = Voe−t / RC Vo +
− C v R v(t ) = Vo e − t / RC
– –
v 2 Vo2 −2 t / RC
• Note that the current changes abruptly: p= = e
i (0− ) = 0 R R
t t
v Vo −t / RC Vo2 −2 x / RC
for t > 0, i (t ) = = e w = ∫ p( x )dx = ∫ e dx
R R 0 0
R
V 1
⇒ i (0+ ) = o = CVo2 (1 − e −2 t / RC )
R 2
2006 2006
Natural Response of an RL Circuit Solving for the Current (t ≥ 0)

• Consider the following circuit, for which the switch is • For t > 0, the circuit reduces to
closed for t < 0, and then opened at t = 0:
i +
t=0 Io Ro L R v
i +
–
Io Ro L R v
– • Applying KVL to the LR circuit:
Notation: • v(t)=i(t)R
0– is used to denote the time just prior to switching • At t=0+, i=I0,
0+ is used to denote the time immediately after switching di (t )
• At arbitrary t>0, i=i(t) and v(t ) = -L
• t<0 the entire system is at steady-state; and the inductor dt
is like short circuit
• The current flowing in the inductor at t = 0– is Io and V
across is 0. • Solution: i (t ) = i (0)e − ( R / L ) t = I0e-(R/L)t
2006 2006
Solving for the Voltage (t > 0) Solving for Power and Energy Delivered (t > 0)
−( R / L )t i (t ) = I o e − ( R / L )t
i(t ) = I oe
+
+
Io Ro L R v
Io Ro L R v
–
–
p = i 2 R = I o2 Re −2 ( R / L ) t
• Note that the voltage changes abruptly: t t
−
v (0 ) = 0 w = ∫ p ( x)dx = ∫ I o2 Re − 2 ( R / L ) x dx
−( R / L ) t 0 0
for t > 0, v(t ) = iR = I o Re
1 2
⇒ v(0 ) = I0R
+ =
2
(
LI o 1 − e − 2 ( R / L )t )
2006 2006
Natural Response Summary Digital Signals

RL Circuit RC Circuit We compute with pulses.
voltage
i + We send beautiful pulses in:
L R C v R
time
–
But we receive lousy-looking
voltage
• Inductor current cannot • Capacitor voltage cannot pulses at the output:
change instantaneously change instantaneously
i ( 0 − ) = i (0 + ) v (0 − ) = v (0 + ) time
Capacitor charging effects are responsible!

i (t ) = i (0)e −t /τ v(t ) = v(0)e −t /τ
L • Every node in a real circuit has capacitance; it’s the charging
• time constant τ= • time constant τ = RC of these capacitances that limits circuit performance (speed)
R
2006 2006
Circuit Model for a Logic Gate Pulse Distortion
• Recall (from Lecture 1) that electronic building blocks R
The input voltage pulse
referred to as “logic gates” are used to implement width must be large
+
logical functions (NAND, NOR, NOT) in digital ICs + enough; otherwise the
– Any logical function can be implemented using these gates. Vin(t) C Vout output pulse is distorted.
– (We need to wait for the output to
• A logic gate can be modeled as a simple RC circuit: –
reach a recognizable logic level,
before changing the input again.)
R
Pulse width = 0.1RC Pulse width = RC Pulse width = 10RC
+ 6 6 6
Vin(t) + C Vout
5 5 5
4
− 4 4
Vout
Vout
Vout
3 3 3
– 2 2 2
1 1 1
0 0 0
switches between “low” (logic 0) 0 1 2 3 4 5 0 1 2 3 4 5 0 5 10 15 20 25
and “high” (logic 1) voltage states Time Time Time
2006 2006
Example First Order Circuits: Forced Response

Suppose a voltage pulse of width R +
vr(t)
- iL(t)
5 µs and height 4 V is applied to the Vin Vout ic(t)
+
input of this circuit beginning at t = 0: C R
R = 2.5 kΩ + +
vs(t) C vc(t) is(t) R L vL(t)
τ = RC = 2.5 µs C = 1 nF -
-
• First, Vout will increase exponentially toward 4 V. -
• When Vin goes back down, Vout will decrease exponentially
back down to 0 V. KVL around the loop: KCL at the node:
t
vr(t) + vc(t) = vs(t) v(t ) 1
What is the peak value of Vout? + ∫ v( x)dx = is (t )
R L −∞
The output increases for 5 µs, or 2 time constants.
dvc (t )
RC + vc (t ) = vs (t ) L diL (t )
It reaches 1-e-2 or 86% of the final value. dt + iL (t ) = is (t )
R dt
0.86 x 4 V = 3.44 V is the peak value
2006 2006
Complete Solution The Time Constant
• Voltages and currents in a 1st order circuit satisfy a • The complementary solution for any 1st
differential equation of the form
dx(t ) order circuit is
x(t ) + τ = f (t )
dt xc (t ) = Ke − t /τ
– f(t) is called the forcing function.
• The complete solution is the sum of particular solution
(forced response) and complementary solution (natural
response). • For an RC circuit, τ = RC
x(t ) = x p (t ) + xc (t )
• For an RL circuit, τ = L/R
– Particular solution satisfies the forcing function
– Complementary solution is used to satisfy the initial conditions.
– The initial conditions determine the value of K.
dxc (t ) Homogeneous
dx p (t )
xc (t ) + τ =0 equation
x p (t ) + τ = f (t ) dt
dt xc (t ) = Ke − t /τ
2006 2006
What Does Xc(t) Look Like? The Particular Solution

• The particular solution xp(t) is usually a
xc (t ) = e− t /τ τ = 10-4 weighted sum of f(t) and its first derivative.
• If f(t) is constant, then xp(t) is constant.
• τ is the amount of time necessary
for an exponential to decay to • If f(t) is sinusoidal, then xp(t) is sinusoidal.
36.7% of its initial value.
• -1/τ is the initial slope of an
exponential with an initial value of
1.
2006 2006
The Particular Solution: F(t) Constant The Particular Solution: F(t) Sinusoid
dxP (t ) dxP (t )
xP (t ) + τ =F xP (t ) + τ = FA sin( wt ) + FB cos( wt )
dt dt
Guess a solution Guess a solution
xP (t ) = A + Bt d ( A + Bt ) xP (t ) = A sin( wt ) + B cos( wt )
( A + Bt ) + τ =F
dt
Equation holds for all time d ( A sin( wt ) + B cos( wt ))
( A sin( wt ) + B cos( wt )) + τ = FA sin( wt ) + FB cos( wt )
( A + Bt ) + τB = F dt
and time variations are
independent and thus each
( A + τB − F ) + ( B )t = 0
( A − τB − FA ) sin( wt ) + ( B + τA − FB ) cos( wt ) = 0
time variation coefficient is
individually zero Equation holds for all time
( A − τB − FA ) = 0
independent and thus each ( B + τA − FB ) = 0
( B) = 0 ( A + τB − F ) = 0
A= F FA + τFB τFA − FB
B=0 individually zero A= B=−
τ 2 +1 τ 2 +1
2006 2006
The Particular Solution: F(t) Exp. The Total Solution: F(t) Sinusoid
dxP (t )
dxP (t ) xP (t ) + τ = FA sin( wt ) + FB cos( wt )
xP (t ) + τ = F1e −αt + F2 dt
dt
Guess a solution xP (t ) = A sin( wt ) + B cos( wt ) FA + τFB
B=−
τFA − FB
A=
xP (t ) = A + Be −αt
d ( A + Be −αt ) τ 2 +1 τ 2 +1
( A + Be −αt ) + τ = F1e −αt + F2 −t
τ
dt xC (t ) = Ke
Equation holds for all time
( A + Be −αt ) − ατBe −αt = F1e −αt + F2 xT (t ) = A sin( wt ) + B cos( wt ) + Ke
−t
τ
independent and thus each ( A − F2 ) + ( B − ατ − F1 )e −αt = 0 Only K is unknown and
is determined by the
individually zero
initial condition at t =0 Example: xT(t=0) = VC(t=0)
( A − F2 ) = 0 −0
τ
( B − ατ − F1 ) = 0 xT (0) = A sin(0) + B cos(0) + Ke = VC (t = 0)
B = ατ + F1 A = F2
xT (0) = B + K = VC (t = 0) K = VC (t = 0) − B
2006 2006
Example 2nd Order Circuits
• Any circuit with a single capacitor, a single
R t=0 inductor, an arbitrary number of sources,
+ +
Vs − C vc
and an arbitrary number of resistors is a
– circuit of order 2.
• Any voltage or current in such a circuit is
the solution to a 2nd order differential
• Given vc(0-)=1, Vs=2 cos(ωt), ω=200. equation.
• Find i(t), vc(t)=?
2006 2006
A 2nd Order RLC Circuit The Differential Equation

i (t)
i (t) + vr(t) -
R R +
+ +
vs(t) C vs(t) C vc(t)
- - -
- vl(t) +
L
KVL around the loop: L
• Application: Filters vr(t) + vc(t) + vl(t) = vs(t)
– A bandpass filter such as the IF amp for 1
t
di (t )
the AM radio. Ri (t ) + ∫ i ( x)dx + L = vs (t )
C −∞ dt
– A lowpass filter with a sharper cutoff R di (t ) 1 d 2i (t ) 1 dvs (t )
+ i (t ) + =
than can be obtained with an RC circuit. L dt LC dt 2 L dt
2006 2006
The Differential Equation The Particular Solution
The voltage and current in a second order circuit is • The particular solution xp(t) is usually a
the solution to a differential equation of the weighted sum of f(t) and its first and
following form: second derivatives.
d 2 x(t ) dx(t ) • If f(t) is constant, then xp(t) is constant.
2
+ 2α + ω02 x(t ) = f (t )
dt dt • If f(t) is sinusoidal, then xp(t) is sinusoidal.
x(t ) = x p (t ) + xc (t )
Xp(t) is the particular solution (forced response)
and Xc(t) is the complementary solution (natural
response).
2006 2006
The Complementary Solution Characteristic Equation

The complementary solution has the following • To find the complementary solution, we
form: st
xc (t ) = Ke need to solve the characteristic equation:
K is a constant determined by initial conditions.
s 2 + 2ζω0 s + ω02 = 0
s is a constant determined by the coefficients of α = ζω0
the differential equation. • The characteristic equation has two roots-
d 2 Ke st dKe st call them s1 and s2.
+ 2α + ω02 Ke st = 0
dt 2 dt
2 st st 2 st xc (t ) = K1e s1t + K 2 e s2t
s Ke + 2α sKe + ω Ke = 0 0
s1 = −ζω0 + ω0 ζ 2 − 1
s 2 + 2α s + ω02 = 0
s2 = −ζω0 − ω0 ζ 2 − 1
2006 2006
Damping Ratio and Natural Frequency Overdamped : Real Unequal Roots
α s1 = −ζω0 + ω0 ζ 2 − 1 • If ζ > 1, s1 and s2 are real and not equal.
ζ =
ω0  −ςω +ω ς 2 −1  t
0 0
 −ςω −ω ς 2 −1  t
0 0
   
damping ratio s2 = −ζω0 − ω0 ζ 2 − 1 ic (t ) = K 1e + K 2e
• The damping ratio determines what type of 1 0.8
0.8 0.6
solution we will get: 0.6
i(t)
0.4
i(t)
– Exponentially decreasing (ζ >1) 0.4
0.2
0.2
– Exponentially decreasing sinusoid (ζ < 1) 0
0
-1.00E-06
-1.00E-06 -0.2
• The natural frequency is ω0 t t

– It determines how fast sinusoids wiggle.
2006 2006
Underdamped: Complex Roots Critically damped: Real Equal Roots

• If ζ < 1, s1 and s2 are complex. • If ζ = 1, s1 and s2 are real and equal.
• Define the following constants:
2
xc (t ) = K1e −ςω0t + K 2te −ςω0t
α = ζω0 ω d = ω0 1 − ζ
xc (t ) = e −α t ( A1 cos ωd t + A2 sin ωd t )
1
Note: The
0.8
0.6
degeneracy of the
0.4
0.2
roots results in the
i(t)
-1.00E-05
0
-0.2 1.00E-05 3.00E-05
extra factor of ‘t’
-0.4
-0.6
-0.8
-1
t
2006 2006
Example Example
For the example, what are ζ and ω0? • ζ = 0.011
• ω0 = 2π455000
i (t) d 2i (t ) R di (t ) 1 1 dvs (t ) • Is this system over damped, under
+ + i (t ) =
dt 2
L dt LC L dt damped, or critically damped?
10Ω
+ • What will the current look like?
769pF d 2 xc (t ) dx (t )
- 2
+ 2ζω0 c + ω02 xc (t ) = 0 1
dt dt 0.8
159µH 0.6
0.4
1 R R C 0.2
i(t)
2
ω =
0 , 2ζω0 = , ζ = -1.00E-05
0
-0.2 1.00E-05 3.00E-05
LC L 2 L -0.4
-0.6
-0.8
-1
t
2006 2006
Slightly Different Example Types of Circuit Excitation

• Increase the resistor to 1kΩ
Linear Time- Linear Time-
• What are ζ and ω0?
Invariant Invariant
i (t) Circuit
1 Circuit
0.8
1kΩ 0.6
Steady-State Excitation OR
i(t)
+ 0.4
vs(t) 769pF 0.2
(DC Steady-State)
- 0 Digital Linear Time-
159µH -1.00E-06
Pulse
Linear Time- Invariant
t Source
Invariant Circuit
ζ = 2.2 Circuit
ω0 = 2π455000 Sinusoidal (Single- Transient Excitation
Frequency) Excitation
AC Steady-State
2006 2006
Why is Single-Frequency Excitation Important? Representing a Square Wave as a Sum of Sinusoids
a b
• Some circuits are driven by a single-frequency
signal(V)
signal(V)
sinusoidal source.
Signal
Signal
• Some circuits are driven by sinusoidal sources
whose frequency changes slowly over time.
• You can express any periodic electrical signal as T i me (ms)
c d
a sum of single-frequency sinusoids – so you
Relative Amplitude
can analyze the response of the (linear, time-
Signal (V)
invariant) circuit to each individual frequency
component and then sum the responses to get
the total response. Frequency (Hz)
(a)Square wave with 1-second period. (b) Fundamental component

• This is known as Fourier Transform and is (dotted) with 1-second period, third-harmonic (solid black) with1/3-second
tremendously important to all kinds of engineering period, and their sum (blue). (c) Sum of first ten components. (d)
disciplines! Spectrum with 20 terms.
2006 2006
Steady-State Sinusoidal Analysis Steady-State Sinusoidal Analysis

• Also known as AC steady-state • Also known as AC steady-state
• Any steady state voltage or current in a linear circuit with • Any steady state voltage or current in a linear circuit with
a sinusoidal source is a sinusoid. a sinusoidal source is a sinusoid.
– This is a consequence of the nature of particular solutions for – This is a consequence of the nature of particular solutions for
sinusoidal forcing functions. sinusoidal forcing functions.
• All AC steady state voltages and currents have the same • All AC steady state voltages and currents have the same
frequency as the source. frequency as the source.
• In order to find a steady state voltage or current, all we • In order to find a steady state voltage or current, all we
need to know is its magnitude and its phase relative to need to know is its magnitude and its phase relative to
the source the source
– We already know its frequency. – We already know its frequency.
• Usually, an AC steady state voltage or current is given • Usually, an AC steady state voltage or current is given
by the particular solution to a differential equation. by the particular solution to a differential equation.
2006 2006
Chapter 5 (Lec. 5.3-6.2) Example 1: 2nd Order RLC Circuit
• OUTLINE t=0
– Phasors as notation for Sinusoids
R
– Arithmetic with Complex Numbers +
Vs C L
– Complex impedances -
– Circuit analysis using complex impdenaces
– Dervative/Integration as multiplication/division
– Phasor Relationship for Circuit Elements
• Reading
– Chap 5
– Appendix A
2006 2006
Example 2: 2nd Order RLC Circuit Why is Single-Frequency Excitation Important?

• Some circuits are driven by a single-frequency
t=0
sinusoidal source.
R • Some circuits are driven by sinusoidal sources
+
Vs C L whose frequency changes slowly over time.
-
• You can express any periodic electrical signal as
a sum of single-frequency sinusoids – so you
can analyze the response of the (linear, time-
invariant) circuit to each individual frequency
component and then sum the responses to get
the total response.
• This is known as Fourier Transform and is
tremendously important to all kinds of engineering
disciplines!
2006 2006
Representing a Square Wave as a Sum of Sinusoids Steady-State Sinusoidal Analysis
a b
• Also known as AC steady-state
signal(V)
signal(V)
• Any steady state voltage or current in a linear circuit with
Signal
Signal
a sinusoidal source is a sinusoid.
– This is a consequence of the nature of particular solutions for
sinusoidal forcing functions.
T i me (ms)
• All AC steady state voltages and currents have the same
c d
frequency as the source.
Relative Amplitude
• In order to find a steady state voltage or current, all we
Signal (V)
need to know is its magnitude and its phase relative to

the source
– We already know its frequency.
Frequency (Hz)
(a)Square wave with 1-second period. (b) Fundamental component • Usually, an AC steady state voltage or current is given
(dotted) with 1-second period, third-harmonic (solid black) with1/3-second by the particular solution to a differential equation.
period, and their sum (blue). (c) Sum of first ten components. (d)
Spectrum with 20 terms.
2006 2006
Sinusoidal Sources Create Too Much Algebra Complex Numbers (1)

dxP (t )
imaginary • x is the real part
xP (t ) + τ = FA sin( wt ) + FB cos( wt ) axis
dt
y
• y is the imaginary part
Guess a solution Two terms to be general j = (−1)
Dervatives • z is the magnitude
z
xP (t ) = A sin( wt ) + B cos( wt )
Addition θ • θ is the phase
d ( A sin( wt ) + B cos( wt )) real
( A sin( wt ) + B cos( wt )) + τ = FA sin( wt ) + FB cos( wt )
dt
axis x = z cos θ y = z sin θ
( A − τB − FA ) sin( wt ) + ( B + τA − FB ) cos( wt ) = 0 x
• Rectangular Coordinates y
Equation holds for all time ( A − τB − FA ) = 0 z = x2 + y2 θ = tan −1
Z = x + jy x
and time variations are ( B + τA − FB ) = 0
• Polar Coordinates: Z = z (cos θ + j sin θ )
independent and thus each F + τF
A = A2 B
τFA − FB
time variation coefficient is B=− Z=z∠θ
τ +1 τ 2 +1 1 = 1e j 0 = 1∠0°
individually zero • Exponential Form:
π
Phasors (vectors that rotate in the complex Z = Z e = zejθ jθ
j = 1e
j
2
= 1∠90°
plane) are a clever alternative.
2006 2006
Complex Numbers (2) Arithmetic With Complex Numbers
• To compute phasor voltages and currents, we
e jθ + e − jθ need to be able to perform computation with
Euler’s Identities cos θ =
2 complex numbers.
e − e − jθ
jθ
– Addition
sin θ =
2j
– Subtraction
e jθ = cos θ + j sin θ – Multiplication
e jθ = cos 2 θ + sin 2 θ = 1 – Division
• (And later use multiplication by jω to replace
Exponential Form of a complex number – Diffrentiation
Z = Z e jθ = ze jθ = z∠θ – Integration
2006 2006
Addition Addition
• Addition is most easily performed in
rectangular coordinates:
A = x + jy Imaginary
B = z + jw Axis
A+B
A + B = (x + z) + j(y + w)
B A
Real
Axis
2006 2006
Subtraction Subtraction
• Subtraction is most easily performed in
rectangular coordinates:
A = x + jy Imaginary
Axis
B = z + jw
A - B = (x - z) + j(y - w) B A
Real
Axis
A-B
2006 2006
Multiplication Multiplication
• Multiplication is most easily performed in
polar coordinates:
A = AM ∠ θ Imaginary
Axis
B = BM ∠ φ A×B
B
A × B = (AM × BM) ∠ (θ + φ) A
Real
Axis
2006 2006
Division Division
• Division is most easily performed in polar
coordinates:
A = AM ∠ θ Imaginary
Axis
B = BM ∠ φ
B
A / B = (AM / BM) ∠ (θ − φ) A
Real
Axis
A/B
2006 2006
Arithmetic Operations of Complex Numbers Phasors

• Add and Subtract: it is easiest to do this in rectangular • Assuming a source voltage is a sinusoid time-
format varying function
– Add/subtract the real and imaginary parts separately
• Multiply and Divide: it is easiest to do this in
v(t) = V cos (ωt + θ)
exponential/polar format • We can write:
– Multiply (divide) the magnitudes v(t ) = V cos(ωt + θ ) = V Re e j (ωt +θ )  = Re Ve j (ωt +θ ) 
– Add (subtract) the phases
jθ1 Define Phasor as Ve jθ = V ∠θ
Z1 = z1e = z1∠θ1 = z1 cos θ1 + jz1 sin θ1
Z 2 = z2 e jθ 2
= z2∠θ 2 = z2 cos θ 2 + jz2 sin θ 2
• Similarly, if the function is v(t) = V sin (ωt + θ)
Z1 + Z 2 = ( z1 cos θ1 + z2 cos θ 2 ) + j ( z1 sin θ1 + z2 sin θ 2 ) π  j (ωt +θ − π2 ) 
v(t ) = V sin(ωt + θ ) = V cos(ωt + θ − ) = Re Ve 
2  
Z1 − Z 2 = ( z1 cos θ1 − z2 cos θ 2 ) + j ( z1 sin θ1 − z2 sin θ 2 )
Z1 × Z 2 = ( z1 × z2 )e j (θ1 +θ2 ) = ( z1 × z2 )∠(θ1 + θ 2 ) Phasor = V ∠ ( )
θ−
π
2
Z1 / Z 2 = ( z1 / z2 )e j (θ1 −θ2 ) = ( z1 / z2 )∠(θ1 − θ 2 )
2006 2006
Phasor: Rotating Complex Vector Complex Exponentials
• We represent a real-valued sinusoid as the real
{ } (
v(t ) = V cos(ωt + φ ) = Re Ve jφ e jwt = Re V e jωt ) part of a complex exponential after multiplying
by e jω.t
Imaginary • Complex exponentials
Axis Rotates at uniform – provide the link between time functions and phasors.
– Allow dervatives and integrals to be replaced by
angular velocity ωt multiplying or dividing by jω
– make solving for AC steady state simple algebra with
complex numbers.
V
Real • Phasors allow us to express current-voltage
ωt+φ
cos(ω φ)
Axis relationships for inductors and capacitors much
like we express the current-voltage relationship
The head start angle is φ. for a resistor.
2006 2006
I-V Relationship for a Capacitor Capacitor Impedance (1)
i(t) + dv(t )
i (t ) = C
C v(t dt
i(t) +
dv(t ) -)
C v(t) i (t ) = C
dt v(t ) = V cos(ωt + θ ) =
V j (ωt +θ ) − j (ωt +θ )
e +e 
- 2
dv(t ) CV d j (ωt +θ ) − j (ωt +θ ) CV
i (t ) = C = e +e  = jω e j (ωt +θ ) − e − j (ωt +θ ) 
dt 2 dt  2
−ωCV j (ωt +θ ) − j (ωt +θ ) π
Suppose that v(t) is a sinusoid: = e −e  = −ωCV sin(ωt + θ ) = ωCV cos(ωt + θ + )
2j 2
v(t) = Re{VM ej(ωt+θ)} V
Zc = =
V ∠θ
=
V π
∠(θ − θ − ) =
1 π
∠(− ) = − j
1
=
1
I  π  ω CV 2 ω C 2 ω C j ω C
Find i(t). I ∠ θ + 
 2
2006 2006
Capacitor Impedance (2) Example
v(t) = 120V cos(377t + 30°)
i(t) + dv(t )
i (t ) = C C = 2µF
C v(t dt
-)
Phasor definition
• What is V?
v(t ) = V cos(ωt + θ ) = Re Ve j (ωt +θ )
 ⇒ V = V ∠θ • What is I?
dv(t )  de j (ωt +θ )  • What is i(t)?
i (t ) = C = Re CV  = Re  jωCVe j (ωt +θ )  ⇒ I = I ∠θ
dt  dt 
V V ∠θ V 1
Zc = = = ∠(θ − θ ) =
I I ∠θ jωCV jωC
2006 2006
Computing the Current Inductor Impedance
i(t) +
di (t )
Note: The differentiation and integration L v(t) v(t ) = L
dt
operations become algebraic operations -
d 1
dt
⇒ jω ∫ dt ⇒
jω V = jωL I
2006 2006
Example Phase
Voltage
i(t) = 1µA cos(2π 9.15 107t + 30°) 7 cos(ωt ) = 7∠0° inductor current
L = 1µH π  π
7 sin(ωt ) = 7 cos(ωt − ) = 7∠  − 
8 2  2
6
• What is I? 4
• What is V? 2
0
• What is v(t)?
-2 0 0.01 0.02 0.03 0.04 0.05
-4
-6
-8 capacitor current
π  π
−7 sin(ωt ) = 7 cos(ωt + ) = 7∠  + 
2  2
2006 2006
Phasor Diagrams Impedance

• A phasor diagram is just a graph of • AC steady-state analysis using phasors
several phasors on the complex plane allows us to express the relationship
(using real and imaginary axes). between current and voltage using a
• A phasor diagram helps to visualize the formula that looks likes Ohm’s law:
relationships between currents and V=IZ
voltages. • Z is called impedance.
• Capacitor: I leads V by 90o
• Inductor: V leads I by 90o
2006 2006
Some Thoughts on Impedance Example: Single Loop Circuit
• Impedance depends on the frequency ω.
20kΩ +
• Impedance is (often) a complex number. +
VC
10V ∠ 0° 1µF
• Impedance allows us to use the same - -
solution techniques for AC steady state as
we use for DC steady state. f=60 Hz, VC=?
How do we find VC?
First compute impedances for resistor and capacitor:
ZR = R= 20kΩ = 20kΩ ∠ 0°
ZC = 1/j (2πf x 1µF) = 2.65kΩ ∠ -90°
2006 2006
Impedance Example What happens when ω changes?

20kΩ ∠ 0°
+ 20kΩ +
+ +
10V ∠ 0° VC 2.65kΩ ∠ -90° 10V ∠ 0° 1µF VC
- - - -
Now use the voltage divider to find VC: ω = 10

Find VC
 2.65kΩ∠ - 90° 
VC = 10V ∠0° 
 2.65kΩ∠ - 90° + 20kΩ∠0° 
VC = 1.31V ∠ - 82.4°
2006 2006
Circuit Analysis Using Complex Impedances Steady-State AC Analysis
• Suitable for AC steady state.
• KVL +
v1 (t ) + v2 (t ) + v3 (t ) = 0 0.1µF
5mA ∠ 0° V
V1 cos (ωt + θ1 ) + V2 cos (ωt + θ 2 ) + V3 cos (ωt + θ3 ) = 0 1kΩ
-
Re V1e j (ωt +θ1 ) + V2 e j (ωt +θ2 ) + V3e j (ωt +θ3 )  = 0
Find v(t) for ω=2π 3000
Phasor Form KVL
V1e j (θ1 ) + V2e j (θ2 ) + V3e j (θ3 ) = 0
V1 + V2 + V3 = 0 +
• Phasor Form KCL I1 + I 2 + I 3 = 0
5mA ∠ 0° V -j530kΩ
• Use complex impedances for inductors and capacitors and
follow same analysis as in chap 2. 1kΩ
-
2006 2006
Find the Equivalent Impedance Change the Frequency

+
+
0.1µF
5mA ∠ 0° V
5mA ∠ 0° Zeq V 1kΩ
-
-
Find v(t) for ω=2π 455000
1000(− j 530 ) 10 ∠0° × 530∠ − 90°
3
Z eq = =
1000 − j 530 1132∠ − 27.9°
+
Z eq = 468.2Ω∠ − 62.1° -j3.5Ω
5mA ∠ 0° V
V = IZ eq = 5mA∠0° × 468.2Ω∠ − 62.1°
1kΩ
V = 2.34V∠ − 62.1° -
v(t ) = 2.34V cos(2π 3000t − 62.1°)
2006 2006
Find an Equivalent Impedance Series Impedance
+
Z1
5mA ∠ 0° Zeq V
Z2 Zeq
- Z3
1000(− j 3.5) 10 3 ∠0° × 3.5∠ − 90°
Z eq = =
1000 − j 3.5 1000∠ − 0.2° Zeq = Z1 + Z2 + Z3
Z eq = 3.5Ω∠ − 89.8° For example:
V = IZ eq = 5mA∠0° × 3.5Ω∠ − 89.8°
V = 17.5mV∠ − 89.8° C1 C2
L1 L2
v(t ) = 17.5mV cos(2π 455000t − 89.8°) 1 1
Zeq = jω(L1+L2) Z eq = +
jωC1 jωC2
2006 2006
Parallel Impedance Steady-State AC Node-Voltage Analysis

C
Z1 Z2 Z3 Zeq I0sin(ωt) I1cos(ωt)

R L
1/Zeq = 1/Z1 + 1/Z2 + 1/Z3

For example:
• Nodal analysis or mesh?
• What are the nodes (or meshes)?
L1 L2 C1 C2 • What happens if the sources are at different
frequencies?
L1 L2 1
Z eq = jω Z eq =
( L1 + L2 ) jω (C1 + C2 )
2006 2006
Thevenin Equivalent
Resistor I-V relationship ZTH
vR = iRR ………….VR = IRR where R is the resistance in ohms, 10V ∠ 0° 20kΩ
VR = phasor voltage, IR = phasor current + + +
(boldface indicates complex quantity) 1µF VC VTH
Capacitor I-V relationship - - -
iC = CdvC/dt ...............Phasor current IC = phasor voltage VC / f=60 Hz
capacitive impedance ZC: IC = VC/ZC
where ZC = 1/jωC , j = (-1)1/2 and boldface ZR = R= 20kΩ = 20kΩ ∠ 0°
indicates complex quantity
ZC = 1/j (2πf x 1µF) = 2.65kΩ ∠ -90°
Inductor I-V relationship
vL = LdiL/dt ...............Phasor voltage VL = phasor current IL/  2.65kΩ∠ - 90° 
VTH = VOC = 10V ∠0°  = 1.31∠ − 82.4
inductive impedance ZL VL = ILZL  2.65 kΩ ∠ - 90 ° + 20 k Ω∠0° 
where ZL = jωL, j = (-1)1/2 and boldface
indicates complex quantity  20kΩ∠0° ⋅ 2.65kΩ∠ - 90° 
ZTH = Z R || Z C = °  = 2.62∠ − 82.4
 2.65kΩ∠ - 90° + 20kΩ∠0° 
2006 2006
Root Mean Square (rms) Values Power: Instantaneous and Time-Average

• rms valued defined as For a Resistor
1 2
T
• The instantaneous power is v(t ) 2
p(t ) = v(t )i (t ) =
T ∫o
vRMS = v (t )dt T = period R
• Assuming a sinusoid gives • The time-average power is

T T T
1
T
1 1 v(t ) 2 1 1 v2
vRMS =
T ∫o
2
vm cos 2 (ωt + θ )dt PAVE = ∫
T 0
p (t )dt = ∫
T 0 R
dt = [ ∫ v(t ) 2 dt ] = rms
R T 0 R
For an Impedance v(t )i (t
• Using an identity gives • The instantaneous power is

2 T
p(t ) = v(t )i (t )
v
vRMS = m ∫ [1 + cos(2ωt + 2θ )]dt
2T o • The time-average power isT T
1 1
∫ p(t )dt = T ∫ v(t )i(t )dt = Re{V
*
• Evaluating at limits gives PAVE = rms ⋅ I rms }
T 0 0
2 v • The reactive power at 2ω is
vRMS
v
= m [T +
1
sin(2ωT + 2θ ) −
1
sin(2θ )] vRMS = m
2T 2ω 2w 2 Q = Im{Vrms ⋅ I *rms } 2
PAVE + Q 2 = (Vrms ⋅ I rms ) 2
2006 2006
Maximum Average Power Transfer Chapter 6 (Lec. 6.3-8.2)
ZTH • OUTLINE
– Frequency Response for Characterization
+
VTH ZLOAD – Asymptotic Frequency Behavior
-
– Log magnitude vs log frequency plot
– Phase vs log frequency plot
• Maximum time average power occurs when
– dB scale
Z LOAD = Z*TH
– Transfer function example
• This presents a resistive impedance to the source
Z total = ZTH + Z*TH • Reading
• Power transferred is – Chap 6.1-6.4
* 2
PAVE = Re{VI*} = Re{V
V
} = 12
V rms – Reader Chapter
2R R
2006 2006
Power: Instantaneous and Time-Average Maximum Average Power Transfer

For a Resistor
• The instantaneous power is v(t ) 2 ZTH
p(t ) = v(t )i (t ) =
R +
• The time-average power is VTH ZLOAD
T T T
-
1 1 v(t ) 2 1 1 v2
PAVE = ∫
T 0
p (t )dt = ∫
T 0 R
dt = [ ∫ v(t ) 2 dt ] = rms
R T 0 R
For an Impedance v(t )i (t
• The instantaneous power is • Maximum time average power occurs when

p(t ) = v(t )i (t ) Z LOAD = Z*TH
• The time-average power isT • This presents a resistive impedance to the source
T
1 1 Z total = ZTH + Z*TH
∫0 p(t )dt = T ∫0 v(t )i(t )dt = Re{Vrms ⋅ I rms }
*
PAVE =
T
• The reactive power at 2ω is • Power transferred is
V* V2
Q = Im{Vrms ⋅ I *rms } 2
PAVE + Q 2 = (Vrms ⋅ I rms ) 2 PAVE = Re{VI*} = Re{V } = 12 rms
2R R
2006 2006
Bel and Decibel (dB) Logarithmic Measure for Power
• A bel (symbol B) is a unit of measure of ratios of power • To express a power in terms of decibels, one starts by
levels, i.e. relative power levels. choosing a reference power, Preference, and writing
– The name was coined in the early 20th century in honor of Power P in decibels = 10 log10(P/Preference)
Alexander Graham Bell, a telecommunications pioneer.
• Exercise:
– The bel is a logarithmic measure. The number of bels for a given
ratio of power levels is calculated by taking the logarithm, to the – Express a power of 50 mW in decibels relative to 1 watt.
base 10, of the ratio. – P (dB) =10 log10 (50 x 10-3) = - 13 dB
– one bel corresponds to a ratio of 10:1. • Exercise:
– B = log10(P1/P2) where P1 and P2 are power levels. – Express a power of 50 mW in decibels relative to 1 mW.
• The bel is too large for everyday use, so the decibel – P (dB) =10 log10 (50) = 17 dB.
(dB), equal to 0.1B, is more commonly used. • dBm to express absolute values of power relative to a
– 1dB = 10 log10(P1/P2) milliwatt.
• dB are used to measure – dBm = 10 log10 (power in milliwatts / 1 milliwatt)
– Electric power, Gain or loss of amplifiers, Insertion loss of filters. – 100 mW = 20 dBm
– 10 mW = 10 dBm
2006 2006
Logarithmic Measures for Voltage or Current Logarithmic Measures for Voltage or Current
From the expression for power ratios in decibels, we can Note that the voltage and current expressions are just
readily derive the corresponding expressions for voltage like the power expression except that they have 20 as
or current ratios. the multiplier instead of 10 because power is
proportional to the square of the voltage or current.
Suppose that the voltage V (or current I) appears across
(or flows in) a resistor whose resistance is R. The
corresponding power dissipated, P, is V2/R (or I2R). We Exercise: How many decibels larger is the voltage of a
can similarly relate the reference voltage or current to the 9-volt transistor battery than that of a 1.5-volt AA
reference power, as battery? Let Vreference = 1.5. The ratio in decibels is
Preference = (Vreference)2/R or Preference= (Ireference)2R. 20 log10(9/1.5) = 20 log10(6) = 16 dB.
Hence,
Voltage, V in decibels = 20log10(V/Vreference)
Current, I, in decibels = 20log10(I/Ireference)
2006 2006
Logarithmic Measures for Voltage or Current Bode Plot
• Plot of magnitude of transfer function vs.

The gain produced by an amplifier or the loss of a filter
is often specified in decibels. frequency
– Both x and y scale are in log scale
The input voltage (current, or power) is taken as the
– Y scale in dB
reference value of voltage (current, or power) in the
decibel defining expression: • Log Frequency Scale
– Decade Ratio of higher to lower frequency
Voltage gain in dB = 20 log10(Voutput/Vinput)
Current gain in dB = 20log10(Ioutput/Iinput = 10
Power gain in dB = 10log10(Poutput/Pinput) – Octave Ratio of higher to lower frequency
=2
Example: The voltage gain of an amplifier whose input
is 0.2 mV and whose output is 0.5 V is
20log10(0.5/0.2x10-3) = 68 dB.
2006 2006
Frequency Response Example Circuit

R2
• The shape of the frequency response of the complex
+
+
ratio of phasors VOUT/VIN is a convenient means of +
C
VIN AVT
+
classifying a circuit behavior and identifying key R1 VT −
VOUT
parameters.
VOUT A = 100
Break point TransferFunction =
VOUT VOUT VIN
Break point R1 = 100,000 Ohms
VIN Gain VIN Gain
VOUT AZ c R2 = 1000 Ohms
=
Low Pass VIN Z R + Zc
High Pass C = 10 uF
Frequency VOUT A(1 / jwC ) A
Frequency = =
VIN R2 + 1 / jωC ) (1 + jωR2C )
FYI: These are log ratio vs log frequency plots

2006 2006
Break Point Values Asymptotic Behavior of Transfer Functions
• When dealing with resonant circuits it is convenient
to refer to the frequency difference between points at Ratio of polynomials form
which the power from the circuit is half that at the
VOUT A + jωB
peak of resonance. =
VIN C + j ωD
• Such frequencies are known as “half-power Special cases
frequencies”, and the power output there referred to Low frequency asymptotic limit
the peak power (at the resonant frequency) is When A = 0 => ω1
VOUT A + jωB A
• 10log10(Phalf-power/Presonance) = 10log10(1/2) = -3 dB. = =
VIN C + jωD ω →0 C When C = 0 => ω-1
High frequency asymptotic limit
VOUT A + jwB jω B B When B = 0 => ω-1
= = =
VIN C + jω D ω → ∞ jω D D When D = 0 => ω+1
2006 2006
Break Points of Transfer Functions Log magnitude versus log frequency plot
Ratio of polynomials form
Magnitude
VOUT A + jωB
=
VIN C + j ωD
Numerator Break Point (slope change upward) 1000
ω1
Occurs when A = |jωB| => ωz = A/B 100
100ω0
Denominator Break Point (slope change downward) 10 ω0
Occurs when C = |jωD| => ωp = C/D 1
1 10 100 1000 Radian
FYI: z is for zero of the numerator and p is for zero of the 0.1 Frequency
denominator giving one over zero or a pole. Filter design
consists of specifying frequency locations of zeros and poles. ω-1
2006 2006
Phase versus log frequency Example: Circuit in Slide #3 Magnitude
Magnitude
Phase A = 100
180 R2 = 1000 Ohms
90 C = 10 uF
1000
A wp = 1/(R2C) = 100
0
100 1000 100 VV OUT
=
A
1 10 Radian IN (1 + jωR2C )
100 100
-90 Frequency Actual value = | 1 + j | =
10 2
-180
1
1 10 100 1000 Radian
0.1 Frequency
2006 2006
Example: Circuit in Slide #3 Phase Bode Plot: Label as dB
VOUT A
Phase
VOUT A =
= VIN (1 + jωR2C )
Magnitude in dB
VIN (1 + jωR2C ) A = 100 A = 100
180 R2 = 1000 Ohms R2 = 1000 Ohms
90 C = 10 uF C = 100 uF
60
A wp = 1/(R2C) = 100
0
100 1000 40
1 10 Radian
-90 Frequency
20
-180 -45o
Actual value is 0
1 10 100 1000 Radian
100∠0 100∠0 -20 Frequency
Phase{ } = Phase{ } = 0 − 45 = −45
|1+ j | 2∠45
Note: Magnitude in dB = 20 log10(VOUT/VIN)
2006 2006
Transfer Function Filters
• Transfer function is a function of frequency • Circuit designed to retain a certain

– Complex quantity frequency range and discard others
– Both magnitude and phase are function of Low-pass: pass low frequencies and reject high
frequency frequencies
High-pass: pass high frequencies and reject low
Two Port
Vin filter network
Vout frequencies
Band-pass: pass some particular range of
frequencies, reject other frequencies outside
H( f ) =
Vout Vout
= ∠ (θ out − θin ) that band
Vin Vin Notch: reject a range of frequencies and pass
H(f) = H ( f )∠θ all other frequencies
2006 2006
Common Filter Transfer Function vs. Freq First-Order Lowpass Filter
VC 1 ( jωC ) 1 1
H( f ) H( f ) H(f) = = = = ∠ − tan −1 (ω RC )
V 1 ( jωC ) + R 1 + jω RC 1 + (ω RC )
2
1 1
Let ωB = and f B =
Low Pass High Pass RC 2π RC
H(f) = H ( f )∠θ
Frequency Frequency
1  f 
H( f ) = , θ = − tan −1  
H( f ) H( f ) 2
 fB 
 f 
1+  
 fB  R +
+
Band Pass Band Reject 1 V C VC
H ( fB ) = = 2−1/ 2 - -
2
Frequency Frequency H ( fB ) 1
20 log10 = 20(− ) log10 2 = −3 dB
H (0) 2
2006 2006
First-Order Highpass Filter First-Order Lowpass Filter
(ω RC ) ∠  π − tan −1 ω RC  VR 1 1  ωL 
VR R jω RC H(f) = = = ∠ − tan −1  
H(f) = = = =  2 ( ) V jω L
 ωL 
2
 R 
V 1 ( jωC ) + R 1 + jω RC 1 + (ω RC )
2
 +1 1 +
R  
 R 
 f 
  R R
 fB  π  f  Let ωB = and f B =
H( f ) = ,θ = − tan −1   L 2π L
 f 
2 2  fB  H(f) = H ( f )∠θ
1+  
 fB  VR 1  f  VR
H( f ) = , θ = − tan −1  
 fB 
2
1  f 
H ( fB ) = = 2−1/ 2 R 1+   R
2 + +  fB  + +
V C VC V L VL
H ( fB ) 1
20 log10 = 20(− ) log10 2 = −3 dB - - - -
H (0) 2
2006 2006
First-Order Highpass Filter First-Order Filter Circuits

jω L ωL
VL R R π  ω L 
H(f) = = = ∠  − tan −1  
V jω L 2
2  R 
+1  ωL  High Pass Low Pass
R 1 +  
 R 
R R
Let ωB = and f B = + R + R
L 2π L VS Low VS High
– C Pass
– L Pass
H(f) = H ( f )∠θ V R
 f 
 
 fB  π  f  R
H( f ) = ,θ = − tan −1   + HR = R / (R + 1/jωC) HR = R / (R + jωL)
2 2  fB 
+
 f  V L VL
1+  
 fB  - - HC = (1/jωC) / (R + 1/jωC) HL = jωL / (R + jωL)
2006 2006
Change of Voltage or Current with
A Change of Frequency High-frequency asymptote of Lowpass filter
One may wish to specify the change of a quantity The high frequency asymptote of magnitude
such as the output voltage of a filter when the Bode plot assumes -20dB/decade slope
frequency changes by a factor of 2 (an octave) or 10
(a decade). As f → ∞
For example, a single-stage RC low-pass filter has at  f 
−1
frequencies above ω = 1/RC an output that changes H( f ) =  

 fB 
at the rate -20dB per decade.
H (10 f B )
20 log10 = −20dB
H ( fB )
2006 2006
Low-frequency asymptote of Highpass filter Second-Order Filter Circuits
As f → 0
 f 
 
 fB   f  Band Pass
H( f ) = →  Z = R + 1/jωC + jωL
 fB 
2
 f 
1+   R HBP = R / Z
 fB  Low C
f →∞
VS + Pass Band HLP = (1/jωC) / Z
–
H ( fB ) Reject
20 log10 = 20dB High L HHP = jωL / Z
H (0.1 f B ) Pass
HBR = HLP + HHP
The low frequency asymptote of magnitude
Bode plot assumes 20dB/decade slope
2006 2006
Series Resonance Parallel Resonance
+
IIN
+
+
VIN
VOUT
VOUT
−
Voltage divider Admittance

VOUT
=
ZR Resonance quality factor VOUT =
IS Resonance quality factor
VIN Z L + Z R + ZC YL + YR + YC
ωL ωL
Substitute branch elements Q= Substitute branch elements Q=
R R
VOUT R
= IS
VIN jω L + R + 1 / jω C
Ratio of reactance to resistance VOUT = Ratio of reactance to resistance
1 + 1 + jwC
j ωL R
Arrange in resonance form Closely related to number Closely related to number
Arrange in resonance form
VOUT
=
R of round trip cycles before of round trip cycles before
VIN R + j (ωL − 1 / ωC ) IS
1/e decay. VOUT =
1 + j (ωC − 1 )
1/e decay.
R ωL
Bandwidth is f0/Q Bandwidth is f0/Q
Maximum when w2 = 1/(LC) Maximum = IS/R when w2 = 1/(LC)
2006 2006
Chapter 14 (Lec. 8.3-9.3) The Operational Amplifier

• OUTLINE • The operational amplifier (“op amp”) is a
– Op-Amp from 2-Port Blocks basic building block used in analog circuits.
– Its behavior is modeled using a dependent source.
– Op-Amp Model and its Idealization
– When combined with resistors, capacitors, and
– Negative Feedback for Stability inductors, it can perform various useful functions:
– Components around Op-Amp define the • amplification/scaling of an input signal
Circuit Function • sign changing (inversion) of an input signal
• addition of multiple input signals
• subtraction of one input signal from another
• Reading • integration (over time) of an input signal
• differentiation (with respect to time) of an input signal
– Chap 14 • analog filtering
• nonlinear functions like exponential, log, sqrt, etc
2006 2006
High Quality Dependent Source In an Amplifier Op Amp Terminals
• 3 signal terminals: 2 inputs and 1 output
• IC op amps have 2 additional terminals for DC
AMPLIFIER SYMBOL AMPLIFIER MODEL power supplies
Differential Amplifier V0 = A( V+ − V− ) Circuit Model in linear region • Common-mode signal= (v1+v2)/2
V+ + V0
A + + + • Differential signal = v1-v2
V− − Ri V1 AV1 V0
− −
− V+ positive power supply
V0 depends only on input (V+ − V-) Inverting input v2 -

v0 output
Non-inverting input v1 +
See the utility of this: this Model when used correctly
mimics the behavior of an amplifier but omits the
complication of the many many transistors and other V – negative power supply
components.
2006 2006
Op Amp Terminal Voltages and Currents Model for Internal Operation

• All voltages are referenced to a common node. • A is differential gain or • Circuit Model
• Current reference directions are into the op amp. open loop gain
• Ideal op amp
V+
+ A→∞ +
ic+ i1
i2 Ri → ∞
– Vcc v1
+ io Ro io
i1 – Ro = 0
v2
+ +
+ ic- Ri vo
– vo – Common mode gain = 0
v1 V– – ( v1 + v2 ) i2
vcm = , vd = v1 − v2 v2 +
– _ –
– 2 A(v1–v2)
Vcc vo = Acm vcm + Ad vd
+ Since vo = A(v1 − v2 ) , Acm = 0
common node
(external to the op amp)
2006 2006
Model and Feedback Op-Amp and Use of Feedback
• Negative feedback • Circuit Model A very high-gain differential amplifier can function in an extremely linear
– connecting the output port to fashion as an operational amplifier by using negative feedback.
the negative input (port 2)
R1 R2 R1 R2
• Positive feedback
– connecting the output port to
+
the positive input (port 1)
i1 − - + +
v1 VIN +
V0 Ri V1 AV1 V0
Ro io + − −
VIN
Ri vo Summing Point
i2 Circuit Model
v2 +
_ – Negative feedback ⇒ Stabilizes the output
A(v1–v2) Hambley Example pp. 644 for Power Steering
We can show that that for A → ∞ and Ri → ∞,
R1 + R 2 Stable, finite, and independent of
V 0 ≅ V IN ⋅
R1 the properties of the OP AMP !
2006 2006
Negative Feedback Summing-Point Constraint

Familiar examples of negative feedback: • Check if under negative feedback
Fundamentally – Small vi result in large vo
Thermostat controlling room temperature pushes toward – Output vo is connected to the inverting input to reduce
Driver controlling direction of automobile stability vi
Photochromic lenses in eyeglasses – Resulting in vi=0
• Summing-point constraint
Familiar examples of positive feedback: – v1 = v2
Fundamentally
pushes toward – i1 = i2 =0
Microphone “squawk” in room sound system
instability or • Virtual short circuit
Mechanical bi-stability in light switches bi-stability
– Not only voltage drop is 0 (which is short circuit), input
Thermonuclear reaction in H-bomb current is 0
– This is different from short circuit, hence called
“virtual” short circuit.
2006 2006
Ideal Op-Amp Analysis Technique Ideal Op-Analysis: Non-Inverting Amplifier
Applies only when Negative Feedback is present in circuit! Yes Negative Feedback is present in this circuit!
Assumption 1: The potential between the op-amp input terminals, v(+) –
Assumption 1: The potential between the op-amp input terminals, v(+) –
v(-), equals zero.
v(-), equals zero.
Assumption 2: The currents flowing into the op-amp’s two input
Assumption 2: The currents flowing into the op-amp’s two input terminals both equal zero.
terminals both equal zero. KCL with currents in only two branches
No Potential Difference R1 R2 v v −v
R1 in in out
No Currents R2 + =0
R1 R2
−
− V0 R + R2
V0 VIN + vout = 1 vin
VIN + R1
EXAMPLE
EXAMPLE
VIN appears here Non-inverting Amplifier
2006 2006
Non-Inverting Amplifier Ideal Op-Amp Analysis: Inverting Amplifier

• Ideal voltage amplifier vo
Yes Negative Feedback is present in circuit!
Closed loop gain = Av = R2
vin R1
+ v0 I2
v1 = v2 = vin , i1 = i2 = 0
v2 _ Use KCL At Node 2.
vin +- VIN
RL V OUT
RL (v − v ) (v − 0) -VR
2 i= 0 2 = 2 Voltage is VR
R2 R2 R1
R1 vo ( R1 + R2 ) VR − VIN VR − VOUT
A= = Only two
+ =0
vin R1 currents R1 R2
for KCL
vin
Input impedance = →∞ R2
i VOUT = VR − (Vin − VR )
R1
Inverting Amplifier with reference voltage
2006 2006
Inverting Amplifier Voltage Follower
vo
• Negative feedback Closed loop gain = Av =
vin + v0
checked
v1 = v2 = 0 , i1 = i2 = 0 v2
vin +
_
• Use summing-point Use KCL At Node 2. - RL
constraint (vin − v2 ) (vout − v2 )
R2 i= =
2 R1 R2
R2 vo R2 = 0
i R1 v vo = −
2 _ R1 R1 → ∞
v0
+ vin (v0 − v2 ) (v2 − 0)
vin +- v1 Input impedance = = R1 i= =
RL i R2 R1
vo ( R1 + R2 ) R
A= = = 1+ 2 = 1
Ideal voltage source – independent of load resistor vin R1 R1
2006 2006
Example 1 Example 1
2 i5 R
• Switch is closed
i4
R v2 i 2 _
v0
2 i5 R v1 = v2 = 0 , i1 = 0 → i3 = 0
+
i3 v1 i 1
+
R RL • Switch is open i4
R v2 i 2 _ i4 =
(vin − v2 ) (v − v )
= i 5= − 0 2
vin - v0
R R
+
i3 v1 i 1 v0 = −vin
v1 = v2 , i1 = 0 → i3 = 0 R RL
vin +- vo
(v − v ) A= = −1 , Rin = R
i3 = in 1 → v1 = v2 = vin → i4 = 0 → i5 = 0 vin 2
R
(v − v )
i 5 = 0 2 → v0 = v2 = vin
R
vo
A= = 1 , Rin → ∞
vin
2006 2006
Example 2 Example 2 (cont’d)
• Design an analog front end v1
+
circuit to an instrument system vin c v0 Rin = Ra + Rb + Rc = 1M Ω
_
– Requires to work with 3 full-scale of v2 R2
input signals (by manual switch): vb b RL Max Av = 10 = (1 + ) Switch at c
2 R1
0 ±1, 0 ±10, 0 ±100 V R2
va a Ra + Rb R Ra + Rb
– For each input range, the output R1 Av = 1 = (1 + 2 ) Switch at b ∴ = 0.1
needs to be 0 ±10 V Ra + Rb + Rc R1 Ra + Rb + Rc
– The input resistance is 1MΩ Ra R Ra
Av = 0.1 = (1 + 2 ) Switch at a ∴ = 0.01
Ra + Rb + Rc R1 Ra + Rb + Rc
R2
vo = (1 + )v1 ∴ Ra = 10k Ω, Rb = 90k Ω, Rc = 900k Ω
R1
v1 = vin Switch at c R2 = 9 R1
Ra + Rb
v1 = vin Switch at b
Ra + Rb + Rc
Ra
v1 = vin Switch at a
Ra + Rb + Rc
2006 2006
Summing Amplifier Difference Amplifier
v1 R1
+
-
R0 R2
+
-
v2 R2 v1 R1
_ v0 _ v0
+
+
-
-
v3 R3
+ +
+
-
v2 R3
R4
2006 2006
Integrator Differentiator
• Want v = K v dt
o ∫ in • Want
• What is the difference

between:
R
C
R
+ + _ v0
vin C V0
+
- - vin +-
2006 2006
Bridge Amplifier Application: Digital-to-Analog Conversion

A DAC can be used to convert the digital representation Binary Analog
of an audio signal into an analog voltage that is then number output
vx (volts)
R0(1+ε) used to drive speakers -- so that you can hear it!
R0 0000 0
0001 .5
_ v0 “Weighted-adder D/A converter” 0010 1
10K 0011 1.5
+ S4
+ 0100 2
vin - 20K 0101 2.5
Ra S3 0110 3
Ra - 40K 5K
vx 8V
+ S2 0111 3.5
80K − 1000 4
−
+ 1001 4.5
+ V0
S1 1010 5
1011 5.5
4-Bit D/A 1100 6
S1 closed if LSB =1 1101 6.5
S2 " if next bit = 1 1110 7
(Transistors are used S3 " if " " = 1 1111 7.5
as electronic switches) S4 " if MSB = 1
MSB LSB
2006 2006
Characteristic of 4-Bit DAC Active Filter
8 • Contain few components
Analog Output (V)
7
• Transfer function that is insensitive to
6
component tolerance
5
4 • Easily adjusted
3 • Require a small spread of components
2 values
1 • Allow a wide range of useful transfer
0 functions
0 2 4 6 8 10 12 14 16
0000
0001 1000 1111
0100
Digital Input
2006 2006
Active Filter Example Active Filter Solution

vo
v1 = v 2 =
k
( v 3 − v1 )
Use KCL At Node A ⇒ = jω C v1
R
C
( v − v3 ) ( v − v1 )
Use KCL At Node B ⇒ in = jω C ( v 3 − v o ) + 3
R R
v3 vo k
v1 =
+
v0 vin 1 − ω 2 R 2 C 2 + jω RC (3 − k )
_ Let ω B = 1 / RC
R R
vin + (k-1)Rf vo k
- v2 H (ω ) = =
v in  ω2 
2
ω2
C
1 − 2 
+ 2
(3 − k ) 2
 ω B  ω B
Rf
ω = 0, H (ω ) = k DC gain
k
ω = ω B , H (ω ) =
3−k
k
ω >> ω B , H (ω ) = ω −2
 ω2 
 2 
 ωB 
20 log H (ω ) decays at a rate of 40 dB / decade
2006 2006
Cascaded Active Filter Example Cascaded Active Filter Solution
vo k2 k
=
vin 1 − ω 2 R2 2C2 2 + jω R2C2 (3 − k2 ) 1 − ω 2 R 2C 2 + jω RC (3 − k )
C Let ωB = 1/ RC , ωB 2 = 1/ R2C2
C2
v3 v1 vo k2 k
+ v0’ v3’ v1’ H (ω ) = =
R
+ v0 vin 2 2
+
R
v2
_
R2 R  ω 2
ω2  ω  ω2
2
vin - (k-1)Rf v2 ’
_
 1 − 2 
+ 2
(3 − k2 ) 2  1 − 2 
+ 2 (3 − k ) 2
C
2
(k2 -1)Rf  ω B2  ω B2  ω B  ωB
C2
Rf
Rf ω = 0, H (ω ) = k2 k DC gain
k2 k
ω = ωB , H (ω ) =
3 − k2 3 − k
k2 k
ω >> ωB , H (ω ) = ω −4
 ω4 
 2 2 
 ωB 2 ωB 
20 log H (ω ) decays at a rate of 80dB / decade
2006 2006
Chapter 10 (Week 10) I-V Characteristics
• OUTLINE I
– Diode Current and Equation In forward bias (+ on p-side) we current increases
have almost unlimited flow rapidly with V
– Some Interesting Circuit Applications (very low resistance).
– Load Line Analysis Qualitatively, the I-V VF
– Solar Cells, Detectors, Zener Diodes characteristics must look like:
– Circuit Analysis with Diodes

– Half-wave Rectifier I
– Clamps and Voltage Doublers using Capacitors
In reverse bias (+ on n-side)
• Reading almost no current can flow.
Qualitatively, the I-V VF
– Hambley 10.1-10.8
characteristics must look like: The current is close
– Supplementary Notes Chapter 2 to zero for any
negative bias
2006 2006
Diode Physical Behavior and Equation The pn Junction I vs. V Equation
Schematic Device I-V characteristic of PN junctions

Symbol
I In EECS 105, 130, and other courses you will learn why the I vs. V
N P
type type relationship for PN junctions is of the form
I
− V+
− V+
I = I 0 (e qV kT − 1)
Qualitative I-V characteristics: Quantitative I-V characteristics:
I V positive, where I0 is a constant proportional to junction area and depending
easy I = I 0 (eqV kT − 1) on doping in P and N regions, q = electronic charge = 1.6 × 10 −19 ,
conduction k is Boltzman constant, and T is absolute temperature.
In which kT/q is 0.026V and IO is a KT q = 0.026V at300°K , a typical value for I0 is 10 −12 − 10 −15 A
constant depending on diode area.
V Typical values: 10-12 to 10-16 A.
Interestingly, the graph of this
V negative, We note that in forward bias, I increases exponentially and is in
equation looks just like the figure to
no the µA-mA range for voltages typically in the range of 0.6-0.8V.
the left.
conduction In reverse bias, the current is essentially zero.
A non-ideality factor n times kT/q is often included.
2006 2006
Diode Ideal (Perfect Rectifier) Model Diode Large-Signal Model (0.7 V Drop)
The equation I = I 0 exp(qV kT − 1)
Simple “Perfect Rectifier” Model 400
- 0.7+ I
(microamp)
is graphed below for I 0 = 10 −15 A
Current
300
10 If we can ignore the small forward- 200

Current
bias voltage drop of a diode, a 100 The Large-Signal
in mA 8
simple effective model is the 0 − V+ Diode Model
6 -5 -3 -1 1
“perfect rectifier,” whose I-V forward bias (V)
4
characteristic is given below:
2 Forward
Voltage in V Improved “Large-Signal Diode” Model: I
0 I
-5 0 5 10 If we choose not to ignore the small
Reverse bias Forward bias
The characteristic is described as Reverse bias Forward bias forward-bias voltage drop of a I ≅ 0, any V < 0 V ≅ 0.7, any I > 0
a “rectifier” – that is, a device that I ≅ 0, any V < 0 V ≅ 0, any I > 0 diode, it is a very good
approximation to regard the voltage V
permits current to pass in only one V 0.7
direction. (The hydraulic analog is drop in forward bias as a constant,
a “check value”.) Hence the about 0.7V. the “Large signal
A perfect rectifier model” results.
symbol: I
− V+
2006 2006
Rectifier Circuit Peak Detector Circuit
Assume the ideal Assume the ideal (perfect rectifier) model.
(perfect rectifier) VS(t)
model. Vi(t)
+
+ + Vi
+ C
VS(t) +
− VR(t) Vi(t) − VC(t)
−
− t −
t
VR(t) VC(t) VC
Key Point:
The capacitor charges
due to one way current
“rectified” version of behavior of the diode.
input waveform
t
2006 2006
pn-Junction Reverse Breakdown Zener Diode

• As the reverse bias voltage increases, the peak electric A Zener diode is designed to operate in the breakdown mode.
field in the depletion region increases. When the electric
field exceeds a critical value (Ecrit ≅ 2x105 V/cm), the ID (A)
reverse (leakage) current
reverse current shows a dramatic increase:
forward
current
breakdown voltage VBD
reverse (leakage) current ID (A) VD (V)
forward current
breakdown voltage VBD

VD (V)
Example:
t
R
+ +
integrated
vs(t) vo(t) circuit
– VBD = 15V –
2006 2006
Load Line Analysis Method Solar cell: Example of simple PN junction
1. Graph the I-V relationships for the non-linear • What is a solar cell?
element and for the rest of the circuit – Device that converts
2. The operating point of the circuit is found from sunlight into electricity
the intersection of these two curves.
I
• How does it work?
– In simple configuration, it is a
RTh I diode made of PN junction
+ VTh/RTh operating point – Incident light is absorbed by
+
material
VTh − V – Creates electron-hole pairs that
– V transport through the material
VTh through
• Diffusion (concentration gradient)
The I-V characteristic of all of the circuit except • Drift (due to electric field)
the non-linear element is called the load line PN Junction Diode
2006 2006
Photovoltaic (Solar) Cell I-V characteristics of the device

• I-V characteristics of a PN
I D = I S (e qVD kT
− 1) − I optical junction is given by
 eV 
I = I S exp( ) − 1 − I L
 kT  Voc
ID (A) where Is is the saturation intensity
depending on band gap and doping
(Vm, Im)
of the material and IL is the Isc
in the dark photocurrent generated due to light
VD (V)
• Efficiency is defined as
with incident light I m .Vm FF *Voc * I sc Voc - Open circuit voltage

η= =
Operating point Light Intensity Light Intensity Isc - Short circuit current
The load line a simple resistor. Imp , Vmp- Current and voltage
FF is the Fill Factor at maximum power
2006 2006
Example 2: Photodiode Photodetector Circuit Using Load Line
• An intrinsic region is placed RTh I I
between the p-type and n-type + operating
− As light
regions VTh + points under intensity
V different light
Wj ≅ Wi-region, so that most of the increases.
conditions. Why?
electron-hole pairs are generated –
in the depletion region
As light shines on the photodiode, carriers V
faster response time are generated by absorption. These excess V
(~10 GHz operation) carriers are swept by the electric field at the
Th
ID (A) junction creating drift current, which is same VTh/RTh

direction as the reverse bias current and
hence negative current. The current is
in the dark proportional to light intensity and hence can load line
provide a direct measurement of light
VD (V) intensity photodetector.
operating point
- What happens when Rth is too large?
with incident light - Why use Vth?
2006 2006
Ideal Diode Model of PN Diode Large-Signal Diode Model

Circuit symbol I-V characteristic Switch model Circuit symbol I-V characteristic Switch model
ID ID (A) ID ID ID (A) ID
+ + +
+
+ −
VDon
VD VD VD VD
forward bias forward bias
–
reverse bias reverse bias
– VD (V) – VD (V) –
VDon
• An ideal diode passes current only in one direction. For a Si pn diode, VDon ≅ 0.7 V
• An ideal diode has the following properties: RULE 1: When ID > 0, VD = VDon
Diode behaves like a voltage
• when ID > 0, VD = 0 RULE 2: When VD < VDon, ID = 0 source in series with a switch:
Diode behaves like a switch:
• when VD < 0, ID = 0 • closed in forward bias mode • closed in forward bias mode
• open in reverse bias mode • open in reverse bias mode
2006 2006
Diode: Large Signal Model How to Analyze Circuits with Diodes
• Use piece-wise linear model A diode has only two states:
• forward biased: ID > 0, VD = 0 V (or 0.7 V)
• reverse biased: ID = 0, VD < 0 V (or 0.7 V)
Procedure:
1. Guess the state(s) of the diode(s)
2. Check to see if KCL and KVL are obeyed.
3. If KCL and KVL are not obeyed, refine your guess
4. Repeat steps 1-3 until KCL and KVL are obeyed.
Example: If vs(t) > 0 V, diode is forward biased
+ (else KVL is disobeyed – try it)
vs(t) + vR(t)
− If vs(t) < 0 V, diode is reverse biased
– (else KVL is disobeyed – try it)
2006 2006
Diode Logic: AND Gate Diode Logic: OR Gate

• Diodes can be used to perform logic functions: • Diodes can be used to perform logic functions:
AND gate OR gate
output voltage is high only if Inputs A and B vary between 0 output voltage is high if
both A and B are high
Volts (“low”) and Vcc (“high”) Inputs A and B vary between 0 either (or both) A and B are high
Vcc Volts (“low”) and Vcc (“high”)
Between what voltage levels
does C vary? Between what voltage levels
does C vary? A
RAND VOUT VOUT
5 5 B C
A C EOC ROR
EOC
B Slope =1
Shift 0.7V Up
Slope =1
Shift 0.7V Down
0
0 5 VIN
0 0.7V
0 5 VIN
2006 2006
Diode Logic: Incompatibility and Decay Digital Logic: Diodes with Dependent Sources
• Diode Only Gates are Basically Incompatible: • EE40 TTL (Transistor-Transistor Logic
AND gate OR gate
output voltage is high only if output voltage is high if
both A and B are high either (or both) A and B are high VOUT
5V
5
Vcc Shift 0.7V
Slope >1
R1 R2
EOC
A A
RAND B F
B COR In practice does
βi1
A CAND ROR VD_ON = 0.7 V
i1 not go below 0.2V
0
EOC 5 VIN
B 0
CAND High want RAND >> ROR

CAND Low want RAND << ROR Incase you are interested: True TTL has at least three
dependent sources that are associated with the three bipolar
Signal Decays with each stage (Not regenerative)
transistors on which it is based.
2006 2006
Device Isolation using pn Junctions Why are pn Junctions Important for ICs?
regions of n-type Si
• The basic building block in digital ICs is the
MOS transistor, whose structure contains
reverse-biased diodes.
n n n n n
– pn junctions are important for electrical isolation of
p-type Si transistors located next to each other at the
surface of a Si wafer.
No current flows if voltages are applied between n-type – The junction capacitance of these diodes can limit
regions, because two pn junctions are “back-to-back” the performance (operating speed) of digital
circuits
n-region n-region
p-region
=> n-type regions isolated in p-type substrate and vice versa
2006 2006
Power Conversion Circuits Rectifier Equivalent circuit
• Converting AC to DC
• Potential applications: Charging a battery V>0.6V, diode = short circuit
Vo=VI-0.6
V<0.6V, diode = open circuit
Vo=0
VI=Vm sin (ωt) R Vo
2006 2006
Half-wave Rectifier Circuits Half-Wave Rectifier

• Adding a capacitor: what does it do?
+
Vm sin (ωt)
C R V0
-
Current
charging
up
capacitor
2006 2006
Level Shift Circuit Voltage Doubler Circuit
- VC1 + - VC1 +
VIN
+
+
+
+
C1 C1
+ VC21 -
VIN VOUT VIN VIN C2 VOUT
R1 R1 VOUT R2
- - -
- - -
t
VOUT
Level Shift Peak Detect
The final output is the peak to peak voltage of the input.

Once the capacitor is charged by the negative most voltage
the rest of the signal is shifted up by that amount.
2006 2006
Week 11 Conductors, Insulators and Semiconductors

• OUTLINE • Solids with “free electrons” – that is electrons not
– Basic Semiconductor Materials directly involved in the inter-atomic bonding- are
– n and p doping
the familiar metals (Cu, Al, Fe, Au, etc).
– Bandgap • Solids with no free electrons are the familiar
– Gauss’s Law
insulators (glass, quartz crystals, ceramics, etc.)
– Poisson Equation • Silicon is an insulator, but at higher
temperatures some of the bonding electrons can
– Depletion approximation
get free and make it a little conducting – hence
– Diode I-V characteristics the term “semiconductor”
– Lasers and LEDs
• Pure silicon is a poor conductor (and a poor
– Solar Cells insulator). It has 4 valence electrons, all of
• Reading which are needed to bond with nearest
– Supplementary Notes Chap 3 neighbors. No free electrons.
2006 2006
The Periodic Table Electronic Bonds in Silicon
III IV V
2-D picture of perfect crystal of pure silicon; double line is a Si-Si
bond with each line representing an electron
Si ion
(charge
+4 q)
Two electrons in each bond
Actual structure is 3-dimensional tetrahedral- just like carbon

bonding in organic and inorganic materials.
Essentially no free electrons, and no conduction - insulator

2006 2006
How to get conduction in Si? Doping Silicon with Donors (n-type)
We must either:
Donors donate mobile electrons (and thus “n-type” silicon)
1) Chemically modify the Si to produce free carriers (permanent) or Example: add arsenic (As) to the silicon crystal:
2) Electrically “induce” them by the field effect (switchable)
For the first approach controlled impurities, “dopants”, are added to

Si: Mobile electron
donated by As ion
Add group V elements (5 bonding electrons vs four for Si),
such as phosphorus or arsenic As
(Extra electrons produce “free electrons” for conduction.)
or
Add group III elements (3 bonding electrons), such as boron

Immobile (stuck) positively charged arsenic ion after 5th electron left
Deficiency of electrons results in “free holes”
The extra electron with As, “breaks free” and becomes a free
electron for conduction
2006 2006
Doping with Acceptors (p-type) Doping
Group III element (boron, typically) is added to the crystal

• Typical doping densities:
Immobile (stuck) negative boron ion after accepting electron from neighboring bond
1016~1019 cm-3
• Atomic density for Si: 5 x
1022 atoms/cm3
Mobile hole con- • 1018 cm-3 is 1 in 50,000
tributed by B ion
and later path – two persons in entire
B
Berkeley wearing a green
hat
• P-n junction effect is like
The “hole” which is a missing bonding electron, breaks free from

the B acceptor and becomes a roaming positive charge, free to
carry current in the semiconductor. It is positively charged.
2006 2006
Shockley’s Parking Garage Analogy for Conduction in Si Shockley’s Parking Garage Analogy for Conduction in Si
Two-story parking garage on a hill: Two-story parking garage on a hill:
If the lower floor is full and top one is empty, no traffic is If one car is moved upstairs, it can move AND THE HOLE
possible. Analog of an insulator. All electrons are ON THE LOWER FLOOR CAN MOVE. Conduction is
locked up. possible. Analog to warmed-up semiconductor. Some
electrons get free (and leave “holes” behind).
2006 2006
Shockley’s Parking Garage Analogy for Conduction in Si
Shockley’s Parking Garage Analogy for Conduction in Si
Two-story parking garage on a hill: Two-story parking garage on a hill:
If an extra car is “donated” to the upper floor, it can move. If a car is removed from the lower floor, it leaves a HOLE
Conduction is possible. Analog to N-type semiconductor. which can move. Conduction is possible. Analog to P-type
(An electron donor is added to the crystal, creating free semiconductor. (Acceptors are added to the crystal,
electrons). “consuming” bonding electrons,creating free holes).
2006 2006
Summary of n- and p-type silicon Junctions of n- and p-type Regions
p-n junctions form the essential basis of all semiconductor devices.

Pure silicon is an insulator. At high temperatures it conducts
weakly. A silicon chip may have 108 to 109 p-n junctions today.
How do they behave*? What happens to the electrons and holes?
If we add an impurity with extra electrons (e.g. arsenic,
What is the electrical circuit model for such junctions?
phosphorus) these extra electrons are set free and we have a
pretty good conductor (n-type silicon). n and p regions are brought into contact :
If we add an impurity with a deficit of electrons (e.g. boron) then aluminum ? aluminum
bonding electrons are missing (holes), and the resulting holes
can move around … again a pretty good conductor (p-type wire
silicon) n p
Now what is really interesting is when we join n-type and p-type

silicon, that is make a pn junction. It has interesting electrical
properties.
*Note that the textbook has a very good explanation.
2006 2006
The pn Junction Diode Depletion Region
Schematic diagram Circuit symbol • When the junction is first formed, mobile carriers diffuse
across the junction (due to the concentration gradients)
ID
p-type n-type – Holes diffuse from the p side to the n side,
leaving behind negatively charged immobile acceptor
net acceptor net donor
+ VD – ions
concentration NA concentration ND
cross-sectional area AD
– Electrons diffuse from the n side to the p side,
leaving behind positively charged immobile donor ions
Physical structure: ID acceptor ions donor ions
(an example) + metal
– +
SiO2 SiO2 – +
p – + n
p-type Si – +
VD – +
For simplicity, assume that
n-type Si A region depleted of mobile carriers is formed at the junction.
the doping profile changes
abruptly at the junction. • The space charge due to immobile ions in the depletion region
– metal establishes an electric field that opposes carrier diffusion.
2006 2006
Depletion Region Approximation Summary: pn-Junction Diode I-V

• When the junction is first formed, mobile carriers diffuse • Under forward bias, the potential barrier is reduced, so
across the junction (due to the concentration gradients) that carriers flow (by diffusion) across the junction
– Holes diffuse from the p side to the n side, – Current increases exponentially with increasing forward bias
leaving behind negatively charged immobile acceptor – The carriers become minority carriers once they cross the
ions junction; as they diffuse in the quasi-neutral regions, they
recombine with majority carriers (supplied by the metal contacts)
– Electrons diffuse from the n side to the p side,
“injection” of minority carriers
leaving behind positively charged immobile donor ions
acceptor ions donor ions • Under reverse bias, the potential barrier is increased, so
–
that negligible carriers flow across the junction
+
– + – If a minority carrier enters the depletion region (by thermal
p – + n
– + generation or diffusion from the quasi-neutral regions), it will be
– + swept across the junction by the built-in electric field
“collection” of minority carriers reverse current ID (A)
A region depleted of mobile carriers is formed at the junction.
• The space charge due to immobile ions in the depletion region
establishes an electric field that opposes carrier diffusion. VD (V)
2006 2006
Charge Density Distribution Effect of Applied Voltage
Charge is stored in the depletion region.
– +
– +
acceptor ions donor ions VD p – + n
– +
– + – +
– +
p – + n
– +
– +
• The quasi-neutral p and n regions have low resistivity,
quasi-neutral p region depletion region quasi-neutral n region whereas the depletion region has high resistivity. Thus,
when an external voltage VD is applied across the diode,
charge density (C/cm3)
almost all of this voltage is dropped across the depletion
region. (Think of a voltage divider circuit.)
• If VD > 0 (forward bias), the potential barrier to carrier
distance diffusion is reduced by the applied voltage.
• If VD < 0 (reverse bias), the potential barrier to carrier
diffusion is increased by the applied voltage.
2006 2006
Forward Bias Reverse Bias

• As VD increases, the potential barrier to carrier • As |VD| increases, the potential barrier to carrier
diffusion across the junction decreases*, and diffusion across the junction increases*; thus, no
current increases exponentially. carriers diffuse across the junction.
The carriers that diffuse across the A very small amount of reverse
– + – +
VD > 0 – + junction become minority carriers in VD < 0 – + current (ID < 0) does flow, due to
p – + n the quasi-neutral regions; they then p – + n minority carriers diffusing from the
– + – +
– + recombine with majority carriers, – + quasi-neutral regions into the depletion
“dying out” with distance. region and drifting across the junction.
ID (Amperes) ID (Amperes)
VD (Volts) VD (Volts)
* Hence, the width of the depletion region decreases. * Hence, the width of the depletion region increases.
2006 2006
Optoelectronic Diodes Example: Photodiode
• Light incident on a pn junction generates electron-hole pairs • An intrinsic region is placed
• Carriers are generated in the depletion region as well as n- between the p-type and n-type
doped and p-doped quasi-neutral regions. regions
• The carriers that are generated in the quasi-neutral regions Wj ≅ Wi-region, so that most of the
diffuse into the depletion region, together with the carriers electron-hole pairs are generated
generated in the depletion region, are swept across the in the depletion region
junction by the electric field
faster response time
(~10 GHz operation)
ID (A)
in the dark
• This results in an additional component of current flowing in
the diode: qVD kT VD (V)
I D = I S (e − 1) − I optical operating point
where Ioptical is proportional to the intensity of the light with incident light
2006 2006
Planck Constant Bandgap Versus Lattice Constant

• Planck’s constant h = 6.625·10-34 J·s
• E=hν=hc/λ
• C is speed of light and hν is photon energy
• The first type of quantum effect is the quantization of
certain physical quantities.
• Quantization first arose in the mathematical formulae of
Max Planck in 1900. Max Planck was analyzing how the
radiation emitted from a body was related to its
temperature, in other words, he was analyzing the
energy of a wave.
• The energy of a wave could not be infinite, so Planck Si
used the property of the wave we designate as the
frequency to define energy. Max Planck discovered a
constant that when multiplied by the frequency of any
wave gives the energy of the wave. This constant is
referred to by the letter h in mathematical formulae. It is
a cornerstone of physics.
2006 2006
Principle of Laser Structure of Semiconductor Diode Laser
• How to build up photon energy? • PIN diode with DHS
Confine the light using mirrors (Double Hetero Junction)
P I N
configuration
• Advantages !!
Spontaneous Emission Stimulated Emission
• Confines both the carriers
Laser the photons Refractive
Index profile
Engineering
Suitable Gain Medium Right Choice of Mirrors

2006 2006
What is a Laser? When does the laser action happen?

Laser is a device that produces • Round trip gain in the cavity should
monochromatic, coherent exceed the losses (absorption, leakage
radiation etc)
Could be very Hazardous !! • The phase matching condition decides the
possible cavity modes
R1= 99.4%
5x 6nm QWs
(30 nm) Hence, the laser has a threshold !!
R2= 99.75%
Edge Emitting Diode Laser Surface Emitting

Power-Current Characteristics
2006 2006
Applications of Violet LDs Laser Fabrication
• Insulating sapphire substrate
requires deep mesa etch and
lateral n-type contact
• Higher density optical storage with • High electrical drive power
shorter wavelength requires a very narrow ridge
to reduce thermal resistance
• High brightness applications like • High current density requires
projection displays thick metal electrodes to
reduce sheet resistance
• High efficiency solid-state lighting with • Difficulty of cleaving GaN on
visible phosphors sapphire makes etched facets
attractive
• Medical/Analytical applications
2006 2006
Blue Diode Laser Week 12 MOSFET (Lec. 12.1-14.1)

• OUTLINE
Looking through the transparent sapphire substrate – The MOSFET as a controlled resistor
– Pinch-off and current saturation
– MOSFET ID vs. VGS characteristic
– NMOS and PMOS I-V characteristics
– Load-line analysis; Q operating point; Bias circuits
– Small-signal equivalent circuits
– Small signal model and Q-point analysis
– Common source amplifier
– Source follower
– Common gate amplifier
– Common-source amplifiers
– Source followers
– Common-source amplifiers
– Input and output impedances
– Gain
• Reading
– Supplementary Notes Chapter 4
– Hambley: Chapter 12.1-12.5
2006 2006
MOSFET Terminals MOSFET Structure
• The voltage applied to the GATE terminal determines whether DEVICE IN CROSS-SECTION
current can flow between the SOURCE & DRAIN terminals. “Metal” “Semiconductor”
“Oxide”
– For an n-channel MOSFET, the SOURCE is biased at a lower G “Metal” gate (Al or Si)
potential (often 0 V) than the DRAIN D
(Electrons flow from SOURCE to DRAIN when VG > VT) S
gate
– For a p-channel MOSFET, the SOURCE is biased at a higher oxide insulator
potential (often the supply voltage VDD) than the DRAIN n n
(Holes flow from SOURCE to DRAIN when VG < VT ) P
• The BODY terminal is usually connected to a fixed potential. • In the absence of gate voltage, no current can flow between S and D.
– For an n-channel MOSFET, the BODY is connected to 0 V
• Above a certain gate to source voltage Vt (the “threshold”), electrons are
– For a p-channel MOSFET, the BODY is connected to VDD induced at the surface beneath the oxide. (Think of it as a capacitor.)
• These electrons can carry current between S and D if a voltage is applied.
2006 2006
MOSFET Circuit Symbols The MOSFET as a Controlled Resistor

NMOS G G • The MOSFET behaves as a resistor when VDS is low:
n+ poly-Si – Drain current ID increases linearly with VDS
n+ n+
– Resistance RDS between SOURCE & DRAIN depends on VGS
S S
• RDS is lowered as VGS increases above VT oxide thickness ≡ tox
p-type Si
NMOSFET Example:
PMOS G G ID
p+ poly-Si VGS = 2 V
p+ p+ S S VGS = 1 V > VT
VDS
n-type Si
Inversion charge density Qi(x) = -Cox[VGS-VT-V(x)]
IDS = 0 if VGS < VT where Cox ≡ εox / tox
2006 2006
Sheet Resistance Revisited MOSFET as a Controlled Resistor (cont’d)
Consider a sample of n-type semiconductor: V DS
V
ID =
I _ R DS
+ L /W L /W
R DS = R s ( L / W ) = =
W µ n Qi µ C (V − V − V DS )
t n ox GS T
homogeneously doped sample
2
average value
W V of V(x)
L I D = µnCox (VGS − VT − DS )VDS
L 2
ρ 1 1 1
Rs = = = =
t σt qµn nt µnQn We can make RDS low by
• applying a large “gate drive” (VGS − VT)
where Qn is the charge per unit area
• making W large and/or L small
2006 2006
Charge in an N-Channel MOSFET What Happens at Larger VDS?

VGS < VT: VGS > VT :
depletion region
(no inversion layer VDS = VGS–VT Inversion-layer
at surface) is “pinched-off”
at the drain end
VGS > VT :
VDS > VGS–VT
VDS ≈ 0 I D = WQinv v
= WQ inv µ n E As VDS increases above VGS–VT ≡ VDSAT,
V  the length of the “pinch-off” region ∆L increases:
VDS > 0 = WQ inv µ n  DS  • “extra” voltage (VDS – VDsat) is dropped across the distance ∆L
(small)  L  • the voltage dropped across the inversion-layer “resistor” remains VDsat
⇒ the drain current ID saturates
Average electron velocity v is proportional to lateral electric field E Note: Electrons are swept into the drain by the E-field when they enter the pinch-off region.
2006 2006
Summary of ID vs. VDS N-MOS I-V Characteristics
• As VDS increases, the inversion-layer charge density at At low VDS we have:
the drain end of the channel is reduced; therefore, ID
ID vs VD at low VDS
does not increase linearly with VDS. W VDS W
ID = = µ n Cox (VGS − VT ) ⋅ VDS
iD(mA) L R L
• When VDS reaches VGS − VT, the channel is “pinched off” VGS = 2 .5V
at the drain end, and ID saturates (i.e. it does not [ Note that this also follows from our
VGS = 1.5V
4 previous analysis where we had :
increase with further increases in VDS). 3 VGS = 1 V
2 I = q W t µn n V/L = Qn µn W/L V
VGS 1 VGS < 0.5
+ VD
because Q= COX (VGS – VT) ]
0 0.5
VDS > VGS - VT
– G
W
D
I DSAT = µ nCox (VGS − VT )2
S 2L At high drain voltage the current stops rising (saturates) due to:
n+ -
VGS - VT
+
n+ • Voltage increase by VDS along channel reduces local excess
gate voltage even to zero (Pinch-Off).
• Electrons reach their velocity saturation limit
pinch-off region
2006 2006
Charge Transport in Silicon Charge Transport in Silicon
At low electric fields, the average speed of But at high electric fields, the average speed
carriers is proportional to the field with of carriers is NOT proportional to the field;
proportionality constant µ; In fact drift velocity = that is the mobility concept fails. In fact
µpE for holes = - µnE for electrons : velocity saturates at 107 cm/sec = 100 km/sec
for both electrons and holes:
Example: µn= 1000 cm2/v-sec, (or 10Km2/KV-sec)
µp= 500 cm2/v-sec This saturation is
observable directly in the
<v> (Km/s) “resistance” of a silicon
resistor at high fields
|<v>| (Km/s) 100 (10KV/cm = 1V/µm)
100 I
10 20 E (KV/cm)
V
10 20 E (KV/cm)
2006 2006
ID vs. VDS Characteristics Channel-Length Modulation
The MOSFET ID-VDS curve consists of two regions: If L is small, the effect of ∆L to reduce the inversion-layer
“resistor” length is significant
1) Resistive or “Triode” Region: 0 < VDS < VGS − VT → ID increases noticeably with ∆L (i.e. with VDS)
W VDS  ID
I D = kn′ V − V − VDS
L  2 
GS T ID = ID′(1 + λVDS)
where kn′ = µ nCox λ is the slope

process transconductance parameter
2) Saturation Region:
VDS > VGS − VT ID′ is the intercept
k n′ W
I DSAT = (VGS − VT )2 VDS
2 L
where k n′ = µ n C ox “CUTOFF” region: VG < VT
2006 2006
P-Channel MOSFET ID vs. VDS MOSFET

• As compared to an n-channel MOSFET, the signs • Symbol and subscript convention
of all the voltages and the currents are reversed: – Upper case for both (e.g. VD) = DC signal (often as bias)
Short-channel PMOSFET I-V – Lower case for both (e.g. vd) = AC signal (often small signal)
– Lower symbol and upper sub (e.g. vD ) = total signal = VD+vd
• NMOS: Three regions of operation
Note that the effects – VDS and VGS normally positive valus
of velocity saturation
– VGS<Vt :cut off mode, IDS=0 for any VDS
are less pronounced
than for an NMOSFET. – VGS>Vt :transistor is turned on
• VDS< VGS-Vt: Triode Region iD = K  2(vGS − Vt )vDS − vDS 2 
Why is this the case?
• VDS> VGS-Vt: Saturation Region iD = K  2(vGS − Vt ) 
2
• Boundary v − V = v W KP
GS t DS K=
L 2
2006 2006
MOSFET Bias Circuits
• PMOS: Three regions of operation (interchange • Use load line to find Quiescent operating point.
> and < from NMOS) • Remember no current flow through the gate.
Fixed-plus Self-Bias CKT
– VDS and VGS Normally negative values VDD VDD
– VGS>Vt :cut off mode, IDS=0 for any VDS
– VGS<Vt :transistor is turned on
• VDS> VGS-Vt: Triode Region iD = K  2(vGS − Vt )vDS − vDS 2  RD RD
• VDS< VGS-Vt: Saturation Region iD = K  2(vGS − Vt ) 2  R1
• Boundary vGS − Vt = vDS W KP VG+vin
K=
L 2
R2
RS
2006 2006
MOSFET Circuit Common Source Amplifier
• First look at DC case to find Q point

VDD
– Use load line technique
– All capacitors are open circuit
RD
– From Q-point, get gm and rd for small signal C
R1
AC model
+
• AC Small signal analysis C RL vo
VG -
– DC source is AC ground (because there is no +
+
AC signal variation). v(t) vin R2
RS C
- -
– All capacitors are short circuit (unless
otherwise specified).
2006 2006
Step 1: find Q point Load line
R2
VG = VDD VDD
R1 + R2
VGS = VG − I D RS
VDD = I D ( RD + RS ) + VDS RD C
R1
+
C VG RL vo
VDS -
+ +
v(t) vin R2
- RS C
-
From load lines, we get ID and hence gm and rd
2006 2006
Small Signal Model Source Follower
VDD
For output impedance Rout: R1

vg = vin , vs = 0 → vgs = vin 1. Turn off all independent C
RR sources. VG C
vo = L D (− g m vgs ) 2. Take away load
RL + RD +
impedance RL + vin R2 +
v RR v(t) - RS vo
Av = o = − g m L D - RL
vin RL + RD vin = 0, vgs = 0, g m vgs = 0 -
vin RR rd RD
Rin = = 1 2 Rout =
iin R1 + R2 rd + RD
2006 2006
R2
VG = VDD VDD
R1 + R2
VGS = VG − I D RS
VDD = I D RS + VDS
R1
C
VG C
+ + +
v(t) vin R2
- RS RL vo
- -
From load lines, we get ID and hence gm and rd
2006 2006
Small Signal Model Common Gate Amplifier
VDD
RD C
RL′ =
1 For output impedance Rout: +
rd −1 + RS −1 + RL −1 1. Turn off all independent RL vo
VG
vgs = vin − vo sources. -
vo = g m vgs RL′ 2. Take away RL
vin = vgs (1 + g m RL′ ) 3. Add Vx and find ix
vx = vs , vg = 0, vgs = −vx + + C
vo g m RL′ v(t) vin
Av = = rd Rs v - RS
vin 1 + g m RL′ Rs′ =
rd + Rs Rs′
(
, ix = x − g m (−vx ) = vx Rs′−1 + g m ) -
Rin =
vin RR
= 1 2 1 -VSS
Rout =
iin R1 + R2 g m + rd −1 + Rs −1
2006 2006
VDD
VGS = 0 − I D RS + VSS The only difference in all three circuits are
VDD + VSS = I D ( RD + RS ) + VDS the intercepts at the axes.
RD C Again from load lines, we get ID and
hence gm and rd
+
VG RL vo
-
+ + C
v(t) vin
- - RS
-VSS
2006 2006
Small Signal Model Week 15 (Lec. 14.3-15.2)

• OUTLINE
– Need for Input Controlled Pull-Up
– CMOS Inverter Analysis
– CMOS Voltage Transfer Characteristic
1 For output impedance Rout: – Combinatorial logic circuits
RL′ =
RL −1 + RD −1 1. Turn off all independent – Logic
vgs = −vin sources. – Binary representations
vo = − g m vgs RL′ 2. Take away RL
vo 3. Add Vx and find ix
– Combinatorial logic circuits
Av = = g m RL′
vin R′ =
RRs
R + Rs
• Reading
vgs
iin = −( g m vgs +
Rs
)
ix =
vx
(
+ g m vgs = vx Rs′−1 + g m ) – Chap 7-7.5
RD
Rin =
vin
=
1
vgs = − g m vgs R′ , but g m R′ ≠ 1∴ vgs = 0 – Supplementary Notes Chapter 4
iin g m + Rs −1 Rout = RD
2006 2006
Digital Circuits – Introduction Analog vs. Digital Signals
• Analog: signal amplitude is continuous with time.
• Digital: signal amplitude is represented by a restricted • Most (but not all) observables are analog
set of discrete numbers.
– Binary: only two values are allowed to represent the signal: High
think of analog vs. digital watches
or low (i.e. logic 1 or 0).
• Digital word: but the most convenient way to represent & transmit
– Each binary digit is called a bit information electronically is to use digital signals
– A series of bits form a word think of telephony
• Byte is a word consisting of 8-bits
• Advantages of digital signal
– Digital signal is more resilient to noise can more easily Analog-to-digital (A/D) & digital-to-analog (D/A)
differentiate high (1) and low (0) conversion is essential (and nothing new)
• Transmission think of a piano keyboard
– Parallel transmission over a bus containing n wires.
• Faster but short distance (internal to a computer or chip)
– Serial transmission (transmit bits sequentially)
• Longer distance
2006 2006
Analog Signal Example: Microphone Voltage Digital Signal Representations

Voltage with normal piano key stroke Voltage with soft pedal applied
50 microvolt 440 Hz signal 25 microvolt 440 Hz signal
Binary numbers can be used to represent any quantity.
60 60 We generally have to agree on some sort of “code”, and
V in microvolts
V in microvolts
40 40
20 20
the dynamic range of the signal in order to know the form
0 0 and the number of binary digits (“bits”) required.
-20 0 1 2 3 4 5 6 7 8 9 10 11 12 -20 0 1 2 3 4 5 6 7 8 9 10 11 12
-40 -40
-60 -60 Example 1: Voltage signal with maximum value 2 Volts
t in milliseconds
t in milliseconds
• Binary two (10) could represent a 2 Volt signal.
50 microvolt 220 Hz signal
60
• To encode the signal to an accuracy of 1 part in 64
V in microvolts
40 (1.5% precision), 6 binary digits (“bits”) are needed

20
0 Analog signal representing piano key A,
-20 0 1 2 3 4 5 6 7 8 9 10 11 12 below middle C (220 Hz) Example 2: Sine wave signal of known frequency and
-40
-60
maximum amplitude 50 µV; 1 µV “resolution” needed.
t in milliseconds
2006 2006
Decimal Numbers: Base 10 Numbers: positional notation
Digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 • Number Base B ⇒ B symbols per digit:

–Base 10 (Decimal): 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
–Base 2 (Binary): 0, 1
Example:
• Number representation:
3271 = (3x103) + (2x102) + (7x101) + (1x100) –d31d30 ... d1d0 is a 32 digit number
–value = d31 × B31 + d30 × B30 + ... + d1 × B1 + d0 × B0
This is a four-digit number. The left hand • Binary: 0,1 (In binary digits called “bits”)
most number (3 in this example) is often 11010 = 1×24 + 1×23 + 0×22 + 1×21 + 0×20
referred as the most significant number = 16 + 8 + 2
and the right most the least significant = 26
number (1 in this example). –Here 5 digit binary # turns into a 2 digit decimal #
2006 2006
Hexadecimal Numbers: Base 16 Digital Signal Representations
• Hexadecimal: Binary numbers can be used to represent any quantity.
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F We generally have to agree on some sort of “code”, and

the dynamic range of the signal in order to know the form
–Normal digits + 6 more from the alphabet and the number of binary digits (“bits”) required.
⇔Hex
• Conversion: Binary⇔
Example 1: Voltage signal with maximum value 2 V and
–1 hex digit represents 16 decimal values minimum of 0 V.
–4 binary digits represent 16 decimal values • Binary two (10) could represent a 2 Volt signal.
⇒1 hex digit replaces 4 binary digits
• To encode the signal to an accuracy of 1 part in 64
(1.5% precision), 6 binary digits (“bits”) are needed
Example 2: Sine wave signal of known frequency and

maximum amplitude 50 µV; 1 µV “resolution” needed.
2006 2006
Resolution Decimal-Binary Conversion
• The size of the smallest element that can • Decimal to Binary

be separated from neighboring elements. – Repeated Division By 2
The term is used to describe imaging • Consider the number 2671.
systems, the frequency separation – Subtraction – if you know your 2N values by
achieved by spectrometers, and so on. heart.
• Binary to Decimal conversion
1100012 = 1x25 +1x24 +0x23 +0x22 + 0x21 + 1x20
= 3210 + 1610 + 110
= 4910
= 4x101 + 9x100
2006 2006
Example 2 (continued) Binary Representation

Possible digital representation for the sine wave signal: • N bit can represent 2N values: typically
Analog representation: Digital representation: from 0 to 2N-1
Amplitude in µV Binary number
1 000001 – 3-bit word can represent 8 values: e.g. 0, 1, 2,
2 000010
3 000011
3, 4, 5, 6, 7
4 000100
5 000101 • Conversion
8 001000 – Integer to binary
16 010000 – Fraction to binary (13.510=1101.12 and
32 100000
0.39210=0.0110012)
50 110010 • Octal and hexadecimal
63 111111
2006 2006
Boolean algebras
• Logic gates • Algebraic structures

– "capture the essence" of the logical operations AND,
– Combine several logic variable inputs to OR and NOT
produce a logic variable output – corresponding set for theoretic operations
• Memory intersection, union and complement
– named after George Boole, an English mathematician
– Memoryless: output at a given instant at University College Cork, who first defined them as
depends the input values of that instant. part of a system of logic in the mid 19th century.
– Momory: output depends on previous and – Boolean algebra was an attempt to use algebraic
techniques to deal with expressions in the
present input values. propositional calculus.
– Today, Boolean algebras find many applications in
electronic design. They were first applied to switching
by Claude Shannon in the 20th century.
2006 2006
Boolean algebras Boolean Algebra

• The operators of Boolean algebra may be • NOT operation (inverter)
A A=0
represented in various ways. Often they are
simply written as AND, OR and NOT. • AND operation A+ A =1
A A= A
• In describing circuits, NAND (NOT AND), NOR
(NOT OR) and XOR (eXclusive OR) may also be A 1= A
used. A 0=0
• Mathematicians often use + for OR and · for A B=B A
AND (since in some ways those operations are • OR operation
( A B) C = A ( B C )
analogous to addition and multiplication in other
algebraic structures) and represent NOT by a A+ A = A
line drawn above the expression being negated. A +1 = 1
A+0 = A
A+ B = B + A
( A + B) + C = A + ( B + C )
2006 2006
Graphic Representation Graphic Representation
A A=0 A+ B
A A+ A =1 A
A AB B
A ⊕ B = AB + AB = ( A + B ) ( A + B ) = A B + A + B
Full square = complete set =1 Exclusive OR=yellow and blue part –
Yellow part = NOT(A) =A intersection/overlap part
White circle = A =exactly when only one of the input is true
2006 2006
Boolean Algebra Examples
• Distributive Property F = A•B•C + A•B•C + (C+D)•(D+E)

A (B + C) = A B + A C
( A + B) C = ( A + B) ( A + C )
• De Morgan’s laws
A+ B = A B
A B = A+ B
• An excellent web site to visit
– http://en.wikipedia.org/wiki/Boolean_algebra
F = C•(A+D+E) + D•E
2006 2006
Logic Functions, Symbols, & Notation Logic Functions, Symbols, & Notation 2
TRUTH A B F
NAME SYMBOL NOTATION TABLE A 0 0 1
“NOR” F F = A+B 0 1 0
A F B 1 0 0
0 1 1 1 0
“NOT” A F F=A 1 0
A B F
A B F 0 0 1
0 0 0 A
A “NAND” F F = A•B 0 1 1
“OR” F F = A+B 0 1 1 B 1 0 1
B 1 0 1 1 1 0
1 1 1
A B F
A B F
A 0 0 0 “XOR” A F F=A+B
0 0 0
“AND” F F = A•B 0 1 0 (exclusive OR) B
0 1 1
1 0 1
B 1 0 0
1 1 0
1 1 1
2006 2006
Circuit Realization Logic Functions, Symbols, & Notation

TRUTH
A ⊕ B = AB + AB = ( A + B) ( A + B) = A B + A + B
NAME SYMBOL NOTATION TABLE
A A F
0 1
A AB “NOT” A F F=A 1 0
B A⊕ B
B A B F
0 0 0
A
“OR” F F = A+B 0 1 1
AB B 1 0 1
1 1 1
A B F
“AND” A F F = A•B
0 0 0
0 1 0
B 1 0 0
1 1 1
2006 2006
Logic Functions, Symbols, & Notation 2 Fan in/Fan out
A B F • Complex digital operations are formed with a
A 0 0 1 variety of gates interconnected to yield the
“NOR” F F = A+B 0 1 0
desired logic function.
B 1 0 0
1 1 0 • Sometimes a number of inputs are connected to
one gate input and output of a gate may be
A B F connected to a number of gates.
0 0 1
A • Fan-in: the maximum number of logic gates that
“NAND” F F = A•B 0 1 1
B 1 0 1 can be connected at the input of a gate without
1 1 0
altering its performance.
A B F
• Fan-out: the maximum number of logic gates
A 0 0 0 that can be connected to the output of a gate
“XOR” F F=A+B 0 1 1 without altering its performance.
(exclusive OR) B 1 0 1
1 1 0 • Typical fan-in and fan-out numbers are 3.
2006 2006
Inverter = NOT Gate Terminology for a Logic Circuit
VDD = Power supply voltage (D is from

Vin Vout Drain) we do not draw the symbol.
VDD
Pull-Up Network = Set of devices used to
carry current from the power supply to
Ideal Transfer Characteristics the output node to charge the output
RPULL UP
node to the power supply voltage.
Vout IOUT Output Pull-Down Network = Set of devices used to
carry current from the output node to ground to
discharge the output node to ground.
VOUT
Pull-Down
VIN (NMOS) IOUT = Current for the device under study.
Vin VTD = Threshold Voltage value of VIN at which the

V/2 V Pull-Down (NMOS transistor) begins to conduct.
VOUT-SAT-D = Value of VOUT beyond which the current IOUT-D
saturates at the (drain) current saturation value IOUT-SAT-D.
2006 2006
Thevenin Model For Pull-Up Device Load Line For Pull-Up Device
IOUT vs. VOUT

VDD For the Pull-Up Resistor and VDD
IOUT(µA)
RPULL UP 100
IOUT vs. VOUT is constrained to be on this line
by the circuit external to the three-terminal
Output device
IOUT
VTHEVENIN = VDD 60
IOUT SHORT CIRCUIT = (VDD/RPULL UP) INORTON
Example: Thevenin VOUT
VDD = 5V and RPULL UP = 100kΩ looking VTHEVENIN
this way 20
VTHEVENIN = 5V
IOUT SHORT CIRCUIT = 50 µA
0 3 5 VOUT(V)
2006 2006
NMOS Resistor Pull-Up Disadvantages of NMOS Logic Gates

VDD
Circuit: Voltage-Transfer Characteristic
vOUT • Large values of RD are required in order to
RD
iD – achieve a low value of VOL
VDD
+
F – keep power consumption low
A
+
vDS = vOUT
iD vIN
vIN = VDD
– – Large resistors are needed, but these take
0 VT VDD
vIN up a lot of space.
VDD/RD • One solution is to replace the resistor with an
NMOSFET that is always on.
increasing
vGS = vIN > VT A F
0 1
vDS 1 0
0 vGS = vin ≤ VT VDD
2006 2006
The CMOS Inverter: Intuitive Perspective CMOS Inverter Voltage Transfer Characteristic
N: sat
CIRCUIT SWITCH MODELS P: sat
VDD
VOUT
VDD VDD VDD N: off G S
P: lin C
VDD D
G S VIN VOUT
Rp N: sat D
P: lin
D G
S
VIN VOUT VOUT VOUT A B D E
D VOL = 0 V VOH = VDD
N: lin
G
Rn P: sat
S
N: lin
P: off
0 VIN
Low static power consumption, since
VIN = VDD VIN = 0 V 0 VDD
one MOSFET is always off in steady state
2006 2006
CMOS Inverter Load-Line Analysis CMOS Inverter Load-Line Analysis: Region A

V VDD V VDD
VIN = VDD + VGSp
GS
p =V – VIN ≤ VTn GS
p =V –
IN -V – IN -V –
DD DD
VOUT = VDD + VDSp VDSp=VOUT-VDD VDSp=VOUT-VDD
IDn=-IDp + IDn=-IDp +
+ +
VIN VOUT VIN VOUT
increasing VIN = 0 V VIN = VDD IDn=-IDp IDn=-IDp
VIN
increasing
VIN
0 VOUT=VDSn 0 VOUT=VDSn
0 VDD 0 VDD
VDSp = - VDD VDSp = 0
2006 2006
CMOS Inverter Load-Line Analysis: Region B CMOS Inverter Load-Line Analysis: Region D
V VDD V VDD
VDD/2 > VIN > VTn GS
p =V – VDD – |VTp| > VIN > VDD/2 GS
p =V –
IN -V – IN -V –
DD DD
VDSp=VOUT-VDD VDSp=VOUT-VDD
IDn=-IDp + IDn=-IDp +
+ +
VIN VOUT VIN VOUT
IDn=-IDp IDn=-IDp
0 VOUT=VDSn 0 VOUT=VDSn
0 VDD 0 VDD
2006 2006
CMOS Inverter Load-Line Analysis: Region E Features of CMOS Digital Circuits

V VDD
VIN > VDD – |VTp| GS
p =V –
IN -V – • The output is always connected to VDD or GND
DD
VDSp=VOUT-VDD in steady state
IDn=-IDp +
+ → Full logic swing; large noise margins
VIN VOUT
IDn=-IDp
→ Logic levels are not dependent upon the relative
sizes of the devices (“ratioless”)
• There is no direct path between VDD and GND

in steady state
→ no static power dissipation
0 VOUT=VDSn
0 VDD
2006 2006
The CMOS Inverter: Current Flow during Switching Power Dissipation due to Direct-Path Current
N: sat
VDD VDD
VOUT P: sat i VDD-VT
N: off S
vIN:
G
VDD P: lin C
VDD D VT
vIN i vOUT
0
G S
N: sat
P: lin
D Ipeak
D
G
VIN i VOUT S
i:
D A B D E
G
S N: lin
0
P: sat tsc
time
N: lin
P: off
0 VIN
0 VDD Energy consumed per switching period: Edp = t scVDD I peak
2006 2006
NMOS NAND Gate NMOS NOR Gate

• Output is low only if both inputs are high • Output is low if either input is high
VDD
VDD
RD
RD
F
F
A
A B
Truth Table Truth Table
A B F A B F
B 0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
2006 2006
N-Channel MOSFET Operation P-Channel MOSFET Operation
An NMOSFET is a closed switch when the input is high A PMOSFET is a closed switch when the input is low
A A
A B A B
B B
X Y X Y X Y X Y
Y = X if A and B Y = X if A and B
Y = X if A or B = (A + B) Y = X if A or B
= (AB)
NMOSFETs pass a “strong” 0 but a “weak” 1
PMOSFETs pass a “strong” 1 but a “weak” 0
2006 2006
Pull-Down and Pull-Up Devices CMOS NAND Gate

• In CMOS logic gates, NMOSFETs are used to connect VDD
A B F
the output to GND, whereas PMOSFETs are used to 0 0 1
connect the output to VDD. 0 1 1
– An NMOSFET functions as a pull-down device when it 1 0 1
is turned on (gate voltage = VDD) A B 1 1 0
– A PMOSFET functions as a pull-up device when it is

turned on (gate voltage = GND)
VDD
F
A1 A
A2 Pull-up
input signals PMOSFETs only
…
AN network
F(A1, A2, …, AN)
A1 B
A2 Pull-down
NMOSFETs only
…
AN network
2006 2006
CMOS NOR Gate CMOS Pass Gate
VDD
A B F
0 0 1
0 1 0
A
A 1 0 0
1 1 0
B X Y Y = X if A
F
B A
A
2006 2006

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Introduction EE 40 Course Overview

• Instructor: Prof. Connie Chang-Hasnain • EECS 40:

Important DATES Grading Policy

Week 1 Electric Charge

Electric Current Electric Current Examples

Q 105 ×1.6 ×10−19

Suppose we force a current of 1 A to flow from C1 to C2:

Electric Potential (Voltage) Electric Power

Attributes: • In this case, if the current turns out to be 1 mA

Sign Convention Example Another Example

Which is the positive battery

How can a circuit element absorb power?

Power Calculation Example Circuit Elements

independent voltage-controlled current-controlled

Ideal Current Source Electrical Resistance

where v = voltage (V), i = current (A), and R = resistance (Ω)

Example: Power Absorbed by a Resistor More Examples

V>0 absorb power; V<0 release power

Construction of a Circuit Model Terminology: Nodes and Branches

• We need to account for undesired as well

Gustav Robert Kirchhoff

Formulation 3: Current entering node = Current leaving node

KCL Example Generalization of KCL

• Use reference polarities to determine whether a

Formulations of Kirchhoff’s Voltage Law A Major Implication of KVL

Formulation 3: Applying KVL in the clockwise direction,

1 2 • Note: Antennas are designed to “pick up”

Path 1: How do we deal with antennas (EECS 117A)?

Path 2: Include a voltage source as the circuit representation

I-V Characteristic of Elements Resistors in Series

Equivalent resistance of resistors in series is the sum

Resistors in Parallel General Formula for Parallel Resistors

Equivalent conductance of resistors in parallel is the sum

Summary Summary (cont’d)

– Norton equivalent circuits

Effect of Voltmeter Measuring Current

Node-Voltage Circuit Analysis Method Nodal Analysis: Example #1

Nodal Analysis: Example #3 Formal Circuit Analysis Methods

1. Select M mesh currents.

Mesh Analysis: Example #2 Mesh Analysis with Dependent Sources

Source Combinations Superposition

Equivalent Circuit Concept Thévenin Equivalent Circuit

I-V characteristic of voltage source: v = VTh

RTh Calculation Example #1 Norton Equivalent Circuit

Norton equivalent circuit

Finding IN and RN Maximum Power Transfer Theorem

source transformation: + iL  VTh 

Finding the value of Rx Finding the value of Rx

KCL => i1 = i3 and i2 = ix

R1 R2 R1 R2 KVL => i3R3 = ixRx and i1R1 = i2R2

RbRc RaRc RaRb

Delta-to-Wye (Pi-to-Tee) Equivalent Circuits ∆-Y and Y-∆

RaRc c R1R2 + R2R3 + R3R1

Comments on Dependent Sources Node-Voltage Method and Dependent Sources

Arrows represent voltage drops

Potential Plot for Two Resistors in Parallel The Capacitor

R2 Q = CVab (stored charge in terms of voltage)

where C is the capacitance of the structure,

C C Electrolytic (polarized) Q(t ) = ∫ ic (t )dt + Q(0)

Note: Q (vc) must be a continuous function of time

Stored Energy A more rigorous derivation

Capacitors in Series Capacitive Voltage Divider

with incident light I m .Vm FF Voc I sc Voc - Open circuit voltage