Advanced Courses in Power Electronic

ADVANCED
ADVANCEDPOWER
POWERELECTRONICS
ELECTRONICS
SEMICONDUCTOR SWITCHES:
—LOSSES & PROTECTION —
Dr. Adel Gastli

Email: adel@gastli.net
http://adel.gastli.net
CONTENTS
1. Introduction
2. Switching Losses
3. Snubbering: Protection of Switching Devices
4. Zero-Current Switching
5. Zero Voltage Switching
6. Summary
Dr. Adel Gastli Semiconductor Switches: Losses & Protection 2

Section 1
INTRODUCTION
Switches are very important and crucial
components in power electronic systems.
They are a substitution of the mechanical
switches, but they are severely limited by the
properties of the semiconductor materials and
the process of manufacturing.
This chapter will examine the losses incurred
during the switching process in a generic
(standard) switch.
Section 2
SWITCHING LOSSES
Losses in switches are characterized

as Switching losses.
These losses are:
– On-state losses
– Off-state losses
– Losses in transition states.

ON-STATE LOSSES
In on state the electric switches have non zero
voltage across them.
The on-state losses are: on son f P =v i
Switch voltage in Forward current
on-state through the
switch
Typical power diodes and transistors have nearly
0.5 to 1 volt on-state voltage across them. The
forward currents can be hundreds of amperes.
amperes
The on-state losses are very significant.
OFF-STATE LOSSES
In off state the electric switches withstand high voltages
and have nonzero leaking current through them.
The off-state losses are:
Poff = vsoff ir
Switch reverse Reverse current
bias voltage in through the
off-state switch
Typical power diodes and transistors have high
reverse off-state voltage across them in
hundreds to thousands of volts.
volts The reverse
currents can be microamps to milliamps.
milliamps
TRANSIENT-STATE LOSSES
Practical switches have limited capabilities
of rate of voltage transition and rate of
current steering.
These nonabrupt transition rates give rise
to power losses in the switching devices.
These losses will be examined for two
types of loads; inductive and capacitive
loads.
Switching with Inductive Load
L >> ⇒ I o = constant
Load inductance Load current
D
L
At t=0 S is off + Io
Io
Freewheel
through diode
+
_ vs S

D
When S is turned on:
L
vD=0 (ideal) Io
+
vswitch = +Vs _ vs S
Switch current builds up to +Io linearly (assumption).
Diode ceases to conduct Switch voltage ramps linearly

down to zero (assumption)
vswitch = 0 (ideal)
D
When S is turned off: L
Io
+
Switch voltage builds up to +Vs _ vs S
linearly while diode is off.
I switch = + I o
After Switch voltage builds up to +Vs the current starts
decreasing.
Diode starts to conduct Switch current ramps linearly
down to zero (assumption)
I switch = 0 (ideal)
D
Switch on
L
Vs
Io
vsw
+
isw _ vs S
Io
Psw
ton1 ton2 Ts toff1 toff2

D turns off D turns on
Psw = Vs I o [ton1 + ton 2 + toff 1 + toff 2 ] f s s max t + t + t + t

1 f =
1
2 on1 on 2 off 1 off 2
Switching power loss

Maximum switching frequency
Switching with Capacitive Load
C >> ⇒ Vo = constant
Load capacitance Load voltage Io
At t=0 S is on Io = I s Is +
Vo
S
−
vsw = 0 C
Diode is reverse biased and does not conduct

Io
When S is turned off
Switch voltage ramps linearly up to +Vo Is + S

Vo
While diode is still off and I switch = I s C −
After build up is over, the diode begins to conduct. Vsw = Vo
Current through switch ramps linearly down to zero.
I switch = 0
Switch turns off
When S is closed Io
Is +
Switch current builds up to Is Vo
S
C −
linearly while diode is on.
vsw = +Vo
After Switch current builds up to Is the diode turn off.
Switch voltage ramps linearly down to zero.
vsw = 0 (ideal)
Io
Switch off
Vo
vsw Is + S
Vo
C −
Io
isw
Psw
ton1 ton2 Ts toff1 toff2

D turns on D turns off
Psw = Vs I o [ton1 + ton 2 + toff 1 + toff 2 ] f s s max t + t + t + t

1 f =
1
2 on1 on 2 off 1 off 2
Switching power loss

Maximum switching frequency
Minimizing Switching Losses
Divert the energy from the switch to a

lossy or non-lossy circuit (Snubbering).
Switch at either zero current or at zero

voltage.

Section 3
SNUBBERING: PROTECTION OF
SWITCHING DEVICES
Limit stresses on the switch to safe

values.
Divert energy during switching transition
from the switch to another circuit. Thus,
reduce power losses in the switch.
Switch stresses:
Maximum transient voltage Protection is required at turn-
on and turn-off of power and
Maximum transient current in overvoltage conditions.
Rate of voltage change dv/dt High rate of voltage and

current transition give rise to
Rate of current change di/dt local hot spots in the switch
that may permanently
damage the devices.
Special circuits are used to slow down the high rate of

transition. These circuits are called snubbering circuits.

TURN-OFF SNUBBER
L Io
R
Inductor L maintains a dc current
Io. It reduces the switching losses
D1 isw
by reducing the voltage across the D2
switch during the transition of Vs +
vsw C
current through the switch. −
Assumptions:
In the following we assume ideal diodes and ideal switch.
The switch is also assumed to have limited maximum rates

of rise and fall transitions of voltage and current.
Without Snubber Capacitor L Io

Prior to turnoff:
D1 isw
isw = I o vsw = 0 D1 is off
+
Vs v sw
−
During turnoff:
vsw : 0 ↑ Vs (linearly) in time t f 1
isw = I o until t = t f 1
D1 remains off until vsw = Vs
t > t f 1 ⇒ isw : I o ↓ 0 (linearly) for duration t f 2
⎛ t ⎞ ⎛ ⎞
Current diverted
isw = I o ⎜1 − ⎟ ⎜ I o − isw = I o t ⎟ through D1 for
⎜ t ⎟ ⎜
⎝ t f 2 ⎟⎠ freewheeling
⎝ f2 ⎠
through L.
Waveforms of voltage current trough switch (without C)
15
Io isw
10
Vs
vsw
tf1
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
t +tf2
2 f1
-6
x 10
Power loss in the switch

120
100
80 Without C
60
40
20
With C
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-6
x 10

Switching trajectory
15
Without C
10
isw
5
With C
0
Vs
0 1 2 3 4 5 6 7 8 9 10
vsw
With Snubber Capacitor L Io

R
Prior to turnoff:
isw = I o vsw = 0 D1 is off D1 isw
D2
Vs +
vsw
During turnoff: −
C
isw : I o ↓ 0 (linearly) in time t f 2

⎛ t ⎞⎟ ⎛ ⎞ Current diverted through
⎜
isw = I o 1 − ⎜ I o − isw = I o t ⎟ D and C and charges
⎜ t ⎟ ⎜
⎝ t f 2 ⎟⎠ 2
⎝ f2 ⎠ capacitor.
1 t 1 Io t 2
vsw = vc = ∫ ( I 0 − isw )dt = vc = vsw : 0 ↑ Vs
C 0 2 C tf2

Waveforms of voltage current trough switch (with C)
15
Io iC
isw
10
Vs
vsw
5
tf 2
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-6
x 10
tf2 is determined by the value of the capacitor.
I ot f 2
C=
2Vs
vsw rises with a small slope.
Note that the initial holding time tf1 for the switch
current at Io is absent.
I o2 ⎛⎜ t ⎞⎟ 2
psw = vswisw = 1− t
⎜ ⎟
2Ct f 2 ⎝ t f 2 ⎠

120
Power loss in the switch
100
80 Without C
60
40
20
With C
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-6
x 10
Note the very significant reduction in the power

loss through the switch in comparison with the
case without C.
The maximum rate of dvsw/dt occurs when the

current has dropped to a low or zero value.
dvsw Io t
max =
dt C tf 2 dvsw Io
max =
t dt C
t ≈ tf2 ⇔ ≈1
tf2
This equation can be used to calculate the

capacitance required for a switch with a specified
maximum dv/dt (slew) rating.

Circuit behavior during turn on
L Io
R
First, let’s consider R=0.
D1 isw
Prior to turnon: +
D2
Vs v sw C
I o freewheels in D1 and L −
D2 is short - circuited and vc = Vs

During turnon:
D1 stays on until isw=Io ⇒ vsw = Vs until isw = I o
When isw = I o ⇒ vsw : Vs ↓ 0 (voltage decrease rate is a function
of snubber circuit capacitor)
isw : I o ↑ I rr + I o until vsw = 0 ⇒ isw : I rr + I o ↓ I o

I rr
Vs
Io
isw vsw
tr t
I rr Current overshoot is determined by the amount of the

charge of C and by the characteristic of diode D1.

A non-zero resistance R takes away the capacitor
energy in the form of heat out of the system thus
retarding the current rise beyond Io.
Diode D2 isolates the rate of fall of the switch

voltage from the snubber capacitor.
Designers restrict the amount of current overshoot

to 20% of Io by selecting R from the following
equation:
Vs
R=
0.2 I o
TURN-ON SNUBBER
Reduces switching losses by
reducing vsw during current D1
Io
transition through switch.
D
Assumptions: Vs +
L R
In the following we assume ideal −
diodes and ideal switch.
vsw+
The switch is also assumed to have −
limited maximum rates of rise and fall isw
transitions of voltage and current.

Prior to turnon:
D1 Io
vsw = Vs isw = 0
D2
D1 is on Vs +
L R
−
During turnon:
t v sw +
isw : 0 ↑ I o (linearly) in time tr isw = I o −
i sw
tr
isw overshoots beyond Io with an amount Irr which depends
on energy stored in snubber inductor and characteristic of
D1.
isw flows also through the snubber inductor, hence, the
inductor voltage instantly reduces vsw to zero.
disw LI o
vsw = Vs − L = Vs −
dt tr
I rr
Io Io
Vs
disw isw
L
dt
vsw
tr t
⎡ LI o ⎤ t
psw = vswisw = Vs I o ⎢1 − ⎥t
⎣ t r s⎦ r
V

Circuit behavior during turn off D1 Io
First, let’s consider R=∞. D2

Vs +
Prior to turnoff: isw = I o , vsw = 0 L
−
R
v sw +
During turnoff: isw = I o ⇒ vsw : 0 ↑ Vs −
i sw
D
1
v+
− sw
(linearly at rated dv/dt)

When vsw = Vs ⇒ D1 turns on ⇒ current I o freewheels.
isw : I o ↓ 0 Inductor energy (1/2LIo2) is
dumped over to the switch.
vsw overshoots and falling rate of isw decreases.
A finite resistance R takes over the inductor energy as heat,
thus retarding voltage overshoot.
OVERVOLTAGE PROTECTION
SNUBBER
So far the role of parasitic inductance of the
conductors in the switching process has been
ignored.
This inductance must be added to the circuit in
series with the source.
Turnoff Voltage
Ls spike Drawback
D1 Io
Vs
Io
i sw isw
Vs vsw
v sw +
− tr t

The following circuit is able to protect the switch
from over voltage.
L D1
Io R Vs
vsw
isw
Io
isw D2
Vs +
v sw C
−
tr t
Prior to turnoff, the snubber capacitor is charged to

Vs through R. Diode D2 is reverse-biased. During
turnoff, Diode D2 clamps the switch to Vs.
SIMULINK SIMULATION
Run ‘psbswitch’ Simulink demo example of ideal
switch with series R-C snubber circuit. (Matlab 6).
VC
1 2 +
v
-
g m
Timer Ideal Switch

+
I_load
-
i
I_load
V_load R
120 Vrms
60 Hz
C
DemuxI_switch L
V_switch
Demux Scope
?
powergui Ideal Switch in switching circuit
More Info
Double click on the More Info button (?) button for details

Section 4
ZERO-CURRENT SWITCHING
Turning on and off switches at zero current is the surest
way of minimizing switching losses.
An inductor in series with the switch will ensure zero
current turn on because current through inductor cannot
build instantaneously.
However, turn off at zero current is impossible.
Adding one capacitor in parallel with the inductor enables
both switchings at zero current.
During turn off L dumps its
C energy on C through D
enabling switch to turn off at
L Sw
zero current.
Section 5
ZERO-VOLTAGE SWITCHING
Turning on and off switches at zero voltage is also the
surest way of minimizing switching losses.
An capacitor in parallel with the switch will ensure zero
voltage turn off because voltage on capacitor cannot build
instantaneously.
However, turn on at zero voltage is not possible.
Adding a diode in series with the capacitor enables both
switchings at zero voltage. (see also turn-off snubber)
During turnoff, D conducts and C
C permits slow voltage buildup on switch.
During turnon, D prevents C to
Sw
discharge through Sw.
SUMMARY
This chapter has covered the power switch
losses involved during on-off switching.
It has also presented the means of

minimizing those losses and protecting the
switches using snubbing circuits, zero-
current switching, or zero-voltage switching.

ADVANCED
ADVANCEDPOWER
POWERELECTRONICS
ELECTRONICS
FIRING CIRCUITS
C1
RD
V 10
1n
Rs R1 M1 VDD
IRF740
80Vdc
0.1 100
V1 = 0 V2
V2 = 15 RG
TD = 0 1k I
TR = 0
TF = 0
PW = 2.5u
PER = 5u
Dr. Adel Gastli

CONTENTS
1. MOSFET Gate Drive

2. BJT Base Drive
3. Isolation of Gate & Base Drives
4. Thyristor Firing Circuit
5. Thyristor Converter Gating Circuit
6. Summary
(Textbook: Sections 17.2, 17.3, 17.4, 17.5, 17.8)
Dr. Adel Gastli Firing Circuits 2

MOSFET Gate Drive
The turn on time of a
MOSFET depends
on the charging time
of the input or gate
capacitance.
The turn-on time can be reduced by connecting an RC

circuit as shown in the figure to charge the gate
capacitance faster
C1
RD
V 10
1n
Rs R1 M1 VDD
IRF740
80Vdc
0.1 100
V1 = 0 V2
V2 = 15 RG
I
TD = 0 1k
TR = 0
TF = 0
PW = 2.5u
PER = 5u
OrCAD circuit simulation

C1=1pF
88.4
75.0
50.0
25.0
2.6us 3.0us 3.5us 4.0us 4.5us 5.0us 5.4us

ID(M1)*5 V(M1:d)
Time
C1=1nF
95
75
50
25
2.51us 3.00us 3.50us 4.00us 4.50us 5.00us 5.27us

V(M1:d) ID(M1)*5
Time

C1=100nF
87.6
75.0
50.0
25.0
2.475us 2.800us 3.200us 3.600us 4.000us 4.400us 4.800us 5.150us

ID(M1)*5 V(M1:d)
Time
When the gate voltage is turned on, the initial

charging current of the capacitance is
IG
VG
IG =
RS + RGS RGS
and the steady state value of gate voltage is

RGVG Typically between 10 and
VGS = 20V in on-state
RS + R1 + RG
where the steady-state

IG
gate-source current is
considered negligible.
In order to achieve switching
speeds of the order of 100 ns or
less, the gate-drive circuit should
have:
– a low output impedance and
– the ability to sink and source
relatively large currents.
Turn off Turn on

100
50
Gate current
-50 Sink
-100
0s 1.0us 2.0us 3.0us 4.0us 5.0us 6.0us
-I(VDD)*5 V(M1:d) IG(M1)*500
Source
Time

A totem-pole arrangement that is capable of
sourcing and sinking a large current is shown in
below.
The PNP- and NPN-
transistors act as
emitter followers and
offer a low
impedance.
These transistors
operate in the linear
region rather than in
saturation mode,
thereby minimizing
the delay time.
The gate signal for the

power MOSFET may be
generated by an op-
amp.
Feedback via the capacitor C regulates the rate of rise

and fall of the gate voltage, thereby controlling the rate
of rise and fall of the MOSFET drain current.
A diode across the capacitor C allows the gate voltage
to change rapidly in one direction only.
There are a number of integrated drive circuits on the
market that are designed to drive transistors and are
capable of sourcing and sinking large currents for most
converters.

VG
0 RD
-15Vdc 10
V
Q1
VDD
R1 Q2N5223
Q3 M1
Q2N5226 D1 80Vdc
1k I
V1 = 0 Dbreak
V2 = 10 V2
TD = 0 IRF740
TR = 0
TF = 0
PW = 2.5us
PER = 5us
0 0
87
75
50
25
2.54us 3.00us 3.50us 4.00us 4.50us 5.00us

ID(M1)*5 V(M1:d)
Time

Key Points
A MOSFET is a voltage-controlled
device.
Applying a gate voltage turns it on

and it draws negligible gate current.
The gate drive circuit should have

low impedance for fast turn-on.
BJT BASE DRIVE
The transistor turning-on time (ton) can be

reduced by allowing base current peaking
during turn-on, resulting in low forced
gain (βF) at the beginning.
After turn on, βF can be increased to a

sufficiently high value to maintain the
transistor in quasi-saturation region.

The turn off time (toff) can be reduced by
reversing base current and allowing base
current peaking during turn-off.
Increasing the reverse base current IB2
decreases the storage time.
Commonly used iB
techniques for optimizing IB1
the base drive are: IBs
– Turn-on control
– Turn-off control t
– Proportional base control -IB2
– Antisaturation control
C1
Turn-on control R1 R2 IB
C IC RC
+
+ VC1 _ +
V −V Limits base current VB
_
E IE _ VCC
I B = 1 BE when VB turns on
R1
(VC1=0)
vB
V1
V −V Final base current 0

t1 t2
I BS = 1 BE t
R1 + R2 value (VC1=IBSR2)
R2 Final C1 charge up vB=0

VC1 ≅ V1
R1 + R2 voltage Base-emitter junction
becomes reverse biased
R1 R2C1 Capacitor charging and C1 discharges through
τ1 =
R1 + R2 time constant R2.
2.0A
Base Current
0A
-2.0A
IB(Q1)
100 Collector-Emitter Voltage
Collector Current
0
-100
V(RC:2) IC(Q1)*5
2.0A
Current in R2
0A
SEL>>
Current in C1
-2.0A
0s 20us 40us 60us 80us 100us 120us
I(R2) I(C1)
Time
Turn off Turn on
Zooming on turn-off transition

2.0A
0A
SEL>>
Negative base current
-2.0A
IB(Q1)
100
-100
V(RC:2) IC(Q1)*5
Capacitor discharge current
1.0A
0A
-1.0A
-2.0A
50.00us 51.00us 52.00us 53.00us
I(R2) I(C1)
Negative currentTime
in R2

Zooming on turn-on transition
1.0A
0.5A
Positive base current (fast current increase)
SEL>>
-0.1A
IB(Q1)
100
-100
V(RC:2) IC(Q1)*5
Capacitor charge current (fast current increase)

1.0A
0A
100us 101us 102us 103us
I(R2) I(C1)
Positive current in
TimeR2 (slow current increase)
R1 R2C1
τ1 = Capacitor charging time constant
R1 + R2
τ 2 = R2C1 Capacitor discharging time constant
To allow sufficient charging and discharging times, the
width of the pulse must be t1 ≥ 5τ 1 and the off period
of the pulse must be t 2 ≥ 5τ 2

The maximum switching frequency is:
1 1 0.2
f s max = = =
Tmin t1 + t 2 τ 1 + τ 2
C1
100n
RC
I Q1 V
R1 R2
10
I
5 15
V1 = 0 V2 MRH1240N/125C
V Vcc
V2 = 15V
I
I
TD = 0 80Vdc
TR = 0
TF = 0
PW = 50us
PER = 100us
PSpice Simulation
0.66A
0A
-1.00A
-1.56A
50.0us 52.0us 54.0us 56.0us
IB(Q1) I(R2) I(C1)
Time
Capacitor provides a negative current spike as the base

charge is removed. Then, the capacitor continues
discharging through R2.
C1
Turn-off control R1 R2 IB
C IC RC
+
+ VC1 _ +
VB E IE
vB = −V2 _
_ VCC
vB
VBE = −(VC + V2 ) V1
t1 t2
t
Reverse voltage across transistor
-V2
base-emitter junction
vB<0
Base-emitter junction
As C1 discharges, reverse voltage
becomes reverse biased
is reduced to steady-state value
and C1 discharges through
-V2
R2.
C1
vB R2 D1
V1
t1 t2 C IC RC
R1 R3 R4 IB
t
+
-V2 +
VB E IE _ VCC
_ C2
Base current peaking during turn-on and turn-off
If different turn-on and turn-off characteristics are

required, a turn-off circuit (using C2 R3, and R4), as
shown in the above Figure, should be added.
The diode D1 isolates the forward base drive circuit

from the reverse base drive circuit during turn-off.

Proportional control
This type of control has advantages over the constant drive
circuit.
If the collector current changes due to change in load demand,
the base drive current is changed in proportion to the collector
current.
When S1 turns on Pulse current flows through Q1 base.
Q1 turns on into saturation IC starts flowing
Corresponding
base current is
induced due to
transformer
action.
Transistor would latch on itself, and S1 can be turned off.
Transformer turns ratio is
N2 IC
= =β
N1 I B
For proper operation of the circuit, the magnetizing current,

which must be much smaller than the collector current,
should be as small as possible.
Switch S1 can be implemented by a small-signal transistor,
and an additional circuitry is necessary to discharge capacitor
C1 and to reset the transformer core during turn-off of the
power transistor, which makes the circuit complex and
expensive.
Antisaturation control
If the transistor is driven hard, the storage time, which is
proportional to the base current, increases and the switching
speed is reduced.
The storage time can be reduced by operating the transistor in

soft saturation instead of hard saturation.
This can be accomplished by clamping the collector-emitter

voltage to a pre-determined level and the collector current is
given by V Cut-off Active
Saturation
CE
VCC − Vcm Clamping voltage

IC = Vcm > VCE (sat )
RC Soft Hard
IB
Without clamping, the base current is adequate to drive transistor hard.

VB − Vd 1 − VBE I2=IC-IL
I B = I1 = IL
RB + Vd2 _
C IC RC
I C = βI B RB
I1
IB
VCE
+
After IC rises, transistor turns VB + Vd1 _ I +
VBE E E _ VCC
on, and clamping takes place _ C2
(due to the fact that diode D2
Collector clamping circuit
gets forward biased and (Baker’s Clamp)
conducts)
VCC − VCE VCC − VBE − Vd 1 + Vd 2

VCE = VBE + Vd 1 − Vd 2 IL = =
RC RC
β
I C = β I B = β ( I1 − I C + I L ) = ( I1 + I L )
1+ β
For clamping, Vd1>Vd2 and this can be accomplished by
connecting two or more diodes in place of D1.
Load resistance RC should satisfy βI B > I L

VCC − VBE − Vd 1 + Vd 2
Since I L = βI B RC > VCC − VBE − Vd 1 + Vd 2
RC
Clamping action results in a reduced collector current and

almost elimination of storage time.
At the same time, a fast turn-on is accomplished.
However, due to increased VCE, the on-state power loss is

increased, whereas the switching power loss is decreased.
Example 17.1: Finding the transistor

voltage and current with clamping
The base drive has VCC=100V, RC=1.5Ω,
Vd1=2.1V, Vd2=0.9V, VBE=15V, RB=2.5Ω,
and β=16.
Calculate:
– Collector current without clamping
– Collector-emitter voltage VCE
– Collector current with clamping

Solution
Without clamping
V − Vd 1 − VBE 15 − 2.1 − 0.7
I B = I1 = B = = 4.88 A
RB 2.5
I C = β I B = 16 × 4.88 = 78.08 A
Clamping voltage
VCE = VBE + Vd 1 − Vd 2 = 0.7 + 2.1 − 0.9 = 1.9V
With clamping
VCC − VCE 100 − 1.9
IL = = = 65.4 A
RC 1. 5
β
IC = (I1 + I L ) = 16 (4.88 + 65.4) = 66.15 A
1+ β 16 + 1
Key points
A BJT is a current controlled device
Base current peaking can reduce the
turn-on time and reversing the base
current can reduce the turn-off time
The storage time of a BJT increases with
the amount of base drive current, and
overdrive should be avoided.

ISOLATION OF GATE & BASE
DRIVES
For power transistors, the control
voltage should be applied between
the gate and the source terminals or
between the base and emitter
terminals.
Power converters generally require
multiple transistors and each
transistor must be gated individually.
Common terminal
for pulses
Ground
terminal
Generates 4 pulses

Terminal g1, which has a voltage of Vg1 with respect to C
cannot be connected directly to gate terminal G1.
Vg1 should be applied between gate terminal G1 and
source terminal S1 of transistor M1.
There is a need for isolation and interfacing circuits
between the logic circuit and power transistors.
However, M2 and M4 can be gated directly without
isolation or interfacing circuits if logic signals are
compatible with gate drive requirements of the
transistors.
The importance of gating a transistor between its

gate and source rather than applying gating voltage
between the gate and common ground can be
demonstrated with the following figure.
VGS = VG − RL I D (VGS )
ID(VGS) varies with VGS
VGS when transistor
turns on and
reaches a steady-
state value (required
to balance the load drain
current)
Load resistance

The effective value of VGS is thus
unpredictable and such an
arrangement is not suitable.
There are basically two ways of
floating or isolating the control or gate
signal with respect to ground:
– Pulse transformers
– Optocouplers

Key point
The low-level gate circuit must be
isolated from the high level power circuit
through isolation devices or techniques
such as optocouplers and pulse
transformers.
THYRISTOR FIRING CIRCUIT
In thyristor converters, different potentials

exist at various terminals.
The power circuit is subjected to a high
voltage, usually greater than 100 V, and
the gate circuit is held at a low voltage,
typically 12 to 30 V.
An isolation circuit is required between an
individual thyristor and its gate-pulse
generating circuit.

The isolation can he accomplished by either pulse
transformers or optocouplers.
An optocoupler could be a phototransistor or photo-
silicon-controlled rectifier (SCR).
A short pulse lo the input of a LED, D1 turns on the
photo-SCR T1; and the power thyristor TL is triggered.
This type of isolation requires a separate power supply
Vcc and increases the cost and weight of the firing
circuit.
Short-Pulse:
When a pulse of adequate voltage is applied to the base of Q1,
the transistor saturates and the dc voltage Vcc appears across
the transformer primary, inducing a pulsed voltage on the
transformer secondary.
When the pulse is removed, Q1 turns off
and a voltage of opposite polarity is
induced across the primary and the
freewheeling diode Dm conducts.
The current due to the
transformer magnetic energy
decays through Dm to zero.
During this transient decay a
corresponding reverse
voltage is induced in the
secondary.
Long-Pulse:
The pulse width can be made
longer by connecting a capacitor
C cross the resistor R.
The transformer carries

unidirectional current
and the magnetic core
can saturate, thereby
limiting the pulse width.
This type of pulse
isolation is suitable for
pulses of typically 50 to
100 μs.
Pulse train:
In many power converters with inductive loads, the
conduction period of a thyristor depends on the load
power factor (PF); therefore, the beginning of
thyristor conduction is not well defined.
In this situation, it is often necessary to trigger the
thyristors continuously.
However, a continuous gating increases thyristor
losses.
A pulse train that is preferable can be obtained with
an auxiliary winding

When transistor Q1 is
turned on, a voltage is
also induced in the
auxiliary winding N3 at the
base of transistor Q1, such
that diode D1 is reverse
biased and Q1 turns off.
In the meantime,
capacitor C1 charges up
through R1 and turns on
Q1 again.
This process of turn-on and turn-off continuous as long as

there is an input signal v1 to the isolator.
In-stead of using the

auxiliary winding as a
blocking oscillator, an
AND-logic gale with an
oscillator (or a timer)
could generate a pulse
train. In practice, the
AND gate cannot drive
transistor Q1 directly,
and a buffer stage is
normally connected
before the transistor.

The output of gate circuits is
normally connected between the
gate and cathode along with other
gate-protecting components.
The resistor Rg in (a) increases the
dvldt capability of the thyristor,
reduces the turn-off time, and
increases the holding and latching
currents.
The capacitor Cg in (b) removes
high-frequency noise components
and increases dv/dt capability and
gate delay lime.
The diode D1 (c) protects the

gate from negative voltage.
However, for asymmetric
silicon-controlled rectifiers,
SCRs, it is desirable to have
some amount of negative gate
voltage to improve the dvldt
capability and also to reduce
the turn-off time.
All these features can be

combined as shown in (d),
where diode D1 allows only the
positive pulses and R1 damps
out any transient oscillation
and limits the gate current.

Key points
Applying a pulse signal turns on a
thyristor
The low-level gate circuit must be
isolated from the high-level power circuit
through isolation techniques
The gate should be protected from
triggering by a high frequency or
interference signal.
THYRISTOR CONVERTER GATING

CIRCUITS
The generation of gating signals for
thyristors of ac-dc converters requires:
– Detecting zero crossing of the input voltage
– Appropriate phase shifting of signals
– Pulse shaping to generate pulses of short
duration
– Pulse isolation through pulse transformer or
optocouplers

DRIVE IC FOR CONVERTERS

There are numerous IC gate drives that are
commercially available for gating power
converters.
These include
– Pulse-width-modulation (PWM) control,
– Power factor correction (PFC) control,
– Combined PWM and PFC control
– Current mode control
– Bridge driver
– Servo driver, half-bridge drivers, stepper motor
driver, thyristor gate driver
– Etc…

These ICs can be used for applications
such as:
– Buck converters for battery chargers
– Dual forward converters for switched
reluctance motor drives
– Full-bridge inverter with current-mode control
– Three-phase inverter for brushless and
induction motor drives
– Push-pull bridge converter for power
supplies
– Synchronous PWM control of switched-mode
power supplies (SMPSs)
An IC gate drive integrates most of the

control functions including some
protection functions to operate under
overload and fault conditions.
The especial purpose ICs for motor
drives include many features such as
– gate driving with protection,
– soft start charging of DC bus,
– linear current sensing of motor phase
current, and
– control algorithms for V/Hz to sensorless
vector or servo control.

SUMMARY
MOSFETs are voltage-controlled devices
requiring low gating power.
Gate signals can be isolated from the power
circuit by pulse transformers or optocouplers.
BJTs are current-controlled devices requiring
reverse base current during turn-off to reduce
storage time, but they have low on state or
saturation voltage.
A mean of isolation between power circuit and
gate circuit is necessary.
The pulse transformers are simple, but leakage

inductance should be very small.
The transformers may be saturated at low
frequency and long pulse. Optocouplers require
separate power supply.
For inductive loads, a pulse train reduces
thyristor loss and is normally used for gating
thyristors, instead of a continuous pulse.
There are numerous drive ICs for drives that
are commercially available for gating power
converters. These ICs integrate logic, gate
isolation, protection, and control functions. As a
result, discrete gate circuits have become
obsolete.

ADVANCED
ADVANCEDPOWER
POWERELECTRONICS
ELECTRONICS
STATIC SWITCHES
Preferred source Static
transfer Critical
Alternate source
Switch Load
Dr. Adel Gastli

CONTENTS
1. Introduction
2. Single-Phase AC Switch
3. Three-Phase AC Switches
4. Three-Phase reversing Switches
5. AC Switches for Bus Transfer
6. DC Switches
7. Solid-State Relays
8. Design of Static Switches
9. Summary
(Textbook: Sections 12.1-12.9)
Dr. Adel Gastli Static Switches 2
INTRODUCTION
Thyristors that can be turned on and off
within a few microseconds may be
operated as fast-acting switches to
replace mechanical and
electromechanical circuit breakers.
For low power dc applications power

transistors can also be used as switches.
Static switches have many advantages:

– Very high switching speeds
– No moving parts
– No contact bounce on closing
In addition to applications as static
switches, the thyristor (or transistor)
circuits can be designed to provide
– time-delay,
– latching,
– over- and undercurrent protection, and
– voltage detection

Transducers for detecting mechanical, electrical,
position, proximity, and so on, can generate the
gating or control signals for the switches.
Static switches can be classified into two mainly
types:
– AC Switches (line commutated, switching speed limited
by supply frequency and turn-off time)
• Single-phase
• Three-phase
– DC switches (forced commutated, switching speed
limited by turn-on and –off times of devices)
SINGLE-PHASE AC SWITCHES
vs , v0 vs , v0
is i T1 i0 Vsm Vsm
T1
iT 2
T2 0 0
vs v0 RL π 2π ωt π 2π ωt
i0 i0
i0 m i0 m
is i0
0 0
TR1 π 2π ωt π 2π ωt
vs v0 RL g1 , g 2 g1 , g 2
1 1
0 π 2π ωt 0 π 2π
ωt
Bidirectional switches Inductive load
Resistive load
Applications
Transformer’s Static Tap-Changing
Control.
– Controls the output voltage of a power
transformer by selecting appropriate taps.
Static VAR Controller (SVC)

– Controls power to an inductor
– Controls power to a capacitor bank
– Controls power to a mixed inductor and
capacitor elements.
Key Points
The switches are turned at the zero
crossing of the input voltage (resistive
load) or output current (inductive load).
The circuit operation is similar to the

single-phase ac voltage controller with a
delay angle α=0.

THREE-PHASE AC SWITCHES
T1
v vab vbc vca
A
a 1 3 5 1
T4
T3
ZL
b θ = ωt
B
4 6 2 4 6
ZL ZL
T6 g1
T5 c
0
C g2
T2 0
g3
a 0
A g4
TR1
ZL 0
b g5
B
TR2 ZL ZL 0
g6
c
C 0
TR3 π 2π
Similar to three-phase ac voltage controller with a delay angle α=0

THREE-PHASE REVERSING SWITCHES

T1
Five thyristor pairs can A

a
be used and gated to T4
T3
produce a phase B b
ZL
reversal to a three- T6
ZL ZL
T5 c
phase load.
C
T2
Common applications T9
in ac (induction &
synchronous) motor T10
T7
rotation reversal.
T8

AC SWITCHES FOR BUS TRANSFER
T1 T’1
T2 T’2
v1 v0 RL v2
Two or more thyristor pairs can be connected in back-to-

back for bus transfer from on supply source to another.
T1 T’1
A A’
a
T4 T’4
T3 ZL T’3
B B’
b ZL ZL
T6 T’6
T5 c T’5
C C’
T2 T’2
DC SWITCHES
In the case of dc switches, the input

voltage is dc and power transistors or fast-
switching thyristors or GTOs can be used.
+ +
RL v0
Dc
_
Vs supply
vg
Base Q1
drive
_ voltage 0 t

Automotive powering systems with 42V batteries
DC
To 42V load
AC
+
42V Distribution boxes
- containing switches
A s and fuses
DC
DC 14V To 14V loads
42V
A Alternator
Dc/dc
+
s Starter motor converter
14V
-
SOLID-STATE RELAYS
Static switches can be used as solid-state
relays (SSRs), which are used for the control of
ac and dc power.
SSRs are used for many applications in
industrial control such as the control of:
– Motors
– Transformers
– Resistance heating
SSRs are normally isolated electrically between
the control circuit and the load circuit by reed
relay, transformer, or optocoupler.

+ + + +
RL v0 v0 RL RB
_ _
vg Vs Vs
dc
Q1 Q1
0 t supply
Reed relay
_ _
isolation
Optocoupler
Dc solid-state relays
+
vg R RL v0 v0
_ Vs
TR Vs ac
supply Control
0 t TR signal
Reed
relay Transformer
isolation
Ac solid-state relays
DESIGN OF STATIC SWITCHES
Solid-state switches are available

commercially with limited voltage and
current rating ranging up to 440V and
from 1 to 50A.
The design of an SSR to meet specific
requirements is simple and requires
determining the voltage and current
ratings of power semiconductor devices.
Study examples 12.1 and 12.2
Summary
Solid-state ac and dc switches have number
of advantages over conventional
electromechanical switches and relays.
With the developments of power
semiconductors devices and integrated
circuits, static switches are used in a wide
range of applications in industrial control.
Static switches can be interfaced with digital
or computer control systems.

ADVANCED
ADVANCEDPOWER
POWERELECTRONICS
ELECTRONICS
PWM INVERTERS
Dr. Adel Gastli

Email: agastli@ieee.org
CONTENTS
CONTENTS
1. Single-Phase Half-Bridge 8. 60-Degree Modulation

Inverter 9. Transformer Connection
2. Single-Phase Bridge 10. Single-Phase Current
Inverter Source
3. Three-Phase Inverter 11. Three-Phase Current
4. Three-Phase PWM Inverter Source
5. Sinusoidal PWM 12. Variable DC Link Inverter
6. Modified Sinusoidal PWM 13. AC Filters
7. Sinusoidal PWM 3-Phase 14. Summary
Textbook: Chapter 6
Dr. Adel Gastli PWM Inverters 2

Single-Phase Half-Bridge Inverter
∞
2VS
vo (t ) = ∑
n =1,3,5,. nπ
sin nωt
=0 for n = 2, 4,..
2
2 π ⎛ VS ⎞ VS
Vo ( rms ) =
π ∫0 ⎜ ⎟ dθ =
⎝ 2 ⎠ 2
2VS
Vo1( rms ) = = 0.45 VS
2π
Performance Parameters
Von
HFn = for n > 1 Harmonic factor of nth harmonic
Vo1
∞
1
THD =
Vo1
∑
n = 2,3,..
Von2 Total Harmonic Distortion factor
∞ 2
1 ⎛ Von ⎞
DF =
Vo1
∑ ⎜ 2 ⎟
n = 2,3,.. ⎝ n ⎠
Distortion factor
Von
DFn = 2
for n > 1 Distortion factor of nth harmonic
Vo1n
Lowest Order Harmonic
LOH ≥ 3% × Vo1 - Frequency is closest to fundamental
- Amplitude is greater than or equal to 3% the fundamental
Example 6.1 (Homework)
Study the example by yourself.
Simulate the circuit and check
the results. (Use any software)
(Life-long learning)
Single-Phase Bridge Inverter

∞
4VS
vo (t ) = ∑ sin nωt
n =1,3,5,. nπ
=0 for n = 2, 4,..
2 π
Vo ( rms ) =
π ∫
0
VS2 dθ = VS
4VS
Vo1( rms ) = = 0.90 VS
2π
Example 6.3
R = 10, L = 31.5mH , C = 112uF , f o = 60 Hz, Vs = 220V , ω = 2π f = 377 rad / s
j − j 23.68
X L = jnω L = j11.87 n Ω, X c = = Ω
nωC n
2 2
⎛ 1 ⎞ ⎛ 23.68 ⎞
Z n = R + ⎜ nω L −
2
⎟ = 10 + ⎜ 11.87 n −
2
⎟
⎝ nωC ⎠ ⎝ n ⎠
⎛ 11.87 n 23.68 ⎞
θ n = tan −1 ⎜ − ⎟
⎝ 10 10n ⎠
∞
4VS
vo (t ) = ∑
n =1,3,5,. nπ
sin nωt
=0 for n = 2, 4,..
∞
vo (t ) 4VS
io (t ) = = ∑ sin(nωt − θ n )
Z n ∠θ n n =1,3,5,. ⎛ 1 ⎞
2
nπ R 2 + ⎜ nω L − ⎟
⎝ nωC ⎠
a. The instantaneous output voltage
v0 (t ) = 280.1sin(377t ) + 93.4 sin(3 × 377t ) + 56.02 sin(5 × 377t )

+ 40.2 sin(7 × 377t ) + 31.12 sin(9 × 377t ) + L
Dividing the output voltage by the load impedance and

considering the appropriate delay due to the load
impedance angles, we can obtain the instantaneous load
current as
i0 (t ) = 18.1sin(377t + 49.72) + 3.17 sin(3 × 377t − 70.17 o )

+ sin(5 × 377t − 79.63o ) + 0.5 sin(7 × 377t − 82.85o )
+ 0.3 sin(9 × 377t − 84.52o ) + L

b. The peak fundamental load current is Im1=18.1A. The
rms current at fundamental frequency is I01=12.8A
c. Considering up to 9th harmonic, the peak load current,

I m = I m21 + I m2 3 + I m2 5 + I m2 7 + I m2 9
= 18.12 + 3.17 2 + 1.0 2 + 0.52 + 0.32
= 18.41A
The rms harmonic load current is
I m2 − I m21 18.412 − 18.12
Ih = = = 2.38 A
2 2
I m2 − I m21
THD = = 18.59%
I m1
d. The rms load current is I m 18.42

I0 ≅ = = 13.02 A
2 2
The total load power is P0 = I 02 R = 13.02 2 × 10 = 1695W
The fundamental output
power is P01 = I 2
01 R = 12 .8 2
× 10 = 1638.4W
P0 1695
e. The average supply current Is = = = 7.7 A
Vs 220
f. The peak transistor current I p ≅ I m = 18.41A
The maximum
I0 I p 18.41
permissible rms I Q max = = = = 9.2 A
transistor current is 2 2 2

g. The waveforms of the output voltage and current and their
fundamental components are shown below.
30
v /10
0
v01/10
20 i0
i
Load Voltage (V) and Current (A)
01
10
Q1,Q2 D1,D2 Q3,Q4 D3,D4
0
-10
-20
-30
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018
Dr. Adel Gastli Time, (sec) PWM Inverters 11
h. The conduction time of each transistor is found

approximately from the previous waveforms as
130.28π
ωtQ = 180 − 49.72 = 130.28o or tQ = = 6.031ms
180 × 377
i. The conduction time for each diode is approximately

T 1
tD = − tQ = − 6.031× 10 −3
2 120
= (8.333 − 6.031) × 10 −3 = 2.302ms
49.72
=
180 × 377

Notes:
This example can be repeated for different
types of loads (R, RL, RLC) with an appropriate
change in load impedance ZL and load angle θn
Gating sequence is as follows:
– Generate two square-wave gating signals vg1 and vg2
at an output frequency f0.
– The gating signals vg3 and vg4 should be the logic
invert of vg2 and vg1 respectively.
– Signals vg1 and vg3 drive Q1 and Q3, respectively,
through gate isolation circuits.
– Signals vg2 and vg4 drive Q2 and Q4, respectively,
without any gate isolation circuits.
THREE-PHASE BRIDGE
INVERTER
Three Single-Phase Inverter

Three-phase Bridge Inverter
180o Conduction
120o Conduction

Three Single-Phase Inverter
9 12 transistors
9 12 diodes
9 3 transformers
9 Risk of voltage unbalance
Transformer secondary
windings can be
connected in Y or Δ.
Δ connection eliminates
triplen harmonics (3, 6,
9,..) Figure 6.4
Three-Phase Bridge Inverter

180o Conduction
Vs 2Vs Vs
van = van = van =
3 3 3
2V V V
vbn = − s vbn = − s vbn = s
3 3 3
V − Vs 2V
vcn = s vcn = vcn = − s
3 3 3
∞
4Vs nπ ⎛ π⎞
vab = ∑ cos sin n⎜ ωt + ⎟
n =1, 3, 5,K nπ 6 ⎝ 6⎠
∞
4Vs nπ ⎛ π⎞
vbc = ∑ cos sin n⎜ ωt − ⎟
n =1, 3, 5,K nπ 6 ⎝ 2⎠
∞
4Vs nπ ⎛ 7π ⎞
vca = ∑ cos sin n⎜ ωt − ⎟
n =1, 3, 5,K nπ 6 ⎝ 6 ⎠
Note that for n=3,9,15,21,... vab=vbc=vca=0

Line-to-line rms voltage
2π / 3 1/ 2
⎡ 2 ⎤
vL = ⎢ ∫0 V d (ωt )⎥⎦
2
⎣ 2π
s
2
= Vs = 0.8165Vs
3
Line-to-line rms harmonic voltage
4Vs nπ 4Vs π
vLn = cos ⇒ vL1 = cos = 0.7797Vs
2nπ 6 2π 6
Phase rms voltage
vL 2Vs
vp = = = 0.4714Vs
3 3

π / 3 2π / 3 π 2π
120o Conduction
Only two transistors remain on at any time.
vab
Vs Vs van = 0
vbc
van = van =
2 2 Vs
V vbn = 0 vbn =
vca
vbn = − s 2
2 Vs V
vcn = 0 vcn = − vcn = − s
2 2
Note: The waveforms of phase voltages are the same as the

waveforms of line voltages with the only difference in the
amplitudes (Vs/2 instead of Vs)
∞
2Vs nπ ⎛ π⎞
van = ∑
n =1, 3, 5,K nπ
cos
6
sin n⎜
⎝
ω t + ⎟
6⎠
∞
2Vs nπ ⎛ π⎞
vbn = ∑ cos sin n⎜ ωt − ⎟
n =1, 3, 5,K nπ 6 ⎝ 2⎠
∞
2Vs nπ ⎛ 7π ⎞
vcn = ∑ cos sin n⎜ ωt − ⎟
n =1, 3, 5,K nπ 6 ⎝ 6 ⎠
vline = 3v ph
Voltage Control of Single-Phase
Inverters
Single-Pulse-Width modulation
Multiple-Pulse-Width Modulation
Sinusoidal-Pulse-Width Modulation
Modified Sinusoidal-Pulse-Width Modulation
Phase Displacement control
Single-Pulse Width Modulation
∞
4VS nδ
vo (t ) = ∑
n =1,3,5,. nπ
sin
2
sin nωt
δ
d= = t −t
ω 2 1
T
= MTs = M
2
Modulation index Switching Period
M=Ar/Ac
2 ( π +δ ) / 2 δ
V0 ( rms ) =
2π ∫π δ
( − )/2
Vs2 dθ = Vs
π
Figure 6.11
Pulse width
α T α2 T
t1 = 1 = (1 − M ) s t2 = = (1 + M ) s
ω 2 ω 2
Prove these
δ
d = = t2 − t1 = MTs two t1 and
ω t2 equations
T
Ts = T is the desired period of the output voltage
2
Harmonic Profile for p =1

∞
4VS nδ
vo (t ) = ∑
n =1,3,5,. nπ
sin
2
sin nωt
The dominant harmonic

is the third.
DF increases
significantly at a low
output voltage (small M).
Figure 6.12
Gating Signals Start
Algorithm Generate a triangular carrier signal v cr

cr
(Magnitude Vcc, Switching Period Tss=T/2)
Compare vcrcr with a dc reference signal vrr
Change frequency
vee=vcrcr-vrr>0 gate signal vgg=0
Change vr to vee=vcrcr-vrr<0 gate signal vgg=1
change the
modulation
vgg should be multiplied by a unity pulse
index and
signal vzz with 50% duty cycle at
hence the
a period of T vg1=vgg*vzz
output g1
voltage rms
vg2
g2 is obtained by inverting the square
signal vzz.
Multiple-Pulse PWM
δ
d = = tm +1 − tm
ω
T
= MTs = M
2p
p π / p +δ / 2
V0( rms ) =
π ∫π / p −δ / 2
Vs2
pδ
= Vs
π
(Prove these integral limits) Figure 6.13

2p
4VS nδ ⎡ ⎛ 3δ ⎞ ⎛ δ ⎞⎤
Bn = ∑ sin ⎢ sin n α
⎜ m + ⎟ − sin n ⎜ π + α + ⎟
π 4 ⎠ ⎥⎦
m
m =1 n 4 ⎣ ⎝ 4 ⎠ ⎝
∞
vo (t ) = ∑
n =1,3,5,.
Bn sin nωt
(See textbook for detailed

calculation of Bn)
Note that the harmonics’

variation as a function of output
voltage has decreased.
Sinusoidal PWM
δm
dm = = tm +1 − tm
ω
∞
vo (t ) = ∑
n =1,3,5,.
Bn sin nωt
2p
δm vo=Vs(g1-g4)
Vo ( rms ) = VS ∑
m =1 π
More practical
LOH = 2p-1
p: number of pulses per
half a cycle
2p
4VS nδ m ⎡ ⎛ 3δ m ⎞ ⎛ δ m ⎞⎤
Bn = ∑ sin ⎢ sin n ⎜ α m + ⎟ − sin n ⎜ π + α m + ⎟ ⎥
m =1 nπ 4 ⎣ ⎝ 4 ⎠ ⎝ 4 ⎠⎦
∞
vo (t ) = ∑
n =1,3,5,.
Bn sin nωt
LOH = 2p-1=9
Significant decrease in DF
and harmonics content.
Commonly used in industrial

applications
Peak Fundamental versus M

For M<1 the maximum
output voltage over the
input voltage ratio
varies linearly with M.
For M>1, the inverter

operation is called
overmodulation.
Overmodulation leads
to basically square
waveform and add
more harmonics. (Not
recommended)
Modified Sinusoidal PWM
δm
dm = = tm +1 − tm
ω
Carrier signal is
modified
Because of the nature of sine waveform, the width of pulses does not
change much with the modulation index near the peak of the sine.

Less number of
switching of power
devices between
60o and 120o
Reduction of
switching losses
Increase of
fundamental
component.
Harmonic
characteristics are
improved.
Phase Displacement
Full-bridge is equivalent to
summation of two half-bridge
inverters where vbo is shifted
180o from vao.
vab = va 0 − vb 0
To vary the output voltage

amplitude, the phase shift of
180o can be varied from 0o to
180o.
Phase Displacement
α
V0 ( rms ) = Vs
π
∞
2Vs
va 0 = ∑
n =1, 3, 5,L nπ
sin nωt
∞
sin n(ωt − α )
2Vs
vb 0 = ∑
n =1, 3, 5,L nπ
∞
4Vs ⎛ nα ⎞ ⎛ α⎞
vab = ∑
n =1, 3, 5,L n π
sin ⎜
⎝ 2
⎟
⎠
cos n ⎜
⎝
ω t −
2
⎟
⎠
4Vs
V01 =
4Vs ⎛α ⎞
sin ⎜ ⎟ 0 ≤ α ≤ π ⇒ 0 ≤ V01 ≤
2π ⎝2⎠ 2π
Fundamental rms is a function of the phase displacement
angle α.
Phase Displacement
To obtain a quarter-wave symmetry at 90o it is
possible to shift the gate signal g1 by α and g3 by
180o-α.
∞ vao
sin n(ωt − α )
2Vs
va 0 = ∑ Vs/2
n =1, 3, 5,L nπ α
-Vs/2
∞
sin n(ωt − π + α )
2Vs
∑
vbo
vb 0 =
n =1, 3, 5,L nπ Vs/2
180o-α 180o+α
∞ -Vs/2
cos(nα )sin (nωt )

4Vs
vab = ∑
n =1, 3, 5,L nπ
van
Vs
cos(α )
4Vs
V01 = 180o
2π -Vs
Voltage Control of Three-Phase

Inverters
Sinusoidal Pulse-Width Modulation
60o PWM
Third-Harmonic PWM
Will not be
covered
Space Vector modulation
Sinusoidal PWM 3-Phase
It is similar to single-phase
SPWM but with 3-reference
sine waveforms shifted by
120o each.
fc
mf =
fo
Frequency modulation
ratio should be odd vab=Vs(g1-g3)
multiple of 3.
Comments:
All phase voltages are identical but 120o

out of phase without even harmonics.
Harmonics multiple of 3 are identical in

amplitude and phase in all the 3-phases.
Thus, the ac output line voltages do not

contain the harmonics multiple of 3.

60-Degree Modulation
Similar to the modified PWM seen earlier.
Flat top between 60o and 120o
Less switching losses

Utilizes more available dc voltage
Higher fundamental in both phase and line voltages
All triplen harmonics are absent in three-phase voltages.
Harmonic Reduction
Phase displacement control

Bipolar output voltage notches
Unipolar output voltage notches
60-Degree modulation
Transformer connections

Phase Displacement Control
It was seen that the nth harmonic can be eliminated

by a proper choice of displacement angle α if:
cos(nα ) = 0
or
90o
α=
n
Thus, the 3rd harmonic can be eliminated if:
α = 30o
Bipolar Notches
A pair of unwanted harmonics at the output of single-
phase inverters can be eliminated by introducing a pair of
symmetrically placed bipolar voltage notches as shown
below.
v0 (θ ) = −v0 (θ + π ) only odd harmonics vo (θ ) = −vo (−θ ) A1→n = 0

(i.e. n=1,3,5,…)
Point symmetry
Half-wave symmetry

∞
vo (t ) = ∑
n =1,3,5,.
Bn sin nωt
4Vs ⎡ α1 α2 π /2
Bn = ∫ sin(nθ )dθ − ∫ sin(nθ )dθ + ∫ sin( nθ )dθ ⎤
π ⎢⎣ 0 α1 α2 ⎥⎦
=
4Vs
[1 − 2 cos nα1 + 2 cos nα 2 ]
nπ
For B3 = B5 = 0 ⇒ α1 = 23.62o and α 2 = 33.3o
These type of equations can be solved iteratively or
using specialized program such as MathCAD or
MATLAB Symbolic Toolbox.
Example of Matlab program for solving such equations

clear, syms a1 a2
equ1 ='1-2*cos(3*as1)+2*cos(3*as2)';
equ2 ='1-2*cos(5*as1)+2*cos(5*as2)';
[as1,as2] = solve(equ1, equ2);
a1=double(as1)*180/pi;
a2=double(as2)*180/pi;
for n=1:length(a1)
if(a1(n)+a2(n)<=90)
n1=n;
break
end
end
a=[a1(n1) a2(n1)]

The previous equation of Bn can be extended to m
notches as follows:
⎡ m
⎤
⎢1 + 2∑ (− 1) cos(nα k )⎥ for n = 1,3,5,...
4Vs
Bn =
k
nπ ⎣ k =1 ⎦
where
π
α1 < α 2 < L < α k <
2
Example 6.4
A single-phase full-wave inverter uses multiple
notches to give bipolar voltage as shown in Figure
6.38 and is required to eliminate the fifth, seventh,
eleventh, and thirteenth harmonics from the output
wave. Determine the number of notches and their
angles.
Figure 6.38

Solution
For elimination of the fifth, seventh, eleventh and
thirteenth harmonics we should have:
B5 = B7 = B11 = B13 = 0
That is m=4 notches per half wave.
⎧1 − 2 cos(5α1 ) + 2 cos(5α 2 ) − 2 cos(5α 3 ) + 2 cos(5α 4 ) = 0
⎪1 − 2 cos(7α ) + 2 cos(7α ) − 2 cos(7α ) + 2 cos(7α ) = 0
⎪ 1 2 3 4
⎨
⎪1 − 2 cos(11α1 ) + 2 cos(11α 2 ) − 2 cos(11α 3 ) + 2 cos(11α 4 ) = 0
⎪⎩1 − 2 cos(13α1 ) + 2 cos(13α 2 ) − 2 cos(13α 3 ) + 2 cos(13α 4 ) = 0
α1 = 10.55o α 2 = 16.09o α 3 = 30.91o α 4 = 32.87 o
Unipolar Voltage Notches

Similarly to bipolar
notches symmetrical
unipolar notches can
also be introduced.
4Vs ⎡ α1 π /2
∫
Bn = sin( n θ ) d θ + ∫ sin(nθ )dθ ⎤
∞ π ⎢⎣ 0 α2 ⎥⎦
vo (t ) = ∑ Bn sin nωt
n =1,3,5,.
=
4Vs
[1 − cos nα1 + cos nα 2 ]
nπ
For B3 = B5 = 0 ⇒ α1 = 17.83o and α 2 = 37.93o
⎡ m
⎤
4V
Bn = s ⎢1 + ∑ (− 1)k
cos (nα )⎥ for n = 1,3,5,...
nπ
k
⎣ k =1 ⎦
Transformer Connection
Output voltages of two or more inverters may be
connected in series through a transformer to
reduce or eliminate certain unwanted harmonics.
Phase shifted
by 60o.
Transformer Connection
π/3
Elimination of third
(an all triplen)
harmonics
vo1 (t ) = A1 sin ωt + A3 sin 3ωt + A5 sin 5ωt + ...

π π π
vo 2 (t ) = A1 sin(ωt − ) + A3 sin 3(ωt − ) + A5 sin 5(ωt − ) + ...
3 3 3
⎡ π π ⎤
vo = vo1 + vo 2 = 3 ⎢ A1 sin(ωt − ) + A5 sin 5(ωt − ) + ..⎥
⎣ 6 6 ⎦
Current Source Inverter
Voltage control
Voltage
Vdc AC Load
Source
Inverter Current varies
with load
impedance
Current control
Current
Vdc AC Load
Source
Inverter voltage varies
with load
impedance
Single-Phase Current Source (Cont’d)
For continuous current flow, 2 switches must always conduct.

Conducting Switches io
Q1, Q2 , D1 , D2 IL
Q3, Q4 , D3, D4 -IL
Q1, Q4 , D1 , D4 0
Q3, Q2 , D3 , D2 0

See Eq. (6.28) p.249
∞
⎛ nδ ⎞
⎟ sin (nωt )
4I L
io (t ) = ∑
n =1, 3, 5,.. nπ
sin ⎜
⎝ 2 ⎠
4I L ⎛δ ⎞
I o1( rms ) = sin ⎜ ⎟
2π ⎝2⎠

Three-Phase Current Source
Similar to voltage
waveform for 180o
conduction (p. 239)
Three-Phase Current Source (Cont’d)
Y-Load Connection
∞
4I L ⎛ nπ ⎞ ⎛ π⎞
From Eq. (6.16a) ia (t ) = ∑
n =1, 3, 5,.. nπ
sin ⎜
⎝ 3
⎟
⎠
sin n ⎜
⎝
ωt +
6
⎟
⎠
Δ-Load Connection
∞
⎛ nπ ⎞
⎟ sin (nωt )
4I L
From Eq. (6.21a) ia (t ) = ∑
n =1, 3, 5,.. nπ
sin ⎜
⎝ 3 ⎠
4I L ⎛π ⎞
I a1( rms ) = sin ⎜ ⎟
2π ⎝3⎠

Alternative Configuration
Current Control Techniques

PWM, SPWM, MSPWM, and
other techniques can be applied
to vary the load current and
improve the quality of its
waveform.

Advantages of the CSI
The advantages of the CSI are:
– Since Idc is controlled and limited, misfiring of
switches, or short-circuit, would not be a
serious problem.
– The peak current of power devices is limited.
– The commutation circuits for thyristors are
simpler.
– It has the ability to handle reactive or
regenerative load without freewheeling
diodes.
Disadvantages of the CSI

A CSI requires a relatively large reactor to
exhibit current-source characteristics and
an extra converter stage to control the
current.
The dynamic response is slower than that
of the VSI.
Due to current transfer from one pair of
switches to another, an output filter is
required to suppress the output voltage
spikes.
Variable DC Link Inverter
Varying the modulation index (or pulse

width) and maintaining the dc input
voltage constant has shown that a range
of harmonics would be present on the
output voltage.
The pulse width can be fixed to eliminate
or reduce certain harmonics and the
output voltage can be controlled by
varying the level of the dc input voltage.
Variable DC Link Inverter (Cont’d)
Drawbacks:
Drawbacks
– Requires additional converter.
– Power cannot be fed-back to the source.

AC Filters
Output of the inverter is “chopped AC
voltage with zero DC component”. In some
applications such as UPS, “high purity” sine
wave output is required.
An LC section low-pass filter is normally
fitted at the inverter output to reduce the
high frequency harmonics.
In some applications such as AC motor
drive, filtering is not required.
AC Filters (Cont’d)
LOW PASS FILTER
L
+ +
C
voi voF LOAD
voi voF

Commonly used output filters
CC filter
filter isis very
very LC
LC tuned
tuned filter
filter CLC
CLC filter
filter isis more
more
simple
simple but but can
can eliminates
eliminates effective
effective inin reducing
reducing
draws
draws more
more only
only one
one harmonics
harmonics of of wide
wide
reactive
reactive power.
power. frequency.
frequency. bandwidth
bandwidth and and
draws
draws less
less reactive
reactive
power.
power.
Usually the nth and higher order harmonics
would be reduced significantly if the filter
impedance Zfn is much smaller than that of
the load ZLn, and a ratio 1:10 is normally
adequate in most of the cases.
Z Ln
Z fn ≤
10
(Study example 6.7 p. 294)

Square waveform No control in
harmonics and
output voltage
magnitude
∞
4VS
vo (t ) = ∑
n =1,3,5,. nπ
sin nωt Cut-off frequency of
the low-pass filter is
=0 for n = 2, 4,.. somewhat fixed
The filter size is dictated by the

VA ratings of the inverter.
PWM waveform
Harmonics are “pushed”
to higher frequencies.
∞
vo (t ) = ∑
n =1,3,5,.
Bn sin nωt Cut-off frequency of
the filter is increased
δm
2p
Vo ( rms ) = VS ∑
m =1 π
Hence the filter components
(i.e. L and C) sizes are reduced.
LOH = 2p-1
Trade off for this flexibility is complexity
p: number of pulses per half a cycle in the switching waveforms.

Summary
An inverter can convert a fixed dc voltage
to a variable or fixed ac voltage and/or
frequency.
Various modulation techniques can be
used to vary the output voltage. With
appropriate choice of switching angles,
specific harmonics can be eliminated.
Summary (Cont’d)
The current source inverter is most suited

for application requiring well defined
controllable current.
A CSI is a dual of a VSI.
In a VSI, the load current depends on load
impedance, whereas the load voltage in a
CSI depends on the load impedance.

ADVANCED
ADVANCEDPOWER
POWERELECTRONICS
ELECTRONICS
RESONANT PULSE INVERTERS
Dr. Adel Gastli

Learning Objectives
To learn the switching techniques for
resonant inverters and their types.
To study the operation and frequency
characteristics of resonant inverters.
To understand the performance
parameters of resonant inverters.
To learn the techniques for analyzing and
designing of some resonant inverters.
Dr. Adel Gastli Resonant Pulse Inverters 2

CONTENTS
1. Introduction
2. Series Resonant Inverter
3. Parallel Resonant Inverter
4. Summary

Introduction
PPsw_loss ➚
sw_loss ➚
ffswsw
Turn
Turn on -off losses
on-off losses could
could
PWM be
be significant
significant portion
portion of
of
PWM total
total power
power loss
loss
Control
Control
High
High di/dt
di/dt && dv/dt
dv/dt
➭➭stress
stress on
on devices
devices
EMI
EMI isis also
also produced
produced due
due
to
to high
high di/dt
di/dt and
and dv/dt
dv/dt in
in
the
the converter
converter waveforms
waveforms
Introduction (Cont’d)
Disadvantages of PWM control can
be eliminated or minimized by
Turning on
Turning and off
on and off when
when
isw or
isw or vvsw
sw
becomes
becomes zerozero
Force
Force zero -crossing by
zero-crossing by Resonant
Resonant Pulse
Pulse
an
an LC-resonant circuit
LC-resonant circuit Inverter
Inverter
Series Resonant Inverter

Unidirectional Switch Type
– Basic Circuit
– Coupled Inductor Circuit
– Half-Bridge Circuit
– Full-Bridge Circuit
– Examples

Basic Series Resonant Inverter
Unidirectional
T1 on
switches
T1 and T2 off
Load
Basic circuit
T2 on
4L
Assume: R < Underdamped
2
Waveforms
Mode 1
Mode 2
m1 m2 m3 m2 m1
Mode 3

Mode 1: Series Resonant Inverter
di1 1
L + Ri1 + ∫ i1 dt + vC1 (t = 0) = VS vC1 (t = 0) = −Vc
dt C
R
− t
i1 (t ) = A1e 2L
sin ωr t Underdamped
1 R2
ωr = − 2 Resonant
LC 4 L frequency
di1 Vs + Vc
A1 = =
dt ωr L Vs + Vc −αt
t =0
i1 (t ) = e sin ωr t
R ωr L
α=
2L
di1 1 ⎛ω ⎞
= 0 = ωr e −αtm cos ωr t m − αe −αtm sin ωr t m ⇒ t m = tan −1 ⎜ r ⎟
dt ωr ⎝α ⎠
1 ⎛ω ⎞
tm = tan −1 ⎜ r ⎟
ωr ⎝α ⎠
π
t m1 =
ωr
i1 (t = t1m ) = 0
vC1 (t = t1m ) = Vc1

= (VS + Vc ) e −απ / ωr + VS
− (Vs + Vc )
e −αt (α sin ωr t + ωr cos ωr t ) + Vs
1 t
vc1 (t ) =
C ∫0
i1 (t )dt − Vc vc1 (t ) =
ωr
i2 (t ) = 0
vC 2 (t ) = VC1
vC 2 (t = t2 m ) = VC 2 = VC1

di3 1 t
L + Ri3 + ∫ i3 dt + vc 3 (t = 0) = 0
dt C 0 vc 3 (t = 0) = Vc 2 = Vc1
Vc1 −αt
i3 (t ) = e sin ωr t
ωr L

π
t3 m =
ωr
i3 (t = t3m ) = 0
vc 3 (t = t3m ) = Vc 3
= −Vc
απ
−
ωr
= −Vc1e
Vc1 −αt
i3 (t ) = − e sin ωr t
ωr L
− Vc1
e −αt (α sin ωr t + ωr cos ωr t ) + Vs
1 t
C ∫0
vc 3 (t ) = i3 (t )dt − Vc1 vc 3 (t ) =
ωr
Parameters
vC1 (t = t1m ) = Vc1 i3 (t = t3m ) = 0
απ
−απ / ωr −
= (VS + Vc ) e + VS vc 3 (t = t3m ) = Vc 3 = Vc = Vc1e ωr
[
Vc 3 = Vc = Vc1e − z = (Vs + Vc )e − z + Vs e − z ]
απ
z= ⇒ Vc e z = (Vs + Vc )e − z + Vs
ωr
( )
⇒ Vc e z − e − z = Vs 1 + e − z ( )
1 + e− z 1+ ez ez
Vc = Vs z − z Vc1 = Vs z − z = Vs z
e −e e −e e −1
Parameters (Cont’d)
ez Vs
Vc1 = Vs z Vc = z
e −1 e −1
Vc1 = Vs + Vc
In
In steady-state
steady-state conditions,
conditions, the
the
peak
peak values
values of
of positive
positive and
and
negative
negative current
current through
through the
the
load
load are
are the
the same.
same.
Parameters (Cont’d)
π π Switch
− = toff > t q
ω0 ω r turn off
time
1
f 0 ≤ f 0(max) =
⎛ π ⎞
2⎜⎜ t q + ⎟⎟
⎝ ωr ⎠
Output voltage
toff : dead zone
frequency
Switch T1 should turn off before

T2 turns on to avoid short-circuit Output frequency is limited

Coupled Inductor Series Resonant
When T11 turns on and
i11(t) starts rising
Voltage across L11

is positive
Voltage across L22

is added to Vcc in
reverse biasing T22
Improved circuit
T22 is forced
to turn off
Half-Bridge Series Resonant Inverter
L1 = L2 & C1 = C2
Power is drawn from the dc

source during both half-cycles of
output voltage.
One half of the load current is

supplied by capacitor C1 or C2 and
other half by the source

Full-Bridge Series Resonant Inverter
High power output power.
When T1 and T2 are fired,

a positive resonant
current flows through the
load; and when T3 and T4
are fired, a negative load
current flows.
The supply current is

continuous, but pulsating Improvement
Remarks
Resonant frequency and available dead-
zone depend on the load and for this
reason, resonant inverters are most
suitable for fixed-load applications.
The inverter load (or resistor) could also
be connected in parallel with the
capacitor.

Example 8.1
R = 2, L = 50 μ H , C = 6 μ F , f o = 7 kHz ,Vs = 220V , ωo = 2π f o = 43,982 rad / s, tq = 10 μ s
1 R2 π π 1
ωr = − 2 = 54,160 rad / s toff = − = 13.42 μ s f o (max) = = 7352 Hz
LC 4 L ωo ω r π
2(tq + )
ωr
R V
α= = 20, 000 Vc = απ / ωsr = 100.4V
2L e −1
1 ω
Vc1 = Vc + Vs = 320.4V tm = tan −1 r = 22.47 μ s
ωr α
VS + Vc −α t
i1 (t = tm ) = I p = e sin ωr tm = 70.82 A
ωr L
T /2
I o ( rms ) = 2 f o ∫ io2 (t )dt = 4.41A Po = RI o2 = 3889 W
o
Po T /2
Is = = 17.68 A I A( average ) = f o ∫ io (t )dt = 17.68 A
VS o
Io
I pk (thyristor ) = I p = 70.82 A I R = = 31.18 A
2
Example 8.1

PSIM SIMULATION
Dead-time

Example 8.2
R = 2, L = 50μ H , C = 3μ F , f o = 7kHz ,Vs = 220V , ωo = 2π f o = 43,982 rad / s, tq = 10 μ s
Example 8.2
R = 2, L = 50 μ H , C1 = C 2 = C = 3 μ F , f o = 7 kHz , V s = 220V , ω o = 2π f o = 43, 982 rad / s , t q = 10 μ s
dio 1 1 R2
2C 2 ∫
L + Rio + io dt + vC 2 ( t = 0) − V S = 0 vC 2 ( t = 0) = −Vc ωr = − 2 = 54,160 rad / s
dt 2 LC 2 4 L
π π 1
C e = C1 + C 2 = 6 μ F , t off = − = 13.42 μ s f o (max) = = 7352 Hz
ωo ωr π
2(t q + )
ωr
R V
α= = 20, 000 Vc = απ / ωsr = 100.4V
2L e −1
1 ω
Vc1 = Vc + Vs = 320.4V tm = tan −1 r = 22.47 μ s
ωr α
VS + Vc −α t
i1 (t = tm ) = I p = e sin ωr tm = 70.82 A
ωr L
T /2
I o ( rms ) = 2 f o ∫ io2 (t )dt = 4.41A Po = RI o2 = 3889 W
o
Po T /2
Is = = 17.68 A I A ( average ) = f o ∫ io (t )dt = 17.68 A
VS o
Io
I pk ( thyristor ) = I p = 70.82 A I R = = 31.18 A
2
PSIM SIMULATION

Parallel Resonant Inverter
Parallel Resonant Circuit

Parallel Resonant Circuit
Current gain
I R V0 / R 1 V0 Z ( jω )
G ( jω ) = = = =
Ii Ii R Ii R iR
1 1
G ( jω ) = =
RY ( jω ) 1 + R + jRωC
jωL
1
=
⎛ R ⎞
1 − j⎜ − RωC ⎟
⎝ ωL ⎠
1 Gain is maximum when:
G ( jω ) =
2
⎛ R ⎞ R
1+ ⎜ − RωC ⎟ − Rω0C = 0
⎝ ωL ⎠ ω0 L
R C 1
Q p = ω0CR = =R ω02 LC = 1 ⇒ ω0 =
ω0 L L LC
1 ω
G ( jω ) = ,u =
⎛ 1⎞ ω0
1 + jQ p ⎜ u − ⎟
1 ⎝ u⎠
G ( jω ) =
⎛ω ω ⎞
2 1
1 + Q p2 ⎜⎜ − 0 ⎟⎟ G ( jω ) =
2
⎝ ω0 ω ⎠ ⎛ 1
1 + Q p2 ⎜ u − ⎟
⎞
⎝ u⎠
ω 1
u= , G ( jω ) =
ω0 ⎛ 1⎞
2
1 + Q p2 ⎜ u − ⎟
⎝ u⎠
Note that maximum gain is obtained for

u=1.
Output power (current) can be controlled

by frequency control (adjusting u=ω/ω0).
See example 8.3 for typical application.

iC + iR + iL = I s
dv v 1 t
C + + ∫ vdt = I s
dt R L 0
I s −αt
v(t ) = e sin ωr t
ωr C
I s −αt
v(t ) = e sin ωr t α=
1
ωr C 2 RC
1 1
ωr = − 2 2 Damping resonant frequency
LC 4 R C
1 ⎛ω ⎞ π Time at which voltage v
tm = tan −1 ⎜ r ⎟ ≅
ωr ⎝ α ⎠ ωr becomes maximum
π 2π
ωr ωr
iC iL
is iR
v


Some Applications
Compared with line frequency

operation, high frequencies
offer the following advantages
in regulated high voltage power
High-voltage supplies such as
this multiple-output model use
supplies:
more efficient and higher-
performance components and
power conversion techniques
Smaller size and weight;
to reduce weight and improve Faster response time;
performance. Lower stored energy;
Higher efficiency;
Applications (Cont’d)
The series resonant inverter can be used in a
dielectric barrier discharge cells (DBDCs)
application (generation of cold plasmas for the
degradation of toxic organic compounds ),
showing its effectiveness in the generation of
the electron discharge by means of a
charge/voltage figure of merit.
Resonant Inverters can be used in resonant
power supply which produces a controllable
high-frequency high-voltage sinusoidal
alternating-current output.

Applications (Cont’d)
Electronic ballasts for
high pressure
discharge lamps.
Induction-Heating
Appliances.
Summary
A resonant pulse inverter can convert a
fixed dc voltage to a fixed or variable ac
voltage at a fixed frequency.
The output frequency which is the same
as the resonant frequency remains
almost fixed.
The parallel resonant inverter is most
suitable for applications with variable load
parameters.

ADVANCED
ADVANCEDPOWER
POWERELECTRONICS
ELECTRONICS
POWER SUPPLIES
Dr. Adel Gastli

Learning Objectives
To understand the operation and analysis
of power supplies
To learn the types and circuit topologies
of power supplies
To learn the parameters of magnetic
circuits
To learn the techniques for designing
transformers and inductors
Dr. Adel Gastli Power Supplies 2

CONTENTS
1. Introduction
2. DC Power Supplies
3. AC Power Supplies
4. Multistage Converters
5. Control Circuits
6. Magnetic Design Considerations
7. Summary

INTRODUCTION
Power supplies used in the industry are often
required to meet the following specifications:
– Isolation between the source and the load.
– High-power density for reduction of size and weight.
– Controlled direction of power flow.
– High conversion efficiency
– Input and output waveforms with a low THD for small
filters.
– Controlled power factor (PF) if the source is an ac
voltage.

Introduction (Cont’d)
The converters discussed previously do
not meet most of these specifications and
multistage conversions are normally
required.
The basic topologies can be categorized
into two types:
– DC power supplies and
– AC Power supplies.
DC POWER SUPPLIES
AC-DC DC
~ converters Load
Input isolation
transformer
Harmonic contents are high

Switched-mode
Switched-mode power
power supplies:
supplies:
Buck,
Buck, Boost,
Boost, Buck-Boost,
Buck-Boost, and
and Cύk
Cύk
converters
converters
DC-DC DC
= converters Load
Do not provide the

necessary isolation and the
output power is low
Common
Common practice
practice is
is to
to use
use multi-
multi-
stage
stage conversions
conversions
Example: AC-DC
Three-stages ~ converter
DC-AC PWM or
converter Resonant Inverter
Inter-stage
isolation
transformer
AC-DC DC
converter Load

Switched-Mode Dc Power Supplies
They have High Efficiency.
They can handle High Load Current at Low Voltages.
There are four common types:
– Flyback forward
– Push-pull
– Half-bridge
– Full-bridge
They have an inverter stage that can operate at very
high frequency. The inverter output ac voltage can be
varied by PWM technique and then rectified by diodes.
Because the inverter can operate at high frequencies,
the ripples on the rectifier dc output can be easily
filtered out with small filters.
is
+ ip + +
D1
vp N p N s vs C RL
vi
_
Q1 + vo
vQ1
_ _
R1
Control
Flyback converter R2 _
vQ1 Ip(pk) ip
Vi+(Np/Ns)Vo
kT
0 T 0
vs t is t
Vo (Np/Ns)Ip(pk)
0 0
t t
-(Ns/Np)Vo
Mode 1: Q1 is on 0 < t ≤ kT
Vs t Primary current starts to build up and stores

ip =
L p energy in primary winding
Primary magnetizing
inductance
Due to opposite polarity
arrangement of windings,
diode D1 is reverse biased.
There is no energy transfer from input to load. C maintains the

output voltage and supplies the load current.
At t=kT (end of mode 1)
Vs kT
I p ( pk ) = i p (t = kT ) = Peak primary current
Lp
Np
I se ( pk ) = I p ( pk ) Peak secondary current
Ns
Mode 2: Q1 is off kT < t ≤ T
ip cannot change instantaneously.

The polarity of windings reverses and
D1 becomes forward biased and turns
on. C is charged and current flows in RL.

ise decreases linearly:
Vot
ise = I se ( pk ) −
Ls
Secondary magnetizing inductance
Under discontinuous conduction mode operation:
Secondary current reaches zero before next turn on of Q1.
Under continuous conduction mode operation:
Secondary current does not reach zero at next turn on of Q1.
Energy is transferred from source to output only during

time interval (0<t<kT)
1
L p I p2 ( pk )
Pi = 2 =
(kV s )2
(prove it)
T 2 fL p
For an efficiency η, the output power is given by:
η (Vs k )2 Vo2
Po = ηPi = =
2 fL p RL
Vo can be kept constant by ηRL

keeping the product VskT Vo = Vs k
2 fL p
constant.
Maximum duty cycle kmax occurs at minimum input voltage
Vs(min)
Vo 2 fL p
For discontinuous k max =
conduction Vs (min) ηRL
ηRL
Vo = Vs (min) k max
2 fL p
Maximum transistor voltage: ⎛ Np ⎞

VQ1(max) = Vs (max) + ⎜⎜ ⎟⎟Vo
⎝ Ns ⎠
Peak primary current is the same 2 Pi 2 Po
as the maximum collector current I C (max) = I p ( pk ) = =
kVs ηkVs
Flyback converter is used mostly in

applications below 100W.
Widely used for high-output voltage and
relatively low-power.
Essential features:
– Simplicity
– Low cost

(Example 14.1 page 606)
Example
The average (or dc) output voltage of the flyback
converter is Vo=24V at a resistive load of R=0.8Ω.
The duty-cycle ratio is k=50% and the switching
frequency is f=1kHz. The turns ratio of the
transformer is a=Ns/Np=0.25. Neglect the losses in
the transformer and the ripple current of the load.
Determine
A. The average input current, Is
B. The efficiency η,
C. The average transistor current, IA
D. The peak transistor current, Ip
E. The rms transistor current, IR
F. The open-circuit transistor voltage, Voc
G. The primary magnetizing inductor, Lp
a = N s / N p = 0.25 and I 0 = V0 / R = 24 / 0.8 = 30 A
(a) The output power P0 = V0 I 0 = 24 × 30 = 720W
The secondary voltage V2 = Vo + Vd = 24 + 0.7 = 24.7V
The primary voltage V1 = V2 / a = 24.7 / 0.25 = 98.8V

The input voltage Vs = V1 + Vt = 98.8 + 1.2 = 100V
The input power Pi = Vs I s = 1.2 I A + Vd I 0 + P0
Substituting IA=Is gives I s (100 − 1.2 ) = 0.7 × 30 + 720

741
Is = = 7.5 A
98.8

(b) The input power Pi = Vs I s = 100 × 7.5 = 750W
P0 720
The efficiency η= = ×100 = 96.0%
Pi 750
(c) The average transistor current I A = I s = 7.5 A

2I A 7.5
(d) The peak transistor current Ip = = 2× = 30 A
k 0.5
k 0.5
(e) The rms transistor current I R = Ip = × 30 = 12.5 A
3 3
(f) The open-circuit transistor current
Voc = Vs + V2 / a = 100 + 24.7 / 0.25 = 198.8V
Vs k 100 × 0.5
(g) The primary inductance L p = = 3 = 1.67 mH
fI p 10 × 30
Forward converter
Forward biased when vp >0 (➭transistor is on)
L1 ➭Energy is not stored in Np
D1 D2
NF is + iL +
+ i Ns vse D3 C RL vo
+ p
_
vp N _
p
vi _
+
Act as ideal transformer
Q1
vQ1
_ _
R1
Control
R2
Unlike flyback, forward converter operates in continuous mode.

Mode 1: Q1 is on 0 < t ≤ kT
Ns Primary current starts to build up and transfers

ip = ise energy from primary to secondary winding and
Np onto L1C filter and load RL through rectifier
diode D2.
Vs t Primary magnetizing current
imag =
Lp
Ns Vs t Total primary current
i = i p + imag
'
p = ise +
Np Lp
Vs kT Total primary current at the
I '
= I p ( pk ) +
L p end of mode 1.
p ( pk )
⎛ Np ⎞ Reflected peak current in

I p ( pk ) = ⎜⎜ ⎟⎟ I L1( pk ) output inductor L1.
⎝ Ns ⎠
I’p(pk)
Imag
Ip(pk)
Imag
kT t
T
Vse =
Ns
Vs
diL1 Vs − Vo
= I L1 ( pk ) = I L1 (0) +
(Vs − Vo )kT
Np dt L1 L1

Mode 2: Q1 is off kT < t ≤ T
ip cannot change instantaneously. The polarity of transformer

voltage reverses. ➭D2 turns off and D1 and D3 turn on.
While D3 is on, energy is delivered to RL through L1.
D2 L1
D1
iL1=iD3 decreases NF is + iL
+
linearly + Ns
vse D3 C RL vo
+ ip
_
Vo vp _
iL1 = I L1 ( pk ) − t vi
_
Np
L1 Q1
+
0 < t ≤ (1 − k )T _ vQ1
_
R1
Control
D1 and NF provide path for magnetizing current returning to input.

R2
Vo (1 − k )T In continuous
I L1 (0) = iL1 (t = (1 − k )T ) = I L1( pk ) − conduction mode
L1 operation.
1 kT 1 kT N s N
Vo =
T ∫ 0
Vse dt = ∫
T 0 Np
Vs dt = s kVs
Np
Np Vs kT Maximum collector current

I C (max) = I '
= I L1( pk ) +
L p during turn-on.
p ( pk )
Ns
⎛ N p ⎞ Maximum collector
VQ1 (max) = Vs (max) + Vt (max) = Vs (max) ⎜⎜1 + ⎟⎟ voltage at turn-off.
⎝ Nt ⎠
Maximum tertiary winding voltage

Vs kT = Vt (1 − k )T
Time integral of Clamping voltage
input voltage when Q1 is off
when Q1 is on
1 Maximum duty-cycle.
Vt N t
= k max = Function of turns ratio
N
Vs N p 1+ t between resetting (tertiary)
Np winding and primary one.
Duty-cycle must be kept below maximum to avoid saturating

the transformer.
Transformer magnetizing current must be reset to zero at the
end of each cycle to avoid saturation (➭tertiary winding).
Remarks:
Forward converter is widely used with output power
below 200W.
It can also be constructed with a much higher output
power.
The limitations are due to the inability of the power
transistor to handle the voltage and current stresses.
Unlike the flyback, the forward converter requires a
minimum load at the output. Otherwise, excess output
voltage can be produced.
To avoid this situation, a large resistance is
permanently connected across the output terminals.
Remarks (cont’d):
Because forward converter does not store energy in
the transformer, for the same output power level, the
size of the transformer can be made smaller than that
for the flyback.
The output current is reasonably constant due to the
action of the output inductor and the freewheeling
diode D3.
As a results, the output filter capacitor can be made
smaller and its ripple current rating can be much lower
than that required for the flyback.
(study example 14.2 page 610)

Push-Pull converter
dc-ac ac-dc D1 I0
+ + +
V1 Np Ns V2 vo
Is _ _ _
+ + +
V1 Np Ns V2
_ _ D2
Vs
Q2 Q1 Q1 on ➭Vs appears across one-half

_ of primary. (+Vs)
Q2 on ➭Vs appears across the other
half of primary. (-Vs)

V1 = aV1 = aVs Average output voltage
Ns
Vo = V2 =
Np
Transistors operate only during half a cycle (50% duty cycle).

Average transistor current IA=Is/2
Peak transistor current Ip=Is
Open circuit voltage is Voc=2Vs
Applicable for low voltage operation
Pus-pull converter is often driven by a constant source Is such

that primary current is a square wave that produces a
secondary voltage.
(study example 14.3 page 612)
Bridge converter
Half-Bridge
dc or Load
Transformer Rectifier
Supply Full-Bridge
Inverter
Half-Bridge Full-Bridge

(a) Circuit (a) Circuit
Modes
Modes
1 2 3 4
1 2 3 4

(b) Waveforms (b) Waveforms
Mode 1: 0 < t ≤ kT
Half-Bridge Converter Full-Bridge Converter
Q1 on Q2 is off Q1 & Q4 are on Q2 & Q3 are off
N s Vs Ns
Vse = Vse = Vs
Np 2 Np
N s Vs Ns
vL1 = − Vo vL1 = Vs − Vo
Np 2 Np
diL1 vL1 1 ⎡ N s Vs ⎤ diL1 vL1 1 ⎡ N s ⎤

= = ⎢ − Vo ⎥ = = ⎢ Vs − Vo ⎥
dt L1 L1 ⎢⎣ N p 2 ⎥⎦ dt L1 L1 ⎢⎣ N p ⎥⎦
1 ⎡ N s Vs ⎤ 1 ⎡ Ns ⎤
I L1 ( pk ) = I L1 (0) + ⎢ − Vo ⎥ kT I L1 ( pk ) = I L1 (0) + ⎢ Vs − Vo ⎥ kT
L1 ⎢⎣ N p 2 ⎥⎦ L1 ⎢⎣ N p ⎥⎦
Mode 2: kT < t ≤ T/2 (0<k ≤ 0.5)
All switches are off. D1 and D2 are forced to conduct

the magnetizing current from mode 1.
diL1 Vo
=− for 0 < t ≤ (0.5 − k )T
dt L1
I L1 (0) = iL1 [t = (0.5 − k )T ]
Vo (0.5 − k )T
= I L1( pk ) −
L1
Mode 3: 0.5T < t ≤ (0.5+k)T

Q1 off Q2 is on Q1 & Q4 are off Q2 & Q3 are on

D1 is reverse biased D1 is reverse biased
D2 conducts D2 conducts
Circuit operates in same manner as in mode 1
Mode 4: (0.5+k)T < t ≤ T

All switches are off. D1 and D2 are forced to conduct

the magnetizing current from mode 3.
Circuit operates in same manner as in mode 2

Average Output Voltage:
Half-Bridge Converter
2 ⎡ kT ⎛⎜ N s Vs ⎞ T / 2 + kT ⎤ N
Vo = ⎢ ∫ − Vo ⎟dt + ∫ − Vo dt ⎥ = s kVs
T ⎢⎣ 0 ⎜⎝ N p 2 ⎟
⎠
T /2
⎥⎦ N p
Full-Bridge Converter
2 ⎡ kT ⎛⎜ N s ⎞
⎟
T / 2 + kT ⎤ N
Vo = ⎢ ∫ Vs − Vo dt + ∫ − Vo dt ⎥ = s 2kVs
T ⎢⎣ 0 ⎜⎝ N p ⎟
⎠
T /2
⎥⎦ N p
Output Power:
Vs I p ( avg ) k 2 Po
Po = Vo I L = ηPi = η I p ( avg ) =
2 ηVs k
Average primary
current
Po
Po = Vo I L = ηPi = ηVs I p ( avg ) k I p ( avg ) =
ηVs k

Switch Current and Voltage:
Assuming that secondary load current reflected to the primary
side is much greater than the magnetizing current then the
maximum collector currents and voltages are given by:
I C (max) = I p ( avg ) =
2 Po VC (max) = Vs (max)
ηVs k max
Maximum collector
Maximum collector voltage during turn-off
current during turn-on
k max ≤ 0.5 (0 ≤ k ≤ 0.5)
Po VC (max) = Vs (max)
I C (max) = I p ( avg ) =
ηVs k max
Remarks on Half-Bridge Converter

Half-bridge converter is widely used for medium-power
applications.
Because of its core-balancing feature, the half-bridge
converter becomes the predominant choice for output
power ranging from 200 to 400W.
Forward versus half-bridge converter:
– In half-bridge the voltage stress on switches is subject to only the
input voltage and is only half of the forward converter.
– Thus, output power is double for half-bridge converter for same
semiconductor devices and magnetic core.
– Because half-bridge circuit is more complex, for applications below
200W, the flyback or forward converter is considered to be better
choice and more cost-effective.
– Above 400W, the primary and switch currents of half-bridge
converter become very high. Thus, it becomes unsuitable for high-
power applications.
Remarks on Full Bridge Converter
Full-bridge converter uses four power switches
instead of two, as in half-bridge.
Therefore, it requires two more gate drives and
secondary windings in the pulse transformer for
gate control circuit.
This means that full bridge converter is more
expensive than half bridge converter.
For the same output power, the maximum collector
current of a full bridge is only half of the half
bridge.
Thus, the output power of a full bridge is twice that
of a half bridge with the same input voltage and
current.
AC POWER SUPPLIES
Commonly used as standby sources for critical loads and in
applications where ac supplies are not available.
Standby sources are usually called Uninterruptible Power
Supply (UPS)
UPS Configurations
Transition time 4 to 5 ms No transition time

Battery
Standby battery is normally either a nickel-
cadmium or lead-acid type.
Nickel-cadmium is preferable to lead-acid
because:
– the electrolyte of a nickel-cadmium battery is non-
corrosive and does not emit explosive gas.
– It has longer life due to its ability to withstand
overheating or discharging.
– However, its cost is at least three times that of lead-
acid battery.
Alternative arrangement of UPS systems
During normal
operation, load is
connected to main
supply through static
switches and
transformer.
The converter
operates as a
rectifier to charge
the battery.
During power failure, static switches disconnect the main
supply and converter operates as an inverter.

Categories of ac power supplies
Switched-mode ac power supplies
Resonant ac power supplies
Bidirectional ac power supplies
Switched-Mode Ac Power Supplies

The size of the transformer in the previous figure can be
reduced by the addition of a high-frequency dc link as
shown below.
High frequency inverter (PWM) Load frequency inverter
Reduction of size of transformer and dc filter

Resonant Ac Power Supplies
The input-stage of the previous configuration can be
replaced by a resonant inverter.
Resonant inverter (High frequency) PWM Control
Reduction of size of transformer and dc filter
Bidirectional Ac Power Supplies

The diode rectifier and output inverter can be combined
by a cycloconverter with bidirectional switches.
Cycloconverter
(high frequency to low frequency)
Power flow can be controlled

in either directions

MULTISTAGE CONVERSIONS
If input is an ac, an input-stage rectifier is
required.
The rectifier and inverter pair can be replaced

by a converter with bidirectional ac switches.

CONTROL CIRCUITS
Varying the duty cycle k can control the voltage of a
converter.
There are commercially available PWm integrated
circuits (IC) controllers that have all the features to build
a PWM switching supply using a minimum number of
discrete components.
A PWM controller consists of four main functional
components:
– An adjustable clock for setting the switching frequency.
– An output voltage error amplifier.
– A sawtooth generator for providing a sawtooth signal that is
synchronized to the clock.
– A comparator that compares the output error signal with
sawtooth signal. The output of the comparator is the signal that
drives the power switch.
Either voltage-mode control or current-mode control is
normally applied.
Voltage-Mode Control
⎛ Z ⎞ Z v A = V A + Δv a
ve = ⎜⎜1 + 2 ⎟⎟VREF − 2 v A = VE + Δve
⎝ Z1 ⎠ Z1
dc components ripple components
⎛ Z ⎞ Z2 ve Δve Small-signal
Z
VE = ⎜⎜1 + 2 ⎟⎟VREF − 2 VA Δve = − Δv A k= Δk =
Z1 Vcr Vcr duty cycle
⎝ Z1 ⎠ Z1
Peak carrier voltage
vA > VREF High error voltage ve is produced
Δve > 0
Δk > 0
k is increased
Voltage-mode
Increase of output voltage control
Feedback dynamics is determined by the error amplifier

circuit consisting of Z11 and Z22.
Current-Mode Control
Inner current feedback loop
Turn-
Turn-on is synchronized
with clock
Outer voltage feedback loop
Switch is turned off when current reaches a certain value ve set but outer voltage loop.
This way current achieves faster response than the voltage mode.
Primary current waveform acts as a sawtooth wave.
The voltage analog of the current may be provided by a small resistance or current
transformer.

Because of its inherent peak current
limiting capability, current-mode control
can enhance reliability of power switches.
Dynamic performance is improved
because of the use of the additional
current information.
Current-mode control effectively reduces
the system to first order by forcing the
inductor current to be related to the
output voltage, thus achieving faster
response.
MAGNETIC DESIGN CONSIDERATIONS

Inductors are used as storage Transformers are commonly
of energy during energy used to step-up or step-down
transfer. voltages
Carry often dc current while Magnetic flux is a key element

trying to supply constant dc in voltage transformation and
current. offering inductance.
Em 2πfNφm
High dc current may saturate E= = = 4.44 fNφm
2 2
the magnetic core making
inductor ineffective. Primary voltage

Transformer Design
V1 = K t fN1φm
⎧4.44 for sinusoidal wave
Kt = ⎨ Apparent transformer
⎩4 for triangular wave
power
N1 = N 2 ⇒ V1 = V2 = V , I1 = I 2 = I and Pt = VI
Pt = K t fNφm I = K t fBm Ac NI
Cross-sectional area
Flux density
of flux path
Ampere-turns NI = K uWa J
Fill factor Window Current

0.4 to 0.6 area density
Pt
Pt = K t fBm Ac K uWa J Ap = AcWa =
K t fBm K u J
J = K j Apx
1
⎡ Pt ×10 ⎤ 4 1− x Relates core area to transformer
Ap = ⎢ ⎥ (cm 4 )
⎢⎣ t m u j ⎥⎦
K fB K K power requirement.
Amount of copper wire, and the amount of iron ferrite or

other core material determine the transformer power
capability Pt.
From calculated value of Ap, the core type can be selected
and the core characteristics and dimensions can be found
from the manufacturer’s data.
Core area Ac for various core types
Study example 14.6 page 633)
Dc Inductor Design
For distributed air gap cores: N 2 μ 0 μ r Ac
L= = ×N2
ℜ lc
For finite air gap length lg: N2 μ A
L= = 0 c ×N2
(see Appendix B) ℜ c + ℜ g l + lc
g
μr
LI
LI LI 2
N= = ×10 ⇒ NI =
4
×10 4
φ Bc Ac Bc Ac
LI 2 × 10 4 ⎡ LI 2 ×10 4 ⎤ Relates to stored

Ap = Wa Ac = =⎢ ⎥ (cm )
4
energy WL=1/2LI2
Bc K u J ⎣⎢ Bc K u K j ⎦⎥
The
The amount
amount ofof copper
copper wire,
wire, and
and the
the amount
amount ofof iron
iron ferrite
ferrite or
or other
other
material,
material, determine
determine the
the inductor’s
inductor’s energy
energy storage capability WLL.. From
storage capability From the
the
calculated
calculated value of App,, the
value of the core
core type
type can
can be
be selected
selected and
and the
the core
core
characteristics
characteristics and
and dimensions
dimensions can can bebe found
found from
from manufacturer’s
manufacturer’s data.
data.
Dr. Adel Gastli Study example 14.7Supplies
Power page 635) 58
Magnetic Saturation
Any dc imbalance may saturate the inductor or
transformer resulting in high-magnetizing
current.
An ideal core should exhibit a very high relative
permeability in the normal operation region and
under dc imbalance conditions.
It should not go into hard saturation.
This saturation problem can be minimized by
having two permeability regions in the core, low
and high permeability.
An air gap may be inserted.
Single toroids Two toroids

High permeability
(Normal operation) High
permeability
Low
Low permeability
Partial gap permeability
(saturation)
These two designs avoid hard saturation of the

magnetic core taking place.

Summary
Industrial power supplies are of two types:
– dc supplies
– ac supplies
In a single stage conversion, the isolating
transformer has to operate at the output
frequency.
To reduce the size of the transformer and
meet the industrial specifications, multistage
conversions are normally required.
Summary (cont’d)
There are various power supply topologies,

depending on the output power requirement
and acceptable complexity.
Converters with bidirectional switches,
which allow the control of power flow in
either direction, require synthesizing the
switching functions to obtain the desired
output waveforms.

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ADVANCED

Dr. Adel Gastli

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 2

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 3

Losses in switches are characterized

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 4

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 7

Switching with Inductive Load

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 8

Switch current builds up to +Io linearly (assumption).

Diode ceases to conduct Switch voltage ramps linearly

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 9

ton1 ton2 Ts toff1 toff2

Psw = Vs I o [ton1 + ton 2 + toff 1 + toff 2 ] f s s max t + t + t + t

Switching power loss

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 11

Switching with Capacitive Load

Diode is reverse biased and does not conduct

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 12

Switch voltage ramps linearly up to +Vo Is + S

After build up is over, the diode begins to conduct. Vsw = Vo

Current through switch ramps linearly down to zero.

Switch turns off

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 13

Switch voltage ramps linearly down to zero.

ton1 ton2 Ts toff1 toff2

Psw = Vs I o [ton1 + ton 2 + toff 1 + toff 2 ] f s s max t + t + t + t

Switching power loss

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 15

Minimizing Switching Losses

Divert the energy from the switch to a

Switch at either zero current or at zero

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 16

Limit stresses on the switch to safe

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 17

Rate of voltage change dv/dt High rate of voltage and

Special circuits are used to slow down the high rate of

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 18

The switch is also assumed to have limited maximum rates

Without Snubber Capacitor L Io

Power loss in the switch

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 22

With Snubber Capacitor L Io

isw : I o ↓ 0 (linearly) in time t f 2

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 24

tf2 is determined by the value of the capacitor.

vsw rises with a small slope.

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 26

Note the very significant reduction in the power

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 27

The maximum rate of dvsw/dt occurs when the

This equation can be used to calculate the

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 28

D2 is short - circuited and vc = Vs

isw : I o ↑ I rr + I o until vsw = 0 ⇒ isw : I rr + I o ↓ I o

I rr Current overshoot is determined by the amount of the

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 30

Diode D2 isolates the rate of fall of the switch

Designers restrict the amount of current overshoot

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 32

Dr. Adel Gastli Semiconductor Switches: Losses & Protection 34

First, let’s consider R=∞. D2

(linearly at rated dv/dt)

Losses in switches are characterized

Divert the energy from the switch to a

Switch at either zero current or at zero

Limit stresses on the switch to safe

It has also presented the means of

The turn-on time can be reduced by connecting an RC

The gate signal for the

Feedback via the capacitor C regulates the rate of rise

Applying a gate voltage turns it on

The gate drive circuit should have

The transistor turning-on time (ton) can be

After turn on, βF can be increased to a