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Clock New inputs to outputs of
dcombinational
signal combinational
I block,available block available
(C+5)-C
En%ble \
n r
signal Pulse width equal to 5 ( m a . gate delay) units
Figure 1: Minimizingglitch power dissipation in a synchronoussequential circuitdesignand various optimizations: (a) Timing waveform
for the clock signal and derivation of the enable signalfor control logic from it. (b) Controllogic comprising n and p control transistors con-
nected to VSS and VDD, respectively, is enabledwhen the last input to the gate arrives. This prevents unnecessarycharging and discharging
to VDDand Vss, respectively, of output capacitanceand internal capacitances in P pull-up and N pull-down and also prevents short-circuit
current during the time when input signals are unsteady. Note that for this particular control logic, two de!laychains are needed, one for the
p and the other for the n control transistor. However, control logic types that control connection to only VDDor only Vss need a single
delay chain, but provide a little less effective glitch power reduction [SI. (c) Glitchesoccurringin a combinationallogic block at the outputs
of gates that have multiple inputs changing asynchronously. (d) Glitches minimized by adding control logic to every potentially glitchy
gate and enabling it through a delay chain when the last input to the gate stabilizes. (e) Control logic enabled later for certain gates not on
any critical path so as to have synchronousevaluation of a number of gates and thereby reduce the number of delay elements required. (f)
Control logic overhead reduced by sharing control logic across multiple synchronouslyevaluating gates. (g) Control logic for certain gates
not on any critical path added and/or enabled later so as to make arrival times of inputs to a fanout gate@)equal, thereby eliminating delay
element, control logic, and wiring overhead for the latter gate.
so in very high-performance circuits and in inputs will have steady-state values latest by
standard-cell based semicustom design, where it five, four, and two time units, respectively.
can be as high as 50% of total power dissipation In order to prevent glitches at the output of gate
[12, 131. However, it should be noted that short- ,001, its control logic can be enabled at time five
circuit currents virtually disappear when VDD - and should re-main enabled for at least five time
V,, + V T ~which
, is somewhat true for digital units, which is the delay of the gate, so that the
signal processors, but not so for microprocessors, gate logic may evaluate completely.
where VDD’Sare relatively higher. Therefore we use an enable signal for
In this paper, we present a new the combinational block with a high period equal
framework called gate triggering for minimizing to the maximum delay for any gate in the block
glitch power dissipation in complementary static (five units for the combinational block of Fig.
CMOS ICs which we discuss in the next section. l(d)). As shown in Figs. I(a) and (d), the enable
An added advantage of our approach is that signal is generated by ANDing clock
short-circuit power dissipation at gates that are complement with the clock signal delayed by
controlled is also minimized. Next, in Sec, 3, we this maximum delay. This initial enable signal is
discuss approaches to minimizing logic and then delayed by various amounts using a delay
wiring overheads in our framework. Sec. 4 chain comprising delay elements as in Fig. l(d).
presents an integer linear programming (ILP) The output of a delay element in this chain
formulation to optimize overheads subject to a provides an appropriately delayed version of the
critical-path delay constraint. Application of the initial enable signal that can be used to trigger a
new approach to test circuits (such as ripple gate(s). For example, in Fig. I(d), gates go1 and
carry adder and array multiplier) in 1 . 2 ~ gl 1, for both of which the last input stabilizes by
technology yields 95% or more elimination of time five, are controlled by the initial enable
glitch power dissipation with negligible area and signal delayed by five time units. Similarly, gate
timing overheads after optimization. Then in g32 is enabled at time nine, since that is when its
Sec. 5 we briefly discuss related previous work. last input (the bottom input) stabilizes. In
Conclusions are in Sec. 6. contrast, gate ,021 does not need any control
logic or enable signal since both of its inputs
2 Proposed Methodology: Gate Triggering have equal delays.
The key idea we employ to minimize Using the above approach, all
glitches is to trigger logic evaluation at a gate potentially glitchy gates are triggered by the
only after all of its inputs have stabilized. For enable signal when the last input to them
this purpose, to every potentially glitchy gate, we stabilizes, thus ideally preventing all glitches in
add some small control logic, which, when the combinational block. In practice, however,
enabled, triggers logic evaluation at the gate (see minor or partial glitches may occur due to the
Fig. l(d)). Essentially, this logic controls gate nonideal behavior of transistors. It should also be
connection to VDD andlor VSS. Fig. l(b) shows noted that short-circuit power dis-sipation in all
one possible type of control logic. Various types triggered gates can be minimized by triggering
of control logic and their analyses and associated them after the last input has stabilized, since
simulation results are the subject of another before triggering, gate connection to V,, and/or
paper [8]. In order to enable the control logic for VSS is cut off by the control logic. However, in
different gates in the combinational logic block most cases, it will not be cost-effective to control
of Fig. l(d) at the proper times (i.e., when the all gates in this manner to minimize short-circuit
last input to the individual gates has stabilized), power dissipation because of the overheads it
we first perform a timing simulation of the will entail. Rather, it will be best to control few
combinational block. Timing simulation is an select gates where potential for glitch and short-
essential step in the design flow of a VLSI chip circuit power savings is maximum.
[18] (e.g., to determine the critical-path delay in The main overheads of our approach are
a combinational block, which in turn determines logic (delay element and control logic) overhead,
the clock period). Hence it does not represent an wiring overhead for generating and routing the
extra step in the application of our method. From enable signal for potentially glitchy gates, and a
this timing simulation, we obtain the delays of delay overhead because of an increased delay for
different gates and also the latest times by which the combinational block. The logic overhead for
the various inputs of a gate will have stabilized. generating the initial enable signal using an
For instance, in Fig. 1(d), gate go1 has a delay of AND gate and a delay element is minimal. We
five time units, and its top, middle, and bottom have observed in our simulations that the delay
overhead is negligible. Note that reducingthe triggered simultaneously. For instance, in Fig.
number of delay elements or the amount of l(e), the set of gates go1 and g l l can be
control logic should lead to lower wiring controlled by the same control logic as shown in
overhead, since each delay element corresponds Fig. l(f). However, it should be noted that
to a distinct enable signal to be routed and each sharing the control logic in this way may mean
control logic corresponds to an enable signal to that the transistors of the ccintrol logic will need
be routed to control it. In the next section, we to be sized up (compared to when no sharing is
provide some ways by which logic overhead, and done) to avoid increase in delay of the
thus wiring overhead, can be minimized. combinational block.
Another way to reduce the amount of
3. Logic and Wiring Overhead Optimization control logic is to schedule the triggering of
earlier gates so that inputs to later gates are
3.1 Delay Element Optimization synchronized. For instance, in Fig. l(g), gates
The delay element overhead depends g l l and g o 2 are triggexed later than normal
primarily upon the total delay provided by all and control logic is added to gate 9 2 1 (compare
delay elements and the number of delay Fig. l(g) to Fig. l(f)) so that all inputs to gates
elements. The number of delay elements in turn 9-12, 922, 903, and g 2 3 are synchronized,
depends upon the number of delayed versions of thereby obviating the need for controlling these
the enable signal needed from the delay chain. gates using control logic. Note again that the
Therefore, the number of delay elements can be gates selected for late triggering are those not on
reduced by synchronously triggering with a any critical path in order not to increase the delay
common enable signal as many gates as possible of the combinational block:. This results in less
after their last inputs have stabilized. For control logic, and possibly less delay element
example, in Fig. l(e), the set of gates go1 and and wiring overhead, since: some enable signals
g l l , the set of gates g02, ,012, g22, and g32, and no longer need to be generated and routed.
the set of gates 803, 813, and g23 are all The various optimizations discussed
triggered synchronously by enable signals above are not exclusive, but may be used in
delayed by five, ten, and fourteen time units, conjunction to various degrees depending upon
respectively. Note that to synchronize, some the combinational logic block under
gates are triggered later than normal (such as consideration to minimize the total overhead. In
g32, and g13 in Fig. l(e) compared to Fig. l(d)). the next section, we formulate this overhead
Also, note that the gates selected for late minimization problem as an integer linear
triggering are not on any critical path (shown program (ILP) subject to a critical-path delay
with bold lines in Fig. l(e)) so as not to increase constraint.
the overall delay of the combinational block. The
application of this optimization thus results in a 4 ILP Formulation for Overhead Minimiza-
much reduced number of delay elements in the tion
delay chain (three in Fig. l(e) compared to five The overhead minimization problem
in Fig. l(d)) Note that a smaller number of delay can be stated as fol-lows:
elements also means a smaller wiring overhead,
since a fewer number of distinct enable signals Problem 1 Minimize a weighted sum of the total
need to be routed. The delay element we chose is amount of delay and the number of delay
a transmission gate with appropriately-sized elements in the delay chain, and the number of
transistors to provide the required amount of gates triggered (which corresponds to the
delay. We selected a transmission gate because it amount of control logic .and wiring required),
requires less area and consumes very little such that: ( I ) there are no glitches, and (2) the
power. A detailed discussion and comparison of critical-path delay of the circuit does not exceed
delay elements motivating our choice is the a specijied upper bound
subject of another paper ([9]). Clearly, the total amount of delay
corresponds to the latest triggering time over all
3.2 Control Logic Optimization gates, while the number of delayelements to the
There are two ways in which control number of distinct gate triggering times (see Fig.
logic may be optimized. First, after applying the I(&). No glitching requires that every gate with
technique to reduce the number of delay asynchronous inputs must be triggered no earlier
elements discussed above, we can use the same than the latest input arrival time for that gate;
control logic to control all gates that are to be obviously, a gate with synchronous inputs will
not glitch and hence should not be triggered. The The second point to be understood is the
problem of glitch minimization, in which the correspondence between the two principal
amount of glitching is part of the objective to be constraints of Problem 1 (i.e.. no glitches and
minimized, as opposed to glitch elimination bounded critical-path delay increase) and the
being considered here, seems to be more constraints of the table. Constraints RI through
difficult, and will be considered in future R7 ensure that a gate is triggered when its inputs
research. The second constraint in Problem 1 are asynchronous.
implies the following theorem. Constraints RR and R9 ensure that whenever a
gate is triggered, its triggering time is no earlier
Theorem 1 There exists a finite set Tu of than the latest input arrival time for the gate, so
triggering time instants for every gate U in the that all glitches are eliminated. We note that the
circuit such that the optimal solution to Problem upper bound on the triggering time for every gate
I is not agected by restricting U ’ S triggering time automatically enforces the constraint on the
to T,. increase in the critical-path delay. The objective
Proof Outline: The latest input arrival time for a function in the table directly corresponds to the
gate in the original circuit (before applying the objective in Problem 1.
glitch-minimization technique) and the upper
bound on critical-path delay set lower and upper 5 Related Work
bounds, respectively, on the triggering time of Glitch and short-circuit power
the gate. Triggering a gate later than the lower dissipation are discussed in [12, 131. Glitch
bound time, rather than triggering it at the lower- estimation, modeling, and propagation issues are
bound time, can lead to lower overhead only if it covered in [3, 11, 161. The importance of glitch
satisfies one of the following two conditions. (1) minimization for various applications is
The gate triggering time synchronizes with the considered in [4, 17, 191. Designing two-level
triggering time of at least one other gate, so that glitch-free circuits using logic redesign,
a common control signal can be used for both assuming only one input changes at a time, is
gates, thereby saving a delay element (see Fig. addressed in [6]. Glitch removal through path
1(f)). (2) The gate triggering time is such that the balancing obtained via, say, transistor sizing or
gate output synchronizes with the arrival of other layout changes, is discussed in [lo, 12, 131; this
inputs to some fan-out gate, thereby saving a can be cumbersome and involves trial and error.
control element at the fan-out gate, which does Furthermore, in deep submicron technologies,
not need to be controlled (see Fig. l(g)). There transistor sizing will not be very effective for
are only a finite set of triggering time instants path balancing since logic delays become
that will lead to one of these two relatively smaller compared to interconnect
synchronizations. delays. Retiming and buffer placement
Space constraints do not permit us to approaches to filter or reduce glitches and glitch
specify and prove what the exact finite set of propagation are described in [2, 71; these
triggering times implied by Theorem 1 is for a approaches, although somewhat effective, entail
gate. appreciable area overheads for flipflops and
The constants, variables, expressions, objective buffers. Glitch reduction at the RTL level in
(corresponding to Problem l), and constraints for control flow intensive designs is given in [15].
the ILP and their descriptions are given for easy Therefore, current methods for glitch
reference in Table 1. Only two points need to be reduction are either (i) not applicable in all
explained, and after that the rest of the ILP is contexts, or (ii) can not be auto-mated and are ad
easily understood by inspection of the detailed hoc, or (iii) are not very effective, or (iv) have
descriptions in the table. First, we need to high areddelay overheads, or (v) restrict the
understand for each variable the constraints that manner in which logic is transformed to a gate
enforce the values indicated for it in the table. realization. There is no methodical, generally
The value of variable PUu,; en-forced by applicable approach to minimizing glitch power
constraints RI, RI, and R3 that of PU.; by Rq,R.? dissipation. Our proposed gate triggering
and R6 that of by RI. and that of A , ; by R8 approach in this paper attempts to overcome all
and Ry.When gate is triggered, the value of Bu,i the above limitations of current approaches.
is enforced by constraints RIOand RI,, otherwise,
by constraints RIO,Rlz and RI.?.The value of Ai is 6 Conclusions
enforced by constraints R14 and R I ~and , finally, Although research into various aspects
that of X i by R16,R I , and RIR. of glitch power dissipation has been undertaken
in the past, most approaches to addressing it are [8] N.R. Mahapatra, S.V. Gariniella, and A. Tareen,
ad hoc and limited in their applicability. This “Efficient techniques for designing static CMOS ICs
paper presented a new framework called gate with very low glitch power diss.ipation,”submitted to
triggering for systematically minimizing glitch ISCAS 2000.
[9] N.R. Mahapatra, A. Tareen, and S.V. Garimella,
power dissipation in static CMOS ICs. The logic “An experimental and analytical comparison of delay
and wiring over-heads of our approach were elements,” Technical Report, Dept. of Computer Sc. &
analyzed and an ILP formulation was given to Eng., SUNY-Buffalo,Buffalo, NY, 1999.
minimize these overheads subject to a critical- [IO] E.J. McCluskey, “Logic design principles with
path delay constraint. Application of the new emphasis on testable semicustomcircuits,” Prentice
approach to test circuits (such as ripple carry Hull, Englewood Cliffs, NJ, 1986.
adder and array multiplier) yields 95% or more [ 1I] F.N. Najm, “A survey of of power estimation
elimination of glitch and, in gates to which techniques in VLSI circuits,” LEEE T-VLSI,Vol. 2,
applied, short-circuit power dissipation with very No. 4, Dec. 1994.
[ 121 M. Pedram, “Power minirnization in IC design:
little to negligible area and timing overheads Principles and applications,” ACM TODAES, Vol. 1,
after optimization. NO. 1, pp. 3-56, Jan. 1996.
[ 131J.M. Rabaey, “Digital Integrate Circuits,”
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Set ot all gates in me combina-
V tional gate network. D,%u E V Delay for gate U.
T = (TO,TI,. . . ,Tm-1)
'et o possible gate tngger- 2;= Set of all possible mggenng
,... ,T,,,,,,L-~)
(Tu,o,Tu.~ timesforgateu.
T:" = Set of all possible input arrival
F:,u EV Set of fan-in gates for gate U.
v
TI I=
.>C:n,-i).
V:'Yo,C:i>.. timesforgateu.
- Variables
1, it the latest input amval - 1, if the earliest input a m v d
I:~',o _< i < IT:I,U E v timeforgateuisT~:;,e~se= I:?, o I i < IT> I, U E v time for gate u is T::~,else =
n n
= I . it the inputs to gate U = 1, if gate U is aiggered at
, ,UEV
At"g are asynchronous (i.e., if gate U < ITul, E timeT,,;,else= 0.
needs to be triggered).
- 1. it the output of gate U be- = 1. if at least one gate is trig-
B,,;.O 5 i < JT,J,uE V comes stableat Tu,; D,.
-
+ Ai.0 5 i < JTJ gered at time T;, else = 0.
- 1. if the latest mggenng
x..o 5 i 5 IT1 time over all gates is Ti,else
-
-