EE141

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Homework 3 to be posted today, Hw 2 due

Lab 3 next week


Midterm on Febr 16

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Last lecture


Sizing inverters

Today’s lecture


Complex logic


Optimizing complex logic

Reading (2.3, 3.3.1-3.3.2)

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Output = f(In) Output = f(In, Previous In)

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At every point in time (except during the switching

transients) each gate output is connected to either
VDD or VSS via a low resistive path.

The outputs of the gates assume at all times the value

of the Boolean function implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).

(Will contrast this later to dynamic circuit style.)

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VDD

In1
PMOS only
In2 PUN

…
InN
F(In1,In2,…InN)
In1
In2 … PDN
NMOS only
InN

PUN and PDN are dual logic networks

PUN and PDN functions are complementary

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Transistor
switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B
AND
X Y Y = X if A AND B
A

B
OR
X Y Y = X if A OR B


NMOS transistors pass a “strong” 0 but a “weak” 1

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PMOS switch closes when switch control is low

A B

NOR
X Y Y = X if A AND B = A + B
A

B
NAND X Y Y = X if A OR B = AB

PMOS transistors pass a “strong” 1 but a “weak” 0

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VDD VDD
PUN
S D
VDD

D 0
VDD S 0
VDD - VTn

VGS
CL CL

PDN VDD
0 VDD
|VTp|

VGS
D CL S CL
VDD

S D

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PUP is the dual to PDN

(can be shown using DeMorgan’s Theorems)
A + B = AB
AB = A + B

Static CMOS gates are always inverting

AND = NAND + INV

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PDN: G = AB
Conduction to GND

PUN: F = A + B = AB
Conduction to VDD

G(In1,In2,In3,…)
F(In1,In2,In3,…)

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B
A
C

D
OUT = D + A • (B + C)
A
D
B C

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Fullrail-to-rail swing


Symmetrical VTC


Propagation delay function of load
capacitance and resistance of transistors


No static power dissipation


Direct path current during switching

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All of these are decoders

Which one is “best”?

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Is it better to drive a big capacitive load

directly with the NAND gate, or after some
buffering?

CL CL


Method to answer both of these questions:

Logical effort


Extension of buffer sizing problem
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In Out
C1 C2 CN
1 2 N CL = CN+1

fi = Ci+1/Ci
For given N: Ci+1/Ci = Ci/Ci-1
To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?

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Cdnand = 6CD 2 2
Cgnand = 4CG = (4/3) Cginv
CD/CG=
2

tpNAND = kR(Cint + CL)

= k(Rmin/W)(WCdnand + CL)
= k(RminCgnand)(Cdnand /Cgnand +CL/(WCgnand))
= k(RminCgnand)(
3/2 +CL/(WCgnand))
= tinv (2
+ (4/3)f)

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4
Cdnor = 6CD
Cgnor = 5CG = (5/3) Cginv
4
CD/CG=

1 1

tpNAND = kR(Cint + CL)

= k(Rmin/W)(WCdnor + CL)
= k(RminCgnor)(Cdnor /Cgnor +CL/(WCgnor))
= k(RminCgnor)(
6/5 +CL/(WCgnor))
= tinv (2
+ (5/3)f)

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tpgate = tinv (p
+ LE
f)

Measure everything in units of tinv (divide by tinv):

p – intrinsic delay (kg) - gate parameter
f(W)

LE – logical effort (k) – gate parameter
f(W)
f – electrical effort (effective fanout)

Normalize everything to an inverter:

LEinv =1, pinv = 

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Gate delay:

Delay = EF + p (measured in units of tinv)

effective fanout intrinsic delay

Effective fanout:
EF = LE f

logical effort electrical fanout = Cout/Cin

Logical effort is a function of topology, independent of sizing

Effective fanout is a function of load/gate size

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Inverter has the smallest logical effort and

intrinsic delay of all static CMOS gates


Logical effort LE is defined as:

(Req,gateCin,gate)/(Req,invCin,inv)


Easiest way to calculate (usually):
–
Size gate to deliver same current as an inverter, take
ratio of gate input capacitance to inverter capacitance


LE increases with gate complexity

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Calculating LE by sizing for same drive strength:

LE = 1 LE = 4/3 LE = 5/3
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t pNAND
Normalized delay (d)

LE= t pINV
p=
d=
LE=
p=
d=

p =
·Fan-in
(for top input) 1 2 3 4 5 6 7
Fan-out (f)

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t pNAND
Normalized delay (d)
LE=4/3 t pINV
p=2

d=(4/3)f+2

LE=1
p=

d=f+

p = ·Fan-in
(for top input) 1 2 3 4 5 6 7
Fan-out (f)

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From Sutherland, Sproull

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Need to set a convention:

What does a gate of size ‘2’ mean?

For an inverter it is clear:


Cinv = 2, Rinv =


For a gate, two possibilities:


Cgate = 2Cinv


Rgate = Rinv/2

In my notes, size  Cgate/Cinv


Size 2 gate has twice the input capacitance of a unit
inverter

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Branching effort:

CL,on_path

CL,off_path

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Effective fanout: EFi = LEifi

Path electrical fanout: F = Cout/Cin
Path logical effort: LE = LE1LE2…LEN
Branching effort: B = b1b2…bN
Path effort: PE = LE 
F

Path delay D = di = pi + EFi

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When each stage bears the same effort:

Effective fanouts: LE1f1 = LE2f2 = … = LENfN

Minimum path delay

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For a given load,

and given input capacitance of the first gate
Find optimal number of stages and optimal sizing

Remember: we can always add inverters to the end of the chain

The ‘best effective fanout’ is still around 4

(3.6 with
=1)

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LE = 1 LE = 5/3 LE = 5/3 LE = 1
f=a f = b/a f = c/b f = 5/c
Electrical fanout, F =

LE =
PE =
EF/stage =
a=
b=
c=
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LE = 1 LE = 5/3 LE = 5/3 LE = 1
f=a f = b/a f = c/b f = 5/c

Electrical fanout, F = 5 5/c = 1.93

LE = 1·(5/3)·(5/3)·1 = (25/9) (5/3)c/b = 1.93
PE = (
LE)·F = (125/9) (5/3)b/a = 1.93
EF/stage = (125/9)^(1/4) = 1.93
a = 1.93
b = 2.23
c = 2.59
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LE=10/3 1 LE=2 5/3 LE=4/3 5/3 4/3 1

LE = 10/3
LE = 10/3
LE = 80/27
P= 8 + 1 P=4 + 2 P= 2 + 2 + 2 + 1

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Branching effort:

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Branching Example 1
15 LE = 1
FO = 90/5 = 18
90
PE = 18 (wrong!)
5
SE1 = (15+15)/5 = 6
15 90 SE2 = 90/15 = 6
PE = 36, not 18!
Introduce new kind of effort to account for branching:
Con-path + Coff-path
•
Branching Effort: b=
Con-path
•
Path Branching Effort: B=
b i

Now we can compute the path effort:

•
Path Effort: PE =
LE·FO·B
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Branching Example 2
Select gate sizes y and z to minimize delay from A to B

Logical Effort: LE = (4/3)3

Electrical Effort: FO = Cout/Cin = 9

Branching Effort: B = 2•3 = 6

Path Effort: PE =
LE·FOB= 128

Work backward for sizes:
Best Stage Effort: SE = PE1/3
5 9C•(4/3)
z= = 2.4C
5
Delay: 3•5 + 3•2 = 21 3z•(4/3)
D= y= = 1.9C
5
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Compute the path effort: PE = (
LE)BF

Find the best number of stages N ~ log4PE


Compute the effective fanout/stage EF = PE1/N


Sketch the path with this number of stages


Work either from either end, find sizes:
Cin = Cout*LE/EF

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

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