REMOTE POWER MONITORING SYSTEM USING

MICROCONTROLLER
A Project report

Submitted in partial fulfillment of the requirement

For the award of the degree of

BACHELOR OF TECHNOLOGY

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

By
B. MOHAN KRISHNA (05391A0468)
B. VIDYA SAGAR (05391A0489)
S.K. RABBANI (05391A0475)
Under the guidance of

(Mr. P.J.REGINALD)
Assistant Professor

Department of Electronics and Communication Engineering

VIGNAN’S ENGINEERING COLLEGE
ISO Certified, NBA & NAAC Accredited with ‘A’ Grade
VADLAMUDI – 522 213
GUNTUR (Dt.)
(2008-09)
 CERTIFICATE
This is to certify that this project report entitled

REMOTE POWER MONITORING USING SYSTEM

MICROCONTROLLER

is a bonafide record of work done by

B. MOHAN KRISHNA (05391A0468)
B. VIDYA SAGAR (05391A0489)
S.K. RABBANI (05391A0475)
Under my guidance and supervision and submitted in partial fulfillment of the requirements for
the award of the degree of Bachelor of Technology in Electronics and Communication
Engineering by the Jawaharlal Nehru Technological University, Kakinada.

(Mr. P.J.REGINALD)
Guide
Certified by the Head of the Department

(Dr. D. VENKATA RAO)

Professor and Head

Department of Electronics and Communication Engineering

VIGNAN’S ENGINEERING COLLEGE
ISO Certified, NBA & NAAC Accredited with ‘A’ Grade
VADLAMUDI – 522 213
GUNTUR (Dt.)
(2008-09)
 ACKNOWLEDGEMENT
The completion of any project brings with it a sense of satisfaction, but it is never
complete without thanking those people who made it possible and whose constant support has
crowned our efforts with success.
We would also like to thank our guide, Mr. P.J.REGINALD Assistant
professor, Dept. of Electronics And Communication for his expert guidance, encouragement
and valuable suggestions at every step.
We would also like to express our gratitude to Dr. D. VENKATA RAO, Head of the
Department, Electronics and Communication V.E.C, Vadlamudi, for encouraging and
inspiring us to carry out the project in the department lab.
We are grateful to our esteemed principal, VIGNAN’S ENGINEERING COLLEGE,
Vadlamudi, Dr. K.V.N.SRINIVASA RAO f o r supporting and funding this endeavor.
We also would like to thank all the staff members of E&C dept., classmates for
providing us with the required facilities and support towards the completion of the project.

PROJECT ASSOCIATES
B. MOHAN KRISHNA (05391A0468)
B. VIDYA SAGAR (05391A0489)
S.K. RABBANI (05391A0475)
 ABSTRACT

Electricity is the modern man's most convenient and useful form of energy without

which the present social infrastructure would not be feasible. The increase in per capita

production is the reflection of the increase in the living standard of people. When

importance of electricity is on the increasing side, then how much should theft of this

energy or illegal consumption of power from the transmission lines be averted? Power theft

has become a great challenge to the electricity board. Our project identifies the Power theft

and indicates it to the Electricity board through Power line. We had also dealt about the

remote monitoring of an energy meter. The project is constructed with the popular

microcontroller MC551 series 8051 microcontroller, power measurement IC, voltage,

current transformers.

The central office is having a PC connected to the different energy meters fixed at

different organizations wireless link. The energy meter connected at the consumer point

continuous reads power data and sends it to the PC. The program written in micro

controller to read and transmit the power data to the PC on request. The PC can connected

to number of users with there unique ID number. Initially PC transmits the ID code to the

energy meters then the corresponding energy meters transmits the energy information to

the PC with the help of this centrally we can monitor energy consumed by different

consumers and useful for analyzing the unauthorized usage. The software is written in the

PC for sending request to the energy meter and receiving the energy meter and receiving

the energy data from consumer point.

CONTENTS
1. INTRODUCTION 1
2. BLOCK DIAGRAM 3
3. POWER MEASURMENT 5
3.1 VOLTAGE TRANSFORMERS 5
3.1.1 PRINCIPLE OF OPERATION 5
3.1.2 TYPICAL TERMS USED FOR SPECIFYING A PT 6
3.2 CURRENT TRANSFORMERS 8
3.2.1 PRINCIPLE OF OPERATION 8
4. ADC0809 9
4.1 PIN CONFIGURATION 10
4.2 FEATURES 10
4.3 KEY SPECIFICATIONS 11
4.4 BLOCK DIAGRAM 11
4.5 FUNCTIONAL DESCRIPTION 12
4.5.1 MULTIPLEXER 12
4.5.2 CONVERTER CHARACTERSTICS 12
5. 89C52 MICROCONTROLLER 14
5.1 INTRODUCTION 14
5.2 DESCRIPTION 15
5.3 FEATURES 15
5.4 PIN DIGRAM 16
5.5 PIN CONFIGURATIONS 17
5.6 PIN DESCRIPTION 17
5.7 MEMORY 23
 5.7.1 ON-CHIP MEMORY 24
5.7.2 EXTERNAL CODE MEMORY 25
5.7.3 EXTERNAL RAM 25
5.7.4 SPECIAL FUNCTION REGISTER (SFR) MEMORY 26
5.8 ADDRESSING MODES 27
5.8.1 IMMEDIATE ADDRESSING 27
5.8.2 DIRECT ADDRESSING 28
5.8.3 EXTERNAL INDIRECT 28
5.9 PROGRAMMING THE FLASH MEMORY 28
5.10 PROGRAMMING ALGORITHM 29
6. SERIAL COMMUNICATION 32
6.1 SPEED OF TRANSMISSION 34
6.2 RS-232 34
6.3 RS-232 CABLING 35
6.4 MAX 232C 38
6.4.1 LOGIC DIAGRAM 39
6.4.2 OPERATING CIRCUIT 39
6.4.3 FEATURES 40
6.4.4 APPLICATIONS 40
6.4.5 RS-232 DRIVERS 40
6.4.6 RS-232 RECEIVERS 41
7.CIRCUIT DIAGRAM 42
8. HARDWARE PHOTOGRAPHY 45
9.RESULT 46
10.CONCLUSION AND SCOPE OF FUTURE WORK 47
11. MICROCONTROLLER PROGRAM 48
12. BIBLIOGRAPHY 71
 1. INTRODUCTION

With the electric industry undergoing change, increased attention is being focused

on power supply reliability and power quality. Power providers and users alike are

concerned about reliable power, whether the focus is on interruptions and disturbances or

extended outages. One of the most critical elements in ensuring reliability is monitoring

power system performance. Monitoring can provide information about power flow and

demand and help identify the cause of power system disturbances. It can even help identify

problem conditions on a power system before they cause interruptions or disturbances.

The implementation of this project is to monitor the power consumed by a model

organization such a household consumers from a centrally located point. Monitoring the

power means calculating the power consumed exactly by the user at a given time. The

power consumed by the user is measured and communicated to the controlling substation

when ever needed by the person at the sub station. The communication can be of two types

1. Wired communication like using the existing transmission lines and sending the

data by modulating with high frequency carrier signal or using the existing

telephone lines.

2. Wireless communication based on the available technologies like IR

communication, Bluetooth technology or GSM technology.

Among these two communications, the one used in our project is wired communication

which suits best for long distance communication. A microcontroller is equipped at the
1
consumers terminal to measure the power consumed by the user at a given instant. The

process is not continuous it does this when ever there is a request from the substation

control person. The power can be on and off to the user from the substation by operating a

relay connected in series to the user. Whenever there is no supply at the user the

information can be obtained at the substation. The practical application of the project can

be implemented along with a data backup for billing and dispatching the bills with out

manual labor and avoid any disturbances in supply at the user side.

The project consists of the topics

1. Power measurement unit

2. 89C52 microcontroller

3. ADC 0809

4. Serial communication with the PC

 Power measurement unit consists of the power measurement by using the

instrument transformers and their features.

 Serial communication with the PC includes the hardware and software

description of how the communication is done using the serial port of a PC

2
2. BLOCK DIAGRAM

The block diagram consists of Load, current transformer, voltage transformer, 89C52

microcontroller, ADC 0809, and a differential relay. The household load to be supplied is

connected in series to the AC supply mains through a switch which is operated by the action

of a relay. Current transformer is used to measure the current required for the user and the

voltage transformer is used to measure the voltage of operation for the user. The measured

values are given to the ADC to convert the analog values to the digital values. These values

are stored in microcontroller registers and the information is transmitted to the pc when ever

there is a request for the data from the remote controlling station. Oscillator is provided for

the ADC and microcontroller for the clock signal and the reference voltage is given for the

each of the IC used.

3
 This supplier side is the basic for the operation of the project; the entire consumer

side is controlled in accordance with the program written on this supplier side. The supplier

side (substation) is located remotely at some distance away from the user and the signal is

sent to the consumer side for data or to control the supply of power to the user. The request

for information and the power data is received from the user side via RS232.

Microcontroller is interfaced to the personal computer serial port through MAX23C to

drive between RS232 and TTL levels.

3. POWER MEASUREMENT

4
 The main aim of the Remote power monitoring is to measure the exact amount of

power that is consumed by the user at a given instant of time so the power measurement

unit is essential and is connected on the consumer side. The power is measured by using the

instrument transformers. Instrument transformers are used for measurement and protective

application, together with equipment such as meters and relays. Their role in electrical

systems is of primary importance as they are a means of "stepping down" the current or

voltage of a system to measurable values, such as 5A or 1A in the case of a current

transformers or 110V or 100V in the case of a voltage transformer. This offers the

advantage that measurement and protective equipment can be standardized on a few values

of current and voltage. The types of instrument transformers available are

 Voltage transformers

 Current transformers

3.1VOLTAGE TRANSFORMERS

3.1.1PRINCIPLE OF OPERATION:

The voltage transformer is one in which "the secondary voltage is substantially

proportional to the primary voltage and differs in phase from it by an angle which is

approximately zero for an appropriate direction of the connections." In an "ideal"

transformer, the secondary voltage vector is exactly opposite and equal to the primary

voltage vector, when multiplied by the turns ratio. In a "practical" transformer, errors are

5
introduced because some current is drawn for the magnetization of the core and because of

drops in the primary and secondary windings due to leakage reactance and winding

resistance. One can thus talk of a voltage error, which is the amount by which the voltage is

less than the applied primary voltage, and the phase error, which is the phase angle by

which the reversed secondary voltage vector is displaced from the primary voltage vector.

3.1.2 TYPICAL TERMS USED FOR SPECIFYING A PT

a. RATED PRIMARY VOLTAGE: This is the rated voltage of the system whose

voltage is required to be stepped down for measurement and protective purposes.

b. RATED SECONDARY VOLTAGE: This is the voltage at which the meters and

protective devices connected to the secondary circuit of the voltage transformer

operate.

c. RATED BURDEN: This is the load in terms of volt-amperes (VA) posed by the

devices in the secondary circuit on the VT. This includes the burden imposed by the

connecting leads. The VT is required to be accurate at both the rated burden and

25% of the rated burden.

d. RATED VOLTAGE FACTOR: Depending on the system in which the VT is to

be used, the rated voltage factors to be specified are different. The table below is

adopted from Indian and International standards.

6
 Rated voltage Rated time
Method of connecting primary winding in system
factor

1.2 Continuous Between phases in any network Between transformer

star-point and earth in any network

1.2-1.5 Continuous Between phase and earth in an effectively earthed

for 30 secondsneutral system

1.2-1.9 Continuous Between phase and earth in a non-effectively earthed

for 30 secondsneutral system with automatic fault tripping

1.2-1.9 Continuous Between phase and earth in an isolated neutral system

for 8 hours without automatic fault tripping or in a resonant earthed

system without automatic fault tripping

e. TEMPERATURE CLASS OF INSULATION: The permissible temperature rise

over the specified ambient temperature. Typically, classes E, B and F.

f. RESIDUAL VOLTAGE TRANSFORMER (RVT): RVTs are used for residual

earth fault protection and for discharging capacitor banks. The secondary residual

voltage winding is connected in open delta. Under normal conditions of operation,

there is no voltage output across the residual voltage winding. When there is an

earth fault, a voltage is developed across the open delta winding which activates the

relay. When using a three phase RVT, the primary neutral should be earthed, as

7
 otherwise third harmonic voltages will appear across the residual winding. 3 phase

RVTs typically have 5 limb construction.

3.2 CURRENT TRANSFORMERS

3.2.1 PRINCIPLE OF OPERATION:

A current transformer is defined as "as an instrument transformer in which the

secondary current is substantially proportional to the primary current (under normal

conditions of operation) and differs in phase from it by an angle which is approximately

zero for an appropriate direction of the connections." This highlights the accuracy

requirement of the current transformer but also important is the isolating function, which

means no matter what the system voltage the secondary circuit need be insulated only for a

low voltage.

The current transformer works on the principle of variable flux. In the "ideal"

current transformer, secondary current would be exactly equal (when multiplied by the

turns ratio) and opposite to the primary current. But, as in the voltage transformer, some of

the primary current or the primary ampere-turns is utilized for magnetizing the core, thus

leaving less than the actual primary ampere turns to be "transformed" into the secondary

ampere-turns. This naturally introduces an error in the transformation. The error is

classified into two-the current or ratio error and the phase error.

8
4. ADC 0809

The ADC0809, data acquisition component is a monolithic CMOS device with an 8-

bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control

logic. The 8-bit A/D converter uses successive approximation as the conversion technique.

The converter features a high impedance chopper stabilized comparator, a 256R voltage

divider with analog switch tree and a successive approximation register. The 8-channel

multiplexer can directly access any of 8-single-ended analog signals. The device eliminates

the need for external zero and full-scale adjustments. Easy interfacing to microprocessors is

provided by the latched and decoded multiplexer address inputs and latched TTL TRI-

STATE® outputs.

The design of the ADC0809 has been optimized by incorporating the most desirable

aspects of several A/D conversion techniques. The ADC0809 offers high speed, high

accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability,

and consumes minimal power. These features make this device ideally suited to applications

from process and machine control to consumer and automotive applications

9
4.1 PIN CONFIGURATION

4.2 FEATURES

 Easy interface to all microprocessors

 Operates ratio metrically or with 5 VDC or analog span adjusted voltage

reference

 No zero or full-scale adjust required

 8-channel multiplexer with address logic

 0V to 5V input range with single 5V power supply

 Outputs meet TTL voltage level specifications

 Standard hermetic or molded 28-pin DIP package

 28-pin molded chip carrier package

10
4.3 KEY SPECIFICATIONS

 Resolution 8 Bits

 Total Unadjusted Error ±1⁄2 LSB and ±1 LSB

 Single Supply 5V DC

 Low Power 15 mW

 Conversion Time 100 μs

4.4 BLOCK DIAGRAM

11
4.5 FUNCTIONAL DESCRIPTION

4.5.1 MULTIPLEXER

The device contains an 8-channel single-ended analog signal multiplexer. A

particular input channel is selected by using the address decoder. Table shows the input

states for the address lines to select any channel. The address is latched into the decoder on

the low-to-high transition of the address latch enable signal.

4.5.2 CONVERTER CHARACTERISTICS

THE CONVERTER

The heart of this single chip data acquisition system is its 8-bit analog-to-digital

converter. The converter is designed to give fast, accurate, and repeatable conversions over a

wide range of temperatures. The converter is partitioned into 3 major sections: the 256R

ladder network, the successive approximation register, and the comparator. The converter’s

12
digital outputs are positive true. The 256R ladder network approach was chosen over the

conventional R/2R ladder because of its inherent monotonicity, which guarantees no missing

digital codes. Monotonicity is particularly important in closed loop feedback control

systems. A non-monotonic relationship can cause oscillations that will be catastrophic for the

system. Additionally, the 256R network does not cause load variations on the reference

voltage.

The bottom resistor and the top resistor of the ladder network in are not the same

value as the remainder of the network. The difference in these resistors causes the output

characteristic to be symmetrical with the zero and full-scale points of the transfer curve. The

first output transition occurs when the analog signal has reached +1⁄2 LSB and succeeding

output transitions occur every 1 LSB later up to full-scale.

The successive approximation register (SAR) performs 8 iterations to approximate

the input voltage. For any SAR type converter, n-iterations are required for an n-bit

converter. In the ADC0809, the approximation technique is extended to 8 bits using the

256R network. The A/D converter’s successive approximation register (SAR) is reset on the

positive edge of the start conversion start pulse. The conversion is begun on the falling edge

of the start conversion pulse. A conversion in process will be interrupted by receipt of a new

start conversion pulse. Continuous conversion may be accomplished by tying the end of

conversion (EOC) output to the SC input. If used in this mode, an external start conversion

pulse should be applied after power up. End-of-conversion will go low between 0 and 8

clock pulses after the rising edge of start conversion.

13
5. 89C52 MICROCONTROLLER

5.1 INTRODUCTION

Micro controller is a true computer on a chip. Microprocessors are intended to be

general-purpose digital computers whereas micro controllers are intended to be special

purpose digital controllers. Generally microprocessors contain a CPU, memory- addressing

units and interrupt handling circuits. Micro controllers have these features as well as timers,

parallel and serial I/O and internal RAM and ROM. Like the microprocessor, a micro

controller is a general-purpose device, but one that is meant to read data, and control its

environmental based on those calculations.

The contrast between a micro controller and a microprocessor is best exemplified by

the fact that microprocessors have many operational codes for moving data from external

memory to CPU; microcontrollers may have one or two. Microprocessors may have one or

two types of bit-handling instructions; micro controllers will have many. The microprocessor

is concerned with the rapid movement of code and data from external addresses to the chip;

the microcontroller is concerned with rapid movements of bits with in the chip. The micro

controller can function as a computer with the addition of no external digital parts; the

microprocessor must have many additional parts to be operational.

Generally 4-bit microcontrollers are intended for use in large volumes as true 1-chip

computers. Typical applications consist of appliances and toys. Eight bit micro controllers

represent a transition zone between the dedicated, high volume, 4-bit micro controllers and
14
the high performance, 16 and 32-bit units. Eight bit micro controllers are very useful word

size for small computing tasks. 16-bit controllers have also been designed to take the

advantage of high level programming languages in the expectation that very little assembly

language programming will be done when employing these controllers in sophisticated

applications. 32 bit controllers are also used in high speed control and signal processing

applications.

5.2 DESCRIPTION

The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with

8K bytes of Flash programmable and erasable read only memory (PEROM). The device is

manufactured using Atmel’s high-density nonvolatile memory technology and is compatible

with the industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the

program memory to be reprogrammed in-system or by a conventional nonvolatile memory

programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel

AT89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective

solution to many embedded control applications.

5.3 FEATURES

1. Compatible with MCS-51™ Products

2. 8K Bytes of In-System Reprogrammable Flash Memory

(Endurance: 1,000 Write/Erase Cycles)

3. Fully Static Operation: 0 Hz to 24 MHz

15
4. Three-level Program Memory Lock

5. 256 x 8-bit Internal RAM

6. 32 Programmable I/O Lines

7. Two 16-bit Timer/Counters

8. Six Interrupt Sources

9. Programmable Serial Channel

10. Low-power Idle and Power-down Modes

5.4 PIN DIAGRAM:

(T2) P1.0 1 40 VCC

2 39
(T2 EX) P1.1 P0.0(AD0)
3 38
P1.2 P0.1(AD1)
4 37
P1.3
5 ATMEL P0.2(AD2)
P1.4 36 P0.3(AD3)
6
P1.5 35 P0.4(AD4)
7
P1.6
8 8 34 P0.5(AD5)

P1.7 33 P0.6(AD6)
9
RST
(RXD) P3.0
10 9 32
31
P0.7(AD7)
EA/VPP
11
(TXD) P3.1 30 ALE/PROG
(INT0) P3.2
12
13
C 29
PSEN
(INT1) P3.3 28 P2.7(A15)
14
(T0) P3.4 15 5 27 P2.6(A14)
(T1) P3.5 15 26 P2.5(A13)
(W R) P3.6 16 2 25 P2.4(A12)
(RD) P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

16
5.5 PIN CONFIGURATIONS

The AT89C52 provides the following standard features: 4K bytes of Flash, 128 bytes

of RAM, 32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt architecture,

a full duplex serial port, and on chip oscillator and clock circuitry. IN addition, the AT89C52

is designed with static logic for operation down to zero frequency and supports two software

selectable power selecting modes. The idle Mode stops the CPU while allowing the RAM,

timer/counters, serial port and interrupt system to continue functioning. The Power down

Mode saves the RAM contents but freezes the oscillator all other chip functions until the

next hardware reset.

5.6 PIN DESCRIPTION

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can

sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high

impedance inputs. Port 0 may also be configured to be the multiplexed low order
17
address/data bus during accesses to external program and data memory. In this mode P0 has

internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs

the code bytes during program verification. External pull ups are required during program

verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output

buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled

high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are

externally being pulled low will source current (IIL) because of the internal pull ups. Port 1

also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the

internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being

pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-

order address byte during fetches from external program memory and during accesses to

external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application, it

uses strong internal pull-ups when emitting 1s. During accesses to external data memory that

uses 8-bit addresses (MOVX @ RI); Port 2 emits the contents of the P2 Special Function

18
Register. Port 2 also receives the high-order address bits and some control signals during

Flash programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output

buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled

high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are

externally being pulled low will source current (IIL) because of the pull ups. Port 3 also

serves the functions of various special features of the AT89C51 as listed below:

Port 3 also receives some control signals for Flash programming and verification.

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running

resets the device.

19
ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during

accesses to external memory. This pin is also the program pulse input (PROG) during Flash

programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator

frequency, and may be used for external timing or clocking purposes. Note, however, that

one ALE pulse is skipped during each access to external Data Memory. If desired, ALE

operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is

active only during a MOVX or MOVC instruction.

PSEN

Program Store Enable is the read strobe to external program memory. When the

AT89C51 is executing code from external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access to external

data memory.

EA/VPP

External Access Enable:

EA must be strapped to GND in order to enable the device to fetch code from

external program memory locations starting at 0000H up to FFFFH. Note, however, that if

lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to

20
VCC for internal program executions. This pin also receives the 12-volt programming enable

voltage (VPP) during Flash programming, for parts that require 12-volt VPP.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating

circuit.

XTAL2

Output from the inverting oscillator amplifier.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier

which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a

quartz crystal or ceramic resonator may be used. To drive the device from an external clock

source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure.

There are no requirements on the duty cycle of the external clock signal, since the input to

the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and

maximum voltage high and low time specifications must be observed.

21
IDLE MODE

In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain

active. The mode is invoked by software. The content of the on-chip RAM and all the special

functions registers remain unchanged during this mode. The idle mode can be terminated by

any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated

by a hardware reset, the device normally resumes program execution, from where it left off,

up to two machine cycles before the internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To

eliminate the possibility of an unexpected write to a port pin when Idle is terminated by

reset, the instruction following the one that invokes Idle should not be one that writes to a

port pin or to external memory.

22
POWER DOWN MODE:

In the power-down mode, the oscillator is stopped, and the instruction that invokes

power-down is the last instruction executed. The on-chip RAM and Special Function

Registers retain their values until the power-down mode is terminated. The only exit from

power-down is hardware reset. Reset redefines the SFRs but does not change the on-chip

RAM. The reset should not be activated before VCC is restored to its normal operating level

and must be held active long enough to allow the oscillator to restart and stabilize.

PROGRAM MEMORY LOCK BITS:

On the chip are three lock bits which can be left un programmed (U) or can be

programmed (P) to obtain the additional features listed in the table below. When lock bit 1 is

programmed, the logic level at the EA pin is sampled and latched during reset. If the device

is powered up without a reset, the latch initializes to a random value, and holds that value

until reset is activated. It is necessary that the latched value of EA be in agreement with the

current logic level at that pin in order for the device to function properly.

5.7 MEMORY

The 8051 has three very general types of memory. To effectively program the 8051 it

is necessary to have a basic understanding of these memory types.

The memory types are illustrated in the following graphic. They are:

23
 1. on-chip memory

2. External Code Memory

3. External RAM

4. Special function register memory

5.7.1 ON-CHIP MEMORY

This refers to any memories (Code, RAM or other) that physically exist on the

microcontroller itself. On- Chip memory can be of several types.

The 8051 has a bank of 128 bytes if Internal RAM. This internal RAM available and

it is also the most flexible in terms of reading, writing, and modifying its contents. Internal

RAM is volatile, so when the 8051 is rest this memory is cleared.

The first 8 bytes (00h-07h) are “register bank 0”. By manipulating certain SFRs, a

program may choose to use register banks 1, 2 or 3. These alternative register banks are

located in internal RAM in addresses 08h through 1Fh. Bit memory also lives and is part of

internal RAM. The 80bytes remaining of Internal RAM, from addresses 30h through 7Fh,

may be used by user variables that need to be accessed frequently or at a high speed. This

area is also utilized by the microcontroller as a storage area for the operating stack. This fact

severely limits the 8051’s stack since, as illustrated in the memory map, the area reserved for

the stack is only 80 bytes and usually it is less since this 80 bytes has to be shared between

stack and user.

24
5.7.2 EXTERNAL CODE MEMORY

This is code (or program) memory that resides off-chip. This is often in the form of

an external (EPROM). Code Memory is the memory that holds the actual 8051 program that

is to be run. This memory is limited to 64K and comes in many shapes ands sizes. Code

Memory may be found on-chip, either burned in to the microcontroller as ROM or EPROM.

Code may also be stored completely off-chip in an external ROM or, more commonly, an

external EPROM. Flash RAM is also another popular method of storing program. Various

combinations of these memory types may also be used-that is to say, it is possible to have 4K

of code memory on-chip and 64K of code memory off-chip in an EPROM.

When the program is stored in-chip the 64K maximum is often reduced to 4K, 8K or

16K. This varies depending on the version of the chip that is being used. Each version offers

how much ROM/EPROM spacer the chip has.

However, code memory is most commonly implemented as off-chip EPROM. This is

especially true in low-cost development systems.

5.7.3 EXTERNAL RAM

This RAM memory resides off-chip. This is often in the form of standard static RAM

or flash RAM.

25
As an obvious of Internal RAM, the 8051 also supports what is called External RAM.

As the name suggests, External RAM is any random access memory which is found

off-chip. Since the memory is off-chip it is not as flexible in terms of accessing, and is also

slower. For example, to increment an Internal RAM location by 1 requires only 1 instruction

and 1 instruction cycle. To increment a 1-byte value stored in External RAM requires 4

instructions and 7 instruction cycles. In this case, external memory is 7 times slower.

What external RAM loses in speed and flexibility it gains in quantity. While internal

RAM is limited to 128 bytes (256 bytes with an 8052), the 8051 supports External RAM up

to 64K.

5.7.4 SPECIAL FUNCTION REGISTER (SFR) MEMORY

Special Function Register (SFRs) are areas of memory that control specific

functionality of the 8051 processor. For example, four SFRs permit access to the 8051’s 32

input/output lines. Another SFR allows a program to read or write to the 8051’s serial port.

Other SFRs allow the user to set the serial baud rate, control and access timers, and configure

the 8051’s interrupt system.

26
5.8 ADDRESSING MODES

An “addressing mode” refers to how you are addressing given memory location. In

summary, the addressing modes are as follows, with an example of each:

Immediate Addressing MOV A,#20H

Direct Addressing MOVA,30H

In Direct Addressing MOV A,@R0

External Direct MOVX A,@DPTR

Code Indirect MOVC @A+DPTR

Each of these addressing modes provides important flexibility.

5.8.1 IMMEDIATE ADDRESSING

Immediate Addressing is so-named because the value to be stored in memory

immediately follows the operation code in memory. That is to say, the instruction itself

dictates what value will be stored in memory. For example, the instruction:

MOV A, #20H

This instruction uses Immediate Addressing because the Accumulator will be loaded

with the value that immediately follows; in this case 20 (hexadecimal). Immediate

addressing is very fast since the value to be loaded is included in the instruction. However,

since the value to be loaded is fixed at compile-time it is not very flexible.

27
5.8.2 DIRECT ADDRESSING

Indirect Addressing is a very powerful addressing which in many cases provides an

exceptional level of flexibility. Indirect Addressing is also only way to access the extra 128

bytes of Internal RAM found on an 8052. Indirect Addressing appears as follows:

MOV A,@R0

5.8.3 EXTERNAL INDIRECT

External memory can also be accessed using a form of indirect addressing which I

call External Indirect Addressing. This form of addressing is usually only used in relatively

small projects that have a very small amount of external RAM. An example of this

addressing mode is

Eg: MOVX @R0, A.

5.9 PROGRAMMING THE FLASH MEMORY

The AT89C52 is normally shipped with the on chip flash memory array in the

erased state (that is, contents FFH) and ready to be programmed. The programming interface

accepts either a high voltage (12-volt) or a low voltage (VCC) program enable signal. The low

voltage programming mode provides enable signal. The low voltage programming mode

provides convenient way to program the AT89C52 inside the user’s system, while the high-

voltage programming mode is compatible with Flash or EPROM programmers. The

28
AT89C52 is shipped with either the high voltage or low voltage programming mode enabled.

The AT89C52 code memory array is programmed byte by byte in either programming mode.

The program any non blank byte in the chip Flash Memory, the entire memory must be

erased using the Chip Erase Mode.

5.10 PROGRAMMING ALGORITHM:

Before programming the AT89C52, the address, the data and control signals should

be set up according to the flash programming mode table. To program the AT89C52, take

the following steps:

1. Input the desired memory location on the address line

2. Input the appropriate data b byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V for the high voltage programming mode.

5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The

byte write cycle is self timed and typically takes no more than 1.5ms. repeat steps 1

through 5, changing the address and data for the entire array or until the end of the

object file is reached.

DATA POLLING:

The AT89C52 features Data Polling to indicate the end of a write cycle. During a

write cycle, an attempted read of the last byte written will result in the complement of the

29
written datum on P0.7. Once the write cycle has been completed, true data are valid on all

outputs, and the next cycle may begin. Data polling may begin any time after a write cycle

had been initiated.

Ready/Busy:

The progress of byte programming can also be monitored by the RDY/BSY output

signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY.P3.4.

is pulled high again when programming is done to indicate READY.

Program Verify:

If the lock bits LB1 and LB2 have not been programmed, the programmed code data

can be read via the address and data lines for verification. The lock bits cannot be verified

directly. Verification of the lock bits is achieved by observing that their features are enabled.

Chip Erase:

The entire Flash array is erased electrically by using the proper combination of

control signals and by holding ALE/PROG low for 10ms. The code array is written with

all”1’s”. The chip erase operation must be executed before the code memory can be re-

programmed.

30
READING THE SIGNATURE BYTES:

The signature bytes are read by the same procedure as a normal verification of locations

030H, 031H and 032H except that P3.6 and P3.7 must be pulled to a logic low. The values

returned are as follows.

(030H)=1EH indicates manufactured by Atmel

(031H)=51H indicates 89C51

(032H)=FFH indicates 12V programming

(032H)=05H indicated 5V programming

PROGRAMMING INTERFACE:

Every code byte in the Flash array can be written and the entire array can be erased

by using the appropriate combination of control signals. The write operation cycle is self

timed and once initiated, will automatically time itself to completion

31
6. SERIAL COMMUNICATION

Serial communication is a popular means of transmitting data between a computer

and a peripheral device such as a programmable instrument or even another computer. Serial

communication uses a transmitter to send data, one bit at a time, over a single

communication line to a receiver. You can use this method when data transfer rates are low

or you must transfer data over long distances. Serial communication is popular because most

computers have one or more serial ports, so no extra hardware is needed other than a cable to

connect the instrument to the computer or two computers together

Serial communication requires that you specify the following four parameters:

 The baud rate of the transmission

 The number of data bits encoding a character

 The sense of the optional parity bit

 The number of stop bits

Each transmitted character is packaged in a character frame that consists of a single

start bit followed by the data bits, the optional parity bit, and the stop bit or bits. Figure

shows a typical character frame.

32
 Baud rate is a measure of how fast data are moving between instruments that use

serial communication. RS-232 uses only two voltage states, called MARK and SPACE. In

such a two-state coding scheme, the baud rate is identical to the maximum number of bits of

information, including control bits, that are transmitted per second. MARK is a negative

voltage, and SPACE is positive. Figure 2 shows how the idealized signal looks on an

oscilloscope. The truth table for RS-232: Signal>3V=0 Signal>-3V=1. The output signal

level usually swings between +12 V and -12 V. The dead area between +3 V and -3 V is

designed to absorb line noise.

A start bit signals the beginning of each character frame. It is a transition from

negative (MARK) to positive (SPACE) voltage. Its duration in seconds is the reciprocal of

the baud rate. If the instrument is transmitting at 9,600 baud, the duration of the start bit and

each subsequent bit is about 0.104 ms.

Data bits are transmitted upside down and backwards. That is, inverted logic is used,

and the order of transmission is from least significant bit (LSB) to most significant bit

33
(MSB). To interpret the data bits in a character frame, you must read from right to left and

read 1 for negative voltage and 0 for positive voltage. An optional parity bit follows the data

bits in the character frame. The parity bit, if present, also follows inverted logic, 1 for

negative voltage and 0 for positive voltage. This bit is included as a simple means of error

handling. You specify ahead of time whether the parity of the transmission is to be even or

odd. If the parity is chosen to be odd, the transmitter then sets the parity bit in such a way as

to make an odd number of ones among the data bits and the parity bit. This transmission uses

odd parity. There are five ones among the data bits, already an odd number, so the parity bit

is set to 0.

6.1 SPEED OF TRANSMISSION:

Knowing the structure of a character frame and the meaning of baud rate as it applies

to serial communication, you can calculate the maximum transmission rate, in characters per

second, for a given communication setting. This rate is just the baud rate divided by the bits

per frame. This is the maximum character transmission rate. The hardware on one end or the

other of the serial link might not be able to reach these rates, for various reasons. There are

many different recommended standards of serial port communication, the most common

types is as following

6.2 RS-232

The RS-232 is a standard developed by the Electronic Industries Association (EIA)

and other interested parties, specifying the serial interface between Data Terminal Equipment
34
(DTE) and Data Communications Equipment (DCE). It is commonly used in computer serial

ports. The RS-232 standard includes electrical signal characteristics (voltage levels),

interface mechanical characteristics (connectors), functional description of interchange

circuits (the function of each electrical signal), and some recipes for common kinds of

terminal-to-modem connections. RS-232C is a long-established standard ("C" is the current

version) that describes the physical interface and protocol for relatively low-speed serial data

communication between computers and related devices. Parts of this standard have been

adopted (with various degrees of fidelity) for use in serial communications between

computers and printers, modems, and other equipment. The serial ports on standard IBM-

compatible personal computers follow RS-232. Somewhere in your PC, typically on a

Universal Asynchronous Receiver/Transmitter (UART) chip on your motherboard, the data

from your computer is transmitted to a serial device from its Data Terminal Equipment

(DTE) interface. Since data in your computer flows along parallel circuits and serial devices

can handle only one bit at a time, the UART chip converts the groups of bits in parallel to a

serial stream of bits. As your PC's DTE agent, it also communicates with the serial device,

which, in accordance with the RS-232C standard, has a complementary interface called the

Data Communications Equipment (DCE) interface.

6.3 RS-232 CABLING

Devices that use serial cables for their communication are split into two categories.

These are DCE and DTE. DCE are devices such as a modem, TA adapter, plotter, and so on,

while DTE is a computer or terminal. RS-232 serial ports come in two sizes, the D-Type 25-
35
pin connector and the D-Type 9-pin connector. Both of these connectors are male on the

back of the PC. Thus, you require a female connector on the device. Table 1 shows the pin

connections for the 9-pin Type connectors.

Function Signal PIN DTE DCE

TxD 3 Output Input

Data
RxD 2 Input Output

RTS 7 Output Input

CTS 8 Input Output

Handshake DSR 6 Input Output

DCD 1 Input Output

STR 4 Output Input

Common Com 5 -- --

Other RI 9 Output Input

36
1. The TD (transmit data) wire is the one through which data from a DTE device is

transmitted to a DCE device. This name can be deceiving, because this wire is used

by a DCE device to receive its data. The TD line is kept in a mark condition by the

DTE device when it is idle. The RD (receive data) wire is the one on which data is

received by a DTE device, and the DCE device keeps this line in a mark condition

when idle.

2. RTS stands for Request To Send. This line and the CTS line are used when

"hardware flow control" is enabled in both the DTE and DCE devices. The DTE

device puts this line in a mark condition to tell the remote device that it is ready and

able to receive data. If the DTE device is not able to receive data (typically because

its receive buffer is almost full), it will put this line in the space condition as a

signal to the DCE to stop sending data. When the DTE device is ready to receive

more data (i.e. after data has been removed from its receive buffer), it will place this

line back in the mark condition. The complement of the RTS wire is CTS, which

stands for Clear To Send. The DCE device puts this line in a mark condition to tell

the DTE device that it is ready to receive the data. Likewise, if the DCE device is

unable to receive data, it will place this line in the space condition. Together, these

two lines make up what is called RTS/CTS or "hardware" flow control. DTR

stands for Data Terminal Ready. Its intended function is very similar to the RTS

line. DSR (Data Set Ready) is the companion to DTR in the same way that CTS is

to RTS. Some serial devices use DTR and DSR as signals to simply confirm that a

device is connected and is turned on. The Software Wedge sets DTR to the mark
37
 state when the serial port is opened and leaves it in that state until the port is closed.

The DTR and DSR lines were originally designed to provide an alternate method of

hardware handshaking. It would be pointless to use both RTS/CTS and DTR/DSR

for flow control signals at the same time. Because of this, DTR and DSR are rarely

used for flow control.

3. CD stands for Carrier Detect. Carrier Detect is used by a modem to signal that it

has a made a connection with another modem, or has detected a carrier tone.

4. The last remaining line is RI or Ring Indicator. A modem toggles the state of this

line when an incoming call rings your phone.

The Carrier Detect (CD) and the Ring Indicator (RI) lines are only available in connections

to a modem. Because most modems transmit status information to a PC when either a

carrier signal is detected (i.e. when a connection is made to another modem) or when the

line is ringing, these two lines are rarely used.

6.4 MAX 232C

MAX 232C is used to interface the transmitter and receiver circuit to the PC. It is

used to match between the RS232C and TTL levels. The MAX232 is a dual driver/receiver

that includes a capacitive voltage generator to supply RS232C voltage levels from a single

5V supply. Each receiver converts RS232C inputs to 5V TTL/CMOS levels. These receivers

have a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30V inputs.

Each driver converts TTL/CMOS input levels into RS232C levels.

38
6.4.1 LOGIC DIAGRAM:

6.4.2 OPERATING CIRCUIT:

39
6.4.3 FEATURES:

 Meets or Exceeds RS232C

 Operates From a Single 5-V Power Supply with 1.0 microF Charge-

Pump Capacitors

 Operates Up To 120 kbit/s

 Two Drivers and Two Receivers

 ±30-V Input Levels

 Low Supply Current of 8 mA Typical

6.4.4 APPLICATIONS

 RS232C

 Battery-Powered Systems

 Terminals

 Modems

 Computers

6.4.5 RS-232 DRIVERS

The typical driver output voltage swing is ±8V when loaded with a nominal 5kΩ RS-

232 receiver and VCC = +5V. Output swing is guaranteed to meet the RS-232C

specification, which calls for ±5V minimum driver output levels under worst-case

40
conditions. These include a minimum 3kΩ load, VCC = +4.5V, and maximum operating

temperature. Unloaded driver output voltage ranges from (V+ -1.3V) to (V- +0.5V). Input

thresholds are both TTL and CMOS compatible. The MAX232 has both a receiver three-

state control line and a low-power shutdown control.

6.4.6 RS-232 RECEIVERS:

RS-232C specifications define a voltage level greater than 3V as logic 0, so all

receivers invert. Input thresholds are set at 0.8V and 2.4V, so receivers respond to TTL level

inputs as well as RS-232C levels. The receiver inputs withstand an input overvoltage up to

±25V and provide input terminating resistors with nominal 5kΩ values. The receiver input

hysteresis is typically 0.5V with a guaranteed minimum of 0.2V.

41
7. CIRCUIT DIAGRAM

The above figure shows the circuit diagram for the consumer side. A relay operated

switch is connected in series with the load. The switch is used to switch on and off the

power. By the relay is initially in on state and whenever the voltage across its terminals

changes the relay senses the voltage and trips which in turns closes the switch. The relay is

connected to the port of the microcontroller through a transistor and zener diode to drive the

relay. The current transformer primary is connected to the load in series to the mains and the
42
secondary is connected across the variable resistance to change the measured value to the

close actual value. The potential transformer primary is connected in parallel to the load to

measure the applied voltage and the secondary is connected to the variable resistance to

adjust the measured value to the close accurate value. The outputs of this are given to the

ADC analog input pins. A 555 timer is connected in astable multivibrator mode and is given

as clock signal to the ADC. The digital outputs are given as inputs to the microcontroller

port. The control pins of the ADC are given from the microcontroller port to select the input

to be received. The voltage and current measured are received in accordance to the inputs

given to the status pins A, B, C by the controller. The ADC starts the conversion at the end

of the pulse Start and sends data at the end of the pulse EOC these are also connected to the

port of the microcontroller. The microcontroller is provided with a quartz crystal to provide

the clock signal, the clock frequency is changed by the capacitors connected to the crystal the

operating frequency in this circuit is 11.0592MHz. A series combination of the resistor and

capacitor is taken and the capacitor voltage is given as the reset logic to the 9th pin of the

microcontroller. The 10th pin of the microcontroller is the RXD pin is connected to the

receiver data pin of RS232. The data from the RXD is stored internally for further

processing. The 11th pin of the microcontroller is the TXD pin is connected to the RS232

which transmits the data from the microcontroller. The microcontroller baud rate is set in

accordance to the frequency of the 555 timer to ensure consistency of data. Thus data is

transmitted from the microcontroller at a preset frequency and the request for data is received

by the microcontroller connected to the port and the further processing is done as per the

code written to calculate the power by taking the correction factors in to consideration.
43
 The computer is programmed so as to send requests for data and receive data via the

serial port. The work at TTL voltage levels and the computer works at RS232C voltage

levels. So to bridge this voltage variation MAX 232C is used which is driver cum receiver.

The driver is connected to the IR transmitter and the receiver is connected to the IR receiver.

The data from data pin of IR receiver is given to the computer and displayed on the screen.

IR transmitter is connected to the computer and the program is written to send the data via

the serial port to the IR transmitter to send data at a given baud rate. The oscillator is

connected to the transmitter to match the transmission with the baud rate. The oscillator used

is 555 timer using astable multivibrator.

44
8. HARDWARE PHOTOGRAPHY

45
9. RESULT

The consumer side is connected to the supply and power is given to the user from the

ac supply mains and the software run on the system is run. Then a menu is displayed on the

screen to select the operation to be done. We can select the buttons to switch on and off the

power and to know the power consumed and the program written in the pc for maximum

detecting the power thefts. Here the obtained power is compared with the maximum power

and if it is more than the maximum power then we can say that the power is being theft.

Thus the monitoring is done using the PC.

46
10. CONCLUSIONS AND SCOPE OF FUTURE WORK

The ability to remotely monitor and/or control power at the rack level can provide a

huge return on investment by providing savings in both man hours and downtime. Remote

monitoring capabilities eliminate the need for manual power audits as well as provide

immediate alerts to potential problems. Remote control allows for quick response and

recovery of stalled hardware either down the hall or across the country. This ability can save

not only travel costs but minimize costly downtime.

The project uses a serial communication technique which has got disadvantages like

loss of data and speed of communication is also less so the more advantageous parallel

communication technique can be used. The wireless technology used is IR communication

which can be used only for short distances ranging up to some meters. So, available

techniques like Bluetooth technology and the GSM technology can be used. The IR

communication fails whenever there is a disturbance or an obstacle in the path from the

transmitter to the receiver so an obstacle detector can be used to avoid this. Also an internet

connection can be enabled to the system so as to provide backup central location or software

extension can be written to provide a data backup.

47
11. MICROCONTROLLER PROGRAM:

;This is remote power monitoring.

;P2.0 = RLY0

;P2.1 = buzzer

;P2.2 = RLY2

;P2.3 = POWER OFF JUMPER

;P2.4 = recharge jumper

;P1 = ADC DATA

;P3.5=B

;P3.4=A

;P3.3=START

;P3.2=ALE

;P0 = DISP DATA

;P2.7 = RS

;P2.6 = R/W
48
 ;P2.5 = EN

; 50H = DISP LOCATION ADD

; 51H = DISP VALUE

; 60H = voltage set value

; 61H = frq set value

; 70H = voltage READ value

; 71H = frq READ value

;***********************************************

TXD MACRO ;TX R6 DATA TO PC

JNB TI,$

CLR TI

MOV SBUF, R6

MACEND

RXD MACRO ; READ FROM PC PUT IT IN R7

JNB RI, $
49
 CLR RI

MOV R7, SBUF

MACEND

ORG 0

LJMP START

ORG 0050H

START: LCALL LCDINI

LCALL DEL

MOV DPTR, #0900H

LCALL TLINE

MOV DPTR, #0910H

LCALL BLINE

LCALL SSEC

MOV DPTR, #0960H

LCALL TLINE
50
 MOV DPTR,#0930H

LCALL BLINE

SETB P2.0

CLR P2.1

LCALL SPINI

MOV R6,#00H

TXD

NEXT:

CLR RI

LCALL XRXD

CJNE R4,#01H,NEXT

CJNE R1,#01H,N2

LCALL DEL

MOV DPTR,#0920H

LCALL TLINE
51
 MOV R6,#01H

TXD

LCALL VSEN

MOV R6, 51H

TXD

MOV 50H, #8BH

LCALL VFDIS

LJMP NEXT

N2: CJNE R1, #02H, N3

LCALL DEL

CLR P2.0

SETB P2.1

LCALL SSEC

LCALL SSEC

LCALL SSEC
52
 CLR P2.1

MOV R6, #02H

TXD

LCALL DEL

MOV R6, #03H

TXD

MOV DPTR, #0940H

LCALL TLINE

LJMP NEXT

N3: CJNE R1, #04H, N4

LCALL DEL

SETB P2.0

MOV R6, #04H

TXD

LCALL DEL
53
 MOV DPTR, #0950H

LCALL TLINE

MOV R6, #05H

TXD

N4: LJMP NEXT

SEC: MOV R5, #03H

M1: MOV R6, #FFH

M2: MOV R7, #FFH

M3: DJNZ R7, M3

DJNZ R6, M2

DJNZ R5, M1

RET

SSEC: MOV R5, #06H

SM1: MOV R6, #FFH

SM2: MOV R7, #FFH

54
SM3: DJNZ R7, SM3

DJNZ R6, SM2

DJNZ R5, SM1

RET

;********* VOLTAGE SENSE ************

VSEN:

mov p1,#FFH

;mov p3,#FFH

SETB P3.2

SETB P3.3

SETB P3.4

SETB P3.5

SETB P3.6

SETB P3.7

CLR P3.2
55
 CLR P3.3

LCALL DEL

CLR P3.4

CLR P3.5

LCALL DEL

SETB P3.2

LCALL DEL

SETB P3.3

LCALL DEL

CLR P3.2

LCALL DEL

CLR P3.3

LCALL SEC

MOV R6,P1

MOV 51H,R6
56
 RET

;********* FREQ SENSE ************

*** 9600 bps, 8bit, 2 STOP Bits, NO PARITY ***

SPINI:

MOV A, #00H

MOV TCON, #40H

MOV TMOD, #20H

MOV SCON, #52H

MOV IE, #9AH

MOV TH1, #A0H

MOV TL1, #A0H

RET

;*******************************************

XRXD: MOV R4, #00H

MOV R5, #1FH

57
XAE: MOV R3, #FFH

XAD: MOV R2, #FFH

XAB: JNB RI, XAC

CLR RI

MOV R1, SBUF

MOV R4, #01H ; STATUS R4 CHK #01 OK, #02 NOT OK

RET

XAC: DJNZ R2, XAB

DJNZ R3, XAD

DJNZ R5, XAE

MOV R4, #02H

RET

;********** LCD INI ****************

LCDINI:

CLR P0.0
58
CLR P0.1

CLR P0.2

CLR P2.5

CLR p2.7

CLR p2.6

MOV P0, #30H

LCALL WRI

CLR p2.7

CLR p2.6

MOV P0, #30H

LCALL WRI

CLR p2.7

CLR p2.6

MOV P0, #30H

LCALL WRI
59
CLR p2.7

CLR p2.6

MOV P0, #38H

LCALL WRI

CLR p2.7

CLR p2.6

MOV P0, #01H

LCALL WRI

CLR p2.7

CLR p2.6

MOV P0, #01H

LCALL WRI

CLR p2.7

CLR p2.6

MOV P0, #01H

60
LCALL WRI

CLR p2.7

CLR p2.6

MOV P0, #02H

LCALL WRI

CLR p2.7

CLR p2.6

MOV P0, #0CH

LCALL WRI

CLR p2.7

CLR p2.6

MOV P0, #1CH

LCALL WRI

CLR p2.7

CLR p2.6
61
 MOV P0, #38H

LCALL WRI

CLR p2.7

CLR p2.6

MOV P0, #06H

LCALL WRI

CLR p2.7

CLR p2.6

MOV P0, #01H

LCALL WRI

RET

TLINE: CLR p2.7

CLR p2.6

MOV P0, #80H

LCALL WRI
62
 MOV R7, #00H

TKL: CLR A

MOVC A,@A+DPTR

MOV P0, A

LCALL WRD

INC DPTR

INC R7

CJNE R7, #10H, TKL

RET

BLINE: CLR p2.7

CLR p2.6

MOV P0, #C0H

LCALL WRI

MOV R7, #00H

BKL: CLR A
63
 MOVC A, @A+DPTR

MOV P0, A

LCALL WRD

INC DPTR

INC R7

CJNE R7, #10H, BKL

RET

;******** INSTRUCTION /DATA WRITE *********

WRI: SETB P2.5

MOV R0, #FFH

DJNZ R0, $

CLR P2.5

MOV R0, #FFH

DJNZ R0, $

RET
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WRD: SETB p2.7 ; REGISTER

CLR p2.6 ;READ WRITE

SETB P2.5 ;ENABLE

MOV R0, #FFH

DJNZ R0, $

CLR P2.5

CLR p2.6

CLR p2.7

RET

DEL: MOV R7, #FFH

DJNZ R7, $

RET

DEL1: MOV R7, #FFH

DJNZ R7, $

RET
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XDEL:

mov r4, #0FH

djnz r4, $

RET

XDEL1: mov r4, #0FH

djnz r4, $

RET

XDEL2: MOV R5, #5FH

GB: mov r4, #FFH

djnz r4, $

DJNZ R5, GB

RET

;*********** DISPLAY *************

VFDIS:

MOV PSW, #18H

66
 MOV R3, 51H

CLR A

MOV A, 50H

MOV P0, A

LCALL WRI

MOV DPTR, #0400H ;DATA BASE

CJNE R3, #00H, GHH

LJMP DTX

GHH: MOV R2, #03H

GHG: INC DPTR

DJNZ R2, GHG

DJNZ R3, GHH

DTX:

CLR A

MOVC A,@A+DPTR
67
MOV P0, A

LCALL WRD

INC DPTR

CLR A

MOVC A, @A+DPTR

MOV P0, A

LCALL WRD

INC DPTR

CLR A

MOVC A, @A+DPTR

MOV P0, A

LCALL WRD

INC DPTR

MOV PSW, #00H

RET
68
;##############################

ORG 0400H

;************ 0

DB #30H

DB #30H

DB #30H

;************ 1

DB #30H

DB #30H

DB #31H

;************ 2

;************ 255

DB #32H

DB #35H

DB #35H
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ORG 0900H

;************ 1 LINE

DB 'REMOTE POWER '

DB ' MONITORING '

DB 'POWER : W'

DB ' '

DB 'OVER POWER DETD.'

DB ' NORMAL LOAD OK '

DB ' WAIT FOR COMM. '

END;

70
12. BIBILOGRAPHY:

1. Microprocessor and interfacing programming and Hardware, 2nd Edition – Douglas V-

Hall, Tata Mc Graw Hill publishing company limited 1999, 290-336

2. Advanced Microprocessor and peripherals architecture program and interfacing by A. K.

Ray and Burichand, Tata Mc Graw Hill publishing company limited 2000, 601-643.

3. A Course in electrical and electronic measurements and instrumentation by A. K. Ray,

Burichand, Tata Mc Graw Hill publishing company limited 1999, 384-425.

4. www.atmel.com.

5. www.en.wikipedia.org.

6. www.cnx.org.

7. www.alldatasheet.com.

8. www.projectguidance.com

9. www.progress-energy.com

10. www.phsmou.or.jp.

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