ECE 645

Implementation of 16 Point radix 2 FFT

Ashwin Chiluka
Vamsi Krishna Teladevalapalli
A. Name of All Team Members:
Ashwin Chiluka
Vamsi Krishna Teladevalapalli

B. Title of the Project:

Implementation of 16-point radix 2 Decimation in frequency Fast Fourier Transform

C. Introduction:
The Discrete Fourier Transform (DFT) plays an important role in the analyses, design and
implementation of the discrete-time signal- processing algorithms and systems It is used to convert
the samples in time domain to frequency domain. The Fast Fourier Transform (FFT) is simply a fast
(computationally efficient) way to calculate the Discrete Fourier Transform (DFT).

The wide usage of DFT’s in Digital Signal Processing applications is the motivation to Implement
FFT’s. DFT is identical to samples of the Fourier transform at equally spaced frequencies.
Consequently, computation of the N-point DFT corresponds to the computation of N samples of the
Fourier transform at N equally spaced frequencies ωk = 2Πk/N. Considering input x[n] to be
complex, N complex multiplications and (N-1) complex additions are required to compute each
value of the DFT, if computed directly from the formula given as

OPERATION DFT FFT 16 POINT DFT 16 POINT FFT

2
Complex Multiplications N N/2(log2N-1) 256 24
Complex Additions N(N-1) N(log2N) 240 64
2
Real Multiplications 4N 2N(log2N-1) 1024 96
Real Additions N(4N-2) 2N(log2N) 992 128

To compute all N values therefore requires a total N2 complex multiplications and N(N-1) complex
additions. Each complex multiplication requires four real multiplications and two real additions and
each complex addition requires two real additions. Therefore a total of 4N2 real multiplications and
N(4N-2) real additions are required. Besides these multiplications and additions there should be
provision for storing N complex input sequences and also to store N output values. Contrary to this
by using Decimation in Frequency FFT radix-2 algorithm the number of complex multiplications
and additions will be reduced to (N/2)log2N and Nlog2N to compute the DFT of a given complex
x[n]. Hence in this project the Decimation in frequency FFT radix-2 algorithm is implemented to
compute the DFT of a sequence.
D. Implemented Arithmetic Unit:

Function: This unit implements a 16-point radix-2, decimation-in-frequency FFT. Fast Fourier
Transform has a wide area of applications in DSP. Since it is computationally intensive, a software
implementation might not meet the timing requirement in real time applications.

Formulas describing the Unit’s operation:

The DFT of a given sequence x[n] can be computed using the formula
N −1
X [k ] = ∑ x [ n ]w Nnk k=0, 1, ………………….., N-1,
n=0
⎛ 2πk ⎞
− j⎜ ⎟n
Where W N = e
n ⎝ N ⎠

The Even and the Odd samples of the DFT of x[n] are calculated using the Decimation in Frequency
radix-2 FFT Algorithm.
The Even samples of the DFT X[K] are given by the formula
N
−1
2
⎛ ⎡ N ⎤ ⎞ rn
X [2r ] = ∑ ⎜⎜ x[ n ] + x ⎢⎣ n + 2 ⎥⎦ ⎟⎟W N r=0,1,………………..,(N/2)-1.
n=0 ⎝ ⎠ 2
The Odd samples of the DFT X[K] are given by the formula
N
−1
2
⎛ ⎡ N ⎤⎞
x[2r + 1] = ∑ ⎜⎜ x[n] − x ⎢n + ⎥ ⎟⎟W NnW Nnr r=0,1,………………..,(N/2)-1.
n =0 ⎝ ⎣ 2 ⎦⎠ 2

Types and sizes of all operands:

Signals Types Sizes

Real x[n] std_logic_vector 32bits
Imag x[n] std_logic_vector 32bits
Real W std_logic_vector 16bits
Imag W std_logic_vector 16bits
Real X[K] std_logic_vector 40bits
Real X[K] std_logic_vector 40bits

Control Signals:

Signals Types Sizes

Start std_logic 1bit
Reset std_logic 1bit
Clock std_logic 1bit
The following diagram can represent the 16-point radix-2 Decimation in frequency Fast Fourier
Transform

E. Real Life application of a given arithmetic unit:

Fast Fourier Transforms are used in many of the Digital Signal Processing applications. This 16
point FFT is used in WLAN modems and mono bit receivers. FFT’s also have wide area of
applications such as Image Processing, Software Radio.

F. Optimization criteria:

The optimization criteria of this project are to increase the throughput to Area ratio. This can be
achieved by using efficient multipliers and adders.
G. Interface:

Real Part

Real Out
Imag Part
16 Point FFT

Start Imag Out

Reset

Clock

The following are the names, types, sizes and modes of the I/0 ports

Names Types Sizes Mode

Real
part std_logic_vector 32bits input
Imag
part std_logic_vector 32bits input
Start std_logic 1bit input
Reset std_logic 1bit input
Clock std_logic 1bit input
Real
out std_logic_vector 40bits output
Imag
out std_logic_vector 40bits output

This section describes the I/O interface of the 16-point FFT. The data I/O and the control pins are
illustrated in the figure. Input and Output Data are represented by fixed-point real and imaginary
components. The input data real and imaginary components are both 32-bit word lengths. The
output data real and imaginary components are both 40-bit word lengths

Precision:
Each value x(n) is represented by 32 bits , 16 bits for real part and 16 bits for imaginary part
respectively. In the 16 bits of real and imaginary parts the Most Significant 8 bits are used to
represent the integer part and the Least Significant 8 bits are used to represent the decimal part.
The Twiddle Factor Wn is represented by 16 bits of which the most significant bit represents the
sign of the number and the next bit represents the integer part while the remaining14 bits
represents the decimal part. The twiddle factor represents a sine value or a cosine value. Since the
sine or a cosine function varies from –1 to 1, the integer part of the twiddle factor is represented
by only 1 bit.

H. Software implementation used to generate test vectors:

Own implementation in C/C++ will be used to generate test vectors for verification of the
implemented arithmetic units.

I. Language, Platform and Tools

• Language: VHDL, C
• Platform: Xilinx FPGAs, ASICs based on 90nm TCBN90G TSMC library.
• Hardware Tools:
o Simulator: Aldec Active HDL v.6.2
o Synthesis Tool: Synplify Pro v.7.3.4/Xilinx XST, Synopsys
o Implementation Tool: Xilinx ISE 6.x
• Software Tool: Visual Studio 6.0

J. List of References:
1. Alan V. Oppenheim, Ronald W. Schafer with John R. Buck, Discrete Time Signal Processing,
Second Edition
2. B. Parhami, Computer Arithmetic, Algorithms and Hardware Designs, 1999
3. James W. Cooley and John W. Tukey, An Algorithm for the Machine Calculation of Complex
Fourier Series
4. Peter J. Ashenden, The Designer’s Guide to VHDL, Second Edition.
5. N. Weste, M. Bickerstaff, T. Arivoli, P.J. Ryan, J. W. Dalton, D.J. Skellern", and T.M. Percivalt A
50Mhz 16Point-FFT processor for WLAN applications