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Joan Lynch
Managing Editor, EDN
275 Washington St
Newton, MA 02458
I have enclosed an article entitled, “SPICE Simulations can Help Engineers Understand
Signal Integrity Issues in High-Speed Digital Designs.”
The article provides useful information to the majority of engineers in the field who do
not understand signal integrity in high-speed digital systems.
Best Regards,
Ken Boorom
M.S.E.E./B.S.E.E. Stanford University
SPICE Simulations Can Help Engineers
Understand Signal Integrity Issues in High-
Speed Digital Systems
There is a better way. SPICE tools allow an engineer to perform simple simulations with various
termination and bus topologies. The simulations work equally well at 10 Mhz or 10 Ghz. They don’t need
exotic high frequency fixturing. They can provide the engineer with a “seat-of-the-pants” understanding
of the behavior of a high speed digital bus. More complex (and expensive) signal integrity tools are
available for exotic and critical applications, where the training and purchase costs are justified.
One such SPICE tool is OrCad’s Pspice. The tool supports the functionality of the original SPICE, and
lets you build circuits with a Graphical User Interface, so you don’t have to memorize SPICE syntax. It
also has a built in graphing waveform function. An evaluation version is available from OrCad’s web site
at: http://www.orcad.com
The interface allows an engineer to perform "what if" scenarios, varying circuit parameters to
understand the effect on the circuit's behavior. The ability to vary a parameter can provide an important
qualitative understanding of a circuit's behavior.
A high-speed digital bus can be modeled with the tool by drawing its equivalent circuit, as shown in
Figure 1.
Figure 1
Any one of the digital interconnects on the left can be modeled as the circuit on the right. The
circuit includes the driver voltage and rise time (Vsrc), the source impedance (Rsrc), any series
impedance added by the designer to match the driver’s impedance to the transmission line
(Rseries), the transmission line, and any terminating capacitance/resistance added by the
designer to terminate the line. By varying the values of the components, different experiments can
be performed. Performing the experiments prior to board layout using a tool like SPICE can
reduce project costs and lead times.
is more realistic, because control signals in digital
@ A Glance circuits are typically active high due to the improved
noise margins.
Easy-to-use PC-based SPICE tools, like PSpice,
can provide useful insights into the behavior of
termination schemes in high-speed digital Several different termination schemes can be
interconnects. As signal rise times are reduced to compared by varying the values of Rseries, Cterm
allow for faster clock speeds, it becomes more and Rterm. If your SPICE tool does not accept 0 or
important for engineers to understand these effects. infinite as a component value, a suitably large or
small number may be substituted:
Figure 2 shows the parameters you will need to
Termination Rseries Cterm Rterm
know to model the circuit.
None 0 0 Infinite
Series 46 Ohms 0 Infinite
Figure 2 Parallel AC 0 10 pF 70 Ohms
Series + Parallel 46 Ohms 10 pF 70 Ohms
Parameter Source Value Once the values are entered, a simulation canbe
Name performed with a single mouse click. Figure 4 shows
Driver Output Manufacturer data 24 Ohms the voltage that would be seen at a device close to
Impedance or experiments the driver. Series termination is the winner here,
Driver Rise Function of driver 0.259 producing the fastest rise-time with the least
Time strength and nsec overshoot.
capacitance seen
at driver Figure 3
Input Mfg Data or Infinite
Impedance of experiments
Driven
Device
Transmission PCB Manufacturer. 24 Ohms
Line Varies with trace
Impedance width. Typical
values for 4-layer
board are 70 Ohms
for 5 mil trace, 58
Ohms for 8-mil
trace.
Transit Time Divide trace length 0.83ns
by speed of wave
in transmission
line, which This graph compares the voltages seen by a
depends on the device close to the driver for the different
board’s dielectric termination schemes. The serially terminated
coefficient. transmission line shows the fastest setting
characteristics, while the unterminated line
Once the circuit model is complete, values shows the most overshoot. Both lines using
must be provided for the components in the parallel termination require a long setting line for
model. These values reflect the physical the series capacitor to charge.
characteristics of the PC board, and the
components that are mounted on it. A fast At high speeds, the location of a device on a
rise time of 0.259 nsec was used to illustrate transmission line can influence both the timing and
the differences between the termination the shape of the transient switching waveform seen
schemes. at its inputs. Figure 4 shows the voltages that
appear at the end of the transmission line. In these
cases, note that the range of the voltages exceeds
For simplicity, the case where signal goes from
those seen in Figure 2.
LOW to HIGH is examined. The HIGH to LOW case
Figure 4
Figure 5
Figure 6
References:
Author’s Biography