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*3924A* (Page : 1) 3924 A

Reg. No. : ................................

Name : .....................................
V Semester B.Tech. Degree Examination, June 2009
Branch : Applied Electronics
Lab : DIGITAL ELECTRONICS LAB (A)
Time : 3 Hours Max. Marks : 100

1. Design a circuit to generate a sequence 0011001111001100. Repeat this sequence.


2. Design a circuit to generate a sequence 0101101001011010. Repeat this sequence.
3. Obtain the waveform on CRO.

4. Obtain the waveform on CRO.

5. Design a synchronous counter using JK FF and external gates for the following
sequence 000, 101, 110, 111, 011, 010, 000.
6. Design a sequence generator for the following sequence 7, 5, 3, 2, 1 and display it.
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Batch 1
*3924A* (Page : 1) 3924 A
Reg. No. : ................................

Name : .....................................

V Semester B.Tech. Degree Examination, June 2009


Branch : Applied Electronics
Lab : DIGITAL ELECTRONICS LAB (A)
Time : 3 Hours Max. Marks : 100

1. Set up a counter to count in the following sequence, {0, 2, 4, 6, 8, 1, 3, 5, 7, 13, 0...

2. Design and set up a 3 bit binary to gray and gray to binary code converter using
mode control switch.

3. Realize the Boolean function using 4 : 1 MUX

Y = F (a, b, c) = ∑ (0, 1, 3, 5, 7)
4. Design and set up a 3 bit comparator using gates.

5. Design and set up an astable multivibrator to generate a square frequency of 2 KHz


uisng 555 timer.

6. Design a circuit to generate a sequence 0101010110101010. Repeat this sequence.

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Batch 2
3924A* (Page : 1) 3924 A
Reg. No. : ................................

Name : .....................................

V Semester B.Tech. Degree Examination, June 2009


Branch : Applied Electronics
Lab : DIGITAL ELECTRONICS LAB (A)
Time : 3 Hours Max. Marks : 100

1. Plot sourcing and sinking currents of TTL NAND gates.

2. A three stage counter must be designed that will count in two different modes
depending on logic level of control line. If control line is high the counter must
count 0, 2, 4, 6, 0. If the control line is low the counter must count up through all
eight states.

3. Design and set up an astable multivibrator to generate a square wave of frequency


1 kHz using 74123 IC.

4. Set up a binary adder cum substractor using 2’s compliment form using IC 7483.

5. Set up all basic logic gates using 2 : 1 MUX.

6. Design and set up a decade counter using JK flip flops.

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Batch 3
3924A* (Page : 1) 3924 A
Reg. No. : ................................

Name : .....................................

V Semester B.Tech. Degree Examination, June 2009


Branch : Applied Electronics
Lab : DIGITAL ELECTRONICS LAB (A)
Time : 3 Hours Max. Marks : 100

1. Set up a mode 60 BCD counter.

2. Design and set up a 4 bit serial subtractor.

3. Design and set up a 4 bit ripple carry adder.

4. Design and set up a mode 10 counter.

5. Design and set up a 4 bit serial adder.

6. Generate a delay of 100 ms.

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Batch 4
3924A* (Page : 1) 3924 A
Reg. No. : ................................

Name : .....................................

V Semester B.Tech. Degree Examination, June 2009


Branch : Applied Electronics
Lab : DIGITAL ELECTRONICS LAB (A)
Time : 3 Hours Max. Marks : 100

1. Design and setup a 3-bit asynchronous down counter using JK Flipflop.

2. Design and setup a 2-bit asynchronous up-down counter using JK Flipflop.

3. Design and setup a 3- bit synchronous up counter using JK Flip flop.

4. Design and setup a 3- bit synchronous up counter using JK Flip flop.

5. Design and setup a 3-bit synchronous down counter using JK Flip flop.

6. Design and setup a mode-6 synchronous self starting counter using JK Flip Flop.

Batch 5