The Design of the Interface for Camera Link and DM642

Dongyun Wang, Xuehua Tao, Rong Hu

School of Electric and Information Engineering ,Zhongyuan University of Technology, Zhengzhou, 450007
E-mail: wdy1964@yahoo.com.cn, ttjj108@126.com,hrhr35@163.com

Abstract: At present, line-scan CCD camera with camera link output cannot be connected with the video ports of DM642. To
this issue, based on the detailed analysis of the camera link interface protocol, three specialized chips were chose for level
conversion; More over, a FIFO buffer has been designed in FPGA combined the camera specification and sequential. It solves
the interface problem between camera and DM642, that is the data butter of the different clock domains. The design has achieved
the control of the line-scan CCD camera and sampling of CCD signal. The tests indicate that, the interface circuit can sample
effectively. Moreover, it has Laid the foundation for further analyzing and processing of image data.
Key Words: Line-scan CCD, Camera Link Interface, FIFO, DM642

Video Data: Video data contains twenty-four bits image

1 INTRODUCTION data and four bits image enables. The four image enables
During the past decades, the embedded image processing signal are defined as: FVAL, LVAL, DVAL and Spare.
system has experienced a great improvement in both They are Frame Valid, Line Valid, Data Valid and Spare.
images quality and real-time. Nowadays, DM642 as TI’s The principle of it is as shown in Fig 1.
high-performance fixed point DSP have become a popular
DSP chip in image processing machines[1]. Meanwhile, the
machine image acquisition system as the front end of all
machine vision system usually got analogy signal from a
CCD camera and captured by video processing chip such
as SAA7113, and then image data is passed to the vision
port of DM642. However, many camera companies
contributed to the development and definition of the
Camera Link standard.
In this paper, the Basler’s L304kc has been chose to be the
CCD camera[2]. And the video output type is camera link
LVDS, base configuration. The number of pixels of L304kc
is 4080 per line. The pixel clock speed is 30MHz in 3 tap
output mode. The LVDS signal cannot connect to the port
of DM642.It is necessary to design a special camera link
interface circuit as the camera interface operation standard
and time sequence. Meantime, It can solve the data buffer
Fig 1. The Principle of the Camera Link
in different clock domain. Based on this we present to
design a FIFO in FPGA to solve the interface problem Channel Link consists of a driver and receiver pair. The
between the camera and the DM642. driver accepts 28 single-ended data signals and a
single-ended clock. The data is serialized 7:1,four data
2 CAMERA LINK INTERFACE DESIGN streams and a dedicated clock are driven over five LVDS
ANALYSIS pairs. The receiver accepts the four LVDS data stream and
LVDS clock, and drives the 28bits and a clock to the board.
Camera Link is a new high-speed serial data interface The L304kc is the line-scan CCD camera, Frame Valid is
standard developed by a consortium of camera and frame not defined, only define the data valid signal DVAL and
grabber companies, including Data Translation. Camera Line Valid signal LVAL.
Link, based on National Semiconductor’s Channel Link
technology, provides a universal, high-speed, serial cable Camera Control Signals: Four LVDS pairs are reserved for
interconnection standard for both digital cameras and general-purpose camera control. They are defined as
image acquisition boards. Camera Link signal is divided camera inputs and frame grabber outputs. Camera
into three categories[3]. manufacturers can define these signals to meet their needs
for a particular product. The signals are: Camera Control1
The standard Camera Link cable provides video data, (CC1), Camera Control2 (CC2), Camera Control3 (CC3),
camera control signals, and serial communication. A single Camera Control4 (CC4),
26-pin cable contains up to 28-bit video data, clock, enable
and control signals.

c
978-1-4244-5182-1/10/$26.00 2010 IEEE 2914
CC1 is only defined in L304Kc as the external clock
synchronization signal (ExSYNC), used to select the
exposure mode for the external trigger or internal trigger.
Serial Communication Signals: Two LVDS pairs have
been allocated for asynchronous serial communication to
and from the camera and frame grabber. Cameras and frame
grabbers should support at least 9600 baud.
Based on the above analysis, we can come to the conclusion
that the main problem of the interface design of the project's
is how to format the three type Camera link signals into
signal which DM642 processor are receivable.
3 CAMERA LINK INTERFACE DESIGN
L304kc is a line-scan CCD camera with LVDS signals
output. Therefore, interface circuit consists of two parts:
one for level conversion of LVDS signal; another is
interface circuit design of the video image data and DSP.
DM642 camera and the interface structure shown in Fig 2.
Fig 2. Camera Link Interface Structure
The Camera Link interface uses a cable assembly
manufactured by 3M, with MDR-26 pin connectors on both
ends. At first video signals comes from CCD camera
thought MDR-26 pin connectors. LVDS signals
respectively enter three LVDS / TTL conversion chip. The
TTL signals is ported to directly into the FIFO of the
FPGA, The FPGA send camera control signal s to camera
and receive the video data into buffer. Whenever the state
of FIFO is half-full, which will trigger DSP to readout the
data in the FIFO. Next we will present respectively the
interface-level video data conversion and interface
processing.
3.1 LVDS / TTL Conversion Circuit
LVDS / TTL conversion is applied in pairs, and its function
is to convert the TTL signal into LVDS signal, or TTL
signal is converted into LVDS signals. In the design of
interface circuits, specialized chips are used in each part of
the differential conversion to be translated into TTL-level
signals.
Serial communication signal is mainly used for the
parameters settings of the camera configuration. In order to
facilitate setting the parameters of the camera, camera
manufacturers have made a special software with the
camera through the serial port, so the chip DS90LV019
were used to convert LVDS signals into TTL signals, and
then the signals will be converted to convert RS-232 level
thought RS-232 chip MAX232. Finally the camera
configuration tool will be used to set the parameter on
computer.
The external synchronization clock signal of the camera can
be controlled by the FPGA[4][5]. The chip DS90LV017 is
used to convert a TTL signal to a pair of LVDS control
signal.
Video signals include five pairs of LVDS, of which four
pairs of video signals and 1 clock signal. We choose
DS90CR288 as a receiver chip, used to receive differential
signal. The output signals are 28-bit data (24-bit image
data, 4 sync signal) and 1 bits TTL-level clock signal.
3.2 Video Data FIFO Interface Design and
Implementation
The video data output mode of L304kc operates in 3tap
8bit. In this mode, L304kc camera operates with a 30MHz
pixel clock. On each clock cycle, the camera transmits 8
bits of data for a red pixel, 8 bits of data for a green pixel, 8
bits of data for a glue pixel, a line valid bit and a data valid
bit. The camera link pixel clock is used to time data
sampling and transmission. As shown in Fig 3, the camera
samples and transmits data on each rising edge of the pixel
clock. Pixel data is only valid when line valid and data valid
bits are both high.
Fig 3. Camera Output Principle
The camera output data cannot be connected directly with
DM642 video port f interface. It is have to design the
specialized interface circuit.
Video data will be read thought DM642's EMIF interface.
However, video data can not be direct connect with
DM642's EMIF[6][7], due to the difference between clock
frequency: the frequency of camera is 30MHz, EMIFA
clock usually works at the 100MHz or 150MHz. From the
above analysis, it is need to add a buffer between the DSP
device and the camera. And the EMIF supports a glueless
interface to the asynchronous device FIFO, so we consider
FIFO as the data buffer. Asynchronous FIFO memory has
the following advantages: there are two separate ports to
read and write access, read and write speed may be
different, and read and write operation can be carried out
simultaneously and do not have to synchronization; data
write in and read out follow the principle of first-in and
first-out, the order of read and write is determined, the read
address and write address is determined by the address
pointer, which is no need for external address.
Mostly the specialized FIFO chip is chose to do the buffer.
However, 24 bits image output need multi-chips cascade
connection. It is too complex. Moreover, we need FPGA to
do some logic. So it is easy to make a embedded FIFO
2010 Chinese Control and Decision Conference 2915
 memory buffer in FPGA[8][9][10]. The design in FPGA
is flexible to achieve different width and depth of the FIFO.
The Altera’s high-effective chip EP1C6Q240C8 is very
suitable. The realization of the FIFO is using the macro
module provided by QuartusĊ. There are two important
parameters to be set: first, the width of FIFO, refers to the
data bit FIFO read and write once. Their width can be
defined. We define write FIFO data width is 24. Second, the
depth of FIFO, refers to the number of FIFO can store N
bits (width) of data. The depth is according to the specific
circumstances of the circuit and the FPGA’s internal Fig5. Write and Read FIFO
resources to determine. We define the depth is 2K. When
the state of FIFO is half-full, the interrupt to be send to
DM642.
The interface circuit is as shown in Fig 4, input port is
controlled by the write enable WEN and write clock signal
WCLK. When WEN is valid, at the rising edge of every
WCLK a bit data will be deposited into FIFO; and output
port is controlled by read enable signal REN and RCLK
read clock signal. The LVAL and DVAL make up WEN
signal. The pixel clock makes up WCLK signal. When
LVAL and DVAL are both high, at the rising edge of pixel Fig6. Read FIFO
clock, the 24-bit video data CAM_D will be write into FIFO is reasonable.
FIFO; after interrupt triggers, FIFO is mapped to the CE3
space of DM642, DSP read FIFO through the DMA. 5 CONCLUSION
In order to receive the video data, we design specialized
RXCLK WCLK RCLK ECLKOUT 1 conversion and interface circuit and make up a FIFO by
LVAL
& WEN REN CE3 FPGA to achieve glueless communication. This interface
DVAL
circuit is suitable for any line-scan CCD camera with
camera link output interface for high-speed data
FIFO
EMIFA acquisition.

HF EXT_ INTx
CAM-D D[0...23] Q[ 23...0] ED[ 23...0]
Fig 4: The Interface Design Circuit
4 THE EXPERIMENT RESULT
Schematic design input mode on QuartusĊ platform is
popular with its simplify. We made a high-speed FIFO on
Quartus Ċ platform, Using the macro function blocks
LPM_FIF0 + in LPM, according to the need to adjust
parameters.
When the first-128 pixel data writes into the FIFO, the
half-full signal trigger interrupt signal. At the same time,
FIFO is mapped to the CE3 space of DM642. Then the
EMIFA begins to read data from the FIFO; When the 128
pixel data is read out, the rdreg will be low-level and stop
reading data. During this period, FIFO still writes the other
half buffer. When the second -128 pixel data is write into
FIFO, DSP begin to read FIFO. In summary, the design of
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2916 2010 Chinese Control and Decision Conference