Training Learning Maps

CAD E N C E T R A I N I N G
LEARNING MAPS
Cadence Training Services learning maps provide a comprehensive visual

overview of the learning opportunities for Cadence customers. They provide
recommended course flows as well as tool experience and knowledge levels to
guide students through a complete learning plan. Learning Maps cover all
Cadence Technologies and reference courses available worldwide. For exact
course names, descriptions, and schedules, please refer to each regional course
catalog on Cadence.com.
TABLE OF CONTENTS
• PCB and Package Design with Allegro Technology
• Custom Design with Virtuoso and Assura Technology
• Digital Design and Encounter Technology
• Digital Verification, Languages, and Methodologies with Incisive Technology
Learning Map for
PCB and Package Design with Allegro® Technology
Logic Design PCB Design Signal Integrity IC Package Library
Design Development
Allegro AMS EE Pspice Advanced Allegro RF PCB SiP RF Architect
Analog Focus
Simulator Adv. Analysis

Analysis
Analog Simulation
Allegro AMS with PSpice
Simulator
Allegro FPGA PCB Editor XL EE Allegro

EE Allegro PCB Editor
Master
GXL
System Planner Adv. Techniques SKILL Language
PCB SI GXL
Allegro GRE XL Allegro Design Entry
IFP HDL SKILL Language
Allegro EE
Allegro Design Allegro PCB Allegro Allegro Design
Experienced
Design Reuse Workbench for Editor Intermediate PCB Power Integrity Workbench for
Engineers and Techniques Administrators
Designers
Allegro System Allegro
Architect PCB SI EMControl
Allegro High-Speed Constraint Management EE
Orcad Capture Allegro PCB Allegro PCB SI Allegro Package Allegro PCB
Editor Basic Foundations Designer Librarian
Techniques
SiP Digital SI
Core
Allegro Design Orcad Capture Allegro SiP Layout Allegro Design

Entry HDL Front- CIS PCB Router Basics Understanding high Workbench for
frequency PCB design –
to-Back Flow Librarians
High-speed, RF,
and EMI
Also available as an Internet Learning Series course EE Denotes Advance with Engineer Explorer class
L, XL, GXL Denotes tiers of Cadence products used in course - Not applicable if no legend
Some course titles may vary. Please refer to your regional catalog for exact titles & course datasheets. Home
Learning Map for
Custom Design with Virtuoso® and Assura® Technology
IC CAD Analog, Mixed-Signal and RF Design Layout Design and Physical Verification
EE
RF Analysis XL, GXL Virtuoso Layout Virtuoso Digital GXL
with Virtuoso Spectre Migrate Implementation
Master
Circuit Simulator
EE EE
Advanced SKILL Behavioral Modeling with EE
Virtuoso Space-based
Using Virtuoso Assura Rules-Writer
Language Programming Verilog-AMS or Router
Spectre Circuit
VHDL-AMS
Simulator Effectively
Analog Modeling with Virtuoso GXL EE Mask Compose

EE Verilog-A Floorplanner Automated Reticle
SKILL Programming Design Synthesis
Experienced
for IC Layout Design

Virtuoso AMS Designer Virtuoso Cadence QRC
Simulation and Analysis
Using OCEAN Chip Assembly Router Techgen Developer
SKILL Development of
Parameterized Cells Virtuoso Analog XL, GXL Cadence QRC User
Virtuoso UltraSim L, XL Virtuoso XL, GXL
Simulation Techniques Full-Chip Simulator Connectivity-Driven Transistor-level
Layout Extraction
SKILL Language Virtuoso Analog L Virtuoso Spectre L Virtuoso Layout L

Assura Physical
Programming Design Environment Circuit Simulator Design Basics Verification (DRC/LVS)
Core
Virtuoso Design
Environment
Virtuoso L, XL
Virtuoso Design Schematic Editor

Environment Setup
Learning Map for
Digital Design with Encounter® Technology
Logic Design Place-and-Route Signoff and Analysis Design Verification
EE EE
Advanced GXL Advanced Logic XL
Master
Signoff Power-Grid Equivalence Checking with

Analysis with Encounter Encounter Conformal EC
Power System
Encounter XL
Conformal ECO
Test Synthesis XL
Using Encounter RTL Extended Checking with L
Compiler XL EE Encounter Conformal EC
Experienced
Low-Power XL EE Signoff
Implementation Power-Grid Analysis with
Low-Power XL Encounter Power System
Synthesis with Encounter Encounter Conformal XL
RTL Compiler Low-Power Verification
EE
Advanced GXL Custom Equivalence GXL
Synthesis with Encounter Checking with Encounter
RTL Compiler Conformal EC
Encounter RTL XL Floorplanning, XL Signoff Timing Analysis XL Logic Equivalence XL

Compiler Physical Synthesis, Place with Encounter Timing Checking with Encounter
and Route (Hierarchical) System Conformal EC
Core
Basic Static Timing Floorplanning, XL Cadence QRC User XL Encounter XL

Analysis Physical Synthesis, Cell-Level Extraction Conformal
Place and Route (Flat) Constraint Designer
Learning Map for
Digital Verification, Languages, and Methodologies with Incisive® Technology
Design & Verification System C/C++

Master
EE EE
Formal XL
SystemVerilog XL
Analysis Advanced Advanced Verification
with IFV Using OVM/UVM
Formal Analysis SystemVerilog XL EE

XL
SystemC Transaction SystemC Synthesis
Fundamentals Assertions Level Modeling Using C to Silicon
Experienced
with IFV Compiler
EE EE
Verification SystemVerilog XL Verification L Incisive XL SystemC Verification
with PSL for Design and with VHDL Simulation of PSL (SCV)
Verification Assertions
VHDL for L Verilog L Incisive XL SystemC XL

Verilog users Language and SystemC, VHDL, Fundamentals
Application and Verilog
Simulation
Core
Verilog for L VHDL L Designing L C++ Language

VHDL users Language and with VHDL
Application
Continued
Learning Map for
Digital Verification, Languages, and Methodologies with Incisive® Technology
Verification Metric-driven Verification Scripting
Verification
Master
Specman XL EE XL
Elite Advanced Planning Using

Verification Enterprise Planner
Specman Elite XL Perl for EDA

Basics for Environment Engineering
Experienced
Developers
Incisive XL EE Tcl Scripting for EDA +

Comprehensive Intro to Tk
Coverage
Specman Elite XL Incisive SystemC, XL

Basics for Environment VHDL, and Verilog
Users Simulation
Core

Training Learning Maps

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CAD E N C E T R A I N I N G

Cadence Training Services learning maps provide a comprehensive visual

Simulator Adv. Analysis

Allegro FPGA PCB Editor XL EE Allegro

Allegro High-Speed Constraint Management EE

Allegro Design Orcad Capture Allegro SiP Layout Allegro Design

Analog Modeling with Virtuoso GXL EE Mask Compose

for IC Layout Design

SKILL Language Virtuoso Analog L Virtuoso Spectre L Virtuoso Layout L

Virtuoso Design Schematic Editor

Signoff Power-Grid Equivalence Checking with

Encounter RTL XL Floorplanning, XL Signoff Timing Analysis XL Logic Equivalence XL

Basic Static Timing Floorplanning, XL Cadence QRC User XL Encounter XL

Design & Verification System C/C++

Formal Analysis SystemVerilog XL EE

with IFV Compiler

VHDL for L Verilog L Incisive XL SystemC XL

Verilog for L VHDL L Designing L C++ Language

Verification Metric-driven Verification Scripting

Elite Advanced Planning Using

Specman Elite XL Perl for EDA

Incisive XL EE Tcl Scripting for EDA +

Specman Elite XL Incisive SystemC, XL

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