Escolar Documentos
Profissional Documentos
Cultura Documentos
I
Phone Jack (PHONES)
I
Knob (OUTPUT LEVEL)
Knob (+IO, +20. +30, +40, +50)
(K29-2648-04) X 5
(El 1-0162-05) (K29-2648-04) X 2
Insulator Ass'y
Phono Jack (COAXIAL)
(El 3-01 31 -05)
1
Electric Circuit Module (OPTICAL)
R: (J02-0356-05) X 2 Cap (~02-0784-05)
L: (JO2-0357-05) X 2 (809-0068-05) Cap
(809-0063-05)
To AC outlet
8 OPEN/CLOSE key ( A )
Press once to open the disc tray. Press again
l
O
l
4D
1 1 1 1 1 1 1 1 1 1 1 @ A b 4 B repeat key
This key lets you define the beginning (A)
and end (B) points of a section of music
to close.
that you want played repeatedly.
@ INDEX keys ( a INDEX El )
Used to specify index numbers within Display window
tracks. @ REPEAT key
@ Disc indicator (DISC) @ SPACE indicator 1-)( Used for repeated play.
(b Manual search keys ( 44 , bb )
These keys let you move quickly forward Confirms that a disc is in the tray.
@ Emphasis indicator (EMPHASIS) @ Disc tray
or backward across the disc. @ Disc out indicator (m) This confirms that the disc in play
Q) Music skip keys ( 4 4 , bbl ) This illuminates (red) when there is was recorded with high frequency
Used to skip forward to the start of the no disc in the tray. emphasis.
next track or back to the start of the
current or preceding track.
0 A-B repeat indicator (mm) 0 Edit indicator (ml)
@ PLAY/PAUSE key ( D II )
8 Maximum track number indica-
tor (MAX TNo.) 88 BE
1 2 3
7 8 9
4
-
511LEEI
,o/!:g1
I
@ Index number (INDEX)/program
number (PNO.)
Shows the current index number
Press to begin play. Press during play to
pausr- or resume play.
Shows the highest track number
'7% ;Es
I
wxTm. 111
- '
12 13 14 1 5 ! 1 2 s
1
1 1 3 ~
IC2 TC74HC174F 1 D-type flip-flop 1 Controls larnps and LEDs for each mode
IC3 TD62003AP Transistor array 1 Transistor array drives larnps and LEDs for each mode
r - i500ms Wait
Dise Motor
rotation start
u Tray close
Returns pickup
to inside
Laser ON u Tracking ON
ldDunl
or more
a
Focus Lens
u
Feed Motor
350ms Wait
9 Focus Lens
a
IF 15 sec
failure
TOC read-out
1
1
Searches start
of 1 st track
and starts play
signal "H"
Disc Motor
brake
SENSE signal
chattering
ii
rernoval. 500 us
"DISC OUT"
indicated Disc Motor
I I
A
. If 1.2 sec
failure
CIRCUIT DESCRIPTION
Test mode
I f the TEST pins are short-circuited when the power is
turned ON, the microprocessor enters test mode. With the
microprocessor set t o test mode, each operation can be
easily checked after making a repaire or adjustment.
With the DP-1 100SG. the microprocessor can be set to
test mode by short-circuiting pin 6 and pin 7 of the CD
PLAYER UNIT (X32-1170-00).
Note': "Set mode" shows the normal status.
c, ,
the TEST pin
short-
circuited?
"01" is
dirplayed.
,,
OPENICLOSE
1 - 1
key.
Effective keys in the Test mode and their functions 6Set mode
1
Disc's Track No. is displayed.
(1) Focus s e ~ o. ............. ON. TRACK NO.
Key 1 1 2 1 3 1 4 1 5
Numeric (digit) Number of tracks 1 1 4 1
16 1
3 2 11000
8 Direction Outward
keys (0-9)
Key 6 1 7 1 8 1 9 1 0
Number of tracks 1 1 4 1 16 132 11000
Direction lnward
When the tray is opened and the closed again in test mode, TRACK
12 9 OPEN/CLOSE NOS. 2, 17. 2. 6. 7. 8. 10. 13 and 22 are automatically programrned
Opening the tray again will cause the unit to enter set mode.
CIRCUIT DESCRIPTION
Flow chart of test mode
Flow chart from tray OPEN status sfter power ON
7 Power O N
Tray
CLOSE
i
1
5 sec.
elapsed?
FI Cancellation
data store
utward
feed of PU
01 displayed
e
?l]
S L T : "Lu?
Outward feed
YES
Cancellation
5 sec.
elapsed?
YES
9
in T N O of tray
9 SLT : "H"?
S L T : "H"?
CLOSE key
pressed?
1 YES l
S L T : Pickup start lirnit switch
CLS : Tray clore detect switch
OPEN : Tray open detect switch
Acceptance of key
CIRCUIT DESCRIPTION
Focus warch & focus servo ON
1 .Osec
h Focus UP
SENSE :
Focus
servo ON
4 I
Disc motor
ON
& b
C
CIRCUIT DESCRIPTION
Tracking sewo ON Disc rnotor stop
Disc motor
Disc motor
brake 4OP
>
l
YES
("SENSE")
3 sec.
elapsed?
2 sec.
Q 200rns WAlT
1 YES
Disc motor
OFocus search
Ga
CIRCUIT DESCRIPTION
a From loading of Q data to display Flow chart from the time the tray opens until the STOP
indicator lights, after pressing the tray.
< START
m4
START
t
Tray
CLOSE
NO
Y ES -1
Loading of al1 of @
96 bit data
Focus servo O N
after focus search
. i
Tracking
,
A
servo ON
NO b
4
Feed servo
ON
4
I TOC load
I
4
STOP display
NO
1
(Top View)
Pd VDD (+5v)
Pc Pe
Pb Pf
Pa pg
SENSE Ph
WFCK pl
SUBQ pi
CRCF GND
FiCI GND
SCOR Pk
FOK PI
GFS G14
RMUTE G13
EMPH G12
DlRC G11
MUTG G10
FGSW G9
SLTSW G8
OPNSW G7
CLSSW G6
K1 G5
K2 G4
K3 G3
K4 G2
DATA G1
XL T RESET
CLK VRUP
LDC VRWWN
XRST CLSM
(4.23MHz) X I OPNM
X2 NC
GND NC
CIRCUIT DESCRIPTION
Pin Function Table
Pin No. I/O 1 Pin Name 1 Functions
O 1 Pd- Pa 1 FL display segment indication and key scan signal output
I 1 SENSE 1 Sensing signal input (from CXDl125QZ. CXA1244S)
I WFCK O data read-off clock input (from CXD112502)
l SUBO Q data input (from CXDl125QZ)
I CRCF O data CRC OK rH")input (from CXD1125QZ)
I RCI Remote control signal input
I SCOR Q data sync signal input (from CXDl125QZ)
I FOK Focus OK ("Ha')input (from CXA1081 M)
I GFS 1 EFM sync OK ("Ha')input (from CXD1125QZ)
O 1 RMUTE 1 Relay mute ON/OFF ("L"/..H")
O EMPH Emphasis ON/OFF ("H"/"L")
O DlRC DlRC signal output (to CXAl244S)
O MUTG MUTG signal output: Mute ON/OFF ("Hm/"L) (to CXD1125Q.Z)
O FGSW Focus gain switch signal output
I SLT SW Start limit switch signal input (SW ON = "L")
I OPN SW Tray open switch signal input (SW ON = "L")
1 CLS SW Tray close switch signal input (SW ON = "L")
I K1
Block diagram
VI
L 5
-
14
O
O a w m Y
U
Z E z
W VI
O
O
m
U
a
U
0
4;i w
l-
Y
LL
W
2'
U
U
-
LL
K
O
LL
a
O
LL
K
.
Z
O
D
J
O
O
-
O
O
N
O
U
>
W O
Y
-
W
K
>
N
V
U
CIRCUIT DESCRIPTION
Explanation of terminals
Terminal No. Terminal name 110 Function
1 RF1 I Input pin of the Ccoupled signal output from the RF summing amp.
2 RF0 O Check point of eye pattern for the RF sumrning amp output pin.
3 RF I RF summing amp feedback input pin.
4 PIN I P-subIL-subselect pin of LD. (DC voltage: in N-sub mode)
5 LD O APC L D amp output pin. (DC voltage: PD open in Nsub mode)
6 PD I APC PD amp input pin. (DC voltage: open)
7 PD1 I RF 1-V amp (1) invert input pin. Current input by connecting t o PIN diode A + C.
8 PD2 I RF 1-V amp (2) invert input pin. Current input by connecting to PIN diode B + D.
- Connected t o GND when using a positive ( + )lnegative (-) dual-voltage power supply.
9 VC
Connected t o VR (pin 14) when using a single-voltage power supply.
1O F I . F 1-V arnp invert input pin. Current input by connecting t o PIN diode F.
11 E 1 E 1-V amp invert input pin. Current input by connecting to PIN diode E.
12 €0 O E 1-V amp output pin.
13 El I E 1-V arnp feedback input pin. For E 1-V amp gain adjustment.
14 VR O DC voltage output pin of (Vcc + V E E ) / ~ .
15 CC2 I Input pin of the Ccoupled signal output from the defect bottom hold.
16 CC 1 O Defectbottom hold output pin.
- Connected to the negative power supply when using a positive ( + Ilnegative (-) dual-voltage power
17 VEE
supply. Connected t o GND when using a single-voltage power supply.
18 FE BlAS I Bias pin at the focus error amp non-invert side. For CMR adjustment of the focus error amp.
19 FE O Focus error amp output pin.
20 TE O Tracking error arnp output pin.
21 DEFECT O Defect comparator output pin. (DC voltage: connected to a 1 0 k n load).
22 MlRR O Mirror comparator output pin. (DC voltage: connected to a l O k n load).
23 CP I Mirror hold capacitor output pin. Mirror comparator non-invert input.
24 CB I Defect bottom hold capacitor connect pin.
- Connected t o GND when using a positive ( + Ilnegative (-) dual-voltage power supply. Connected to
25 DGND
GND (VEE) when using a single-voltage power supply.
26 ASY I Auto asymmetry control input pin:
27 EFM O EFM comparator output pin. (DC voltage: connected t o a l O k n load).
28 FOK O FOK comparator output pin. (DC voltage: connected to a 1 0 k n load).
-
29 L D ON I L D ONIOFF select pin. (DC voltage: when L D ON).
VCC
10K
1b
IP02 I VB
RF I - V amplifier
-IB+D) FE
-(A+C)
VA FOCUS
ERROR
C 2 25P- 164 K AMP
CIRCUIT DESCRIPTION
Tracking error amp The difference between the E 1-V amp and the F 1-V
The current from the side spot photodiodes is input to amp is calculated by the tracking error amp, and the photo.
pins E and F and is converted to a voltage by the E 1-V diode (E-F) current is converted to a voltage and output.
arnp and F 1-V arnp respectively. That is:
VTE= (VE- VF) X 3.2
V~=iFX403kQ
= (iE-iF) X 1290k Q
V ~ = i E x 2 6 0 k!2 X +
R A / ( R B + ~ ~(RA
~ )+260k)
Focus OK circuit C34 is used to determine the time constants of the EFM
The focus OK circuit creates a timing window, turning comparator, the HPF in the mirror circuit, and the LPF
the focusing servo ON with the focus search status. in the focus OK amp. Normally, C34 = O.01pF is selected,
While the RF signal is present at pin 2, its HPF output with fc = 1kHz. This will prevent degradation of the block
is present at pin 1. At the same time, the LPF output error rate due to an RF envelope lack caused by cracks, etc.
~~~~~~~
(opposite phase) of the focus OK amp is obtained. on the disc.
The focus OK output is inverted when VRFI -VRFO
= -0.37V.
'% 15 K QK FOK
0.625V
Oo
tracks (mirror section). In addition, the output goes "H"
I
when -a defect is detected. The time constant of the mirror (BOTTOM
hold should be quite larger when compared with the HOLD)
traverse signal.
I
I
I 0.033~
I
I
MIRROR AMP
I
I
i
- - - - - - - - - -h - Ji
MlRRoR
I
b
CowARAToR DGNo
CIRCUIT DESCRIPTION
EFM comparator The EFM comparator is designed as a current switching
The EFM comparator converts the RF signal into a type, and the "H" and "L" levels are not equal to the
binary coded signal. Since asymmetry caused by disper- power voltages. Therefore, feedback is required via a
sion when manufacturing the discs cannot be reduced by CMOS buffer.
AC coupling only, the reference voltage of the EFM com- R9. RIO, C3 and C8 constitute a LPF to obtain the DC
parator is controlled using the characteristics that the cornponent of (Vcc+DGND)/2 (VI. If the cut-off frequency
present probability of a 1 or O is 50% each for the binary (fc) is set to more than 500Hz. leakage of the EFM low fre-
coded EFM signal. quency signals will be greatly increased and will result in
a degradation of the block error rate.
AUTO ASYMMETRY
RF1
I
L-------- ,,,- --------
EFM COMMRATOR
-----A
1
Defect circuit
After inverting the RF1 signal, the defect circuit bottom
a
holds with the two long/short time constants. The bottom
hold with a shorter time constant responds to a mirror
defect of more than 0.1 msec on the disc, and the bottom b
hold with a longer time constant holds the mirror level
obtained immediately before the defective section. These
signals are C-coupled, then differentiated with level shift-
BOTTOM
ing. The signals are compared with each other to generates Broken line CC2
the rnirror defect detecting signals. Continuous
n n H
line CC1
e 2- -LL
1 Amsec M A X
EFECT BOTTOM
DEFECT AMP
CIRCUIT DESCRIPTION
Servo signal processor CXAl244S
(X32-1170-00 : I C I )
CXA1244S is a bipolar IC developed for servo of com-
pact disc (CD) players, and it provides the following func-
-
Terminal connection diagram
29 TG 1
tions. TAO
OTracking control (servo ONIOFF, single track jump, TAO
multiple track jump, gain control, phase compensation SENSE DlRC
V) SL@
control, brake circuit)
0 Sled control (servo ONIOFF, fast forward, fast
XRST 3N SLO
DATA S LO
reverse)
sX 21
FE@
F EO
CLK 10 O
MlRR 11 20 FE
TZC 12 19 ATSC
TE 13 18 FS3
ISET 14 17 VEE
VCC 15 16 SRCH
Block diagram
TG2 TA@ TE0 TE@ SENSE C.OUT XRST DATA XLT CKL MlRR TZC TE ISET VCC
CIRCUIT DESCRIPTION
k
input level exceeds the
wind camparatbr level CLK
CONTROL IVTH = 'Vcc x 13%).
1 1 1 1 But fhis is no1 used in 1
fhis equipmenl.
t w c k w twck
1 1 Judoement output of
positive or negative ol w
1Ifck
tracking zero cross.
tracking error.
When used at the timr
TRACKING
TZC of ringle track lump.
MODE
DlRC ir reduced 10
"Ln on defection of , 1 ,
Execution of instruction
TZC t . in FWD JUMF
or on derection of +
1
tWL
1 27
TZC 1 in R E V JUMP
CIRCUIT DESCRIPTION
Systern control
*
ADDRESS DATA
COMMAND SENSE
D7 D6 D5 D4 D3 D2 Dl DO
FS4 FS3 . FS2 FS1
FOCUSCONTROL O O O O FOCUS GAlN SEARCH SEARCH FZC
ON DOWN ON UP
ANTl BREAK TG2 TG1 *
TRACKINGCONTROL O O O 1 AS
SHOCK ON GAIN SET
TRACKING* SLED*
TRACKINGMODE O O 1 O TZC
MODE MODE
OFF
SERVO ON SERVOON
FWD JUMP FWD MOVE
REV JUMP
- -
TRACKING
MODE
Block diagram L Y VI
U O
C, Y V mI
W
VI
1
subcoae
Sync Detector
1 1 ~ubcode
Demodulotor
~ u b c o r ~O
Regis ter
e
VOO
GFS
VOD
LOC K
TEST
FSW
XRST
M DP
MUTG
MDS
MD1
MON
MD2
VCOO MD3
PSSL
SLOB
vss
VSS
XTAO
X'TAL circuit
XTA l
timing generoior
I
w
!
(:xo:::z3
Digit01 Filter
WDCK
LRCK
CNlN DOTX
CIRCUIT DESCRIPTION
Explanation of terminais
Terminal No. Terminal name I/O Function
1 FSW O Time constant switching output of output filter of spindle motor.
2 MON O ONIOFF control output of spindle motor.
3 M DP O Drive output of spindle motor. Rough speed control in CLV-S mode and phase control in CLV-P mode.
4 M DS O Drive output of spindle motor. Speed control in CLV-P mode.
5 EFM I EFM signal input from RF amplifier.
6 AS Y O Output for controlling the slice level of EFM signal.
Samples the GFS signal with WFCKI16, and outputs "H" when the level is high.
7 LOCK O When it is "L" for eight times, in arow, outputs "L".
8 VCOO O VCO output. f = 8.6436MHz when locked t o EFM signal.
9 VCOl I VCO input.
1O TEST l (OV)
11 PD0 O Phase cornparison output of EFM signal and VC012.
12 Vss - GND (OV)
13 CLK I Serial data transmission clock input from CPU. Data is latched at rising edge of a dock.
14 X LT I Latch input from CPU. Data (serial data from CPU) from the 8 bit shift register is latched in each
-
Notes: PLCK : VC0/2 output. f = 4.3218MHz when locked t o the EFM
ClFI
C l F2
:}Error correction status rnaiitor output for C l decode.
signal.
UGFS : Non-protected frarne sync pattern output.
GTOP : Frarne sync protect status display output.
C2F1
C2F2
i
} ~ r r o rcorrection status rnonitor output for C2 decode. RAOV : 14 frarne jitter absorption R A M overflow and underflow
C2PO : C2 pointer signal. display output.
C2F L : Correction status output. Goes "H" when the currently C4LR : Strobe signal. 176.4kHz.
-
corrected C2 series data cannot be corrected. C210 : C210 invert output.
RFCK : Read frarne clock output. 7.35MHz when locked t o the C210 : Bit clock output. 2.1 168MHz.
crystal line. D A T A : Audio signal serial data output.
WFCK : Write frarne clock output. 7.35MHz when locked t o the
crystal line.
CIRCUIT DESCRIPTION
Explanation of functions
CPU interface to three terminals, XLT, CLK and DATA. The address
1) Data input and data of each terminal are as shown in Table 6-2, and
Each register may be set by input of 4 bit address, and their functions are as follows. The contents of each register
4 bit data from LSB in the timing that is shown in Fig. 6-2 become entirely O when XRST = "L".
CLK
terminal
X LT
terminal
Registers
Valid
A-E
1
D3 : GSEM Provided for switching framesynk. protection 16 when D2 = 1.
D2 : GSEL characteristics in correspondence t o the time D l : Tp Used for setting the period of peak hold in
D l : WSEL of playback and time of access. Details the CLV-S mode. Peak hold is made in the
DO : ATTM will be described in the paragraph of "EFM period of RFCK/4 when D l = O or in the
demodulation". period of RFCK/2 when D l = 1.
DO : ATTM Used for attenuating audio signals by 12dB, DO : GAIN Used for setting the gain of MDP terminal
and the details will be described in the para- output in the CLV-S and CLV-H modes.
graph of "DIA interface". It is -12dB (time of 314 out of the period of
ORegisters B and C - Counter set, more significant 4 RFCK/2 is of high impedance) when DO = O
bits (register C) and less significant 4 bits (register B) or is OdB when DO = 1.
these registers are used for setting the tracking count
value. the data of registers B and C are preset in the counter
through the 4 bit buffer register assigned by address.
CIRCUIT DESCRIPTION
0 Register E-CLV mode
It is as shown in Table 6-2.
The details of each mode will be described in the paragraph
o f C L V servo control.
Dn=O Dn= 1
ZCMT 03 Zero-cross MUTE off Zero-cross MUTE on
HZPD D2 PDC pin is always active PDC pin is "Z" at the trailing edge of GFS
NCLV Dl CLV-P servo for the frame sync signal CLV-P servo for the base coanter
CRCQ DO CRCF is not superimposed on SUBQ SUBQ = CRCF at the raising edge of SCOR
+2 Register A
1 13
*3 Register D
DIV D3
O 1 RFCK/4 & WFCK/4 Phase comparison frequency
1 1 RFCKl8 & WFCK/8 in CLV-P mode
O RFCK/32 Bottom hold period in
TB D2
1 RFCK/16 CLV-S. CLV-H mode
O RFCK/4 Peak hold frequency i n
Tp Dl
1 RFCKl2 CLV-S mode
O -12dB Gain at MDP terminal in
GAlN DO
1 OdB CLV-S. CLV-H mode
+4 Register E
1 Mode 1 D3-DO 1 MDP terminal 1 MDS terminal IFSW terminal 1 MON terminal 1
STOP 10000 1 L Z L L
r
KICK 11000 1 H Z L H
BRAKE 1 0 10 L Z L H
CLV-S 1 11O C LV-S Z L H
CLV-H 1 10 0 CLV-H Z i H
CLV-P 1 1 1 1 1 1 CLV-P 1 CLV-P Z H
CLV-A 0 110 CLV-S or CLV-P Z or CLV-P L or Z H
Z : High impedance
List of registers
CIRCUIT DESCRIPTION
3) Trakcing counter O) is loaded in registers and the address is set at "6".
This counter is provided for facilitating track jump. a signal (COMPLETE) that is of HlGH level up to "n"
Load the number of tracks t o be jumped in register B and pulses an.3 is of LOW level after "n" pulses is output of
C. Count of CNlN pulses is started at raising edge of XLT SENSE terminal. When the address is set at "C", signal
after it was loaded in either register B or C. (m) of CNINl2n ( H z ) is output.
When n (n = 256 is meant when register B = register C = The tracking counter timing chart is shown in Fig. 6-3.
Register
B,C X n ( n = 256 when "O" is loaded)
X L T terminal
l
I
C N l N terminal
COMPLETE
X I
I
I
I
COUNT
X I
I I I 1
Tracking counter timing chart
D7-D4 B E Others
I l I
I I I
l l I Z : High impedance
SENSE terminal COMPLETE
SQCK
SUBQ 1 *5 X Q4 X 03 )( 0 2 )( Q1 X Q8 X a77 X
'5 : CRCF when CRCQflag is "1". undefined when " 0 .
SQEX= "L" level
so SI
SQCK
SQCK terminal
SQEX terminal
CIRCUIT DESCRIPTION
EFM demodulation made by TRI STATE out of PD0 terminal. The mean value
1) Playback of bit clock by EFM-PLL circuit of PD0 terminal is about 112 VDD if synchronized, but
-
The EFM signal read out of the optical block contains the mean value drops when VCO becomes higher. On the
a clock cornponent of 2.16MHz. Therefore, it is possible to other hand, the mean value increases when VCO becornes
take out a bit clock (PLCK) of 4.32MHz synchronized less.
with this clock by the EFM-PLL circuit. The timing charts of EFM terminal, EFMO, PLCK and
At each edge of EFM signal, phase comparison is made PD0 are shown in Fig. 6-7.
with PLCK, which is 112 of VCO, is made and output is
E F M terminal 1I l
EFMO 1
1
1
l l I l
PLCK
I I 1I I
l
1 1l II I II
,
l I
.l I I
P D 0 terminal - -- - n-
I I
I ;----
- Z
l I
-u-- I
l
Z : High irnpedance
E FM terminal
EFMO
I I !
PLCK
! I
1
I
1
I
I I I I
1
I
I
I
I
I
I
P D 0 terminal
Z : High irnpedance
E F M terminal
I I
EFMO 1I
I
I 1
I
1 I I
PLCK
I
I
I
l
I
l
1 I I I
I
1
I
I
I I
I I I
P D 0 terminal - J
L
-
I I
- I I
I I I
u---- I - 1
Z : High impedance
Timing charts of EFM-PLL circuit
CIRCUIT DESCRIPTION
2) Detection, protection and interpolation of frame 3) EFM demodulation
synchronizing signals 14 bit data is taken out of the 23 bit shift register and is
There are cases during recording where the same pattern demodulated to 8 bit data through 14 + 8 conversion
is detected in the data due to the influence of drop-out circuit composed of array logics. Then a write request
and jitter, even if a pattern that is same as the synchroni- (WREQ) signal is output to the RAM interface block,
zing signal will not appear. and the data is then output to the data bus (DB08-
On the other hand, there also are cases where original DBO1) terminals) of the RAM in accordance with the
frame synchronizing signal is not detected. Therefore, OENB signal transmitted from said block.
protection and interpolation are required besides detection.
The edge portion only of EFM signal (EFMO) latched
with PLCK is converted to "1" and the rest to "O", and Sub code demodulation
then input is to a 23 bit shift register and a frame synchro- 1) Sub code demodulation
nizing signal is detected. synchronizing signals SO, SI of 14 bit sub codes are
In order to protect a frame synchronizing signal, a detected out of the 23 bit shift register. and sampling is
window is provided and the same patterns outside of this made in the timing that is synchronized with WFCK.
window are removed. This width can be selected with After delay of $0 by one frame, SO + SI is output out
WSEL. If no frame synchronizing signal is located in this of SCOR terminal and SO . SI is output out of SBSO ter-
window, interpolation is made with a signal produced by minal (only when SCOR = H.)
588-mal counter (4.3218MHzl588 = 7.35kHz) Data (P-W) of sub' codes only is input to the register
A 4 bit counter for counting the number of these frarnes in the timing synchronized with WFCK after EFM demo-
t o be interpolated is provided, and when its count reaches dulation; and sub code Q is output out of SUBQ terminal,
the level selected with GSEL, GSEM, the window is ignored and at the same time, i t is loaded in the 8 bit shift register
and the 4 bit counter is reset with the next frame synchro- and is output out of SBSO terminal in correspondence to
nizing signal. the GTOP terminal is of "H" while this opera- a clock from EXCK terminal.
tion is performed. Further, GFS terminal is of "H" when The detials of this timing will be shown in the paragraph
the frame synchronizing signal generated by the 588-mal of CP.U interface.
counter for making interpolation is synchronized with the 2) Sub code O error detection
frame synchronizing signal from the disc. The CRC sub code result is output from the CRCF pin
The frarne synchronizing signal before passage through in synchronism with the SCOR pin. I t goes "L" when an
the window or the wondow is output out of UGFS (DA05 error is detected. A t the same time as the CRCQ flag is
terminal at the time when PSSL = L.) "l", the CRCF flag is output frorn the SUBQ pin during
the time frorn the rising edge of the SCOR pin to the
trailing edge of the SUBQ pin. This timing is detialed in
GSEM GSEL
C-i
WSEL Window width
Number of frames t o
be interpolated
13 clock
17 clock
O O 2 frames Window
O 1 4 frames Window
Frame synchronizing signal before
1 O 8 frarnes
Passage through window.
1 1 13 frarnes Window
MON
-
"1" in CLV-S mode
"1" in CLV-P mode
MDS
"CLV-P mode
- - - - - -- - - - - .- - - - - - -
/
CLV-S mode
-----
Z : High impedance
'
\
I
II
Peak hold Initial StatUS Initial status II
I1
II
FF
(22 and up) 1 O F, JJi
I
14-
FF
(23 and up) ,
\ 1 -
<L
\
Bottom hold
FF
(22 and UP)
O
1
Initial status
1
[,\ 1 7
Initial status
1
(1
FF
t
- 1
O\
1
!'
,
9 ( 1
--
(23 and up) ' 1
TP
Latch
F
(22
F and up)
FF
(23 and up)
\\\
\
\,1 &$
j G
4 TB c
a and
(22 t up) h l-+'"-/
RFCK terminal
MDP terminal
(when OdB)
MDP terminal
(when -12dB)
MDP terminal
WFCK14 i 1
(or WFCKl8) I I
Z : High impedance
WFCK
I 1
I
I
l
I 288~+
I
M DS
I
(2) When rotation becomes fast
2 8 0 ~
WFCK
I I I l
I I
WFCK
I I I l
I
8 Interpolation and DIA converter interface. 16 bit data is alternately output to L-ch and R-ch,
1) Interpolation circuit block R-ch data is output in the section in which LRCK is "L"
3 byte data can be obtained with a Read to DIA and L-ch data is output in the section in which LRCK is
request. They are C2 pointer, less significant 8 bits and "H". C2PO signal outputs C2 pointer to the 16 bit data
more significant 8 bits. The total 16 bits constitute the directed to DAO1-DA16 (PSSL = H), DA16 (PSSL = L).
data generated per sampling (2's complement.) In other words, it means that the 16 bit data that is output
The C2 pointer expresses the reliability of this 16 bit when C2PO is "H" is interpolated data.
data. Therefore, data with C2 pointer is subject to inter-
polation in this block.
2) Explanation of muting and attenuator
In the muting block i t is possible to mute (- dB) or
attenuate (-12dB) the audio signal in accordance with
the MUTG terminal and ATTM signal of the CPU interface
block.
O : Without C2 pointer
X : With C2 pointer -12dB
--dB See Note
-12dB See Note
Mean value interpolation
1
B = (A+C)
2 NOTE : When the MUTG is set to "H" level with the NCLV
flag set to "O", the read base counter value is con-
1 : When pointers are continuous tinuously loaded into the write base counter as
H= - (E+I)
2 well as the muting.
Except at CLV-A, CLV-P, CLV-S, or CLV-A' with
the NCLV flag set to "l", the base counter is
loaded.
Previous value hold
F=G=E
CIRCUIT DESCRIPTION
Mode setting MD3 pin : Mainly for selection of the digital filter func-
The various kinds of mode can be set by combining the tion.
following pins. (Refer to the table below.) PSSL pin : Mainly for selection between serial and
MD1 pin : Mainly for selection of the oscillator clock at parallel output.
the XTAl or XTAO pin. SLOB pin : Selection between offset binary and 2's
MD2 pin : Mainly for selection of the digital out func- complement.
tion.
(Note)
8M/16M : Selection of clock, X T A L or XTAO. 8.4672MHzI PIS : Parallel outputlserial output
16.9344MHz OB/2's : Offset binary/2's cornplement
DO OFF/ON : Digital out OFFION CD ROMIAUDIO : Compatible t o CD ROM/Compatible t o audio
D F OFFION : Digital filter OFFION
1
DAO1 + C l F I : Error correction status monitor
DA02 + C l F2 : output at C l decode.
DA16 + DATA : Serial data output (MSB or LSB first
output).
1
DA03 + C2F1 : Error correction status monitor
DA04 -* C2F2 : output at C2 decode.
DA05 + C2FL : Correction status output,
C2FL = C2FI.CZF2.
CIRCUIT DESCRIPTION
5) Selection of OFFSET BINARYIS'S COMPLEMENT Counterrneasuresto defect
When the SLOB pin is "H", an offset binary signal is To counter a defect, the PDC pin is set to "Hi-Z"
output, and when it is "L", a 2's complement signal is out- during the time until GFS goes "H" again after inverting
put. from "H" to 'IL" or after approx. 0.55rns has elapsed.
6) Selection of CD ROMIAUDIO cornpatibility However, this operation is perforrned only when the HZPD
When MD1 = MD2 = MD3 = "H", the player is compa- flag of register 9 is "1 ". When HZPD = "O", it will never be
tible with a CD ROM and outputs the C2 pointer for each set to "Hi-Z".
byte. At the same tirne, the average value interpolation and The signal switching between the rough servo in the
the previous value holding operations are not perforrned. CLV-A or CLV-A' mode and the PLL servo is output from
For example, when there is an error in the upper 8 bits of the LOCK pin. After the GFS signal is sampled at WFCKI
the 16 bits, only the C2 pointer corresponding to the upper 16, and when the signal is "l", the LOCK pin goes "H",
8' bits goes "Hu, and the lower 8 bits are processed as the when a "O" is present 8 times in a row, the LOCK pin goes
correct data. "LU.
DIA Interface This operation is sirnilar to that for the FSW pin. How-
The player incorporates a DIA interface output (digital ever, while the FSW outputs a fixed signal when not in
output) and the digital signal is output frorn the DOTX pin. CLV-A' mode, the LOCK pin always output the above
The digital signal is output after passing through interpola- signa 1.
tion, mute and attenuator circuits. The 4 control bits (IDO,
ID1, COPY, EMPHASIS) in the C-bit channel status per-
form a CRC check and are revised only when it's OK.
Timing chart
-
WDCK \ / 7 /
APTR r
APTL /
*PSSL = "L"
DAOI-DAM mf
l
4-P-
I 1 Min 47211s
)i lm)mA
DAOl -DA04 ( C I F I , C l F2, C2F1, C2F2) are cleared when a period
of minimum 472 ns has elapsed since RFCK was deactivated.
ANDing signal of C2F1 and C2F2 is output out of C2FL termnal.
WFCK \
I
l I
35 period with DA09
-(bA09 is of about 4.32MHz) A
WFCK 7 1 \
WFCK
\ 1 \ \
RFCK
1
\ \ / \ \
C4LR
I I
(DA13) \
WDCK
- /
L X
(DAlO) -/
DA16*
(DATA) X Lch (MÇB) 16
1 l I
C2PO (DA06')
when compatible
with audio
C2PO corresponding to the L c h 16-bit data
K
I I
C2PO (DA06')
C2PO corresponding t o the upper C2PO corre~pondingto the lower
when compatible
with a CD-ROM 8-bits of L-ch data 8-bits of L-ch data
I l
Timing chart of C2PO output (when PSSL="L")
'RAOV becomes "H" for one frame (synchronizedwith WFCK) when a jitter that exceeds
I 4 frarnes is generated between RFCK and WFCK.
w
RAOV F c K 3 ~ [ ~ [ ~ ~
Min 47211s
Block Diagram
Vpr
GND
Ciiluniri D r c i i liv
A6
1/01
-
- 1/08 Data input/output
CE Chip enable input
A5 -
A4
WE Write enable input
-
A3 OE Outfit enable input
A2 Vcc +5v
Al
END Ground
AU
101
1 02
l 03
GND
51
CIRCUIT DESCRIPTION
Reset IC: M51951ASL (X32-1170-00: ICI 1)
Output
Operating Waveform
Power voltage
CIRCUIT DESCRIPTION
DA Converter: PCM56P-K
(X25-3050-00: I C l , lC2)
Block diagraml
Terminal connection diagram
OUT
Explanation of terminais
Terminal No. Terminal name Function Terminal No. Terminal name Function
1 -Vcc Analog negative power supply. 9 Vout Voltage output
2 DIG GND Digital ground. 1O RF Feedback resistor.
3 +VL Logic positive power supply. 11 S.J Surnrning junction (op arnp. input).
4 NC No connection. 12 ANA GND Analog ground.
5 CK Clock input. 13 lout Current output.
6 LEC Latch enable control input. 14 MSB ADJ MSB adjustment terminal.
7 DATA Data input. 15 V POT Potentiorneter terminal.
8 -V L Logic negative power supply 16 + Vcc Analog positive power supply.
1
CIRCUIT DESCRIPTION
Digital filter: SM5804D
(X25-3050-00: I C I 4)
Block diagram
CIRCUIT DESCRIPTION
Explanation of Pins
W i t h this LSI, the switching b e t w e e n the serial a n d parallel in- of t h e functions o f pins X I t o X I 6 a n d Yi to Y16 rnay b e
putsloutputs is perforrned b y the K L a n d K L pins. Some changed b y this switching.
AH the terrninals o f this unit function w i t h PlSL = H. Note: ip designates an input jack with a pull-up resistor.
- -
PlSL = H PISL = L
Pin No.
Function
Pin Name 110 Pin Name 110
-
SIMD iP Serial input mode switching.
1
X5 ip Parallel data input (Bit 5).
-
SIE0 iP B CH serial input enable.
2
X4 ip Parallel data input (Bit 4 ) .
-
SIEA [P A CH serial input enable.
3
X3 ip Parallel data input (Bit 3).
BCKl [P Serial input bit clock input.
4
X2 ip Parallel data input (Bit 2).
SID iP Serial input data
5
X1 ip Parallel data input (LSB).
6 44CI iP f-- ip 44 1 kHz sync clock input.
-
7 ABSL 1P ip -ABSL= H-44
ABSL=L-44
CI clock, HIL = A CHIE CH
CI clock, HIL = B CHIA CH.
13 XT l I
m=H-Clock input.
C m = L-X'tal oscillation input.
-
- CKSL= H-(Open).
14 XT O O
C m = L-X'tal oscillation output.
-
-
. LSBO= H-MSB-first serial output.
LSBo -
-
20 1P t-- iP LSBO = L-LSB-fis serial output.
21 (NCI (NC)
-
22 (NC) (NC)
23 (NC) i (NC)
24 (NC) (NC)
25 DGA O O A CH deglitch control output.
26 DGB O O B CH deglitch control output.
55
CIRCUIT DESCRIPTION
- - d
PlSL = H PlSL = L
Pin No. Function
Pin Narne 110 Pin Narne 110
SODB O B CH serial data output.
28 -
Y2 O Parallel output iinverted, Bit 2).
(NC) Hz (NC)
35
Vg O Parallel output iinverted, Bit 8).
(NC) Hz iNCi
36
-
Y9 O Parallel output iinverted, Bit 9).
(NC) Hz (NC)
37 -
Y 1O O Parallel output (inverted, Bit 10).
iNC) Hz (NC)
38 -
Y1 1 O Parallel output (inverted, Bit 1 1).
(NC) Hz (NC)
39
v.7 O Parallel output (inverted, Bit 12).
(NC) Hz (NC)
40
n-3 O Parallel output (inverted, Bit 13).
(NC) Hz (NC)
41
-
Y 14 O Parallel output (inverted, Bit 14).
(NC) Hz (NC)
42
-
Y15 O Parallel output iinverted, Bit 15).
(NC) Hz (NC)
43 -
Y16 O Parallel output (inverted, MSB).
44
-
POSL i~ ip
m=
- H-Serial output systern.
POSL= L-Parallel output systern.
. KjFB= H-2's cornplernent display output.
45 YOFB 1P IP
mTFB= L-Offset binary display output.
46 Voo /
,- +ve power supply pin ( 5 V).
-
-
. XOFB= H-2's cornplernent display input.
47 x m IP IP
m B = L-Offset binary display input.
48 KL iP ip
m=H-Serial input systern.
P~SL
= L- parallei input systern.
49 (NC) iNCI
56
CIRCUIT DESCRIPTION
- -
PlSL = H PlSL = L
Pin No. Function
Pin Name Il0 Pin Name 110
(NC) iP (NC)
50
XI6 ip Parallel data input (MSB).
(NC) iP INC)
51
XI5 ip Parallel data input (Bit 1 5 ) .
(NC) iP (NC)
52
XI4 ip Parallel data input (Bit 1 4 )
(NC) iP (NC)
53
XI3 ip Paraltel data input (Bit 13).
(NC) iP (NC)
54
XI2 ip Parallel data input (Bit 1 2 ) .
(NC) iP (NC)
55
XI 1 ip Parallel data input (Bit 11 ) .
(NC) iP (NC)
56
X 1O ip Parallel data input (Bit 1 0 ) .
(NC) ip (NC)
57
X9 ip Parallel data input (Bit 9)
(NCI i~ (NCI
58
X8 ip Parallel data input (Bit 8 )
(NC) iP (NC)
59
X7 ip Parallel data input (Bit 7 ) .
- LSBl=
LSBl 1P
- H- MSB-first serial input
60 LSBl = L- LSB-first serial input
-
Senal Output Timing (SOMD = L, SCSL = H, system clock = 4.2336 MHz)
CLEAR 10 ID 2D 20 3D 30 GND
CIRCUIT DESCRIPTION
Transistor array (X25-3040-00: IC3)
TD62003AP DARLINGTON DRIVER
Pin configuration
01 02 03 04 05 06 07 COMMON
COMMON
INPUT OUTPUT
I I
L - - - - - -- GND
Il 12 13 14 15 16 17 GND
Block diagram
Test disk
9 DAC OUTPUT Type 4 to the output OdB signal 1.9-2.OVrms
-
Test disk
1O DAC DISTORTION Type 4 to the output -20dB signal Minimum distortion
-
Test disk
11 DAC DISTORTION Type 4 to the output OdB signal Minimun distortion
-
loti Type 4 disk: SONY )S-18 Test Oisk or !quivalent.
REGLAGE
RECLACE 1 RECLACE 1
RECLACE DE LA 1 POINT 1
D' ENTREE DE SORTIE LECTURE ( D' ALIGNEMENT ALIGNEMENT POUR FIG
-
Court-circuiter les] Quand 1' alimentation
broches TEST et est de 0.15 à 0.4iX.
mettre sous tensio le niveau RF de
Appliquer la section pour passer dans 1.OVc-c ou plus.
dëtecteur du compteu le mode d' essai. TE (asservissement
1 PUISSANCE LASER - de puissance optique Appuyer sur ouvert) de 2.OYc-c 01 (a)
sur la lentille la touche REPEAT. plus et le reseau de
du capteur. le plateau s'ouvre diffraction aligne
et le LD emet de correctement. le cap
la lumiëre. teur est acceptable. -
1 1 VCO
1
Raccorder un
compteur de frëquence
à CNI1 (PLCK).
(X32-1110) 1
1
1' alimentation.
Mode d'arrêt
Entrer en mode de
test en mettant
Raccorder un 1' alimentation en Yerifier
r cil loscope comme suit circuit tout en que le réseau de
RESEAU DE Disque test CHI: RF court-circuitant diffraction est
4 DIFFRACTION Type 4 (X29-1810 broche test) la broche test. correctement aligné.
CH2: TE Presser la touche (Le réseau ne'peut
(X32-1110 broche 1) CHECK et s' assurer pas ëtre ajuste.)
que 1' aff ichage
Entrer en mode de
test en mettant
1 Raccorder un 1' alimentation en
>scilloscopecomme suit circuit tout en Symétrie entre les
BALANCE D' ERREUR Disque test CHI: RF court-circuitant TE BALANCE formes supërieure et
5 D' ALIGNEMENT Type 4 (X29-1810 broche test) la broche test. VR3 inférieure ou
CH2: TE Presser la touche (X29-1870) DC=Ot0,05V
(X32-1110 broche 1) CHECK et s'assurer
que l'affichage
1 est "0300'.
Raccorder un
)scilloscope comme suit. Presser la touche
BALANCE D' ERREUR Disque test CHI: RF PLAY et s'assurer FE BALANCE
6 DEMISEAUPOINT Type 4 (X29-1810 broche test) que l'affichage VR4 Forme optimum
CH2: TE est ' 0500 ' (X29-1810)
(X32-1110 broche 1)
Disque test Type 4
Appliguer un signal Utiliser un gabarit Couper CAlN DE
GAIN DE MlSE AU 900Hz. 40mYrms d' asservissement 1' alimentation et MlSE AU POINT
7 POINT â la troche 2 de ou raccorder un FPH de la redonner VRI
CN3 sur la plaquette 4'7kIi. 410pF puis presser (X29-1810)
X32-1110. la troche 1 de CN3. la touch PLAY.
Disque test Type 4
Apyliauer un signal Utiliser un gabarit
9OOHz. 40mVrms d' asservissement CAlN D' ALIGNEMENT
8 1 CAlN D'ALICNEMEN. â la troche 4 de ou raccorder un FPH de
CN3 sur la plaquette 41kQ. 410pF
PLAY VR2
(X29-1870)
1 1
1
132-1110. latroche5deCN3.
( Raccorder un voltmètre 1 Lire le signal 1
9 1 SORTIE DAC Disque test
Type 4
1 CA sur la borne de 1
sortie (FIXED).
IkHz. 0dB dans
la piste n' 2.
1
YRl: C
VR2: D
(X25-3050)
1 1.9-2.OYrms 1 (h)
Raccorder un voltmétre Lire le signal YR3: C
DISTORSrOti DAC Disque test CA sur la borne de IkHz. -20dB dans VR4: D Distortion minimum (h)
Type 4 sortie (FIXED). la piste n' 15. (125-3050)
Raccorder un voltmëtre Lire le signal YR5: C
DISTORTION DAC Disque tes1 CA sur la borne de 100Hz. OdB dans YR6: D Distortion minimum (hl
Type 4 1 sortie (FIXED). 1 la piste n. 4. 1 (X25-3050) 1
:Remarque)Disque de type :Disque test SONY YEDS-18 ou ëquivalent.
El NCANGS- AUSGANCS- 1 SPIELER- 1 ABCLEICH- 1 1
NU. GEGENSTAND El NSTELLUN El NSTELLUNGE El NSTELLUNG PUNKT ABGLEICHUNG 1 ABB
1 DieStifteTEST 1 1 lenn bei einer .1
kurzschlieBen und Spannung von 0.15 bis
die Spannungsver- 0.4 n Y der RF-Pegel
Das Sensorteil sorguns einschalten. 1.OVs-s oder mehr.
des optiscben um den Test-Modus TE (Servo-Of fen)
1 LASERLEISTUNG Leistungmeters auf zu aktivieren. Die 2,OVs-s betragt und
die Aufnehnerlinse Taste REPEAT drücken das Beugungsgitter
ansetzen. dann offnet sich richtig ausgerichtet
der Trager. und die ist. ist der Abtaster
1 LD gibt Licht aus. 1 in Ordnung. 1
1 Die Stifte TEST (
kurzschlieBen und
die Spannungsver- Stromwert + 5.5mA
BETR 1 EBSSTROM DES Ein-Cleichstrom- sorguns einschalten. auf den Lasertonab-
LASERTONABNEHYERS Amperemeter zwischen um den Test-Modus nehmer markiert.
2 (Nur wenn der CN2 Stift 6 und zu aktivieren. Die - Venn der Strom 40mA
Tonabnehmer defekt iem Muster anschlieBen. Taste REPEAT drucken. oder mehr über den
zu sein scheint) (X32-1170) dann offnet sich obigen lert liegt.
der Trager. und die ist er defekt.
LD gibt Licht aus.
Einen Frequenzzahler Die Spannungsversor-
an CNll(PLCK) gung aus-und dann L9
anschlieBen. wieder einschalten. (X32-1170)
(X32-1170) Stop-Betriebsart
Den Testst ift kurz-
schlieBen und dabei
Ein Oszilloskop die Spannungsversor- Priifen.
rie folgt anschlieBen: gung einschalten. un ob das Beugungsgitte
Testdisc Kanal 1: RF den Testmodus zu akti- richtig ausgerichtet
(X29-1870 Teststift) vieren. Die CHECK- - ist.(Das Citter
TYP 4
Kanal 2: TE Taste driicken und kann nicht
(X32-1170 Stift 1) prufen. da0 ' 0300 " eingestellt werden.)
auf dem Display
1
angezeigt wird.
1 Den Testst ift kurz- 1
schl ieBen und dabei
Ein Oszilloskop die Spannungsversor-
wie folgt anschlieBen: gung einschalten. un Symmetrie zwischen
SPURHALTEFEHLER- Testdisc Kanal 1: RF den Testnodus zu akti- TE BALANCE oberen und umteren
5 AUSCLEI CH TYP 4 (X29-1870 Teststift) vieren. Die CHECK- VR3 Mustern oder (e)
Kanal 2: TE Taste driicken und (X29-1810) Cleichstrom
(X32-1170 Stift 1) prufen. da0 ' 0300 ' DC=OfO.O5V
auf den Display
angezeigt wird.
Ein Oazilloskop
1
rie folgt anschlie0en: Die PLAY-Taste FOKUS-
FOKUS- Testdisc Kanal 1: RF driicken und prüfen. FEHLERAUSCLEICH
6 FEHLERAUSCLEICH TYP 4 (X29-1810 Teststift) da0 ' 0500 ' VR4 Optimales Ausenmuste Cf)
Kanal 2: TE auf dem Display (X29-1870)
(X32-1110 Stift 1) angezeigt wird.
Testdisc Type 4 Eine Servo-Lehre v e r Die Spannungsversor-
Ein 900Hz. 40mVrns wenden oder ein 47kQ. gung aus-und dann FOKUSVERSTARKUNC
7 (
FOKUSVERSTARKUNC Signal an Stift 2 410pF TiefpaDfilter wieder einschalten. VR1 40mVrms (9)
von CN3 an platine an Stift 1 von CN3 dann die PLAY-Taste (X29-1810)
132-1110 anlegen. anschl ieBen. drueken.
Testdisc Type 4 Eine Servo-Lehre ver-
Ein 900Hz. 40mVrms wenden oder ein 47kP. SPUHALTE-
SPURHALTE- Signal an Stift 4 470pF TiefpaBf ilter PLAY VERSTARKUNG 4OmVrms (B)
VERSTARKUNC von CN3 an platine an Stift 5 von CN3 VR2
X32-1170 anlegen. anschlieBen. (X29-1810)
Ein lechselstroai-
9 1 DAC-AUSCANC
Testdisc.
TYP 4
Voltmeter an die Aus- Das IkHz. OdB Signal
gangsklemme(F1XED)
- -
anschl ie0en.
in Titel Nr. 2
wiedergeben.
VR1: L
VR2: R
(X29-1870)
Ein Yechselstrom-
4-
Testdisc Voltmeter an die Aus- Das 1kHz. -20dB Signal VR3: L
DAC-VERZERRUNC TYP 4 gangsklemme(F1XED) in Tite1 Nr. 15 VR4: R Minimale Verzerrung (b)
anschlieBen. wiedergeben. (X29-1810)
Ein lechselstrom-
Testdisc Voltmeter an die Aus- Das 100Hz. OdB Signal VR5: L
II 1
DAC-VERZERRUNC Type 4 gangsklemme(F1XED) in Titel Nr. 4 VR6: R Minimale Verzerrung Ch)
1 anschliesen. 1
wiedergeben. 1 (X29-1870) 1 1
(Hinveis) TYP 4 Disc: SQNY YEDS-18 Testdisc oder Aquivalent.
4. Description of Signal Waveforms, Connection of Measuring Instruments/Descriptiondes formes d'onde des signaux,
connexion des instruments de mesure/Beschreibung der Signal-Wellenformen, Anschlui3 der Mefiinstrumente
CH2 T.Error
2.0VIdiv
CH2 T.Error
2.0Vldiv
+O(V)
-
Wenn der Nebenstrahl die gleiche Bitreihe wie der
Hauptstrahl wahrend der Diffraktionsgitter-Einstellung
Projection (Photo. 3) verfolgt und den RF-Triggerpunkt auf die im Foto
(2wecldiv) Projection (photo. 3) gezeigte Position bringt, wird eine "Hervorstehung"
Hervorstehung
(Foto. 3) verursacht, die in der T.Error-Wellenform beobachtet
werden kann. 63
ADJUSTMENTIREGLAGEIABGLEICH
RF signal and E.Spot signal in test mode (PLAY).
I f the diffraction grating has been adjusted properly,
the influence of triggering is observed on the E.Spot
waveform of approx. 1% after RF signal, in the form
of a projection.
Signal RF et signal E.Spot en mode de test (PLAY).
CH1 RF
1.OV/div Si le réseau de diffraction a été ajusté correctement,
l'influence du déclenchement s'observe sur la forme
d'onde E.Spot d'environ 1 2 p après le signal RF, sous
la forme d'une projection.
RF-Signal und E.Spot-Signal im Testmodus (PLAY).
Wenn das Diffraktionsgitter richtig eingestellt wurde,
CH2 E.Spot
wird der EinfluB des Triggers in der E.Spot-Wellenforrn
0.1 Vldiv etwa 1 2 p nach dem RF-Signal in der Form einer
AC coupling for Hervorstehung beobachtet.
CH2 only
Couplage CA pour canal 2 seulement
. . - nur für Kanal2
AC-Ko~oluno
(2pecldiv) L lori
pro~ect
Projection
(Photo. 4)
Hervorstehung 4,
RF signal and T.Error signal: in test mode (Focusing
ON) (Disc type 4)
Adjust T.Error so that the waveform is syrnrnetrical
above and below OV. (VR3 of X29-1780-00)
Signal RF et signal T.Error; en mode test (mise au point
ON). (Disque de type 4)
Ajuster T.Error pour que la forme d'onde soit symé-
trique en-dessus et au-dessous de OV. (VR3 de
X29-1780-00)
RF-Signal und T.Error-Signal; im Testmodus (Fokussie-
rung eingeschaltet). (Disc-Typ 4)
T.Error so einstellen, daB die Wellenform über und
unter OV syrnmetrisch ist. (VR3 von X29-1780-00)
(Foto. 7)
(9)
Oscilloscope
1 pin 5 ptn
Pickup u
Capteur Optical power meter
Abnehmer Compteur de puissance optique
Optikleistungsmesser
(f) FOCUS GAIN (g) TRACKING GAIN
f=9OOHz f=900Hz
4OrnV rms 40rnV rrns
Millivoltmeter
Millivoltmbtre
l
VOLTAGE CHECK TABLE
PC BOARD (Component Side New)
f r ,
2
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83
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Note:
We follow a policy of continuous development.
For this reason specifications may be changed without notice.
Note:
Component and circuitry are subject to modificationto insure best opera-
tion under differing local conditions. This manual is based on the Europe
(E) standard, and provides information on regional cirucuit modification
through use of alternate schematic diagrams, and informationon regional
component variations through use of parts list.
KENWOOD CORPORATION
Shionogi Shibuya Building, 17-5. 2-chome Shibuya. Shibuya-ku, Tokyo 150. Japan