###############################################################

# Generated by: Cadence Innovus 17.14-s077_1

# OS: Linux x86_64(Host ID cad15)
# Generated on: Mon Sep 7 15:07:32 2020
# Design: topdesign
# Command: report_timing -nworst 10 >
/home/fxece/Desktop/adc/pnr/dinesh/report05092020/cts/reporttiming_nworst.txt
###############################################################
Path 1: VIOLATED Setup Check with Pin pdtop_count_reg[1005]/CK
Endpoint: pdtop_count_reg[1005]/D (v) checked with leading edge of 'clk'
Beginpoint: pdtop_count_reg[88]/Q (v) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: Worst
Other End Arrival Time 0.469
- Setup 0.198
+ Phase Shift 1.000
- Uncertainty 0.100
= Required Time 1.171
- Arrival Time 2.840
= Slack Time -1.669
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.573
= Beginpoint Arrival Time 0.573

+-------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival |
Required |
| | | | | Time | Time
|
|-----------------------+-------------+------------+-------+---------
+----------|
| pdtop_count_reg[88] | CK ^ | | | 0.573 |
-1.096 |
| pdtop_count_reg[88] | CK ^ -> Q v | SDFFRHQX4 | 0.429 | 1.002 |
-0.667 |
| g184743 | B v -> Y ^ | NOR2X6 | 0.091 | 1.093 |
-0.576 |
| g182723 | A ^ -> Y ^ | CLKAND2X6 | 0.134 | 1.228 |
-0.441 |
| FE_RC_5535_0 | B ^ -> Y v | NAND3X8 | 0.113 | 1.341 |
-0.328 |
| g181957 | B v -> Y ^ | NOR2X8 | 0.089 | 1.430 |
-0.239 |
| g181580 | A ^ -> Y v | NAND2X8 | 0.078 | 1.508 |
-0.161 |
| FE_RC_496_0 | A v -> Y ^ | NOR2X8 | 0.091 | 1.599 |
-0.070 |
| g181199 | B ^ -> Y v | NAND2X8 | 0.073 | 1.672 |
0.003 |
| g181086 | A v -> Y ^ | NOR2X8 | 0.084 | 1.757 |
0.088 |
| g180971 | B ^ -> Y v | NAND2X8 | 0.104 | 1.861 |
0.192 |
| g180730 | A v -> Y ^ | NOR2X8 | 0.101 | 1.962 |
0.293 |
| g180703 | A ^ -> Y ^ | CLKAND2X6 | 0.135 | 2.097 |
0.428 |
| g180315_dup1 | B ^ -> Y ^ | CLKAND2X12 | 0.154 | 2.252 |
0.582 |
 | g180137 | B ^ -> Y ^ | CLKAND2X12 | 0.200 | 2.451 |
0.782 |
| FE_OCPC15582_n_5457 | A ^ -> Y ^ | CLKBUFX2 | 0.181 | 2.632 |
0.963 |
| FE_RC_5251_0 | A1 ^ -> Y v | AOI22X4 | 0.095 | 2.727 |
1.058 |
| FE_RC_931_0 | B v -> Y ^ | NOR2BX2 | 0.068 | 2.795 |
1.126 |
| FE_RC_930_0 | B0 ^ -> Y v | AOI21X1 | 0.045 | 2.840 |
1.171 |
| pdtop_count_reg[1005] | D v | SDFFRX2 | 0.000 | 2.840 |
1.171 |

+-------------------------------------------------------------------------------+
Path 2: VIOLATED Setup Check with Pin pdtop_count_reg[1005]/CK
Endpoint: pdtop_count_reg[1005]/D (v) checked with leading edge of 'clk'
Beginpoint: pdtop_count_reg[88]/Q (v) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: Worst
Other End Arrival Time 0.469
- Setup 0.198
+ Phase Shift 1.000
- Uncertainty 0.100
= Required Time 1.171
- Arrival Time 2.840
= Slack Time -1.669
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.573
= Beginpoint Arrival Time 0.573

+-------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival |
Required |
| | | | | Time | Time
|
|-----------------------+-------------+------------+-------+---------
+----------|
| pdtop_count_reg[88] | CK ^ | | | 0.573 |
-1.096 |
| pdtop_count_reg[88] | CK ^ -> Q v | SDFFRHQX4 | 0.429 | 1.002 |
-0.667 |
| g184743 | B v -> Y ^ | NOR2X6 | 0.091 | 1.093 |
-0.576 |
| g182723 | A ^ -> Y ^ | CLKAND2X6 | 0.134 | 1.228 |
-0.441 |
| FE_RC_5535_0 | B ^ -> Y v | NAND3X8 | 0.113 | 1.341 |
-0.328 |
| g181957 | B v -> Y ^ | NOR2X8 | 0.089 | 1.430 |
-0.239 |
| g181580 | A ^ -> Y v | NAND2X8 | 0.078 | 1.508 |
-0.161 |
| FE_RC_496_0 | A v -> Y ^ | NOR2X8 | 0.091 | 1.599 |
-0.070 |
| g181199 | B ^ -> Y v | NAND2X8 | 0.073 | 1.672 |
0.003 |
| g181086 | A v -> Y ^ | NOR2X8 | 0.084 | 1.757 |
0.088 |
| g180971 | B ^ -> Y v | NAND2X8 | 0.104 | 1.861 |
0.192 |
 | g180730 | A v -> Y ^ | NOR2X8 | 0.101 | 1.962 |
0.293 |
| g180703 | A ^ -> Y ^ | CLKAND2X6 | 0.135 | 2.097 |
0.428 |
| g180315_dup1 | B ^ -> Y ^ | CLKAND2X12 | 0.154 | 2.252 |
0.583 |
| g180137 | B ^ -> Y ^ | CLKAND2X12 | 0.200 | 2.451 |
0.782 |
| FE_OCPC15582_n_5457 | A ^ -> Y ^ | CLKBUFX2 | 0.181 | 2.632 |
0.963 |
| FE_RC_5251_0 | A1 ^ -> Y v | AOI22X4 | 0.095 | 2.727 |
1.058 |
| FE_RC_931_0 | B v -> Y ^ | NOR2BX2 | 0.068 | 2.795 |
1.126 |
| FE_RC_930_0 | B0 ^ -> Y v | AOI21X1 | 0.045 | 2.840 |
1.171 |
| pdtop_count_reg[1005] | D v | SDFFRX2 | 0.000 | 2.840 |
1.171 |

+-------------------------------------------------------------------------------+
Path 3: VIOLATED Setup Check with Pin pdtop_count_reg[1005]/CK
Endpoint: pdtop_count_reg[1005]/D (v) checked with leading edge of 'clk'
Beginpoint: pdtop_count_reg[88]/Q (v) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: Worst
Other End Arrival Time 0.469
- Setup 0.198
+ Phase Shift 1.000
- Uncertainty 0.100
= Required Time 1.171
- Arrival Time 2.840
= Slack Time -1.669
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.573
= Beginpoint Arrival Time 0.573

+-------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival |
Required |
| | | | | Time | Time
|
|-----------------------+-------------+------------+-------+---------
+----------|
| pdtop_count_reg[88] | CK ^ | | | 0.573 |
-1.096 |
| pdtop_count_reg[88] | CK ^ -> Q v | SDFFRHQX4 | 0.429 | 1.002 |
-0.667 |
| g184743 | B v -> Y ^ | NOR2X6 | 0.091 | 1.093 |
-0.576 |
| g182723 | A ^ -> Y ^ | CLKAND2X6 | 0.134 | 1.228 |
-0.441 |
| FE_RC_5535_0 | B ^ -> Y v | NAND3X8 | 0.113 | 1.341 |
-0.328 |
| g181957 | B v -> Y ^ | NOR2X8 | 0.089 | 1.430 |
-0.239 |
| g181580 | A ^ -> Y v | NAND2X8 | 0.078 | 1.508 |
-0.161 |
| FE_RC_496_0 | A v -> Y ^ | NOR2X8 | 0.091 | 1.599 |
-0.070 |
 | g181199 | B ^ -> Y v | NAND2X8 | 0.073 | 1.672 |
0.003 |
| g181086 | A v -> Y ^ | NOR2X8 | 0.084 | 1.757 |
0.088 |
| g180971 | B ^ -> Y v | NAND2X8 | 0.104 | 1.861 |
0.192 |
| g180730 | A v -> Y ^ | NOR2X8 | 0.101 | 1.962 |
0.293 |
| g180703 | A ^ -> Y ^ | CLKAND2X6 | 0.135 | 2.097 |
0.428 |
| g180315_dup1 | B ^ -> Y ^ | CLKAND2X12 | 0.154 | 2.252 |
0.583 |
| g180137 | B ^ -> Y ^ | CLKAND2X12 | 0.200 | 2.451 |
0.782 |
| FE_OCPC15582_n_5457 | A ^ -> Y ^ | CLKBUFX2 | 0.181 | 2.632 |
0.963 |
| FE_RC_5251_0 | A1 ^ -> Y v | AOI22X4 | 0.095 | 2.727 |
1.058 |
| FE_RC_931_0 | B v -> Y ^ | NOR2BX2 | 0.068 | 2.795 |
1.126 |
| FE_RC_930_0 | B0 ^ -> Y v | AOI21X1 | 0.045 | 2.840 |
1.171 |
| pdtop_count_reg[1005] | D v | SDFFRX2 | 0.000 | 2.840 |
1.171 |

+-------------------------------------------------------------------------------+
Path 4: VIOLATED Setup Check with Pin pdtop_count_reg[1005]/CK
Endpoint: pdtop_count_reg[1005]/D (v) checked with leading edge of 'clk'
Beginpoint: pdtop_count_reg[88]/Q (v) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: Worst
Other End Arrival Time 0.469
- Setup 0.198
+ Phase Shift 1.000
- Uncertainty 0.100
= Required Time 1.171
- Arrival Time 2.840
= Slack Time -1.669
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.573
= Beginpoint Arrival Time 0.573

+-------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival |
Required |
| | | | | Time | Time
|
|-----------------------+-------------+------------+-------+---------
+----------|
| pdtop_count_reg[88] | CK ^ | | | 0.573 |
-1.095 |
| pdtop_count_reg[88] | CK ^ -> Q v | SDFFRHQX4 | 0.429 | 1.002 |
-0.667 |
| g184743 | B v -> Y ^ | NOR2X6 | 0.091 | 1.093 |
-0.575 |
| g182723 | A ^ -> Y ^ | CLKAND2X6 | 0.134 | 1.228 |
-0.441 |
| FE_RC_5535_0 | B ^ -> Y v | NAND3X8 | 0.113 | 1.341 |
-0.328 |
 | g181957 | B v -> Y ^ | NOR2X8 | 0.089 | 1.430 |
-0.239 |
| g181580 | A ^ -> Y v | NAND2X8 | 0.078 | 1.508 |
-0.161 |
| FE_RC_496_0 | A v -> Y ^ | NOR2X8 | 0.091 | 1.599 |
-0.070 |
| g181199 | B ^ -> Y v | NAND2X8 | 0.073 | 1.672 |
0.004 |
| g181086 | A v -> Y ^ | NOR2X8 | 0.084 | 1.757 |
0.088 |
| g180971 | B ^ -> Y v | NAND2X8 | 0.104 | 1.861 |
0.192 |
| g180730 | A v -> Y ^ | NOR2X8 | 0.101 | 1.962 |
0.293 |
| g180703 | A ^ -> Y ^ | CLKAND2X6 | 0.135 | 2.097 |
0.429 |
| g180315_dup1 | B ^ -> Y ^ | CLKAND2X12 | 0.154 | 2.252 |
0.583 |
| g180137 | B ^ -> Y ^ | CLKAND2X12 | 0.200 | 2.451 |
0.782 |
| FE_OCPC15582_n_5457 | A ^ -> Y ^ | CLKBUFX2 | 0.181 | 2.632 |
0.963 |
| FE_RC_5251_0 | A1 ^ -> Y v | AOI22X4 | 0.095 | 2.727 |
1.058 |
| FE_RC_931_0 | B v -> Y ^ | NOR2BX2 | 0.068 | 2.795 |
1.126 |
| FE_RC_930_0 | B0 ^ -> Y v | AOI21X1 | 0.045 | 2.840 |
1.171 |
| pdtop_count_reg[1005] | D v | SDFFRX2 | 0.000 | 2.840 |
1.171 |

+-------------------------------------------------------------------------------+
Path 5: VIOLATED Setup Check with Pin pdtop_count_reg[427]/CK
Endpoint: pdtop_count_reg[427]/D (^) checked with leading edge of 'clk'
Beginpoint: pdtop_count_reg[87]/Q (^) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: Worst
Other End Arrival Time 0.472
- Setup 0.223
+ Phase Shift 1.000
- Uncertainty 0.100
= Required Time 1.149
- Arrival Time 2.807
= Slack Time -1.658
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.574
= Beginpoint Arrival Time 0.574

+------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival | Required
|
| | | | | Time | Time
|
|----------------------+-------------+------------+-------+---------
+----------|
| pdtop_count_reg[87] | CK ^ | | | 0.574 | -1.084
|
| pdtop_count_reg[87] | CK ^ -> Q ^ | SDFFRHQX4 | 0.431 | 1.005 | -0.653
|
 | g184668 | A ^ -> Y ^ | CLKAND2X6 | 0.136 | 1.141 | -0.517
|
| FE_RC_5888_0 | A ^ -> Y v | NAND3X8 | 0.108 | 1.249 | -0.409
|
| FE_RC_3133_0 | B v -> Y ^ | NOR2X8 | 0.090 | 1.339 | -0.320
|
| FE_RC_3132_0 | B ^ -> Y v | NAND2X8 | 0.097 | 1.435 | -0.223
|
| FE_RC_2862_0 | A v -> Y ^ | NOR3X8 | 0.118 | 1.553 | -0.105
|
| g181234 | A ^ -> Y ^ | CLKAND2X12 | 0.142 | 1.695 | 0.037
|
| FE_RC_1497_0 | B ^ -> Y v | NAND2X6 | 0.073 | 1.769 | 0.111
|
| FE_RC_1496_0 | B v -> Y ^ | NOR2X8 | 0.103 | 1.872 | 0.213
|
| g180861 | A ^ -> Y ^ | CLKAND2X12 | 0.175 | 2.046 | 0.388
|
| g180574 | B ^ -> Y ^ | CLKAND2X12 | 0.162 | 2.208 | 0.550
|
| FE_OCPC15316_n_5078 | A ^ -> Y ^ | CLKBUFX6 | 0.105 | 2.314 | 0.655
|
| FE_RC_1971_0 | A ^ -> Y v | CLKINVX4 | 0.041 | 2.355 | 0.697
|
| FE_RC_1970_0 | B v -> Y ^ | NOR2X6 | 0.072 | 2.427 | 0.769
|
| g179857_dup | B ^ -> Y ^ | CLKAND2X6 | 0.122 | 2.550 | 0.891
|
| FE_RC_451_0 | A ^ -> Y v | CLKINVX3 | 0.046 | 2.596 | 0.938
|
| g179009 | B v -> Y ^ | NOR2X4 | 0.056 | 2.652 | 0.993
|
| FE_RC_1252_0 | B0 ^ -> Y v | AOI21X2 | 0.044 | 2.695 | 1.037
|
| g176513__5019 | S0 v -> Y ^ | MXI2X1 | 0.111 | 2.807 | 1.148
|
| pdtop_count_reg[427] | D ^ | SDFFRHQX4 | 0.000 | 2.807 | 1.149
|

+------------------------------------------------------------------------------+
Path 6: VIOLATED Setup Check with Pin pdtop_count_reg[427]/CK
Endpoint: pdtop_count_reg[427]/D (^) checked with leading edge of 'clk'
Beginpoint: pdtop_count_reg[87]/Q (^) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: Worst
Other End Arrival Time 0.472
- Setup 0.223
+ Phase Shift 1.000
- Uncertainty 0.100
= Required Time 1.149
- Arrival Time 2.806
= Slack Time -1.658
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.574
= Beginpoint Arrival Time 0.574

+------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival | Required
|
 | | | | | Time | Time
|
|----------------------+-------------+------------+-------+---------
+----------|
| pdtop_count_reg[87] | CK ^ | | | 0.574 | -1.084
|
| pdtop_count_reg[87] | CK ^ -> Q ^ | SDFFRHQX4 | 0.431 | 1.005 | -0.653
|
| g184668 | A ^ -> Y ^ | CLKAND2X6 | 0.136 | 1.141 | -0.517
|
| FE_RC_5888_0 | A ^ -> Y v | NAND3X8 | 0.108 | 1.249 | -0.409
|
| FE_RC_3133_0 | B v -> Y ^ | NOR2X8 | 0.090 | 1.339 | -0.319
|
| FE_RC_3132_0 | B ^ -> Y v | NAND2X8 | 0.097 | 1.435 | -0.223
|
| FE_RC_2862_0 | A v -> Y ^ | NOR3X8 | 0.118 | 1.553 | -0.105
|
| g181234 | A ^ -> Y ^ | CLKAND2X12 | 0.142 | 1.695 | 0.037
|
| FE_RC_1497_0 | B ^ -> Y v | NAND2X6 | 0.073 | 1.769 | 0.111
|
| FE_RC_1496_0 | B v -> Y ^ | NOR2X8 | 0.103 | 1.872 | 0.214
|
| g180861 | A ^ -> Y ^ | CLKAND2X12 | 0.175 | 2.046 | 0.388
|
| g180574 | B ^ -> Y ^ | CLKAND2X12 | 0.162 | 2.208 | 0.550
|
| FE_OCPC15316_n_5078 | A ^ -> Y ^ | CLKBUFX6 | 0.105 | 2.314 | 0.656
|
| FE_RC_1971_0 | A ^ -> Y v | CLKINVX4 | 0.041 | 2.355 | 0.697
|
| FE_RC_1970_0 | B v -> Y ^ | NOR2X6 | 0.072 | 2.427 | 0.769
|
| g179857_dup | B ^ -> Y ^ | CLKAND2X6 | 0.122 | 2.550 | 0.892
|
| FE_RC_451_0 | A ^ -> Y v | CLKINVX3 | 0.046 | 2.596 | 0.938
|
| g179009 | B v -> Y ^ | NOR2X4 | 0.056 | 2.652 | 0.994
|
| FE_RC_1252_0 | B0 ^ -> Y v | AOI21X2 | 0.043 | 2.695 | 1.037
|
| g176513__5019 | S0 v -> Y ^ | MXI2X1 | 0.111 | 2.806 | 1.148
|
| pdtop_count_reg[427] | D ^ | SDFFRHQX4 | 0.000 | 2.806 | 1.149
|

+------------------------------------------------------------------------------+
Path 7: VIOLATED Setup Check with Pin pdtop_count_reg[1005]/CK
Endpoint: pdtop_count_reg[1005]/D (v) checked with leading edge of 'clk'
Beginpoint: pdtop_count_reg[134]/Q (v) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: Worst
Other End Arrival Time 0.469
- Setup 0.198
+ Phase Shift 1.000
- Uncertainty 0.100
= Required Time 1.171
- Arrival Time 2.825
= Slack Time -1.654
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.572
= Beginpoint Arrival Time 0.572

+-------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival |
Required |
| | | | | Time | Time
|
|-----------------------+-------------+------------+-------+---------
+----------|
| pdtop_count_reg[134] | CK ^ | | | 0.572 |
-1.082 |
| pdtop_count_reg[134] | CK ^ -> Q v | SDFFRX4 | 0.408 | 0.981 |
-0.673 |
| g184374 | B v -> Y ^ | NOR2X4 | 0.097 | 1.078 |
-0.576 |
| g183130 | A ^ -> Y v | NAND2X6 | 0.084 | 1.162 |
-0.492 |
| g182587 | A v -> Y ^ | NOR2X8 | 0.091 | 1.252 |
-0.402 |
| g181919 | A ^ -> Y v | NAND2X8 | 0.074 | 1.327 |
-0.327 |
| FE_OCPC15338_n_3968 | A v -> Y v | CLKBUFX6 | 0.121 | 1.447 |
-0.207 |
| FE_RC_671_0 | B v -> Y ^ | NOR3X8 | 0.124 | 1.571 |
-0.083 |
| FE_RC_670_0 | A ^ -> Y v | NAND2X6 | 0.090 | 1.661 |
0.007 |
| g181086 | B v -> Y ^ | NOR2X8 | 0.081 | 1.742 |
0.088 |
| g180971 | B ^ -> Y v | NAND2X8 | 0.104 | 1.846 |
0.192 |
| g180730 | A v -> Y ^ | NOR2X8 | 0.101 | 1.947 |
0.293 |
| g180703 | A ^ -> Y ^ | CLKAND2X6 | 0.135 | 2.082 |
0.428 |
| g180315_dup1 | B ^ -> Y ^ | CLKAND2X12 | 0.154 | 2.236 |
0.582 |
| g180137 | B ^ -> Y ^ | CLKAND2X12 | 0.200 | 2.436 |
0.782 |
| FE_OCPC15582_n_5457 | A ^ -> Y ^ | CLKBUFX2 | 0.181 | 2.617 |
0.963 |
| FE_RC_5251_0 | A1 ^ -> Y v | AOI22X4 | 0.095 | 2.712 |
1.058 |
| FE_RC_931_0 | B v -> Y ^ | NOR2BX2 | 0.068 | 2.780 |
1.126 |
| FE_RC_930_0 | B0 ^ -> Y v | AOI21X1 | 0.045 | 2.825 |
1.171 |
| pdtop_count_reg[1005] | D v | SDFFRX2 | 0.000 | 2.825 |
1.171 |

+-------------------------------------------------------------------------------+
Path 8: VIOLATED Setup Check with Pin pdtop_count_reg[1005]/CK
Endpoint: pdtop_count_reg[1005]/D (v) checked with leading edge of 'clk'
Beginpoint: pdtop_count_reg[134]/Q (v) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: Worst
Other End Arrival Time 0.469
- Setup 0.198
+ Phase Shift 1.000
- Uncertainty 0.100
= Required Time 1.171
- Arrival Time 2.825
= Slack Time -1.654
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.572
= Beginpoint Arrival Time 0.572

+-------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival |
Required |
| | | | | Time | Time
|
|-----------------------+-------------+------------+-------+---------
+----------|
| pdtop_count_reg[134] | CK ^ | | | 0.572 |
-1.082 |
| pdtop_count_reg[134] | CK ^ -> Q v | SDFFRX4 | 0.408 | 0.981 |
-0.673 |
| g184374 | B v -> Y ^ | NOR2X4 | 0.097 | 1.078 |
-0.576 |
| g183130 | A ^ -> Y v | NAND2X6 | 0.084 | 1.162 |
-0.492 |
| g182587 | A v -> Y ^ | NOR2X8 | 0.091 | 1.252 |
-0.401 |
| g181919 | A ^ -> Y v | NAND2X8 | 0.074 | 1.327 |
-0.327 |
| FE_OCPC15338_n_3968 | A v -> Y v | CLKBUFX6 | 0.121 | 1.447 |
-0.206 |
| FE_RC_671_0 | B v -> Y ^ | NOR3X8 | 0.124 | 1.571 |
-0.083 |
| FE_RC_670_0 | A ^ -> Y v | NAND2X6 | 0.090 | 1.661 |
0.007 |
| g181086 | B v -> Y ^ | NOR2X8 | 0.081 | 1.742 |
0.088 |
| g180971 | B ^ -> Y v | NAND2X8 | 0.104 | 1.846 |
0.192 |
| g180730 | A v -> Y ^ | NOR2X8 | 0.101 | 1.947 |
0.293 |
| g180703 | A ^ -> Y ^ | CLKAND2X6 | 0.135 | 2.082 |
0.428 |
| g180315_dup1 | B ^ -> Y ^ | CLKAND2X12 | 0.154 | 2.236 |
0.583 |
| g180137 | B ^ -> Y ^ | CLKAND2X12 | 0.200 | 2.436 |
0.782 |
| FE_OCPC15582_n_5457 | A ^ -> Y ^ | CLKBUFX2 | 0.181 | 2.617 |
0.963 |
| FE_RC_5251_0 | A1 ^ -> Y v | AOI22X4 | 0.095 | 2.711 |
1.058 |
| FE_RC_931_0 | B v -> Y ^ | NOR2BX2 | 0.068 | 2.780 |
1.126 |
| FE_RC_930_0 | B0 ^ -> Y v | AOI21X1 | 0.045 | 2.825 |
1.171 |
| pdtop_count_reg[1005] | D v | SDFFRX2 | 0.000 | 2.825 |
1.171 |
+-------------------------------------------------------------------------------+
Path 9: VIOLATED Setup Check with Pin pdtop_count_reg[1005]/CK
Endpoint: pdtop_count_reg[1005]/D (v) checked with leading edge of 'clk'
Beginpoint: pdtop_count_reg[134]/Q (v) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: Worst
Other End Arrival Time 0.469
- Setup 0.198
+ Phase Shift 1.000
- Uncertainty 0.100
= Required Time 1.171
- Arrival Time 2.825
= Slack Time -1.654
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.572
= Beginpoint Arrival Time 0.572

+-------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival |
Required |
| | | | | Time | Time
|
|-----------------------+-------------+------------+-------+---------
+----------|
| pdtop_count_reg[134] | CK ^ | | | 0.572 |
-1.082 |
| pdtop_count_reg[134] | CK ^ -> Q v | SDFFRX4 | 0.408 | 0.981 |
-0.673 |
| g184374 | B v -> Y ^ | NOR2X4 | 0.097 | 1.078 |
-0.576 |
| g183130 | A ^ -> Y v | NAND2X6 | 0.084 | 1.162 |
-0.492 |
| g182587 | A v -> Y ^ | NOR2X8 | 0.091 | 1.252 |
-0.401 |
| g181919 | A ^ -> Y v | NAND2X8 | 0.074 | 1.327 |
-0.327 |
| FE_OCPC15338_n_3968 | A v -> Y v | CLKBUFX6 | 0.121 | 1.447 |
-0.206 |
| FE_RC_671_0 | B v -> Y ^ | NOR3X8 | 0.124 | 1.571 |
-0.083 |
| FE_RC_670_0 | A ^ -> Y v | NAND2X6 | 0.090 | 1.661 |
0.007 |
| g181086 | B v -> Y ^ | NOR2X8 | 0.081 | 1.742 |
0.088 |
| g180971 | B ^ -> Y v | NAND2X8 | 0.104 | 1.846 |
0.192 |
| g180730 | A v -> Y ^ | NOR2X8 | 0.101 | 1.947 |
0.293 |
| g180703 | A ^ -> Y ^ | CLKAND2X6 | 0.135 | 2.082 |
0.428 |
| g180315_dup1 | B ^ -> Y ^ | CLKAND2X12 | 0.154 | 2.236 |
0.583 |
| g180137 | B ^ -> Y ^ | CLKAND2X12 | 0.200 | 2.436 |
0.782 |
| FE_OCPC15582_n_5457 | A ^ -> Y ^ | CLKBUFX2 | 0.181 | 2.617 |
0.963 |
| FE_RC_5251_0 | A1 ^ -> Y v | AOI22X4 | 0.095 | 2.712 |
1.058 |
| FE_RC_931_0 | B v -> Y ^ | NOR2BX2 | 0.068 | 2.780 |
1.126 |
| FE_RC_930_0 | B0 ^ -> Y v | AOI21X1 | 0.045 | 2.825 |
1.171 |
| pdtop_count_reg[1005] | D v | SDFFRX2 | 0.000 | 2.825 |
1.171 |

+-------------------------------------------------------------------------------+
Path 10: VIOLATED Setup Check with Pin pdtop_count_reg[1005]/CK
Endpoint: pdtop_count_reg[1005]/D (^) checked with leading edge of 'clk'
Beginpoint: pdtop_count_reg[88]/Q (v) triggered by leading edge of 'clk'
Path Groups: {clk}
Analysis View: Worst
Other End Arrival Time 0.469
- Setup 0.198
+ Phase Shift 1.000
- Uncertainty 0.100
= Required Time 1.171
- Arrival Time 2.825
= Slack Time -1.654
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.573
= Beginpoint Arrival Time 0.573

+-------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival |
Required |
| | | | | Time | Time
|
|-----------------------+-------------+------------+-------+---------
+----------|
| pdtop_count_reg[88] | CK ^ | | | 0.573 |
-1.080 |
| pdtop_count_reg[88] | CK ^ -> Q v | SDFFRHQX4 | 0.429 | 1.002 |
-0.652 |
| g184743 | B v -> Y ^ | NOR2X6 | 0.091 | 1.093 |
-0.560 |
| g182723 | A ^ -> Y ^ | CLKAND2X6 | 0.134 | 1.228 |
-0.426 |
| FE_RC_5535_0 | B ^ -> Y v | NAND3X8 | 0.113 | 1.341 |
-0.313 |
| g181957 | B v -> Y ^ | NOR2X8 | 0.089 | 1.430 |
-0.224 |
| g181580 | A ^ -> Y v | NAND2X8 | 0.078 | 1.508 |
-0.146 |
| FE_RC_496_0 | A v -> Y ^ | NOR2X8 | 0.091 | 1.599 |
-0.055 |
| g181199 | B ^ -> Y v | NAND2X8 | 0.073 | 1.672 |
0.019 |
| g181086 | A v -> Y ^ | NOR2X8 | 0.084 | 1.757 |
0.103 |
| g180971 | B ^ -> Y v | NAND2X8 | 0.104 | 1.861 |
0.207 |
| g180730 | A v -> Y ^ | NOR2X8 | 0.101 | 1.962 |
0.308 |
| g180703 | A ^ -> Y ^ | CLKAND2X6 | 0.135 | 2.097 |
0.444 |
| g180315_dup1 | B ^ -> Y ^ | CLKAND2X12 | 0.154 | 2.252 |
0.598 |
| g180137 | B ^ -> Y ^ | CLKAND2X12 | 0.200 | 2.451 |
0.797 |
| FE_OCPC15582_n_5457 | A ^ -> Y ^ | CLKBUFX2 | 0.181 | 2.632 |
0.978 |
| FE_RC_5251_0 | A1 ^ -> Y v | AOI22X4 | 0.095 | 2.727 |
1.073 |
| FE_RC_930_0 | A1 v -> Y ^ | AOI21X1 | 0.098 | 2.825 |
1.171 |
| pdtop_count_reg[1005] | D ^ | SDFFRX2 | 0.000 | 2.825 |
1.171 |

+-------------------------------------------------------------------------------+