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ARM920T
System-on-Chip Platform OS Processor
Product Overview
DVI 0024A © Copyright ARM Limited 2000. All rights reserved. Page 1
ARM Confidential - Draft
ARM920T
ARM920T Macrocell
The ARM920T macrocell is based on External IPA[31:0]
Instruction Instruction
coprocessor
the ARM9TDMI Harvard architecture cache MMU
interface
processor core, with an efficient five
IMVA[31:0]
stage pipeline. The architecture of
the processor core or integer unit is
R13
described in more detail page 9. ID[31:0]
IVA[31:0]
To reduce the effect of main memory
bandwidth and latency on Trace ARM9TDMI AMBA ASB
performance, the ARM920T interface Processor core CP15 bus
port (Integral EmbeddedICE) interface
includes:
• instruction cache DVA[31:0] DD[31:0] Write
• data cache buffer
• MMU R13
DMVA[31:0] DPA[31:0]
• TLBs
• write buffer JTAG
Data Data Write back
• physical address TAG RAM cache MMU PATAG RAM WBPA[31:0]
Caches DINDEX[5:0]
Page 2 © Copyright ARM Limited 2000. All rights reserved. DVI 0024A
ARM Confidential - Draft
ARM920T
System controller
The system controller oversees the
interaction between the instruction
and data Cache and the Bus
Interface Unit. It controls internal
arbitration between the blocks and
stalls appropriate blocks when
required. The system controller
arbitrates between instruction and
data access to schedule single or
simultaneous requests to the MMUs
and the Bus Interface Unit. The
system controller receives
acknowledgement from each
resource to allow execution to
continue.
DVI 0024A © Copyright ARM Limited 2000. All rights reserved. Page3
ARM Confidential - Draft
The ARMv4T Architecture
Registers Current Program Status Register Four classes of
(CPSR). The CPSR holds:
The ARM9TDMI processor core instructions
consists of a 32-bit datapath and • four ALU flags (Negative, Zero, The ARM and Thumb instruction sets
associated control logic. That Carry, and Overflow), can be divided into four broad
datapath contains 31 general- classes of instruction:
• two interrupt disable bits (one for
purpose registers, coupled to a full
each type of interrupt),
shifter, Arithmetic Logic Unit, and • data processing instructions
multiplier. At any one time 16 • a bit to indicate ARM or Thumb
registers are visible to the user. The execution, • load and store instructions
remainder are synonyms used to • and five bits to encode the • branch instructions
speed up exception processing. current processor mode. • coprocessor instructions.
Register 15 is the Program Counter
All five exception modes also have a
(PC) and can be used in all Data processing
Saved Program Status Register
instructions to reference data relative
(SPSR) which holds the CPSR of the The data processing instructions
to the current instruction. R14 holds
task immediately before the operate on data held in general
the return address after a subroutine
exception occurred. purpose registers. Of the two source
call. R13 is used (by software
convention) as a stack pointer. operands, one is always a register.
Exception types The other has two basic forms:
Page 4 © Copyright ARM Limited 2000. All rights reserved. DVI 0024A
ARM Confidential - Draft
The ARMv4T Architecture
Load and store single register subroutine return address and the
instructions can transfer a 32-bit PC values are in general-purpose
word, a 16-bit halfword and an 8-bit registers, very efficient subroutine
byte between memory and a register. calls can be constructed.
Byte and halfword loads might be
automatically zero extended or sign Branch
extended as they are loaded. Swap
instructions perform an atomic load As well as allowing any data
and store as a synchronization processing or load instruction to
primitive. change control flow (by writing the
PC) a standard branch instruction is
Addressing modes provided with 24-bit signed offset,
allowing forward and backward
Load and store instructions have
branches of up to 32MB.
three primary addressing modes:
DVI 0024A © Copyright ARM Limited 2000. All rights reserved. Page 5
ARM Confidential - Draft
The ARMv4T Architecture
Page 6 © Copyright ARM Limited 2000. All rights reserved. DVI 0024A
ARM Confidential - Draft
The ARMv4T Architecture
DVI 0024A © Copyright ARM Limited 2000. All rights reserved. Page 7
ARM Confidential - Draft
The ARMv4T Architecture
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7
R8 R8 R8 R8 R8 R8_FIQ
R9 R9 R9 R9 R9 R9_FIQ
PC PC PC PC PC PC
Page 8 © Copyright ARM Limited 2000. All rights reserved. DVI 0024A
ARM Confidential - Draft
ARM920T
ARM9TDMI processor • 32-bit ARM instruction set ARM9TDMI integer
core • 16-bit Thumb instruction set. pipeline stages
The ARM instruction set allows a
The ARM9TDMI processor core The integer pipeline consists of five
program to achieve maximum
implements the ARMv4T Instruction stages to maximize instruction
performance with the minimum
Set Architecture (ISA). The ARMv4T throughput on ARM9TDMI:
number of instructions.
ISA is a superset of the ARMv4 ISA
(implemented by the StrongARM® F: Fetch
The majority of ARM9TDMI
processor) with additional support for
instructions are executed in a single
Thumb instruction set (16-bit D: Decode and register read
cycle. These are shown in the
compressed ARM instruction set).
ARM9TDMI instruction execution
The ARMv4T ISA is implemented by E: Execute shift and alu, or
timing table on page 10.
the ARM7™ Thumb family; giving full address calculate, or
upward compatibility to the ARM9™ multiply
The simpler Thumb instruction set
Thumb family.
offers much increased code density
M: Memory access and multiply
increasing space optimization. Code
Performance and code can switch between the ARM and
W: Write register
density Thumb instruction sets on any
procedure call.
ARM9TDMI executes two instruction
sets:
Write Port D
Read Port B
Immediate
Multiplier
Instruction
Decode
Instruction Write Port L2
Queue
Read Port S1
Write Port L1
Read Port S2
DVI 0024A © Copyright ARM Limited 2000. All rights reserved. Page 9
ARM Confidential - Draft
ARM920T
Pipelining Table 1: ARM9TDMI instruction execution timing
By overlapping the various stages of
execution, ARM9TDMI maximizes Instruction class Issue cycles Result delay
the clock rate achievable to execute
each instruction. It delivers a Condition failed 1 NA
throughput approaching one
ALU instruction 1 0
instruction per cycle.
ALU instruction with register shift 2 0
32-bit data buses MOV PC, Rx 3 NA
ARM9TDMI provides 32-bit data
buses: ALU instruction dest = PC 4 0
MUL 1..7 1..7
• between the processor core and
the instruction and data caches MSR (flags only) 1 0
Page 10 © Copyright ARM Limited 2000. All rights reserved. DVI 0024A
ARM Confidential - Draft
System Issues and Third Party Support
JTAG debug The ARM Architecture today enjoys • 20+ Real Time Operating
broad third party support. The Systems including:
The internal state of the ARM920T ARM9 Thumb Family processors - Windriver VxWorks
is examined through a JTAG-style strong software compatibility with
serial interface, which allows - Sun Microsystems Chorus
existing ARM families ensures that
instructions to be serially inserted its users benefit immediately from - JavaOS
into the pipeline of the core without existing support. ARM is working - Microtec VRTX
using the external data bus. with its software, EDA, and - JMI
Therefore, when in debug state, a semiconductor partners to extend - Embedded System Products
store-multiple (STM) can be this support to use new ARM9 RTXC
inserted into the instruction pipeline. Family features. - Integrated Systems pSOS.
This exports the contents of the
• Major OS including:
ARM9TDMI registers. This data can
be serially shifted out without
Current support - Microsoft WindowsCE
affecting the rest of the system. Support for the ARM Architecture - PSION EPOC
today includes: - NetBSD
AMBA bus architecture - Linux UNIX
• ARM Developer Suite (ADS) - Geoworks
The ARM9 Thumb Family
- Integrated development • Application software
processors are designed for use environment
with the AMBA multi-master on-chip components:
- C, C++, assembler, simulators
bus architecture. AMBA includes an and windowing source-level - speech and image
Advanced System Bus (ASB) debugger compression
connecting processors and high- - Available on Windows95, - software modem
bandwidth peripherals and memory WindowsNT, and Unix. - Chinese character input
interfaces, and a low-power - ARM Multi-ICE™ JTAG network protocols
peripheral bus allowing a large interface - Digital AC3 decode
number of low-bandwidth - Allows EmbeddedICE - MPEG3 encode and decode
peripherals. software debug of ARM - MPEG4 decode and encode
processor systems
The ARM920T ASB implementation • Hardware/software
- integrates with the ADS.
provides a 32-bit address bus and a cosimulation tools from leading
• ARMulator instruction-accurate EDA Vendors.
32-bit data bus for high-bandwidth software simulator
data transfers made possible by on- For more information, see
chip memory and modern SDRAM • Development boards www.arm.com
and RAMBUS memories. • Design Simulation Models
provide signoff quality ASIC-
Everything you need simulation
• Software toolkits available from
ARM provides a wide range of ARM, Cygnus/GNU,Greenhills,
products and services to support its JavaSoft, MetaWare, Microtec,
processor families, including and Windriver allowing software
software development tools, development in C, C++, Java,
development boards, models, FORTRAN, Pascal, Ada, and
applications software, training, and assembler.
consulting services.
DVI 0024A © Copyright ARM Limited 2000. All rights reserved. Page 11
ARM Confidential - Draft
Contacting ARM
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ARM7, ARM9, ARM10, ARM7TDMI, ARM9E-S, ARM920T ARM926E-S, ARM9TDMI, EmbeddedICE, and AMBA are trademarks of ARM Limited
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are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness
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Page 12 © Copyright ARM Limited 2000. All rights reserved. DVI 0024A
ARM Confidential - Draft