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layout techniques
AVT
σ (VT ) = , what is AVT ?
WL
• AVT is reported to be ~1 mV*um per nm
oxide thickness (JSSC, 39:1, 2004 p157-
168)
– Example: 0.35um process with Tox=7nm,
AVT=7mV*um.
– FET with W=L=2um
(With λ=0.2um, this is 10/10 λ),
σ(VT)=7mV*um/sqrt(2um*2um)=3.5mV
Cheng, Roy, Asenov ESSCIRC 2003 – Minch measured value is 2.4mV
σ (log I ds )
Ids Ids
Serrano-Gotarredeno, Linares-Barranco 2000
I0
A
random variation
1. From 1.2u to 0.35u, FETs with same λ dim have same Δ logI
mismatch. (not true for deeper submicron, gets worse).
2. Cap matching depends on absolute size.
Much better
(if you can
afford it)
better
Even better:
1. Use dummy devices on ends
2. Use common centroid
Relative
capacitance
Shielding from substrate noise Never connect digital ground to the substrate
• V=LdI/dt noise on digital ground yanks around local
substrate. This can move backgate on analog FETs,
severely affecting them.
Digital circuit
Analog circuit
1. Draw schematic/simulate 1. Lakshmikumar, K.R. Hadaway, R.A. Copeland, M.A. “Characterisation and modeling of mismatch in MOS
transistors for precision analog design”, IEEE J. Solid-State Circuits 1986, 21:6, p 1057-1066
2. Draw layout 2. M. J. M. Pelgrom, A. C. J. Duinmaiger, and A. P. G. Welbers, “Matching properties of MOS transistors for
3. Extract schematic and layout to SPICE netlist 3.
precision analog design,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.
Aleksandra Pavasovi, Andreas G. Andreou and Charles R. Westgate, “Characterization of subthreshold MOS
4. Run LVS tool to compare netlists mismatch in transistors for VLSI systems”, Analog Int. Circuits and Signal Processing, 1994, 6:1, p 75-85
4. Forti, F. Wright, M.E. “Measurement of MOS current mismatch in the weak inversion region”, IEEE J. Solid-
5. Interpret output to spot differences State Circuits 1994, 29:2, p 138-142
5. T. Mizuno, J. Okamura, A. Toriumi, "Experimental Study of Threshold Voltage Fluctuation due to statistical
6. Fix layout (or maybe schematic) – iterate to 3. variation of channel dopant number in MOSFETs," IEEE Trans. Electron Devices, vol. ED-41, pp. 2216-2221,
1994.
6. Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A New 5-Parameter MOS Transistor Mismatch
Note: LVS has many options, e.g. check transistor Model," IEEE Electron Device Letters, vol. 21, No. 1, pp. 37-39. January 2000. (PDF 144K, 3 pages)
geometry, check R & C values, collapse 7. Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "Systematic Width-and-Length Dependent CMOS
Transistor Mismatch Characterization and Simulation," Analog Integrated Circuits and Signal Processing,
stacked logic – you need to make sure you are Kluwer Academic Publishers, December 1999. (PDF 1.4M, 26 pages)
using reasonable options 8. T. Serrano-Gotarredona and B. Linares-Barranco, "A 5-Parameters Mismatch Model for Short Channel MOS
Transistors," Proceedings of the 1999 European Solid State Circuits Conference (ESSCIRC99), pp. 440-443,
1999. (PDF 266K, 4 pages)
9. “The matching of small capacitors for analog VLSI”, Minch et. Al. ISCAS 1996 p 239-241