A shared bus is a frequently-used interconnection channel, to which multiple masters can be

connected. It is a single resource which can carry only one transaction at a time. So the protocol of
shared buses must include a sequence of operations called arbitration which selects a unique
commander. In this paper, we propose a coded self arbitration scheme that provides smoothly-
distributed waiting time to all bus masters. In the proposed scheme, when there are more than one
request on the shared bus, the bus master with the longest waiting time wins and the bus is allocated

to the master. Each bus master requires a log2 n -bit counter where n is the number of bus
masters. And we have evaluated the proposed scheme and compared it with starvationfree
arbitration schemes studied so far. According to our simulation, the proposed scheme shows the best
distribution of waiting time reguardless of bus request rates.

Index Terms:

This paper presents the dynamic bus arbiter architecture for a system on chip design. The
conventional bus-distribution algorithms, such as the static fixed priority and the round robin, show
several defects that are bus starvation, and low system performance because of bus distribution
latency in a bus cycle time. The proposed dynamic bus architecture is based on a probability bus
distribution algorithm and uses an adaptive ticket value method to solve the impartiality and
starvation problems. The simulation results show that the proposed algorithm reduces the buffer size
of a master by 11% and decreases the bus request latency of a master by 50%.

ABSTRACT

A VLSI-densed shared-bus distributed system is a computer system consisting of a large number of

VLSI processing units (VPUs) connected to one another by a high-speed bus. Data traffic in such a
system is characterized by three distinct features: large population, bursty transmission, and task-
dependent accesses with priority. A bus arbitration scheme is required to resolve contentions when
several VPUs generate requests simultaneously. Conventional schemes such as daisy chaining,
polling, and independent requests are shown to be inadequate. In this paper, a multiaccess code-
deciphering (MACD) scheme is proposed. Two versions of the scheme are studied. The first version is
a load-dependent scheme that can resolve contentions of N VPUs in an average time of O(log K/2N)
steps where K is equal to the bus width. The second version estimates the number of contending
VPUs and resolves contention in a constant average time independent of load. The proposed
schemes can support task-dependent accesses with priority.