Hitachi 51F500

Dec 2004 (ver g) Training Materials Prepared by: ALVIE RODGERS C.E.T.
2002 and 2003

MODEL RELEASE
DIGITAL
HD READY PTV
Chassis Model # Aspect
DP-27 51SWX20B 16X9
57SWX20B
65SWX20B
DP-27D 57TWX20B 16X9

65TWX20B
DP-26 65XWX20B 16X9

57XWX20B
51XWX20B
DP-24 43FWX20B 16X9
DP-23G 57GWX20B 16X9

51GWX20B
DP-23K 46F500 16X9
DP-23 57UWX20B 16X9

57F500
57G500
51UWX20B
51F500
51G500
CONTENTS... 2002 DP-2X Chassis Projection Television Information

INSTRUCTOR… Alvie Rodgers C.E.T. (Chamblee, GA.)
THIS PAGE LEFT BLANK
Materials prepared by
Dec 2004 (ver f) DP-2X TABLE OF CONTENTS Alvie Rodgers C.E.T.
TOPICS PAGE
SECTION (1) POWER SUPPLY DIAGRAMS:
• +6V Lo Voltage Regulation Circuit Diagram Explained ------------------------------------------ 01-01
• +6V Lo Voltage Regulation Circuit Diagram DP-26 and DP-27 ------------------------------------- 01-02
• +6V Lo Voltage Regulation Circuit Diagram DP-23, DP-23G and DP-24 ---------------------------- 01-03
• Power On Relay Controls Circuit Diagram Explained --------------------------------------------- 01-04
• Power On Relay Controls Circuit Diagram DP-23, DP-23G and DP-24------------------------------- 01-06
• Power On Relay Controls Circuit Diagram DP-26 --------------------------------------------------- 01-07
• Power On Relay Controls Circuit Diagram DP-27 and DP-27D ------------------------------------- 01-08
• Low Voltage Shut Down Circuit Diagram Explained --------------------------------------------- 01-09
• Low Voltage Shut Down Circuit Diagram ----------------------------------------------------------- 01-13
• SW +115V Hi Voltage Regulation Circuit Diagram Explained ---------------------------------- 01-14
• SW +115V Hi Voltage Regulation Circuit Diagram ----------------------------------------------- 01-15
• Additional Hi Voltage Shut Down Circuit Diagram Explained ----------------------------------- 01-16
• Additional Hi Voltage Shut Down Circuit Diagram ------------------------------------------------ 01-17
• Protect (Deflection) Hi Volt Shut Down Circuit Diagram Explained --------------------------- 01-18
• Protect (Deflection) Hi Volt Shut Down Circuit Diagram ---------------------------------------- 01-19
• LEDs (Visual Trouble Shooting) Lo Voltage Power Supply Circuit Diagram Explained ---- 01-20
• LEDs (Visual Trouble Shooting) Circuit Diagram DP-23, 23G and DP-24 ------------------------------- 01-21
• LEDs (Visual Trouble Shooting) Circuit Diagram DP-26 ------------------------------------------------ 01-22
• LEDs (Visual Trouble Shooting) Circuit Diagram DP-27 and DP-27D ----------------------------------- 01-23
SECTION (2) MICROPROCESSOR INFORMATION:

• Microprocessor DATA COMMUNICATION Explanation ------------------------------------- 02-01
• Microprocessor DATA COMMUNICATION Circuit Diagram DP-23, 23G, 24, 27 & 27D ---------- 02-04
• Microprocessor DATA COMMUNICATION Circuit Diagram DP-26------------------------------ 02-05
• Microprocessor Sync Input Circuit Diagram Explained ----------------------------------------- 02-06
• Microprocessor Sync Input Circuit Diagram Circuit Diagram DP-23, 23G, 27 & 27D ---------------- 02-07
• Microprocessor Sync Input Circuit Diagram Circuit Diagram DP-24 -------------------------------- 02-08
• Microprocessor Sync Input Circuit Diagram Circuit Diagram DP-26 -------------------------------- 02-09
SECTION (3) VIDEO CIRCUIT INFORMATION:

• Video NTSC Circuit Diagram Explained ----------------------------------------------------------- 03-01
• Video NTSC Circuit Diagram Circuit Diagram DP-23, 23G, 27 & 27D -------------------------------- 03-03
• Video NTSC Circuit Diagram Circuit Diagram DP-24 ------------------------------------------------ 03-04
• Video NTSC Circuit Diagram Circuit Diagram DP-26 ------------------------------------------------ 03-05
• Video Component, OSD & NTSC Circuit Diagram Explanation -------------------------------- 03-06
• Video Component, OSD & NTSC Circuit Diagram DP-23, 23G, 27 & 27D ------------------------ 03-08
• Video Component, OSD & NTSC Circuit Diagram DP-24 ---------------------------------------- 03-09
• Video Component, OSD & NTSC Circuit Diagram DP-26 ---------------------------------------- 03-10
• ATSC (Digital Tuner) Block Diagram DP-26 Only ------------------------------------------------- 03-11
Continued on Next Page
Table of Contents Page 1 of 4

Dec 2003 (ver g) DP-2X TABLE OF CONTENTS Alvie Rodgers C.E.T.
TOPICS PAGE
SECTION (3) VIDEO CIRCUIT INFORMATION: (Continued)
• Rainforest IC Pulse Explanation Explained -------------------------------------------------------- 03-12
• ABL Circuit Diagram Explanation ------------------------------------------------------------------- 03-13
• ABL Circuit Diagram ---------------------------------------------------------------------------------- 03-14
• ABL Switch (Black Side Bars) Circuit Diagram and Explanation ------------------------------ 03-15
• Audio Video Mute Circuit Diagram Explanation ------------------------------------------------- 03-16
• Audio Video Mute Circuit Diagram ----------------------------------------------------------------- 03-18
• DVI Input Circuit Diagram ---------------------------------------------------------------------------- 03-19
• Component Sync Circuit Diagram Explanation ----------------------------------------------------- 03-20
• Component Sync Circuit Diagram --------------------------------------------------------------------- 03-21
SECTION (4) AUDIO CIRCUIT INFORMATION:

• Audio Main Terminal Circuit Diagram Explanation ---------------------------------------------- 04-01
• Audio Main Terminal Circuit Diagram ------------------------------------------------------------- 04-02
SECTION (5) DEFLECTION CIRCUIT:

• Horizontal Drive Circuit Diagram Explanation --------------------------------------------------- 05-01
• Horizontal Drive Circuit Diagram ------------------------------------------------------------------ 05-03
• IH01 Horizontal Drive IC Voltages and Waveforms (Also, Not Running Info.) ------------ 05-04
• Sweep Loss Detection Circuit Diagram Explanation ---------------------------------------------- 05-05
• Sweep Loss Detection Circuit Diagram ------------------------------------------------------------- 05-06
• Vertical Output Circuit Diagram Explanation ---------------------------------------------------- 05-07
• Vertical Output Circuit Diagram -------------------------------------------------------------------- 05-08
• Pincushion Circuit Diagram-------------------------------------------------------------------------- 05-09
• Pincushion Circuit Diagram-------------------------------------------------------------------------- 05-10
SECTION (6) DIGITAL CONVERGENCE CIRCUIT INFORMATION:

• Digital Convergence Interconnect Circuit Diagram Explanation ------------------------------ 06-01
• Digital Convergence Interconnect Circuit Diagram DP-23, 23G, 26, 27 & 27D ----------------------- 06-05
• Digital Convergence Interconnect Circuit Diagram DP-24 ------------------------------------------ 06-06
• Remote CLU4321UG (Digital Convergence Mode Functions) DP-23, DP-23G & DP-24 -------- 06-07
• Remote CLU5721TSI (Digital Convergence Mode Functions) DP-26 -------------------------- 06-08
• Remote CLU5722TSI (Digital Convergence Mode Functions) DP-27 -------------------------- 06-09
• 43" Overlay Dimensions ----------------------------------------------------------------------------- 06-10
SECTION (7) ADJUSTMENT INFORMATION:

• Adjustment Order ------------------------------------------------------------------------------------ 07-01
• Pre Heat Run ------------------------------------------------------------------------------------------ 07-02
• Cut Off Adjustment ----------------------------------------------------------------------------------- 07-03
• Pre-Focus Adjustment -------------------------------------------------------------------------------- 07-04
Continued on Next Page Table of Contents Page 2 of 4

TOPICS PAGE
SECTION (7) ADJUSTMENT INFORMATION (Continued):
• DCU Crosshatch Phase Settings ------------------------------------------------------------------- 07-05
• Horizontal Position (Coarse) Adjustment --------------------------------------------------------- 07-06
• Raster Tilt Adjustment ------------------------------------------------------------------------------- 07-07
• Beam Alignment Adjustment ------------------------------------------------------------------------ 07-08
• Off-Set for Red and Blue Raster Position Adjustment ----------------------------------------- 07-09
• Vertical Size Adjustment ----------------------------------------------------------------------------- 07-10
• Horizontal Size Adjustment -------------------------------------------------------------------------- 07-11
• Beam Form Adjustment ------------------------------------------------------------------------------ 07-12
• Lens Focus Adjustment ------------------------------------------------------------------------------- 07-13
• Static Focus Adjustment ------------------------------------------------------------------------------ 07-14
• DCU Character Set-Up and DCU Data Confirmation Adjustment -------------------------- 07-15
• DCU Pattern (Sensor Position) Set-Up Adjustment --------------------------------------------- 07-16
• Remote CLU5721TSI (Digital Convergence Mode Functions) --------------------------------- 07-21
• Remote CLU5722TSI (Digital Convergence Mode Functions) --------------------------------- 07-22
• Remote CLU4321UG (Digital Convergence Mode Functions) ---------------------------------- 07-23
• Read from ROM Notes ------------------------------------------------------------------------------ 07-24
◊ DIGITAL CONVERGENCE ALIGNMENT PROCEDURE ------------------------------ 07-25

◊ (Clearing RAM) Clearing Digital Convergence Data -------------------------------------------- 07-25
◊ Centering Magnet Adjustment ---------------------------------------------------------------------- 07-25
◊ Static Centering Adjustment (Freeze Button) ------------------------------------------------------ 07-26
◊ Green 3X3 Mode Adjustment ------------------------------------------------------------------------ 07-27
◊ Red and Blue 3X3 Mode Adjustment --------------------------------------------------------------- 07-28
◊ Green 7X5 Mode Adjustment ------------------------------------------------------------------------ 07-29
◊ Red and Blue 7X5 Mode Adjustment --------------------------------------------------------------- 07-30
◊ Green 9X13 Mode Adjustment ----------------------------------------------------------------------- 07-31
◊ Red and Blue 9X13 Mode Adjustment -------------------------------------------------------------- 07-32
◊ Storing Digital Convergence Data (Write to ROM) ---------------------------------------------- 07-33
◊ Initializing Magic Focus Sensors ------------------------------------------------------------------- 07-34
◊ Convergence Touch Up Minor Adjustments ------------------------------------------------------ 07-35
◊ ERROR CODES for DCU HD FOCUS Description -------------------------------------------- 07-36
• Blue De-Focus Adjustment --------------------------------------------------------------------------- 07-37
• White Balance and Sub Brightness Adjustment ------------------------------------------------- 07-38
• White Balance Adjustment Flow Chart ------------------------------------------------------------ 07-39
• Sub Picture (PIP) Amplitude Adjustment --------------------------------------------------------- 07-40
• Horizontal Position (Fine) Adjustment ------------------------------------------------------------- 07-41
• Magnet Locations ------------------------------------------------------------------------------------- 07-42
Continued on Next Page

TOPICS PAGE
SECTION (8) MISCELLANEOUS INFORMATION:

• Rear Panel DP-27 and DP-27D (Terminal Input) Drawing -------------------------------------- 08-01
• Rear Panel DP-23 and DP-23G (Terminal Input) Drawing -------------------------------------- 08-02
• Rear Panel DP-26 (Terminal Input) Drawing ----------------------------------------------------- 08-03
• Rear Panel DP-24 (43FWX20B Only Terminal Input) Drawing ------------------------------- 08-04
• Signal PWB Drawing --------------------------------------------------------------------------------- 08-05
• Deflection PWB Drawing ---------------------------------------------------------------------------- 08-06
• Power Supply PWB Drawing ----------------------------------------------------------------------- 08-07
• CRT PWBs Drawing ---------------------------------------------------------------------------------- 08-08
• All but DP-24 Front Control PWBs Drawing ---------------------------------------------------- 08-09
• DP-24 Front Control PWBs Drawing -------------------------------------------------------------- 08-10
SECTION (9) THINGS YOU SHOULD KNOW / SERVICE BULLETINS / ETC….:

• This section changes often, the index for this section is shown on the
Things You Should Know section divider.
Please go to Section 9 section divider cover page for details ------------------------------------- 09-00
• Download this Section Separately.

POWER SUPPLY
INFORMATION
DP-2X
CHASSIS DIAGRAMS
SECTION 1
DP-2X +6V POWER SUPPLY REGULATION EXPLANATION
+6V Power Supply Circuit Diagram explanation: The Primary Chassis Discussed is the DP-27 and DP-27D.
(See DP-26, DP-27 and DP-27D +6V Regulation Circuit Diagram for details).
(Also, see DP-23, DP-23G and DP-24 +6V Regulation Circuit Diagram for details).
Note: Items described below for the DP-23, 23G and DP-24 are shown in brackets [ ].
THIS POWER SUPPLY RUNS ALL THE TIME:

When a Projection set is plugged into an AC outlet, it must produce a power supply to energize certain circuits.
These circuits are responsible for monitoring the Infrared input or Front control Keys as well as the Auxiliary
inputs if the Auto Link feature is active.
These power supplies are generally labeled as Always power supplies or Standby power supplies. As an example
A+6V would indicate a +6V power supply that’s always present. If the power supply has an Sby prefix, (example
Sby +6V) this too is always present if the set is plugged into the AC outlet.
The DP-2X power supply Standby voltages are regulated by monitoring the Control +6V which becomes the
Sby +5V after it is regulated by I909.
The Control +6V is generated on the Secondary of T901 pin 10 [7]. The pulse is rectified by D941 and filtered
by C954 and becomes a +6V Power Supply.
REGULATION: Note: Items for the DP-23, 23G and DP-24 are shown in brackets [ ].
The primary route for the Control +6V is to pin 3 of I909 and output as Sby. +5V from pin 2.
However, the regulation route is to pin 1 of I904. Internally, the LED is illuminated by degrees dependant upon
the Control +6V voltage fluctuations. The internal receiver receives this light and acts as a variable resistor from
pin 4 to pin 3 ground. This action causes pin 6 of I901 to manipulate the internal oscillator within I901. This in
turn causes the frequency of the drive pulse delivered to the Gate of the internal SMOSFET (Switch Metal Oxide
Semiconductor Field Effect Transistor) to manipulate the frequency of the pulse generated on the primary of
T901. Pin 6 [3] of T901 is routed to pin 1 of I901 which is the Drain of the SMOSFET. The source is connected
internally to pin 2 and then to floating ground pin 9 [6] of T901. The floating ground is monitored by three [two]
low ohm resistors, R908, R909 and R910 [R908, R909] to hot ground. Here, the current drain of the internal
SMOSFET is monitored. If this current exceeds a specific value, the voltage developed by these low ohm resis-
tors is routed back into pin 5 which is the Over Current Protection circuit. This pin will inhibit the drive signal to
the gate of the SMOSFET. As soon as the excessive current situation is eliminated, the IC will recover and con-
tinue functioning.
B+ GENERATION FOR THE LOW VOLTAGE POWER SUPPLY DRIVER IC:

Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage. I901 requires
16V DC to operate normal. However, it will begin operation at 6.8V DC on pin 3 of I901.
When AC is applied, AC is routed through the main fuse F901 (a 6 Amp fuse), then through the Line filter L901
to prevent any internal high frequency radiation for radiating back into the AC power line. After passing the fil-
ters it arrives at the main full wave bridge rectifier D901 where it is converted to Raw 150V DC voltage to be
supplied to the power supply switching transformer T901 pin 2 [1].
However, one leg of the AC is routed to a half wave rectifier D904 where it is rectified, routed through R906 and
R907 (both a 68K ohm resistor), filtered by C911, clamped by a 30V Zener D907 and made available to pin (3)
of I901 as start up voltage. When this voltage reaches 6.8Vdc, the internal Regulator of I901 is turned On and
begins the operation of I901.
When the power supply begins to operate by turning on and off the internal Switch MOS FET, the Raw 150V DC
routed through T901, to I901 in on pin 1 (Drain) and out on pin 2 which is the Source. The Source of the internal
Switch MOS FET is routed out of pin 2 through three low ohm resistors to hot ground. When the internal Switch
MOS FET turns on, it causes the transformer to saturate building up the magnet field. When the internal Switch
MOS FET turns off, the magnet field collapses and the EMF is coupled over to the secondary windings, as well
as the drive windings. The drive windings at pin 8 [5] of T901 produce a run voltage pulse which is rectified by
D905, filtered by C911 then routed clamped by D907 and now becomes run voltage (16V) for I901 pin 3.
Note too that Hot Ground is the Negative Leg of the bridge rectifier D901 and the Floating Ground is pin 9 [6] of
T901.
PAGE 01-01
DP-26, DP-27 and DP-27D CHASSIS POWER SUPPLY Sby +6V REGULATION
Lo Voltage Power Supply
T902
8
AC
9 R913
D904 Start Up Run

R906
D901 R907 D905

D910
16.3V
Osc B+
C911
150V 3 D907 R911
F902 BD 7
1 D
2 I901 OCP C916 R914
5
Driver/
Output IC D906 R912
6
S 2 C914
6 FB/OLP
T901 ABS
C910A
4 R908
D908 R916 0.47
R909
Ohm
R910
C918 C917 C915
R917
Hot Ground from
negative leg of
Bridge D901
FB
Floating Ground
I904 R915 from pin 9 of T901
2 4
R958 Cold Ground Pin 11
D953 3
1 Secondary of
R957 T901
Regulator Photocoupler
C904
Control C969
PPS3
+6V
T901
D941 1.79A I909 0.0685A
10
3 +5V 2 2 Sby +5V
Reg
11 C954 C972 C985 C973
1
PAGE 01-02
DP-23, DP- 23G and DP-24 Chassis
+6.0 V Low Voltage Regulation
T901
5
AC
6 R913
D904 R906
D901 R907 Start Up D905 Run

D910
16.3V
3 C911 D907 R911
150V
Osc B+
F902 BD 7
1 D
1 I901 OCP 5 C916 R914
C913
Driver/
D906 R912
Output IC
3
S 2 C914
6 FB/OLP
T901 ABS
C910A
4 R908
D908 R916
R909
0.47
C918 C917 C915 Ohm
R917
Hot Ground from
FB negative leg of
Bridge D901
Floating Ground
I904 R915 from pin 6 of T901
2 4
R958
D953 3
1
R957
Regulator Photocoupler
C904 Cold Ground from

pin 8 of T901
Control C969
PPS3
+6V
T901
D941 1.79A I909 0.0685A
7
3 +5V 2 2 Sby +5V
Reg
C954 C972 C985 C973
8
1
PAGE 01-03
DP-2X POWER ON RELAY CONTROLS EXPLANATION
Relay Controls Circuit Diagram explanation:

(See DP-23, DP-23G, DP-24 and DP-27, DP-27D Relay Controls Circuit Diagram for details)
POWER ON:
When the Customer presses the Power On button on the Front control panel or the Remote control, the Micro-
processor I001 output a High from pin 59. This high is routed to the base of Q026 which turns this transistor On
and it’s collector connected to the Sty +5V line goes low. This action in turn causes the base of Q025 to go low
and turns Q025 to turn Off. Q025 collector is also connected to the Sby +5V line and it’s collector pulls up to
5V.
This high is routed to the PPS3 connector pin 4. Provided the Short Detection transistor Q903 isn’t activated,
(See the Lo Voltage Power Supply Shut Down Circuit for details), then the High from pin 4 is routed to the base
of Q908 turning it On.
When Q908 turns on, it’s collector is connected to the Sby +5V line. It’s emitter pulls up and supplies a high to
the base of Q907 turning it On. When Q907 turns on, it causes the following relays to energize.
RELAYS ENERGIZED BY Q907 (DP-23, DP-23G, DP-24, DP-27 and DP-27D:

Note: This description refers specifically to the DP-27 and DP-27D chassis. Components identified inside brack-
ets [ ] are for the DP-23, 23G and DP-24 chassis.
S901
This completes the path for AC to reach the High Voltage power supply bridge diode D902. (See the High Volt-
age Regulation Circuit for details). This action starts the High Voltage power supply SW+115V for the deflection
circuit.
S902
This completes the path for the pulse generated from pin 14 [11] of T901, (+38V for DP-26, DP-27 and DP-27D)
and [+29V for DP-23, DP-23G and DP-24] to reach the Audio B+ rectifier diode D944. Here the Audio +38V
[+29V] is generated and output from the PPS5 connector pins 1, 2 and 3 and on to the Audio output circuit.
S903
This completes the path for the pulse generated from pin 10 [7] of T901 (Control +6V), rectified by diode D941
which produces SW+6V to reach the PPS4 connector pins 7 and 6 and on to IP52 (Switched +3.3V regulator)
and IP53 (Switched +5V regulator) on the Signal PWB.
S905
This completes the path for the pulse generated from pin 13 [10] of T901 (+35V) to reach the Tuning Voltage B+
rectifier diode D943. Here the SW+35V is generated and output from the PPS3 connector pin 8 and on to the
Tuners pin 9.
DP-26 ONLY: RELAYS ENERGIZED BY POWER _1 and POWER _2:

(See DP-26 Relay Controls Circuit Diagram for details)
Power _1: (High when the Set is turned On.)

• When the Customer presses the Power On button on the Front control panel or the Remote control, the
Microprocessor I001 output a High from pin 59. This high is routed to the base of Q026 which turns this
transistor On and it’s collector connected to the Sty +5V line goes low. This action in turn causes the
base of Q025 to go low and turns Q025 to turn Off. Q025 collector is also connected to the Sby +5V
line and it’s collector pulls up to 5V.
• This high is routed to the PPS3 connector pin 4. Provided the Short Detection transistor Q904 isn’t ac-
tivated, (See the Lo Voltage Power Supply Shut Down Circuit for details), then the High from pin 4 is
routed to the base of Q907 turning it On.
• When Q907 turns on, it causes the following relays to energize.
(Continued on page 5)
PAGE 01-04
DP-2X POWER ON RELAY CONTROLS EXPLANATION
RELAYS ENERGIZED BY Q907: Activated by Power _1

• S901
This completes the path for AC to reach the High Voltage power supply bridge diode D902. (See the
High Voltage Regulation Circuit for details). This action start the High Voltage power supply
SW+115V for the deflection circuit.
• S902
This completes the path for the pulse generated from pin 14 of T901, (+38V) to reach the Audio B+ rec-
tifier diode D944. Here the Audio +38V is generated and output from the PPS5 connector pins 1, 2 and
3 and on to the Audio output circuit.
• S903
This completes the path for the pulse generated from pin 10 of T901 (Control +6V), rectified by diode
D941 which produces SW+6V to reach the PPS4 connector pins 7 and 6 and on to IP52 (Switched
+3.3V regulator) and IP53 (Switched +5V regulator) on the Signal PWB.
Power _2: (High when the set is turned On and/or when the Timer is On).
• When the Customer presses the Power On button on the Front control panel or the Remote control, the
Microprocessor I001 output a High from pin 58. This high is routed to two different circuits.
• DM +9V REGULATOR:
• When Power _2 goes high, it's routed to pin 2 of IP01 on the Signal PWB. This is the DM +9V regula-
tor and it turns on. Input to pin 5 is the DM +10V, IP01 regulates this down to 9V and output it from pin
3 to the Digital Module (ATSC Tuner) pin 12 PMS1.
• The DM +9V is also routed to the Terminal PWB pin 21of the PST2 connector. This turns on the Selec-
tor IC IX01 and the Monitor Out Circuit.
• Power _2 is also routed to the PPS3 connector pin 4 and then to the Power Supply. This high is routed
to the base of Q909 turning it On.
• When Q909 turns on, it causes the following relays to energize.
RELAYS ENERGIZED BY Q909: Activated by Power _2

• S905
This completes the path for the pulse generated from pin 13 of T901 (+35V) to reach the Tuning Volt-
age B+ rectifier diode D943. Here the SW+35V is generated and output from the PPS3 connector pin 8
and on to the Tuners pin 9. This voltage is also routed out the PPS7 connector pin 6 DM +28V, to be-
come tuning voltage for the Digital Tuner (ATSC) via pin 1 of the PMS2 connector.
• S906
This completes the path for the pulse generated from pin 17 (Digital Module +10V) of T901 to reach the
rectifier diode D945. Here the DM +10V is generated and output from the PPS7 connector pin 2 and 3
and on to the DM +9V regulator IP01. Input to pin 5, IP01 regulates this down to +9V and outputs it
from pin 3 to the Digital Module (ATSC Tuner) pin 12 of the PMS1 connector.
TIMER (Unattended Recording) OPERATION:

NOTE: Power _2 is also high when the Timer is set for unattended recordings. When the Timer is activated, the
Tuners, Selector IC and Monitor output become active. During this time, Power_1 remains Low.
This way, the Selector IC, Tuners, Audio Circuit and Monitor outputs remain active.
The Table below shows the logic state of Power _1 and Power _2.
MODE POWER _1 POWER _2
Stand By L L
Timer L H
Power ON H H
PAGE 01-05
DP-23, DP-23G and DP-24 Chassis Power On Relay Controls
T901 S-902 Audio Power Sby 5V comes from I909 pin 2

Supply Relay PPS5
+29V E911 D944 L922 GREEN L.E.D. 1.30A
11 1
C978 R985 2 Audio + 29V
12 C962 3
Sby +5V C957 R992
4 Audio Gnd
L921 D965 5 Audio Gnd
6 Audio Gnd
S-905 SW +35V
+35V Supply Relay D943 7 Audio Gnd
10
PPS3
0.0165A
8 SW + 35V
C961 C956 3 Gnd
On Off
7 Gnd
D954 Q907 R960
2 Sby +5V
Q908
T901 R962 R963 POWER _1 I001
8 R959 4 59
Micro
R961 On Q025 Q026
C957
Off
S-903 SW +6V Q903
Control +6V Supply Relay Sby +5V
Short Det.
See Power Supply Shut Down Circuit
7
PPS4
D941 L923 1.33A
S-901 Main 7
Power Relay SW + 6V
C959 6
C954 AC to D902 5 Gnd
High Voltage
4 Gnd
Power Supply
AC
3 Gnd
PAGE 01-06
DP-26 RELAY CONTROLS
Audio S-902
SW +35V Relay PPS5
+38V E911 D944 L922 GREEN L.E.D. 1.55A
14 1
T901 C978 R985 2 Audio + 38V
15 C952 3
Sby +5V R992 D965
C957 4 Audio Gnd
L921 5 Audio Gnd Sby 5V comes
6 Audio Gnd from I909 pin 3
S-906 Digital 7 Audio Gnd
E912 Module 10 V Relay D945
1.55 A
17 2 DM +10V
3 DM +10V
T901 C963 From D942 0.36 A POWER POWER
16 1 Sby +10V MODE
Sby +5V C958 _1 _2
4 Audio Gnd
Q909 5 Audio Gnd Stand By L L
0.006 A
6 DM +28V
7 N/C Timer L H
S-905 SW +35V R963 R973
C968 PPS7 TV On H H
+35V Supply Relay D943 R984
13
PPS3 On
C956 5 POWER _2 Off From Micro Pin 58
C961 1.30A
On Off 1 SW + 35V
0.25 A SBY + 5V
2 From I909
D954 Q907 R960 3 Gnd
T901 7 Gnd On
R962 R963
11 R959 4 POWER _1 Off From Micro Pin 59
D972 C957 Q904
PPS4
S-903 SW +6V Short Det.
Control +6V Supply Relay Sby +5V 1
See Power Supply 1.06A SW + 9V From I911
2
Shut Down Circuit 1.54A
10 7
SW + 6V
D941 L923 6
S-901 Main
Power Relay
5 Gnd
C954 High Voltage 3 Gnd
Power Supply
PAGE 01-07
AC
DP-27 and DP-27D CHASSIS RELAY CONTROLS on the POWER SUPPLY
T901 S-902 Audio Power Sby 5V comes from I909 pin 3
Supply Relay PPS5
+38V E911 D944 L922 GREEN L.E.D. 1.95A
14 1
C978 R985 2 Audio + 38V
15 C962 3
Sby +5V C957 R992
4 Audio Gnd
6 Audio Gnd
S-905 SW +35V
+35V Supply Relay D943 7 Audio Gnd
13
PPS3
0.0165A
8 SW + 35V
C961 C956 3 Gnd
On Off
7 Gnd
D954 Q907 R960
2 Sby +5V
Q908
R962 R963 POWER _1 I001
11 R959 4 59
Micro
R961 On Q025 Q026
C957
Off
Control +6V S-903 SW +6V Q903

Supply Relay Sby +5V
Short Det.
See Power Supply Shut Down Circuit
10
PPS4
D941 L923 1.33A
S-901 Main 7
Power Relay SW + 6V
C959 6
High Voltage
4 Gnd
Power Supply
AC
3 Gnd
PAGE 01-08
DP-2X LOW VOLTAGE POWER SHUT DOWN EXPLANATION
Low Voltage Power Supply Shut Down Circuit Diagram explanation:

(See DP-27 Signal Power Supply (Low Voltage) Shut-Down Circuit Diagram for details)
The Low Voltage power supply is centered around the Switching Transformer T901 and I901.
This power supply creates the Standby voltages SBY +5V which runs anytime the set is plugged into an AC out-
let. It also creates other voltages that are Switched on when the Set is turned on.
Audio +38V
SW +35V
SW +9V
SW +HVcc
The following explanation will describe the Low Voltage Power Supply Shut Down Circuit.
POWER SUPPLY SHUTDOWN PHOTO COUPLER I905 EXPLANATION

This chassis utilizes I901 as the Osc.\Driver \Switch for the Low Voltage power supply, just as the previous chas-
sis have done. The Shutdown circuit, (cold ground side detection), removes I901 B+ at pin 3 via the following
circuit, I905 (the Photo Coupler), which isolates the Hot ground from the Cold ground and couples the Shutdown
signal to the Hot Ground side, Q902 on the hot ground side and Q901 which latches Q902 on. When Q902 is on,
it removes B+ from pin (3) of I901 (the Vin pin).
The Power Supply utilizes a Shutdown circuit that can trigger Q902 from 2 input sources. (1 of these Short De-
tection circuits are not operational in Stand By mode). I905 is activated by a Low being applied to pin 2, which
forward biases the internal LED. The light from this internal LED is then coupled to the receiver transistor. The
receiver transistor turns On and output a High from pin 3. This high is routed to the base of Q902 turning it On,
which grounds out the Vin at pin (3) of I901, disabling the power supply. Q901 will keep a high on the base of
Q902 as long as there is any voltage available at its Emitter.
The individual Shut Down circuits will be discussed later.
GENERAL INFORMATION:
All of the Power Supply Shutdown circuitry can be broken down into the following category;
• Voltage Missing Detection or Short Detection
• Voltage Too High Detection
• Excessive Current Detection
• Negative Voltage Loss Detection
The following will explain all of these commonly used circuits. The Service Technician should become familiar
with the appearance of these circuit and their function.
VOLTAGE LOSS or SHORT DETECTION

(See Figure 1)
One circuit used is the Voltage Loss Detection cir-
cuit. This is a very simple circuit that detects a loss of Any Positive
a particular power supply and supplies a Pull-Down B+ Supply
path for the base of a PNP transistor. Voltage
This circuit consist of a diode connected by its cath- Loss B+
ode to a positive B+ power supply. Under normal Detector
conditions, the diode is reversed biases, which keeps Q1
the base of Q1 pulled up, forcing it OFF. However, if
there is a short or excessive load on the B+ line that’s
being monitored, the diode in effect will have a LOW
Figure 1 Shut-Down Signal
on its cathode, turning it ON. This will allow a cur-
rent path for the base bias of Q1, which will turn it
ON and generates a Shutdown Signal.
PAGE 01-09
VOLTAGE TOO HIGH DETECTION Any Positive

(See Figure 2)
B+ Supply
Another circuit used is the Voltage Too High Detec- Voltage Too High
tion circuit. In the example shown in Figure 2, the Detector
zener diode D1 is connected to a voltage divider. If
the voltage source rises too high, the voltage at the
divider center point will rise as well and trigger or fire
the zener diode which produces a Shutdown signal.
Shut-Down Signal Figure 2
EXCESSIVE CURRENT DETECTION
(See Figure 3)
One very common circuit used in many Hitachi tele-
vision products is the B+ Excessive Current Sensing R1 0.47
circuit. In this circuit is a low ohm resistor in series B+
with the particular power supply, (labeled B+ in the Current Sensor
drawing). The value of this resistor is determined by
the maximum current allowable within a particular Base
power supply. In the case of Figure 1, the value is Bias
shown as a 0.47 ohm, however it could be any low
ohm value. When the current demand increases, the
voltage drop across the resistor increases. If the volt-
age drop is sufficient to reduce the voltage on the base Shut-Down Signal
of the transistor, the transistor will conduct, producing Figure 3
a Shutdown signal that is directed to the appropriate
circuit.
NEGATIVE VOLTAGE LOSS DETECTION

(See Figure 4) Shut-Down Signal
The purpose of the Negative Voltage Loss detection circuit is to
compare the negative voltage with its’ counter part positive volt-
age. If at any time, the negative voltage drops or disappears, the
circuit will produce a Shutdown signal. Voltage
In Figure 5, there are two resistors of equal value. One to the Loss
positive voltage, (shown here as +12V) and one to the negative
Detector
voltage, (shown here as -12V). At their tie point, (neutral point),
the voltage is effectually zero (0) volts. If however, the negative
voltage is lost due to an excessive load or defective negative
voltage regulator, the neutral point will go positive. This in turn Figure 4 +12V -12V
will cause the zener diode to fire, creating a Shutdown Signal.
SPECIFIC INFORMATION:
In addition, there are 7 Hot Ground side Shutdown inputs that are specifically detected by the main power driver
IC I901. These sensors circuits protect I901 from excessive current, temperature or over voltage.
HOT GROUND SIDE SHUT DOWN SENSING CIRCUITS. (Specific to I901).
LATCHED SHUT DOWN MONITORS: (AC must be removed to recover).

1. (OVP) Pin 3 is monitored for Over Voltage Protection at pin 3 of I901.
2. (TSD) I901 itself is monitored for Excessive Heat. This block is labeled TSD. (Thermal Sensing Device).
3. (OLP) Over Load Protection monitors the difference between the Hot Ground and Floating Ground.
RECOVERING SHUT DOWN INPUT: (Driver IC will recover on it’s own when trouble is removed.)
4. (OCP) Pin 5 monitors the low ohm resistors, R908, R909, and R910. If these resistors have an excessive
PAGE 01-10
current condition caused by monitoring the current through the internal Switch MOS FET, the voltage will
rise and pin 5 has an internal Over Voltage detection op-amp. If this voltage rises enough to trigger this op-
amp, the IC will stop producing a drive signal.
5. (ABS) Pin 4 also has C915 monitoring spike current in case the CRTs “Snap” indicating a quick discharge
of High Voltage.
6. (BD) Pin 7 Monitors the Run Voltage generated by pin 18 of T901 for excessive voltage.
COLD GROUND SIDE SHUT DOWN SENSING CIRCUITS. (AC must be removed to recover).
(See DP-27 Signal Power Supply (Low Voltage) Shut-Down Circuit Diagram for details)
Looking at Pin 2 of I905 the shut down events are triggered by two routes.
D963, D962:
The cathode of D963 is connected through R982 to pin 10 of PPS3. This in turn is connected to R298 which is
connected directly to the 3.3V power supply produced by IP81 on the Signal PWB. If something were to load
this line down, D963 would forward bias and supply a current path for pin 2 of I905. This in turn would produce
a Shut Down event. See Power Supply Shutdown Photo Coupler I905 Explanation on the previous page.
Q910:
This transistor’s base is connected to Q911 through D955. Q911 emitter is connected to Q912. This transistor is
the Shut down enable circuit.
DP-27 SHUT DOWN CIRCUIT:

There are a total of 3 individual Shutdown inputs to the photo coupler I905.
There are a total of 3 individual Shutdown inputs to the Relay Inhibit transistor Q903 from the power supply.
There are a total of 4 individual Shutdown inputs to the Relay Inhibit transistor Q903 from the Deflection Cir-
cuit. For a total of 10 individual Shutdown inputs that will kill the Lo Voltage Power Supply. (Note: The Hi Volt-
age Power Supply Shutdown will be discussed later.)
All of the Cold Ground side Shutdown detection circuits can be categorized by the two previously described cir-
cuits
In the following explanation, the Shutdown circuits will be grouped. This will assist the Service Technician with
trouble shooting the Chassis, by understanding these circuits and having the associated circuit routs, the techni-
cian can then “Divide and Conquer”.
Voltage Loss Detection through I905 Photo coupler
• Shorted STBY +3.3V generated by IP81 and monitored by (R298) on Signal PWB through PPS3 pin 10
to (D963) on Low Voltage Power Supply PWB. Labeled PROT-SBY on the Schematic.
• Shorted SW+2.2V (IP52 pin 5) on Signal PWB monitored by RP53 through PPS3 pin 11 to to (D961)
on Low Voltage Power Supply PWB. Labeled PROT-SW on the Schematic.
• Shorted SW+3.3V (IP52 pin 2) on Signal PWB monitored by DP53, RP53 through PPS3 pin 11 to to
(D961) on Low Voltage Power Supply PWB. Labeled PROT-SW on the Schematic.
• Shorted SW+5V (IP53 pin 2) on Signal PWB monitored by DP54, RP53 through PPS3 pin 11 to to
Q903 Relay Inhibit Activation.

From the Power Supply.
SW +115V Voltage Too High Detection
• Monitored by (D927) See additional Shut Down Circuit Diagram for details.
SW +115V Excessive Current Detection
• Monitored by (Q905) See additional Shut Down Circuit Diagram for details
PAGE 01-11
SW –28V Loss Detection

• Monitored by (D937) See additional Shut Down Circuit Diagram for details
From the Deflection Circuit PPD3 connector pin 6.

Vertical B+ 28V Voltage Excessive Current Detection
• Monitored by (Q604) See Deflection Protect Power Supply Shutdown Diagram for details.
Excessive High Voltage Detection
• Monitored by (DH15) See Deflection Protect Power Supply Shutdown Diagram for details.
-5V Loss Detection
• Monitored by (DK90) See Deflection Protect Power Supply Shutdown Diagram for details.
Side Pincushion Failure Detection
• Monitored by (D702, D703) See Deflection Protect Power Supply Shutdown Diagram for details
If any one of these circuits activate the base of Q903 will go High and remove the Power On High from PPS3
connector pin 4 and the power supply will STOP.
SOME SHUTDOWN CIRCUITS ARE DEFEATED IN STANDBY MODE. (Set Off).

As indicated in the Power Supply (Lo Voltage) Shutdown circuit diagram, 3 of the shut down inputs are not ac-
tive when the set is in standby.
• Shorted SW+2.2V (IP52 pin 5) on Signal PWB monitored by RP53 through PPS3 pin 11 to to (D961)
on Low Voltage Power Supply PWB. Labeled PROT-SW on the Schematic.
• Shorted SW+3.3V (IP52 pin 2) on Signal PWB monitored by DP53, RP53 through PPS3 pin 11 to to
• Shorted SW+5V (IP53 pin 2) on Signal PWB monitored by DP54, RP53 through PPS3 pin 11 to to
These voltage loss sensing circuits are defeated because the SW (Switched) power supplies are turned off in
standby. So to prevent faults triggering of the shutdown circuit, the sensing circuits are turned off also..
Q911 supplies the high for shutdown if any of the voltage loss circuits become activated. Q911 requires emitter
voltage to operated. Emitter voltage is supplied from the emitter of Q912. Q912s base is connected to the power
on/off line. When the set is not on or turned off, the power on/off line goes Low. This Low pulls the cathode of
D956 low, removing the base voltage of Q912 turning it OFF. This removes the emitter voltage from Q911 and
this circuit can not function. The base of Q912 is also connected to the SW +6V line. This voltage must be active
for this circuit to function.
B+ GENERATION FOR THE LOW VOLTAGE POWER SUPPLY DRIVER IC:

16V DC to operate normal. However, it will begin operation at 6.8V DC on pin (3) of I901.
When AC is applied, AC is routed through the main fuse F901 (a 6 Amp fuse), then through the Line filter L901
to prevent any internal high frequency radiation for radiating back into the AC power line. After passing the fil-
ters it arrives at the main full wave bridge rectifier D901 where it is converted to Raw 150V DC voltage to be
supplied to the power supply switching transformer T901 pin (2).
However, one leg of the AC is routed to a half wave rectifier D904 where it is rectified, routed through R906 and
R907 (both a 68K ohm resistor), filtered by C911, clamped by a 30V Zener D907 and made available to pin (3)
of I901 as start up voltage. When this voltage reaches 6.8Vdc, the internal Regulator of I901 is turned On and
begins the operation of I901.
routed through T901, in on pin 1 (Drain) and out on pin 2 which is the Source. The Source of the internal Switch
MOS FET is routed out of pin (2) through three low ohm resistors to hot ground. When the internal Switch MOS
FET turns on, it causes the transformer to saturate building up the magnet field. When the internal Switch MOS
FET turns off, the magnet field collapses and the EMF is coupled over to the secondary windings, as well as the
drive windings. The drive windings at pin (8) produce a run voltage pulse which is rectified by D905, filtered by
C911 then routed clamped by D907 and now becomes run voltage (16V) for I901 pin 3.
PAGE 01-12
DP-2X SIGNAL POWER SUPPLY (Low Voltage) SHUT-DOWN CIRCUIT
T901
D904 R906 D905 D941
R907 16.97V 8 10 Control +6V
R913
C911 C955
D907 9 11
16.3V 3 Vin
D952
I901
Power IC
R956
R919 I905
AC 47 Ohm
C919
4 1
Q901
R920
3 2
Monitors R922
SW +5V Q902
SW +3.3V Q910
SW +2.5V
and D962
C920 HZS3C1
Stby +3.3V C969 R964
R921
for Short
D963
PPS3
R982
To R298 Protect _Sby
10
Monitors IP81 3.3V Reg
HZS4A1 Q911 D955 R965
To RP53 D961 D960 R967
Protect _Sw
Monitors IP52 11
+5V Reg
and IP53 R980 D957 R966
SW +35V 8
Sby +5V
S-905
D946 C970 SW +6V
S901 SW +35V SW +35V
Relay Supply Q912
Relay R969
C956
See Relay Control
Diagram for all R968
AC R963 D956
Q908 Relay Controls
220
To Hi Volt C971 +6V
Power R962
Supply Q907 1K PPS3
C957 R962
D954 R960
4 Power _1 S-903 SW +6V
Supply Relay
R939 On Off
R959 C987
10K
HZS11B1 Q904 I909
See additional 2
Q903 Power Supply Shut
Sby +5V
D933 R940 Down Circuits
Protect _Def 6
4 from Deflection C944 R938 A
PPD3
See Deflection Shut
Down Circuits
PAGE 01-13
DP-2X SW +115V POWER SUPPLY REGULATION EXPLANATION
Hi-Voltage Power Supply Circuit Diagram explanation:

(See DP-27 Chassis Power Supply SW+115V Regulation Circuit Diagram for details)
THIS POWER SUPPLY RUNS ONLY WHEN THE SET IS TURNED ON:
TURNING ON THE SW +115V POWER SUPPLY:

When the Set is turned on, the Microprocessor I001 Outputs a Power On command via pin 59. This Power On
command is routed through Q025 and Q026 to the PPS3 connector pin 4. This High will be passed to the base of
Q908 provided the Short Detection Shut Down sensor Q903 isn’t activated. When the base of Q908 goes high,
it’s emitter will go high and drive the base of Q907 high turning it on. This will supply a ground path for the
power on Relay S901 turning it on. When the relay is energized, AC is supplied to the Bridge rectifier D902.
See Relay Controls on the Power Supply for details.
This rectifier develops raw 150V which is routed through F903 to Pins 1 and 2 of T902. This voltage is routed
through the primary coil inside T902 and out pins 5 and 6 to pin 3 of I902 which is the Drain of the internal
Switch MOS FET. The Ground return path for the primary voltage is out pin 2 of I902 which is the Source of the
internal Switch MOS FET and then through three low ohm resistors R926, R927 and R928. See SW+115V
Regulation Circuit Diagram for details.
SW +115 REGULATION
SW +115V pulse is generated from pin 11 of T902. This pulse is rectified by D915, filtered by C927 and then
routed through the Excessive Current sensing circuit R941 and Q905.
The primary route for the SW +115V is through E907, L914 to pin 9 and 10 of PPD6 and output as SW +115V
to the Deflection Circuit.
However, the regulation route is through E906 to pin 1 of I907. Internally, the regulator transistor works as a
variable resistor whose resistance is dependant upon the SW +115V voltage fluctuations. The internal variable
resistor manipulates the current flow from pin 2 to pin 3 ground. This will cause the voltage at pin 2 of I906 to be
manipulated. Internally, the LED is illuminated by degrees dependant upon the SW +115V voltage fluctuations.
The internal receiver receives this light and acts as a variable resistor from pin 4 to pin 3 which is the regulation
control signal.
This action causes pin 1 of I902 to manipulate the internal oscillator within I902. This in turn causes the fre-
quency of the drive pulse delivered to the Gate of the internal SMOSFET (Switch Metal Oxide Semiconductor
Field Effect Transistor) to manipulate the frequency of the pulse generated on the primary of T902. The current
drain of the internal SMOSFET is monitored by the three low ohm resistors mentioned above. If this current ex-
ceeds a specific value, the voltage developed by these low ohm resistors is routed back into pin 1 which is the
Over Current Protection circuit as well as the Regulation Control pin. This pin will inhibit the drive signal to the
gate of the SMOSFET. As soon as the excessive current situation is eliminated, the IC will recover and continue
functioning.
B+ GENERATION FOR THE HIGH VOLTAGE POWER SUPPLY DRIVER IC:

16V DC to operate normal. However, it will begin operation at 6.8V DC on pin 4 of I902.
When AC is applied to the main full wave bridge rectifier D902 where it is converted to Raw 150V DC voltage
to be supplied to the power supply switching transformer T902 pin 1 and 2.
However, one leg of the AC is routed to a half wave rectifier consisting of R924 and R925 (both a 3.9K ohm re-
sistor), filtered by C923, clamped by a 36V Zener D912 and made available to pin 4 of I902 as start up voltage.
When this voltage reaches 6.8Vdc, the internal Regulator of I902 is turned On and begins the operation of I902.
routed through T902, in on pin 1 (Drain) and out on pin 2 which is the Source. The Source of the internal Switch
MOS FET is routed out of pin (2) through three low ohm resistors to hot ground. When the internal Switch MOS
FET turns on, it causes the transformer to saturate building up the magnet field. When the internal Switch MOS
FET turns off, the magnet field collapses and the EMF is coupled over to the secondary windings, as well as the
drive windings. The drive windings at pin (8) produce a run voltage pulse which is rectified by D911, filtered by
C923 then routed clamped by D912 and now becomes run voltage (16V) for I902 pin 4.
The RED LED D915 can be used to determine if the B+ to I902 is present or not.
PAGE 01-14
DP-2X CHASSIS POWER SUPPLY SW +115V REGULATION
High Voltage Power Supply
T902
8
7.5P/P
9 SW + 115V
Start Up Run
R930
AC
R924 R925 D911 FB R937
From Relay S901 D914
16.3V
4 I906 1
R935
C923
D912 4 Osc B+
R931 3 2
D915 R932
OCP 1 Regulator Photocoupler
RED L.E.D.
I902
C926
R934 R929 D913
AC for D902 Driver/ Hot Ground from
Supplied from Output IC pin 9 of T902
Relay S901
3 D S 2
From Bridge D902
150V I907
T902 6 1 2
R926
1 R927
R928 R936
F903 2
0.22 D922
Ohm
C942 C941
5
E906
6 0.5K 3
C933
R941 3K PPD6
T902 E907
D915 Q905 L914 0.69A
11 0.47 Ohm
9 SW +115V
C927 R943 R942 Deflection 10 SW +115V

12 B+ 115V
C945
R945
D924
D925 D927 Cold Ground from

X-Ray pin 12 of T902
Protect
D926
R946 C905
D928
PAGE 01-15
DP-2X ADDITIONAL SHUTDOWN CIRCUITS EXPLANATION
Additional Power Supply Shut Down Circuit Diagram explanation:

(See DP-27 Additional Power Supply Shut Down Diagram for details)
Use this explanation and Diagram in conjunction with the following diagrams.
DP-2X Signal Power Supply (Low Voltage) Shut Down Circuit (Continuation A)
The following circuits are routed to the Lo Voltage Shut Down Circuit through connection point (A) de-
picted on the Circuit drawing:
SW +115V EXCESSIVE CURRENT DETECTION

(See Figure 1)
One very common circuit used in many Hitachi tele- R941 0.47
vision products is the B+ Excessive Current Sensing SW +115V
circuit. In this circuit is a low ohm resistor in series Current Sensor
with the SW +115V. The value of this resistor 0.47
ohm. When the current demand increases, the voltage Base
drop across the resistor increases. If the voltage drop Bias
is sufficient to reduce the voltage on the base of Q905
Q905, the transistor will conduct, producing a Shut-
down signal that is directed to the appropriate circuit
indicated on the drawing as point (A).
NEGATIVE VOLTAGE LOSS DETECTION

(See Figure 2) Figure 2 Shut-Down Signal
The purpose of the Negative Voltage Loss detection circuit is to Voltage
compare the negative voltage with its’ counter part positive volt-
age. If at any time, the negative voltage drops or disappears, the
Loss D936
circuit will produce a Shutdown signal. Detector
In Figure 2, there are two resistors of equal value, (15K). One to D937
the positive voltage SW +28V and one to the negative voltage
SW –28V. At their tie point, (neutral point), the voltage is effec-
tually zero (0) volts. If however, the negative voltage is lost, the
neutral point will go positive. This in turn will cause the zener D940
diode D937 to fire, creating a Shutdown Signal through D936 SW +28V SW -28V
and on to the appropriate circuit indicated on the drawing as
point (A).
Note: The LED D940 used for visual trouble shooting is illuminated by the current draw from +28V to the –28V
supply.
VOLTAGE TOO HIGH DETECTION

(See Figure 3)
Another circuit used is the Voltage Too High Detec- SW +115V
tion circuit. In the example shown in Figure 3, the D927
zener diode D927 is connected to a voltage divider. If Voltage Too
the voltage source rises too high, the voltage at the
divider center point will rise as well and trigger or fire
High Detector
the zener diode which produces a Shutdown signal D926
Shut-Down
through D926 and on to the appropriate circuit indi-
Figure 3 Signal
cated on the drawing as point (A).
PAGE 01-16
DP-2X ADDITIONAL POWER SUPPLY SHUT DOWN DIAGRAM
C933
R941 3K
T902 D915 Q905 E907 Deflection B+ 115V
0.47 Ohm
11
R945
C927 R943 R942 Deflection B+ (115V)
12
C945 Excessive Voltage Det.
R946
D924 D927
Deflection B+ (115V)
D928
Excessive Current Det.
R944 C946 D925

Deflection B+ 115V
D926
See Signal Power Supply

(Lo Voltage)
Shut Down Circuit A
Diagram
for continuation.
D936 PPD6
L914 0.69A
SW-28V Short or Loss Det. D937 9 SW +115V
10 SW +115V
D940
C934
R952 R951
10K
T902 E901 L912 L915 0.575A
D917
5 SW -28V
15 - -
C928
13 + +
D971 C949
3 Gnd
C935
10K 4 Gnd
T902 E902 D918 L913 L916 1.09A
1 SW +28V
14 + +
C929 C950 2 SW +28V
- -
PAGE 01-17
DP-2X PROTECT SHUTDOWN CIRCUIT EXPLANATION
Protect Shut Down Circuit Diagram explanation:

(See DP-27 Protect Shut Down Diagram for details)
Use this explanation and Diagram in conjunction with the following diagram,
DP-2X Signal Power Supply (Low Voltage) Shut Down Circuit (PROTECT _DEF)
The following circuits are routed to the Lo Voltage Shut Down Circuit through connection point
(PROTECT _DEF) depicted on the Circuit drawing:
EXCESSIVE HIGH VOLTAGE DETECTION

Whenever the High Voltage fluctuates, every other pin off the flyback will fluctuate as well. In this case, a lower
voltage source can be used to determine the status of the High Voltage.
Pin 5 (50P) is used to monitor for excessive High Voltage. The pulse off the flyback is rectified by DH13 and
filtered by CH17. This voltage sets on the cathode of two zener diodes DH15 and DH14.
DH15 is a HZ22V zener. If the voltage at the cathode rises too high, the zener will fire and send a Shut Down
signal through PPD3 pin 6. This signal is routed to the appropriate circuit on the Lo Voltage Shut Down Circuit.
The Shut Down signal is depicted as PROTECT _DEF.
DH14 is a HZ36V zener. If the voltage at the cathode rises too high, the zener will fire and send a Shut Down
signal through to pin 7 of IH01 which is the OVP input pin. This high will cause IH01 to stop producing the Hi
Voltage Drive signal from pin 1.
EXCESSIVE CURRENT TO THE VERTICAL OUTPUT IC DETECTION

(See Figure 1)
This circuit uses a low ohm resistor R629 in series R629 0.68
with the SW +28V. The value of this resistor 0.68 SW +28V
ohm. When the current demand increases, the volt- Current Sensor
age drop across the resistor increases. If the voltage
drop is sufficient to reduce the voltage on the base of Base
Q604, the transistor will conduct, producing a Shut- Bias
down signal through D608 through PPD3 pin 6. This Q604
signal is routed to the appropriate circuit on the Lo
Voltage Shut Down Circuit. The Shut Down signal
is depicted as PROTECT _DEF.
SIDE PINCUSHION FAILURE DETECTION
If the side pincushion circuit fails in such a way as to produce an excessive high on the cathode of D702 (a
HZS7C3) the zener will fire producing a Shutdown signal through D703 through PPD3 pin 6. This signal is
routed to the appropriate circuit on the Lo Voltage Shut Down Circuit. The Shut Down signal is depicted as
PROTECT _DEF.
-5V LOSS DETECTION

The purpose of the Negative Voltage Loss detection circuit is to compare the Shut-Down Signal
negative voltage with its’ counter part positive voltage. If at any time, the nega- Voltage
tive voltage drops or disappears, the circuit will produce a Shutdown signal.
Loss
In Figure 2, there are two resistors of equal value. One to the positive voltage DK90
+5V and one to the negative voltage -5V). At their tie point, (neutral point), the Detector
voltage is effectually zero (0) volts. If the negative voltage is lost, the neutral
point will go positive. This high is routed through DK90 through PPD3 pin 6.
This signal is routed to the appropriate circuit on the Lo Voltage Shut Down Cir-
cuit. The Shut Down signal is depicted as PROTECT _DEF. +5V -5V
Figure 2
PAGE 01-18
DP-2X DEFLECTION PROTECT POWER SUPPLY SHUTDOWN DIAGRAM
RH32 allows ABL fluctuations to Flyback Hi Volt

manipulate the Trigger Point of Shut High Voltage H. Drive
Down as screen brightness varies. ABL TH01 Sensing Circuit
is inverse proportionate to brightness. ABL Voltage
Too High Det. RH23
This prevents false triggering. DH13 RH26 IH01
ABL 3 5 7 OVP
5OP LH06 DH14
Active 4
RH32 Stops H. Drive
Normal
PPD3
29.01V
PROTECT _DEF 6
DH15 RH24 CH17
See Power Supply Shut Down
Circuit Diagram for continuation.
Excessive Hi Any fluctuations in High Voltage will
Vertical Output Circuit Voltage Det. also be reflected by the 50P output P/P.
By monitoring the 50P (50 Pulse) rises
28V in High Voltage will be sensed. If High
I601
Voltage climbs too high, DH15 will fire
10 and trigger a shut down event.
R629 0.68 Ohm

Side Pincushion Circuit
Q604
D702 monitors the Side Pin
R631 Drive IC. If the voltage at I701
R630 pin 7 rises too high, D702
C610 will fire generating a Shut 7
Down high.
R717
D608 R632 D703 D702

Excessive Vertical HZS7C3 Side Pin Failure
Current Det. High Det.
Convergence Out Circuit

If the Vertical Output IC has a problem,
R629 will sense the current rise. The RK97
voltage drop will be reflected at the base -5V -5V Loss
of Q604 turning it on and producing a RK98 Detection
Shut Down high. DK90 +5V
A loss of the Negative 5V will cause the

positive 5V to be felt on the anode of
DK90 which forward biases the diode
and delivers a Shut Down high.
PAGE 01-19
DP-2X LED (Visual Trouble Detection) CIRCUIT EXPLANATION
LED Used for Visual Trouble Shooting Circuit Diagram explanation:

(See DP-2X LED (Visual Trouble Detection) Diodes Signal Power Supply Diagram for details)
5 LEDS, 4 GREEN AND 1 RED

In the DP-2X chassis, there are 5 total LEDs that can be used for Visual Trouble shooting. 4 Green and 1 Red.
Use these LEDs to determine if the set is experiencing a problem.
The LEDs can be used in the following ways.
OFF:
• If the LED is off, then the power supply that is being monitored is unavailable. (Excluding the possibility
that the LED itself is malfunctioning). NOTE: If D940 LED opens, then the set will be in shut down condi-
tion because of it’s current flow explained below.
• If the LED turns on but then quickly goes off before the others, then the power supply that is being moni-
tored can be suspected.
RED LED D915

D915 is used to monitor the Start Up and Run voltage for the Driver IC I902. This IC is used to generate the fol-
lowing voltages.
SW +115V
220V
HEATER
SW+7V
SW-7V
SW +28V
SW -28V
This LED is attached to pin 4 of I902. If the voltage is missing, the LED will not light.
GREEN LEDs D965, D954, D940 and D928.

D965 (Audio +38V)
• Monitors the Audio +38V output from the PPS5 connector pin 1, 2 and 3.
D954 (SW +9V)
• Monitors the SW +9V generated by the SW +9V regulator I911 pin 3 output from the PPS4 connector
pin 1 and 2.
D940 (SW +28V)
• Monitors the SW +28V output from the PPD6 connector pin 1 and 2.
• Note: This LED requires the SW –28V power supply to be functioning to operated. If the LED opens, or
the negative SW –28V is shorted, this LED will not illuminate and the set will shut down.
D928 (SW +115V)
• Monitors the SW +115V output from the PPD6 connector pin 9 and 10.
PAGE 01-20
DP-23, DP-23G and DP-24 CHASSIS
L.E.D. (Visual Troubleshooting) Low Voltage Power Supply
(5 Total L.E.D. for visual trouble sensing , 4 Green and 1 Red)
S-902 Audio Power
Supply Relay D944 GREEN L.E.D. PPS5
T901 E911 1.55A L922 1.30A
11 1
2 Audio + 29V
C962 R985 3
12 Sty +5V R992 C978
C957 4 Audio Gnd
On PPS3 6 Audio Gnd
Off R990 7 Audio Gnd
Power _1 4 2
I911
D942 SW+9V GREEN L.E.D. L924 PPS4
T901 E909 1.92A 0.57A
Reg
9 5 3 1
SW + 9V
R979 2
1 4
8 R977 3 Gnd
C960 C955 C977
4 Gnd
R976 D954 5 Gnd
T902 D918 PPD6

1.13A L913 L916 1.09A
14 1 + 28V
+28V E902
R952 See Shut 2 + 28V
13 C935 C929 C950 Down Circuit
D940 GREEN L.E.D.
R951 D937 D936
- 28V
T902 +115V D915 R941 0.47 Ohm E907 L914 0.69A

11 9 SW + 115V
+115V R945
Q905 Over 10 SW + 115V
12 C933 Current
C927 R946
C945 6 Gnd
D928 GREEN L.E.D. 7 Gnd

SW + 115V
R930
From Pin 8 T902
Osc B+ Start Up Run
AC D911 7.5P/P
R924 R925 D914
16.3V
From 4 I906 1
Relay R935
S901 D912 4 R931
3 2
C923 R932
D915 I902 1 Regulator Photocoupler
Driver/Output IC
RED L.E.D.
R934
6 From I907 pin 2 of
Hot Ground from D913 Regulator IC
R922
pin 9 of T902
PAGE 01-21
DP-26 CHASSIS
L.E.D. (Visual Trouble Detection) Diodes Signal Power Supply
(5 Total L.E.D. for visual trouble sensing observation, 4 Green and 1 Red)
S-902 Audio Power
T901 E911 1.55A L922 1.55A
14 1
2 Audio + 38V
C962 R985 3
15 Sby+5V R992 C978
C957 4 Audio Gnd
On PPS3 6 Audio Gnd
Power _1 4 2
I911
T901 E909 1.92A 0.67A
Reg
12 5 3 1
SW + 9V
R979 2
1 4
11 R977 3 Gnd
C960 C976 C977
4 Gnd
R978 D954 5 Gnd
T902 D918 PPD6

1.13A L913 L916 1.09A
14 1 + 28V
+28V E902 GREEN L.E.D.
D940
R951 D937 D936
- 28V
T902 +115V D916 R941 0.47 Ohm E907 L914 0.69A

11 9 SW + 115V
+115V R945
Q905 Over 10 SW + 115V
12 C933 Current
C927 R946
C945 6 Gnd

SW + 115V
R930
From Pin 8 T902
Osc B+ Start Up Run D911 7.5P/P R937
AC
R924 R925 D914
16.3V
From 4 I906 1
Relay R935
S901 D912 4 R931
3 2
C923 R932
Driver/Output IC
RED L.E.D.
R934
D922
pin 9 of T902
PAGE 01-22
DP-27/D CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES SIGNAL POWER SUPPLY
(5 Total L.E.D. for visual trouble sensing observation, 4 Green and 1 Red)
S-902 Audio Power
T901 E911 1.55A L922 1.55A
14 1
2 Audio + 38V
C962 R985 3
15 Sby+5V R992 C978
C957 4 Audio Gnd
On PPS3 6 Audio Gnd
Power _1 4 2
I911
T901 E909 1.92A 0.67A
Reg
9 5 3 1
SW + 9V
R979 2
1 4
8 R977 3 Gnd
C960 C976 C977
4 Gnd
R978 D954 5 Gnd
T902 D918 PPD6

1.13A L913 L916 1.09A
14 1 + 28V
+28V E902 GREEN L.E.D.
D940
R951 D937 D936
- 28V
T902 +115V D916 R941 0.47 Ohm E907 L914 0.69A

11 9 SW + 115V
+115V R945
Q905 Over 10 SW + 115V
12 C933 Current
C927 R946
C945 6 Gnd

SW + 115V
R930
From Pin 8 T902
Osc B+ Start Up Run D911 7.5P/P R937
AC
R924 R925 D914
16.3V
From 4 I906 1
Relay R935
S901 D912 4 R931
3 2
C923 R932
Driver/Output IC
RED L.E.D.
R934
D922
pin 9 of T902
PAGE 01-23
NOTES
MICROPROCESSOR
INFORMATION
DP-2X
CHASSIS DIAGRAMS
SECTION 2
DP-2X MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT EXPLANATION
PinP Tuner U302 (monaural only, but audio not used).

The Microprocessor controls the Main Tuner by SDA2 (Data) and SCL2 (Clock) I2C communication lines.
SCL2 and SDA2 lines for the Main Tuner are output from the Microprocessor at pins (31 SDA2 and 28 SCL2)
respectively. These lines go directly to the Main Tuner, SDA2 at pin (5) and SCL2 at pin (4). These lines control
band switching, programmable divider set-up information, pulse swallow tuning selection, etc...
EEPROM I003
The EEPROM is ROM for many different functions of the Microprocessor. Channel Scan or Memory List, Cus-
tomer set ups for Video, Audio, Surround etc… are memorized as well. Also, some of the Microprocessors inter-
nal sub routines have variables that are stored in the EEPROM, such as the window for Closed Caption detection.
Data and Clock lines are SDA1 from pin (30) of the Microprocessor to pin (5) of the EEPROM and SCL1 from
pin (29) of the Microprocessor to pin (6) of the EEPROM. Data travels in both directions on the Data line.
Flex Converter FC04

The projection television is capable of displaying NTSC as well as ATSC (SDTV) including HD (High Defini-
tion). The Flex Converter is responsible for receiving any video input and converting it to 33.75 Khz output. This
output is controlled by sync and by the customer’s menu and how it is set up. The set up can be 4X3 or 16X9 for
DTV, or letterbox. This set also has something called “16X9 Normal Mode”. This bypasses the Flex Converter
completely and inputs the 1080i signal directly to the Rainforest IC I401. The Flex Converter can take any
NTSC, S-In, Component, NTSC or Progressive, Interlaced, 480I, 720P, 1080i signal.
Control for the Flex Converter is Clock, Data and Enable lines.
Clock, Data and Enable lines for the Flex Converter are output from the Microprocessor at pins (52 Data, 53
Clock and 55 FCENABLE). The FCENABLE line is routed through the PFC1 connector pin 12 and the
FCDATA line is routed through the PFC1 connector pin 11, the FC Clock is routed through the PFC1 connector
pin 10.
The Clock, Data and Enable lines must be routed through the Level Shift IC I007 to be brought up to 5V.
Clock is input to I007 at pins (2 Clock) and is output at pins (18).
Data is input to I007 at pins (4 Clock) and is output at pins (16).
Enable is input to I007 at pins (6 Clock) and is output at pins (14).
Data from the Flex Converter is also sent back to the Microprocessor. Data from the Flex is sent out of the PFC1
connector pin 11 to pin 5 of I007, level shifted down to 3.3V and output at pin 15 into pin 51 of the Microproces-
sor I001.
Level Shift I007

The Microprocessor operates at 3.3Vdc. Most of the Circuits controlled by the Microprocessor operate at 5Vdc.
The Level Shift IC steps up the DC voltage to accommodate.
• Pin 18 outputs a Clock signal, used by the Flex Converter
• Pin 14 outputs an Enable signal, used by the Flex Converter
• Pin 16 outputs a Data signal, used by the Flex Converter.
• Pin 15 outputs Data, sent from the Flex Converter
Rainforest I401 (Video/Chroma Processor)

The Video Processing IC (Rainforest) is responsible for controlling video/chroma processing before the signal is
made available to the CRTs. Some of the emphasis circuits are controlled by the customer’s menu. As well as
some of them being controlled by AI, (Artificial Intelligence).
Communication from the Microprocessor via pins (31 SDA2 and 28 SCL2) to the Rainforest IC pins (31 and 30)
respectively.
BBE Control IA01 (Surround)

The DP-2X chassis utilizes BBE Surround.
Communication from the Microprocessor via pins (31 SDA2 and 28 SCL2) to the BBE IC pins (13 and 14) re-
spectively.
PAGE 02-02
DP-2X MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT EXPLANATION
ON THE TERMINAL PWB: (Through the connector PST2)
A/V Selector IX01

The A/V Selector IC is responsible for selecting the input source for the Main Picture as well as the source for
the PinP or Sub picture. Communication from the Microprocessor via pins (30 SDA1 and 29 SCL1) to the PST2
connector pins (5 and 4) respectively then to IX01 pins (34 and 33) respectively.
Main Video Chroma IZ02

The Main Video Chroma IC processes the video and chroma from the 3D Y/C circuit for the main picture. It re-
ceives the Y and chroma and prepares it for the Flex Converter by outputting Y Cr/Cb (NTSC Only). Communi-
cation from the Microprocessor via pins (31 SDA2 and 28 SCL2) to connector PST2 pins (2 and 1) then to IZ02
pins (13 and 14) respectively.
Sub Video Chroma IZ01 (PinP)
The PinP Video Chroma IC processes the video and chroma from the 2 Line Comb filter circuit for the Sub pic-
ture. It receives the Y and chroma and prepares it for the Flex Converter by outputting Y Cr/Cb (NTSC Only).
Communication from the Microprocessor via pins (31 SDA2 and 28 SCL2) to connector PST2 pins (2 and 1)
then to IZ02 pins (13 and 14) respectively.
Y Pr/Pb Selector IX02

Any input that is not already in the Y Pr/Pb or Y Cr/Cb state, will have be converted to this state by I501.
The Main Y Pr/Pb Selector IC selects the appropriate input between the Tuner, AV Inputs, S-Inputs or Compo-
nents. Communication from the Microprocessor via pins (31 SDA2 and 28 SCL2) to connector PST2 pins (2 and
1) to IX04 pins (31 and 30) respectively.
3D Y/C IW01 (IC mounted directly on the Terminal PWB).

The 3D Y/C IC is a Luminance/Chrominance separator, as well as a 3D adder. Separation takes place digitally.
Using advanced separation technology, this circuit separates using multiple lines and doesn’t produce dot pattern
interference or dot crawl. The 3D effect is a process of adding additional emphasis signals to the Luminance and
Chrominance. These signals relate specifically to transitions. Transitions are the point where the signal goes from
dark to light or vice versa. The 3D adds a little more black before the transition goes to white and a little more
white just before it gets to white. It also adds a little more white just before it goes dark and a little more dark just
before it arrives. This gives the impression that the signal pops out of the screen or a 3D effect.
The Microprocessor communicates with the 3D Y/C IC via I2C bus data and clock. The communications ports
from the Microprocessor are pins (31 SDA2 and 28 SCL2) to connector PST2 pins (2 and 1) to the 3D Y/C
IW01 pins (60 and 59) respectively.
The Microprocessor also is able to turn on and off circuits within the 3D Y/C circuit determined by customer
menu set-up.
DP-26 MICROPROCESSOR DATA COMMUNICATIONS DIAGRAM
The DP-26 has the addition of the Digital Module (ATSC Tuner).
PAGE 02-03
DP-23, 23G, 24, 27 and 27D CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
PST2
SDA1 Terminal PWB
5 34 SDA1 IX01
IOO1 SCL1
4 33 SCL1 A/V Select
PiP Main
IW01 IZ01 Sub IZ02 Main IX02

IA01 14 Video/Chroma Video/Chroma Y Pr/Pb
3D-Y/C Y Pr/Pb SW Y Pr/Pb SW SELECTOR
BBE Control
13
60 59 13 14 13 14 26 27
I401 SDA2 SDA2
31 2
Rainforest
SCL2 SCL2
Sweep Cont. 30 1
SDA1
SDA1 30 5 SDA1 IOO3
SCL1
SCL1 29 6 SCL1 EEPROM
SDA2
SDA2 31 5 SDA2 U301
SCL2 Tuner 1 Main
SCL2 28 4 SCL2
4 SCL2 U302
5 SDA2 Tuner PinP
PFC1 U303
FCData 51 15 5
Data / Key Out 2 52 4 I007 16 11 FCData FC04
FLEX
FCEnable 55 6 3.3V -> 5V 14 12 FC Enable &
Level Shift
Clock / Key Out 1 PinP
53 2 18 10 FC Clock
SIGNAL PWB
PAGE 02-04
DP-26 Chassis Microprocessor Data Communications
PST2
SDA1 Terminal PWB
5 34 SDA1 IX01
IOO1 SCL1
4 33 SCL1 A/V Select
PiP Main
IW01 IZ01 Sub IZ02 Main IX02

IA01 14 Video/Chroma Video/Chroma Y Pr/Pb
3D-Y/C Y Pr/Pb SW Y Pr/Pb SW SELECTOR
BBE Control
13
60 59 13 14 13 14 26 27
I401 SDA2 SDA2
31 2
Rainforest
SCL2 SCL2
Sweep Cont. 30 1
SDA1
SDA1 30 5 SDA1 IOO3
SCL1
SCL1 29 6 SCL1 EEPROM
SDA2
SDA2 31 5 SDA2 U301
SCL2 Tuner 1 Main
SCL2 28 4 SCL2
PMS1
DM ENABLE IN 20 5 DM ENIN UD2002 4 SCL2 U302
DM TXD 66 8 DM TXD Digital Module Tuner PinP
5 SDA2
DM RXD 67 6 DM RXD ATSC Tuner
DM SCK 68 4 DM SCK
DM Enable Out 69 9 DM. ENOUT
DM RESET 70 2 DM RESET
PFC1 U303
FCData 51 15 5
Data / Key Out 2 52 4 16 11 FCData FC04
I007 FLEX SIGNAL PWB
FCEnable 55 6 3.3V -> 5V 14 12 FC Enable &
Level Shift PinP
Clock / Key Out 1 53 2 18 10 FC Clock
PAGE 02-05
DP-2X MICROPROCESSOR NTSC SYNC INPUT CIRCUIT EXPLANATION
Microprocessor NTSC Sync circuit diagram.

(See DP-2X Chassis NTSC Sync to Microprocessor Signal Path Diagram for Details)
The Microprocessor I001 must have Sync inputs from the Chassis to Lock it’s generation of OSD, Closed Cap-
tion, Customer’s Menu, Service Menu, etc…..
The Chassis feeds back this information in the form of Blanking pulses and Sync from the Video. The following
describes the types of feedback sync signals.
(62) H BLK (Horizontal Blanking):

• H Blk is input to the Microprocessor at Pin 62. H Blk is generated from the Deflection Transformer pulse
off pin 7 of T701, wave shaped by Q706. Then routed out the PPD2 connector pin 8 to the Power Supply.
Then out the PPS2 connector pin 8 to the Signal PWB. From here it is sent to the base of Q024 where it
gets level shifted and inverted and into pin 62 of the Microprocessor.
(64) V BLK (Vertical Blanking):

• V Blk is input to the Microprocessor at Pin 64. V Blk is generated from the Vertical Output IC I601 pin
11. Then routed out the PPD2 connector pin 12 to the Power Supply. Then out the PPS2 connector pin 12
to the Signal PWB. From here it is sent to the base of Q023 where it gets level shifted and inverted and
into pin 64 of the Microprocessor.
(93) MAIN AFC (Automatic Frequency Control):

• Main AFC is input to the Microprocessor at Pin 93. Main AFC is generated from the Main Tuner U301
pin 16. Then routed to Q020 and Q015. Then into pin 93 of the Microprocessor.
• The Microprocessor uses this input signal to align or adjust the precise Oscillator and Programmable di-
vider settings within the Main Tuner for proper Reception.
(92) SUB AFC (Automatic Frequency Control for PinP Tuner):

• Sub AFC is input to the Microprocessor at Pin 92. Sub AFC is generated from the Sub Tuner U302 pin
16. Then routed to Q016 and Q017. Then into pin 92 of the Microprocessor.
• The Microprocessor uses this input signal to align or adjust the precise Oscillator and Programmable di-
vider settings within the PinP Tuner for proper Reception.
(100) MAIN CCD IN:

• The Microprocessor receives Main Sync information and strips the Closed Caption Data from line 21.
This composite sync signal is supplied to the Microprocessor from I005 pin 14. It uses this same input for
stripping V Chip Data.
• When an NTSC component input is supplied to Input 2, this is called 480i. This must also be monitored
for Closed Caption data and for V. Chip Data. If Input 2 is selected and it is 480i (NTSC), then the Micro-
processor outputs a Main CCD Select signal from pin 73 to I005 pin 11 to select 480i input at pin 13.
• NOTE: Component inputs other than 480i (NTSC) are not able to display Closed Caption Data.
(97) Sub CCD IN:

• The Microprocessor receives Sub Sync information and strips the V Chip Data. This composite sync sig-
nal is supplied to the Microprocessor from I005 pin 15.
• When an NTSC component input is supplied to Input 2, this is called 480i. This must also be monitored
for V. Chip Data. If Input 2 is selected as PinP source and it is 480i (NTSC), then the Microprocessor out-
puts a Sub CCD Select signal from pin 74 to I005 pin 10 to select 480i input at pin 1.
(23) M/S Sync Det (Main / Sub Sync Detection):

• The composite sync signal from either Main or PinP (Sub) is supplied to the Microprocessor from I005
pin 4. The Microprocessor uses the Sync signal to activate the AFC loop, and for Auto Programming.
When the channels are changed for the PinP Tuner, the Microprocessor outputs a short control signal from
pin 24 (SD Sel) to I005 pin 9. I005 then outputs the Sub composite sync signal input on pin 5. Normally
this IC outputs the Main composite sync signal input on pin 3.
PAGE 02-06
DP-23, 23G, 27 and DP-27D SERIES CHASSIS NTSC SYNC to MICROPROCESSOR SIGNAL PATH
Lum/Audio Selector IC
PST2
Aux Input 5 Composite 5 PFT QX12 Q008 I005 Q010
5V V3V Main Hi 9
2 22 V4 IX01 44 12 3 Z Q005
Avx 5 In Sub 4
V3Y 7 24 Y4 5
Main Y Lo Q006 Q004
S-5 In V3C
9 26 C4 /Video 480i Hi 10
QX17 Q014 1 Y Q018
11 28 S4 Sub 15
S5 Det. VOut1 53 10 2 Lo Q012
480i Hi 11
Front Control PWB Sub Y 15 13 X1 Q019
Y In Main 14
/Video
Signal PWB 2 of 2 (480i) 12 Lo
PST1
Main PiP Video and Sub Video 16
U301 18 23 63 Video
Main Tuner are the same. SW +9V
TV1V NTSC
U302 For 480i I001

TV2V Main CCD Sel 73
PinP TUNER (Mono) 18 480i Y Component
19 60 PinP
Always PinP Video Only for CCD Sub CCD Sel 74
& V Chip
SD Sel 24
NTSC Only
Aux Input 3 Composite 3
V3 15
21 Main CCD In 100
Part of Jack S-Y1
S3 Det.
S-3 In
17 Sub CCD In 97
S-C1
19 M/S Sync
Q024 23
Aux Input 4 Composite 4 Det
V4 8 62 HBlk
Aux Inputs
S-Y1 59
Part of Jack 14 Q023
S4 Det. IX02 Sub CCD In for
S-4 In
10 64 VBlk V. Chip Data
S-C1
12 Input 2 30 5 Q020 Q015
Circuit Diagram
Composite
93 Main AFC
2 In
Input 2 Q016 Q017 Main CCD Infor
Component 2 Y Composite 2
See Component Sync Separation
CCD & V Chip

92 Sub AFC
QX33 QX34
Input 1 Component 1 Y Micro
480i Only Processor
Terminal PWB SIGNAL PWB 1 of 2
PAGE 02-07
DP-24 Chassis Microprocessor Sync Input
PST2
5V V3V Main Hi 9
10 22 V4 IX01 44 12 3 Z Q005
Avx 5 In Sub 4
V3Y 5 24 Y4 5
Main Y Lo Q006 Q004
S-5 In V3C
3 26 C4 /Video 480i Hi 10
QX17 Q014 1 Y Q018
1 28 S4 Sub 15
S5 Det. VOut1 53 10 2 Lo Q012
480i Hi 11
Front Control PWB Sub Y 15 13 X1 Q019
Y In Main 14
/Video
Signal PWB 2 of 2 (480i) 12 Lo
PST1
Main PiP Video and Sub Video 16
U301 18 23 63 Video
Main Tuner are the same. SW +9V
TV1V NTSC
U302 I001
TV2V For 480i Main CCD Sel 73
PinP TUNER (Mono) 18 480i
19 60 PinP
Always PinP Video Composite Sub CCD Sel 74
Only for CCD
SD Sel 24
& V Chip
Aux Input 3 Composite 3
V3 15
21 Main CCD In 100
Part of Jack S-Y1
S3 Det.
S-3 In
17 Sub CCD In 97
S-C1
19 M/S Sync
Q024 23
V4 8 62 HBlk
Aux Inputs
S-Y1 59
S-4 In
S-C1
12 Input 2 30 5 Q020 Q015
Circuit Diagram
Composite
93 Main AFC
2 In
CCD & V Chip

92 Sub AFC
QX33 QX34
Input 1 Component 1 Y Composite 2 Micro
480i Only Processor
PAGE 02-08
DP-26 SERIES CHASSIS NTSC SYNC to MICROPROCESSOR SIGNAL PATH
PST2
5V V3V Main Hi 9
2 22 V4 IX01 44 12 3 Z Q005
Avx 5 In Sub 4
V3Y 7 24 Y4 5
Main Y Lo Q006 Q004
S-5 In V3C
9 26 C4 /Video 480i Hi 10
QX17 Q014 1 Y Q018
Front Control 11 28 S4 Sub 15
S5 Det. VOut1 53 10 2 Lo Q012
PWB
480i Hi 11
Sub Y 15 13 X1 Q019
Y In Main 14
Signal PWB 2 of 2 /Video
PST1 (480i) 12 Lo
UD2002 7 28 3 DM Y 16
PiP Video and Sub Video
Digital Module 5 30 5 DM C are the same. SW +9V
Main
U301 18 23 63 Video I001
Main Tuner TV1V NTSC 480i Main CCD Sel 73
For 480i
U302 PinP TUNER Y Component Sub CCD Sel 74
18 19 60 PinP
Always PinP TV2V Video Only for CCD
SD Sel 24
& V Chip
Aux Input 3 Composite 3 NTSC Only
V3 15
21 Main CCD In 100
Part of Jack S-Y1
S3 Det.
S-3 In
17 Sub CCD In 97
S-C1
19 M/S Sync
Q024 23
V4 8 62 HBlk
Aux Inputs
S-Y1 59
S-4 In
S-C1
12 Input 2 30 5 Q020 Q015
Circuit Diagram
Composite
93 Main AFC
2 In
CCD & V Chip

92 Sub AFC
QX33 QX34
Input 1 Component 1 Y Micro
480i Only Processor
PAGE 02-09
VIDEO
INFORMATION
DP-2X
CHASSIS DIAGRAMS
SECTION 3
DP-2X NTSC VIDEO SIGNAL PATH CIRCUIT EXPLANATION
(See DP-2X Chassis Video Signal Path-NTSC Circuit Diagram for details)
It’s important to note that this Chassis horizontal deflection operates at 33.75Khz at all times. Even though this is twice as fast
as NTSC, the set will still display NTSC video with no problem. This is accomplished by the Flex Converter. The Flex Con-
verter will manipulate any input, be it NTSC, Component 480i, 480P, 720P, 1080i to the appropriate Horizontal Frequency
rate of 33.75Khz. This makes this chassis very versatile in it’s application.
The following will discuss the signal flow as show in the above listed Circuit Diagram.
TUNER INPUTS:
These sets utilizes two tuners, (DP-26 also has an ATSC Digital Tuner UD2002) one for the Main picture U301 and one for
the PinP (Sub) picture U302. U301 is an intergraded tuner with RF front end, IF decoding, Audio Decoding to Lt/Rt. The
tuner communicates with the Microprocessor via I2C bus. (See Microprocessor Data Communications Circuit Diagram for
details).
The PinP tuner U302 is also an intergraded tuner, however the Audio output is not used.
Both tuners output their respected composite video via pin 18.
• U301 Main Tuner Output pin 18 to PST1 connector pin 23, to the Selector IC IX01 pin 63.
• U302 PinP (Sub) Tuner Output pin 18 to PST1 connector pin 19, to the Selector IC IX01 pin 60.
(DP-26 ONLY):
• UD2002
◊ LUMINANCE: The ATSC (QAM) Tuner (Digital Tuner) Outputs DM Y from pin 7 to the PST1 connector pin
28, to the Selector IC IX01 pin 3.
◊ CHROMINANCE: The ATSC (QAM) Tuner (Digital Tuner) Outputs DM C from pin 5 to the PST1 connector
pin 30, to the Selector IC IX01 pin 5.
These inputs are used while viewing an SDTV or HDTV source, so that there will be an output from the Monitor
Video Jack.
NOTE: The DP-26 has a Digital Tuner (ATSC-8VSB and Cable QAM Tuner). This tuner is UD2002 which also is
the input/output access for IEEE1394. (See the ATSC Block Diagram which is coming up after the Component,
OSD and NTSC Diagram). Even though this explanation is related to NTSC, the ATSC tuner is involved because of
the Video Output on the (Monitor Out) jack. When ATSC or QAM is viewed, the monitor out just have video out-
put. This is accomplished by the ATSC (Digital Tuner) having a Y/C output sent to the NTSC circuit for this pur-
pose.
AUXILIARY INPUT:
This chassis utilizes 5 separate inputs plus a newly added input called DVI. The following will break down those input routes
to the Selector IC IX01.
(1) INPUT 1: This input is only for Component Inputs Y Pr/Pb (31.5Khz to 33.75Khz ATSC) and will not accept Compos-
ite on the Y input. Input one’s Y line is input directly into IX02 pin 59 (Y Pr/Pb Selector).
(2) INPUT 2: This input will accept Component Inputs Y Pr/ Pv (31.5Khz to 33.75Khz ATSC) or Y Cr/Cb (15,735Hz.
NTSC). It will also accept Composite Video input as long as there is no Pr plug inserted. Input 2 is routed into the Selec-
tor IC IX01 pin 30.
(3) INPUT 3: This is NTSC composite input only. It also has an accompanying S-Input. Remember that the S-Input takes
priority over composite input, when S-Input is active. Input 3 is routed into the Selector IC IX01 pin 15. The S-Input
inputs are pin 10 for Y (Luminance) and pin 17 for C (Chroma). When an S-Jack is inserted into the plug, an internal
mechanical switch is activated which produces a low to the Selector IC IX01 pin 21 and the Selector IC notifies the Mi-
croprocessor that and S-Jack is installed.
(4) INPUT 4: This is NTSC composite input only. It also has an accompanying S-Input. Remember that the S-Input takes
priority over composite input, when S-Input is active. Input 4 is routed into the Selector IC IX01 pin 8. The S-Input in-
puts are pin 8 for Y (Luminance) and pin 12 for C (Chroma). When an S-Jack is inserted into the plug, an internal me-
chanical switch is activated which produces a low to the Selector IC IX01 pin 14 and the Selector IC notifies the Micro-
processor that and S-Jack is installed.
(5) INPUT 5: On the Front Control Panel. This is NTSC composite input only. It also has an accompanying S-Input. Re-
member that the S-Input takes priority over composite input, when S-Input is active. Video Input 5 is routed through the
PFT connector pin 2 (pin 10 for DP24 only), into the Selector IC IX01 pin 22. The S-Input inputs are routed through the
PFT connector pin 7 (pin 5 for DP24 only) for Y and pin 9 (pin 3 for DP24 only) for C, into the Selector IC IX01 pin 24
for Y (Luminance) and pin 26 for C (Chroma). When an S-Jack is inserted into the plug, an internal mechanical switch is
activated which produces a low through the PFT connector pin 11 (pin 1 for DP24 only), into the Selector IC IX01 pin
28 and the Selector IC notifies the Microprocessor that and S-Jack is installed.
(Continued on page 03-02)
PAGE 03-01
DP-2X NTSC VIDEO SIGNAL PATH CIRCUIT EXPLANATION
(Continued from page 03-01)
COMPOSITE VIDEO PATH:

When a composite input is selected, it must be broken down into it respective parts, Y and C. This is accomplished for the
Main video by the 3D Y/C and for the PinP (Sub) picture by the 2-Line Comb filter.
MAIN: The Main composite output is routed out of the Selector IC IX01 pin 44 to QX13. Then through the video low pass
filter comprised of QW01, QW02, and QW04. It arrives at the 3D Y/C chip IW01 pin 88. Here the composite video is sepa-
rated into Y/C 3D enhanced, and output on the following pins, Y from pin 84 and C from pin 83.
Y COMPONENT (For Composite In).
The Y component is then routed through a low pas filter comprised of QW09, LPF XW01, QW10, and QW12 into the Main
Video/Chroma Processor IC IZ02.
Note too that the Y component is also routed into the PinP (Sub) Video/Chroma Processor IC IZ01 pin 2. This is for when the
customer presses the Swap button when the PinP Sub window is on.
C COMPONENT: (For Composite In).

The C component is then routed through a low pas filter comprised of QW13, LPF XW02, QW14, and QW15. Then the
chroma must be routed through the TILT circuit. This circuit compensates for the phase relationship of flesh tones between
composite and component. This circuit is comprised of QZ04 and QZ05. Not shown is the switch that enables this phase rota-
tion circuit. The output control is from the selector IC IX01 pin 59 to Q207. From QZ05 the Chroma component is routed
into pin 16 of the Main Video/Chroma Processor IC IZ02.
Note too that the Chroma component is also routed into the PinP (Sub) Video/Chroma Processor IC IZ01 pin 16. This is for
when the customer presses the Swap button when the PinP Sub window is on.
S-INPUT 3, 4 and/or 5:
When the S-Input is selected, it already is separated into it’s Y and C components. In this case, it is routed directly into the
Main Video Chroma Processor IZ02. It is output from the Selector IC IX01 pin 44, through QX13, QX25, and into the Main
Video Chroma Processor IZ02 pin 4. The Chroma component is output from the Selector IC IX01 pin 47, through QX14,
QX26, and into the Main Video Chroma Processor IZ02 pin 19.
The responsibility of IZ02 is to now convert the separated Y/C components of the Main picture into a usable format for the
Flex Converter. The Flex Converter FC4 utilizes component inputs Y Pr/Pb or Y Cr/Cb. IZ02 outputs only NTSC, so it’s
output are Y Cr/Cb. Y from pin 24, Cr from pin 22, and Cb from pin 23.
Y is then routed through QZ10 to the connector PST1 pin 7.
Cr is then routed through QZ08 to the connector PST1 pin 4.
Cb is then routed through QZ09 to the connector PST1 pin 5.
(See the DP-2X Chassis Video Signal Path-NTSC, Component, OSD for continuation).
PinP (Sub) Video Path:

The PinP (Sub) composite video is output from the Selector IC IX01 pin 53, through QV09, QV10, and into the 2-Line Comb
Filter IV01 pin 4. It is separated into it’s individual Y/C components.
The Y (Luminance) component of the PinP (Sub) picture is then output pin 15, through QV01, low pass filter XV01, through
QV02, QV04 and back into the Selector IC IX01 pin 49.
The C (Chroma) component of the PinP (Sub) picture is then output pin 13, through QV05, low pass filter XV02, through
QV06, QV08 and back into the Selector IC IX01 pin 51.
From here, the Selector IC IX01 output the Y from pin 56 through QX15, QX27 into the PinP (Sub) Video/Chroma Processor
IZ01 pin 4.
The C component from pin 58 through QX16, QX28 into the PinP (Sub) Video/Chroma Processor IZ01 pin 19.
IZ01:
The responsibility of IZ01 is to now convert the separated Y/C components of the PinP (Sub) picture into a usable format for
the Flex Converter. The Flex Converter FC4 utilizes component inputs Y Pr/Pb or Y Cr/Cb. IZ01 outputs only NTSC, so it’s
output are Y Cr/Cb. Y from pin 24, Cr from pin 22, and Cb from pin 23.
Y is then routed through QZ01 to the connector PST2 pin 23.
Cr is then routed through QZ03 to the connector PST2 pin 26.
Cb is then routed through QZ02 to the connector PST2 pin 24.
(See the DP-2X Chassis Video Signal Path-NTSC, Component, OSD for continuation).
NOTE: The DP-23, 23G, 26, 27 and 27D all have a DVI input. Shown in the Component input path.
The DP-24 Does NOT have a DVI input.
PAGE 03-02
DP-23, DP-23G, DP-27 and DP-27D CHASSIS VIDEO SIGNAL PATH - NTSC
SIGNAL PST1 QV09 QV10 TERMINAL PWB

U301 V Out 1 53 4 V In
18 PWB 23 63 TV QV04 QV02 QV01 IV01
Main Tuner
Y In 1 49 9 XV01 18 15 Y Out 2Line Y/C
Separator For PinP Only
U302 18 19 XV02 1
60 V6 C In 1 51 3 13 C Out
Sub Tuner
QV08 QV06 QV05
Front Control PWB PFT Y Out 1 56 4 Y2 In IZ01 Sub
QX15 QX27
Aux 5 Video V3V SUB OUT QX16 QX28
V5 2 22 V4 C Out 1 58 Video/Chroma
19 C2 In Processor QZ03 PST2
Aux 5 S-Y V3Y
7 24 Y4
S5 Aux 5 S-C V3C Sub Cr Out 22 26
9 26 C4 QZ02
S-5 Det. 2 Y1 In
11 28 S-4 Sub Cb Out 23 24
SEE DVI
SIGNAL PATH 16 C1 In Sub Y Out 24 QZ01
23
See Component Signal Path for DIAGRAM
Component 1 Video 480i Y Cr/Cb for DVI PATH
IX01
NTSC, Component, OSD for continuation
See the DP-2X Chassis Video Signal Path-
IX02 A/V Select QZ10

V1 59 7
Y Pr/Pb Select QX12 QZ09
Component 1 Video See Micro. 5
Aux 2 Video (Component Y) Sync Path QZ08 -6db
V2 30 V5 MAIN 4
Pr No Input for Composite OUT
Pr 7 S-1 QX13 QX25 PST1 IZ02 MAIN
V/Y Video/Chroma
Aux 3 Video 44 4 Y2
V3 15 V3 Out 2 Processor
Aux 1 S-Y 2 Y1
17 Y3 QX14 QX26 Main Cr Out 22
S3 C
Aux 1 S-C 47 19 C2
19 C3 Out 2
S-3 Det. Main Cb Out 23
21 S-3 16 C1
VIDEO LPF Main Y Out 24
Aux 4 Video 8 QW01 QW02 QW04
V4 V2 QZ05
Aux 2 S-Y 10 88 V In
Y2 IW01
S4 Aux 2 S-C 12 C2 3D Y/C
Chroma Tilt Y AMP Y LPF
S-4 Det. Separator
14 Correction QW12 QW10 XW01 QW09
S-2
84 Y Out AYO
Monitor Out Video 41 V Out 3 MON QZ04
MON Monitor Out S-Y C AMP C LPF
39 Y Out 3 OUT QW15 QW14 XW02 QW13
OUT Monitor Out S-C
37 C Out 3 83 C Out ACO
TERMINAL PWB
PAGE 03-03
DP-24 Chassis Video NTSC
SIGNAL PST1 QV09 QV10

U301 V Out 1 53 4 V In
18 PWB 23 63 TV QV04 QV02 QV01 IV01 TERMINAL PWB
Main Tuner
Y In 1 49 9 XV01 18 15 Y Out 2Line Y/C
Separator
U302 18 19 XV02 1
60 V6 C In 1 51 3 13 C Out For PinP Only
Sub Tuner
QV08 QV06 QV05
Front Control PWB PFT Y Out 1 56 4 Y2 InIZ01 SUB Video/Chroma
QX15 QX27 Processor
Aux 5 Video V3V SUB OUT QX16 QX28
Sub Video
V5 10 22 V4 C Out 1 58 19 C2 In Chroma
Aux 5 S-Y V3Y QZ03 PST2
5 24 Y4
S5 Aux 5 S-C V3C Sub Cr Out 22 26
3 26 C4 QZ02
S-5 Det. 2 Y1 In
1 28 S-4 Sub Cb Out 23 24
16 C1 In QZ01
Sub Y Out 24 23
See Component Signal Path for
Signal Path
Component 1 Video 480i Y Cr/Cb

See Component
IX01
PiP Video= Sub Video
V1 59 7
Component 1 Video See NTSC 5
V2 30 V5 MAIN 4
Pr No Input for Composite OUT IZ02 MAIN
Pr 7 S-1 QX13 QX95 PST1
V/Y Video/Chroma
Aux 3 Video 44 4 Y2 Processor
V3 15 V3 Out 2
Aux 1 S-Y 2 Y1
S3 C
Aux 1 S-C 47 19 C2
19 C3 Out 2
21 S-3 16 C1
V4 V2 QZ05
Aux 2 S-Y 10 88 V In IW01
Y2
S-4 Det.
14 Correction QW12 QW10 XW01 QW09 Separator
S-2
84 Y Out AYO
OUT Monitor Out S-C
TERMINAL PWB
PAGE 03-04
DP-26 CHASSIS VIDEO SIGNAL PATH - NTSC
SIGNAL PWB PST1 SEE DVI SIGNAL PATH DIAGRAM for DVI PATH
QV09 QV10 TERMINAL PWB
U301 Main Tuner 18 23 63 TV V Out 1 53 4 V In
QV04 QV02 QV01 IV01
U302 Sub Tuner 18 19 60 V6 2Line Y/C
Y In 1 49 9 XV01 18 15 Y Out
Separator For PinP Only
UD2002 7 28 3 DM Y
C In 1 51 3 XV02 1 13 C Out
Digital Module 5 30 5 DM C
QV08 QV06 QV05
Y Out 1 56 4 Y2 In IZ01 Sub
Front Control PWB PFT QX15 QX27
SUB OUT QX16 QX28 Video/Chroma
Aux 5 Video V3V 19 C2 In PST2
V5 2 22 V4 C Out 1 58 Processor QZ03
Aux 5 S-Y V3Y Sub Cr Out 22
7 24 Y4 26
S5 Aux 5 S-C V3C QZ02
9 26 C4 2 Y1 In
S-5 Det. Sub Cb Out 23 24
11 28 S-4 QZ01
16 C1 In Sub Y Out 24 23
See Component Signal Path for
Component 1 Video 480i Y Cr/Cb IX01
NTSC, Component, OSD for continuation
See the DP-2X Chassis Video Signal Path-

V1 59 7
Component 1 Video See Micro. 5
V2 30 V5 MAIN 4
Pr No Input for Composite OUT
Pr 7 S-1 QX13 QX25 PST1 IZ02 MAIN
V/Y Video/Chroma
Aux 3 Video 44 4 Y2
V3 15 V3 Out 2 Processor
Aux 1 S-Y 2 Y1
S3 C
Aux 1 S-C 47 19 C2
19 C3 Out 2
21 S-3 16 C1
V4 V2 QZ05
Aux 2 S-Y 10 88 V In
Y2 IW01
S-4 Det. Separator
14 Correction QW12 QW10 XW01 QW09
S-2
84 Y Out AYO
OUT Monitor Out S-C
TERMINAL PWB
PAGE 03-05
DP-2X CHASSIS VIDEO SIGNAL PATH-NTSC, COMPONENT, OSD CIRCUIT EXPLANATION
(See the Chassis Video Signal Path-NTSC, Component, OSD for details)
(See Video Signal Path-NTSC Circuit Diagram for details about NTSC)
It’s important to note that this Chassis horizontal deflection operates at 33.75Khz at all times. Even though this is
twice as fast as NTSC, the set will still display NTSC video with no problem. This is accomplished by the Flex
Converter. The Flex Converter will manipulate any input, be it NTSC, Component 480i, 480P, 720P, 1080i to the
appropriate Horizontal Frequency rate of 33.75Khz. This makes this chassis very versatile in it’s application.
The following will discuss the Component signal path and the continuation of the NTSC signal path.
COMPONENT INPUTS 1 and/or 2:

This chassis utilizes 5 separate inputs plus a newly added input called DVI. The following will break down those
input routes to the Y Pr/Pb Selector IC IX02.
(1) INPUT 1: This input is only for Component Inputs Y Pr/Pb (31.5Khz to 33.75Khz ATSC) and will not ac-
cept Composite on the Y input.
• The Y line is input directly into the Y Pr/Pb Selector IX02 pin 59.
• The Cr/Pr line is input directly into the Y Pr/Pb Selector IX02 pin 63.
• The Cv/Pb line is input directly into the Y Pr/Pb Selector IX02 pin 62.
(2) INPUT 2: This input will accept Component Inputs Y Pr/ Pv (31.5Khz to 33.75Khz ATSC) or Y Cr/Cb
(15,735Hz. NTSC). It will also accept Composite Video input as long as there is no Pr plug inserted.
• The Y line is input directly into the Y Pr/Pb Selector IX02 pin 5.
• The Cr/Pr line is input directly into the Y Pr/Pb Selector IX02 pin 9.
• The Cv/Pb line is input directly into the Y Pr/Pb Selector IX02 pin 7.
• Input 2 Composite Video is routed into the Selector IC IX01 pin 30.
(3) DVI INPUT (Digital Video Interface): This input will accept Component Inputs Y Pr/ Pv (31.5Khz to
33.75Khz ATSC) only. (See DVI Signal Path for further details). (NOT in the DP24 Chassis).
• The Y line is input from the PET connector pin 5 into the Y Pr/Pb Selector IX02 pin 53.
• The Pr line is input from the PET connector pin 3 into the Y Pr/Pb Selector IX02 pin 57.
• The Pb line is input from the PET connector pin 7 into the Y Pr/Pb Selector IX02 pin 55.
(4) DIGITAL TUNER (ATSC) UD2002 INPUT: These inputs are provided from the Digital Tuner (ATSC).
The ATSC Tuner output DM-Y, DM-Pb and DM-Pr. (Only in the DP26 Chassis). (See DP-26 Component,
OSD, NTSC Signal Path for specifics).
• DM-HY (Luminance) from PMS2 pin 16, through PST1 pin 13 to Y Pr/Pb Selector IX02 pin 15.
• DM-Pb (Blue Chroma) from PMS2 pin 14, through PST1 pin 15 to Y Pr/Pb Selector IX02 pin 17.
• DM-Pr (Red Chroma) from PMS2 pin 12, through PST1 pin 17 to Y Pr/Pb Selector IX02 pin 19.
◊ NOTE: When receiving a SDTV or HDTV signal, the Digital Module also outputs Composite Video/
Chroma for the Monitor Output. (See DP-26 NTSC Signal Path for specifics).
COMPONENT VIDEO PATH:
The output from the Y Pr/Pb Selector IX02 is then routed to the Video/Chroma Y Pr/Pb Switch.
IZ01 is used to select the PinP (Sub) picture source. Either from component inputs or from the separated NTSC
inputs as described in the DP-2X Chassis Video Signal Path-NTSC Circuit Diagram.
• The Sub Y component is output from the pin 50 through QX19 into the PinP (Sub) Video/Chroma Y Pr/
Pb Switch IZ01 pin 30.
• The Sub Cr/Pr component is output from the pin 46 through QX21 into the PinP (Sub) Video/Chroma Y
Pr/Pb Switch IZ01 pin 28.
• The Sub Cb/Pb component is output from the pin 48 through QX20 into the PinP (Sub) Video/Chroma
Y Pr/Pb Switch IZ01 pin 29.
• Main NTSC Y component is input into the PinP (Sub) Video/Chroma Y Pr/Pb Switch IZ01 pin 2.
• PinP (Sub) NTSC Y component is input into the PinP (Sub) Video/Chroma Y Pr/Pb Switch IZ01 pin 4.
IZ02 is used to select the Main picture source. Either from component inputs or from the separated NTSC inputs
as described in the DP-2X Chassis Video Signal Path-NTSC Circuit Diagram.
• The Main Y component is output from the pin 44 through QX24 into the Main Video/Chroma Y Pr/Pb
PAGE 03-06
DP-2X CHASSIS VIDEO SIGNAL PATH-NTSC, COMPONENT, OSD CIRCUIT EXPLANATION
Switch IZ02 pin 30.

• The Main Cr/Pr component is output from the pin 40 through QX22 into the Main Video/Chroma Y Pr/
• The Main Cb/Pb component is output from the pin 42 through QX23 into the Main Video/Chroma Y Pr/
• Main NTSC Y component is input into the Main Video/Chroma Y Pr/Pb Switch IZ02 pin 2.
• PinP (Sub) NTSC Y component is input into the Main Video/Chroma Y Pr/Pb Switch IZ02 pin 4.
To the Flex Converter U303:

After the selection has been made as to the source for the Main and PinP (Sub) picture, IZ01 and IZ02 output the
appropriate signal. IZ01 outputs the PinP (Sub) picture and IZ02 outputs the Main picture.
(1) OUTPUT from IZ02 Main Picture: This output is routed from;
• Main Y component Pin 24 through QZ10 to the connector PST1 pin 7. Here the signal is split.
◊ The primary path is through Q306 to the Flex Converter U303 connector PFC1 pin 3.
◊ The secondary path is for 1080i input signals ONLY. In this case, the signal is input directly into
the Rainforest IC. The path is through Q406 and into the Rainforest IC I401 pin 8.
• Main Cr/Pr component Pin 22 through QZ08 to the connector PST1 pin 4. Here the signal is split.
• Main Cb/Pb component Pin 23 through QZ09 to the connector PST1 pin 5. Here the signal is split.
(2) OUTPUT from IZ01 PinP (Sub) Picture: This output is routed from;
• PinP (Sub) Y component Pin 24 through QZ01 to the connector PST2 pin 23. Then to the Flex Con-
verter U303 connector PFC1 pin 17.
• PinP (Sub) Cr/Pr component Pin 22 through QZ03 to the connector PST2 pin 26. Then to the Flex
Converter U303 connector PFC1 pin 19.
• PinP (Sub) Cb/Pb component Pin 23 through QZ02 to the connector PST2 pin 24. Then to the Flex
Converter U303 connector PFC1 pin 18.
FLEX CONVERTER OUTPUT:
The Flex Converter outputs only one horizontal frequency and that is 33.75Khz (540P) which relates specifically
to 1080i deflection rate. So in other words, all inputs are upconverted to the higher deflection rate. 1080i is routed
directly to the Rainforest IC I401 and has no need for Flex Converter manipulation.
This can be a trouble shooting tool if the Flex Converter is suspected as having problems. Simply input a true
1080i signal and bypass the Flex Converter.
The output from the Flex Converter is as follows;
• Y is output from pin 16 of the PFC2 connector, through Q403 and into the Rainforest IC pin 3.
• Pr is output from pin 20 of the PFC2 connector, through Q401 and into the Rainforest IC pin 5.
• Pb is output from pin 18 of the PFC2 connector, through Q402 and into the Rainforest IC pin 4.
RAINFOREST IC I401:
This IC processes the input signal source, adjust brightness, contrast, color, tint, etc… and add (if necessary) PinP
(Sub) picture information and/or OSD information and output the Main Picture as R, G and B.
Red is output pin 43, Blue is output pin 41 and Green is output pin 42.
OSD:
OSD can be introduced via the Microprocessor and/or in the same fashion the Digital Convergence Module can
introduce it’s information. OSD from Microprocessor is Red pin 39, Blue pin 37 and Green pin 38.
Digital Convergence Information is input Red pin 35, Blue pin 33 and Green pin 34.
(See Digital Convergence Interface Circuit Diagram Explanation for details).
PAGE 03-07
DP-23, DP-23G, DP-27 and DP-27D Chassis Video Signal Path - NTSC,Component, OSD
SIGNAL PWB POWER PWB SIGNAL PWB Q422 RAINFOREST IC

UKDG PDG PPD1 PPS1 35 Analog R In
QK06 Q421 I401
Dig R Out 20 2 2 34 Analog G In RGB
QK07
Dig G Out 21 4 4 Q420 Processor
QK08 33 Analog B In
Dig B Out 22 5 5 Q419
39 OSD R In
Q418 R Out 43
Digital Conv. 38 OSD G In To
OSD R 32
Unit G Out 42 CPT
Q417 37 OSD B In
I001 OSD G 33 Q404 PWBs
DEFLECTION PWB Micro- 10 Pr 2 In B Out 41
processor Q405
OSD B 34 9 Pb 2 In
Q406
See DVI Input 8 Y 2 In
Signal Diagram IX02 Pr 1 In Pb 1 In Y 1 In
Y/Pb/Pr NTSC MAIN Y In 2
PET IZ02 5 4 3
Selector S-In MAIN Y In 4 MAIN
Video/Chroma
DVI 3 57 DVI PR PFC1
QX22 Y Pr/Pb Switch
INPUT
7 55 DVI PB MAIN Pr-Out 2 40 28 Cr/Pr R In
From PST1
DVI MAIN QX23
5 53 DVI Y (G) 42 29 Cb/Pb B In QZ08 Q308
INPUT Pb-Out 2
PWB QX24 Main Cr/Pr Out 22 4 5 U303
12 64 DVI Det MAIN Y-Out 2 44 30 D-Sync 1/Y3/ G In QZ09 Q307 FC4
Main Cb/Pb Out 23 5 4
63 COMP 1 (Cr/Pr) UNIT
V1 6 D-Sync 2 In QZ10 Q306
61 COMP 1 (Cb/Pb) Main Y Out 24 7 3 PFC2
Q401
59 COMP 1 (Y)
NTSC MAIN Y In 2 IZ01 MAIN Pr Out
SUB 20
9 COMP 2 (Cr/Pr) Sub MAIN Y In 4 Video/Chroma Q402
V2 COMP 2 (Cb/Pb) Y Pr/Pb Switch Pb Out
7
PST2 18
5 COMP 2 (Y) QX21
QZ03 SUB Q403
SUB Pr-Out 1 46 28 Cr/Pr R In Y Out
QX20 Sub CrPr Out 22 26 19 16
SUB Pb-Out 1 48 29 Cb/Pb B In QZ02
QX19 Sub Cb/Pb Out 23 24 18
SUB Y-Out 1 50 30 D-Sync 1/Y3/ G In QZ01
Sub Y Out 24 23 17
6 D-Sync 2 In
TERMINAL PWB SIGNAL PWB
PAGE 03-08
DP-24 Chassis Video Component OSD & NTSC
POWER PWB SIGNAL PWB Q422 RAINFOREST IC

QK06 Q421 I401
QK07
QK08 33 Analog B In
Dig B Out 22 5 5 Q419
39 OSD R In
Q418 R Out 43
OSD R 32
Unit G Out 42 CPT
Q417 37 OSD B In
DEFLECTION PWB Micro- 10 Pr 2 In B Out 41
processor Q405
OSD B 34 9 Pb 2 In
Q406
8 Y 2 In
IX02 Pr 1 In Pb 1 In Y 1 In
IZ02 5 4 3
Video/Chroma
PFC1
QX22 Y Pr/Pb Switch
MAIN Pr-Out 2 40 28 Cr/Pr R In
PST1
MAIN QX23
42 29 Cb/Pb B In QZ08 Q308
Pb-Out 2
QX24 Main Cr/Pr Out 22 4 5 U303
MAIN Y-Out 2 44 30 D-Sync 1/Y3/ G In Q307
QZ09 FC4
63 COMP 1 (Cr/Pr) UNIT
Q401
59 COMP 1 (Y)
NTSC MAIN Y In 2 IZ01 MAIN Pr Out
SUB 20
9 COMP 2 (Cr/Pr) Sub MAIN Y In 4 Video/Chroma Q402
7
PST2 18
5 COMP 2 (Y) QX21
QZ03 SUB Q403
QX20 Sub CrPr Out 22 26 19 16
QX19 Sub Cb/Pb Out 23 24 18
SUB Y-Out 1 50 30 D-Sync 1/Y3/ G In QZ01
Sub Y Out 24 23 17
6 D-Sync 2 In
TERMINAL PWB SIGNAL PWB
PAGE 03-09
DP-26 Chassis Video Signal Path - NTSC, Component, OSD
POWER PWB Q422 RAINFOREST IC

QK06 Q421 I401
QK07
QK08 33 Analog B In
Dig B Out 22 5 5 Q419
39 OSD R In
Q418 R Out 43
OSD R 32
Unit G Out 42 CPT
Q417 37 OSD B In
Micro- 10 Pr 2 In B Out 41
DEFLECTION PWB Q405
processor OSD B 34 9 Pb 2 In
See DVI Input Q406
Signal 8 Y 2 In
Diagram IX02 Pr 1 In Pb 1 In Y 1 In
PET IZ02 5 4 3
Video/Chroma
DVI 3 57 DVI PR PFC1
QX22 Y Pr/Pb Switch
INPUT
7 55 DVI PB MAIN Pr-Out 2 40 28 Cr/Pr R In
From PST1
DVI MAIN QX23
5 53 DVI Y (G) 42 29 Cb/Pb B In QZ08 Q308 U303
INPUT Pb-Out 2
PWB QX24 Main Cr/Pr Out 22 4 5 FC4
12 64 DVI Det MAIN Y-Out 2 44 30 D-Sync 1/Y3/ G In QZ09 Q307 UNIT
63 COMP 1 (Cr/Pr)
NTSC MAIN Y In Q401
59 COMP 1 (Y)
2 IZ01 MAIN Pr Out
SUB 20
COMP 2 (Cr/Pr) Sub MAIN Y In
9
4 Video/Chroma Q402
7
PST2 18
5 COMP 2 (Y) QX21
QZ03 SUB Q403
PST1 QX20 Sub CrPr Out 22 26 19 16
FLEX CONVERTER
From 13 15 DM Y QX19 Sub Cb/Pb Out 23 24 18

ATSC SUB Y-Out 1 50 30 D-Sync 1/Y3/ G In QZ01
Digital 15 17 DM PB
Tuner Sub Y Out 24 23 17
UD2002 17 19 DM PR 6 D-Sync 2 In
Signal PWB
SIGNAL PWB
PAGE 03-10
TERMINAL PWB
DP-2X RAINFOREST IC INFORMATION (I401)
YM/P-MUTE/
SCP IN FBP IN
Max 9V
BLK
6.2 ~ 9V Blanking
3.7 ~ 9V
CLAMP
2.4 ~ 5.8V P Mute
1.7 ~ 3.3V H-AFC 3.0V

Black Peak BLK 1.5V 0.9 ~ 2.1V Half Tone
0 ~ 0.5V Internal
Pin 17 Pin 24 Pin 52
Pin 17 = SCP.
Black Peak: This input is utilized for establishing the Black Peak level used in Black Peak expansion
circuit. Here the Black Peak is expanded towards Black to increase the contrast ratio.
CLAMP: The clamp pulse is utilized for DC restoration and blanking timing.
Pin 24 = FBP. Combination of the following.

Fly back pulse: 1.5V ~ 3.0V H-AFC: This input is received from the Horizontal Blanking (H. Blk)
signal generated in the Deflection circuit by Q706. This signal is used as a sample pulse in the
Horizontal AFC circuit, which synchronizes the Horizontal Drive signal with the incoming Video sync
signal input at pin 16. In Through Mode, pin 8.
Fly back pulse: 3.0V ~ 9.0V Max: This input is received from the Flex Converter and is a
combination of Horizontal and Vertical blanking signals.
H Blk from the Flex Converter Pin 12 through Q412
V Blk from the Flex Converter Pin 11 through Q411
Used within the Rainforest is for DC restoration, Pedestal level detection and Clamping signals, such
as Burst Gate Pulse.
Pin 52 = YM/P-MUTE/BLK. Combination of the following.

INTERNAL: 0.0V ~ 0.5V Used internal within the Rainforest IC.
HALFTONE: 0.9V ~ 2.1V: This input is received from the Microprocessor and is used to establish
the Transparency effect of OSD. This also mutes the video in exact timing with On Screen Display
pulses (OSD). Half Tone from the Microprocessor Pin 22 through Q415.
P MUTE: 2.4V ~ 5.8V: Not Used.
PAGE 03-12
Block Diagram of UD2002
ATSC / QAM / IEEE1394 Interface Module
Front-End Board Memory Card

Board
IF BCM3510
RAM for
IF circuit VSB/QAM
256QAM Memory
AGC Demodulator Memory
Card I/F Card
I/F
Main Board Memory

IF
Card I/F
Digital I2C
Tuner 64MB
ATSC TS
AGC SDRAM
CATV
SPD
RF IN TC90A55TB Optical
HL Decoder I/F
Y/C, V YSD-038
64MB MPG DAC
SDRAM
Demux
Decoder Graphics
Glue Sub
Graphics DAC
NTSC AC-3 Down Logic 1/2 CPU
Encoder Decoder Mix
L,R NTSC
DAC
TS out Encoder SH4
TS in
DAC Main 64MB
Glue Logic 2/2 Peripherals
CPU
CPU SDRAM
bus
CPU SCI
I2C bus 16MB
SCI Y/Pb/Pr FLASH
TS
L,R Y/C Y Pr/Pb SCI

IEEE
1394 Modem Analog NTSC HD
I/F IEEE1394 IEEE1394 Board Audio Video Video
Physical Link
Analog Digital
Power Power
Supply Supply
IEEE1394 Board RAM Modem
PTV Signal Board
I/F
PAGE 03-11
DP-2X ABL CIRCUIT EXPLANATION
(See ABL Circuit Diagram for details)

The ABL voltage is generated from the ABL pin (3) of the Flyback transformer TH01. The ABL pull-up resis-
tors are RH27 and RH28. They receive their pull up voltage from the SW +115V B+ line for Deflection gener-
ated from the Power Supply.
ABL VOLTAGE OPERATION

The ABL voltage is determined by the current draw through the Flyback transformer. As the picture brightness
becomes brighter or increases, the demand for replacement of the High Voltage being consumed is greater. In
this case, the Flyback will work harder and the current through the Flyback increases. This in turn will decrease
the ABL voltage. The ABL voltage is inversely proportionate to screen brightness.
Also connected to the ABL voltage line is DH16. This zener diode acts as a clamp for the ABL voltage. If the
ABL voltage tries to increase above 9V due to a dark scene which decreases the current demand on the flyback,
the ABL voltage will rise to the point that DH16 dumps the excess voltage into the 9V line.
ACCL TRANSISTOR OPERATION

The ABL voltage is routed through the PPD2 connector pin 3 to the Power Supply PWB, then to PPS2 connector
pin 3 to the Signal PWB. Then the ABL voltage is routed through the acceleration circuit RA54 and D404 to the
base of Q413. Under normal conditions, this transistor is nearly saturated. Q413 determines the voltage being
supplied to the cathode of D403, which is connected to pin 53 of the Rainforest IC, I401. During an ABL voltage
decrease due to an excessive bright circumstance, the base of Q413 will go down, this will drop the emitter volt-
age which in turn drops the cathode voltage of D403. This in turn will pull voltage away from pin 53 of the Rain-
forest IC, I401. Internally, this reduces the contrast and brightness voltage which is being controlled by the I2C
bus data communication from the Microprocessor arriving at pins 30 and 31 of the Rainforest IC and reduces the
overall brightness, preventing blooming as well as reducing the Color saturation level to prevent color smear.
ABL SWITCH QH03

New for this chassis is the ability to change the brightness level of the Side Panels when watching a NTSC 4X3
image. When a 4X3 images is displayed on a 16X9 set, the sides do not reach the edges. To avoid excessive age-
ing at the 4X3 display area, the side panels IRE levels are raised. However, sometimes the customer may want to
turn the side gray panels off. Through the Video Advanced features Menu the customer can now do this. When
the Side panels are turned off, the overall average ABL level for the image is reduced. To compensate, QH03
ABL Switch is added. When the customer selects Black Side panels, the Microprocessor I001 tells the Rainforest
IC I401 via I2C communication to output a high from the DAC2 line pin 36. This high is routed through the
PPS2 connector pin 2 on the Signal PWB to the Power Supply PWB. Then from the PPD2 connector pin 2 on
the Power Supply PWB to the PPD2 connector on the Deflection PWB and finally to the base of QH03 turning it
On.
With QH03 turned on, the Resistor RH29 connected to the collector is added to the ABL pull up circuit and the
ABL level drops slightly to compensate for the side panel loss of brightness.
The Difference between chassis for the ABL circuit relate to the values of Resistors RH24, RH25 and RH32.
See diagram for details.
Gray Side Bars Black Side Bars
PAGE 03-13
DP-2X Chassis A.B.L. Circuit Diagram
RA54 R453 Q413 HVcc +9V 19

ABL I401 Micro
R450 D403 R449 ABL Rainforest I001
R452 IC
53
C426 C425 R483
D404 R451 SDA2 31 31 SDA2
C423
C424
SCL2 30 28 SCL2
36 DAC2 R484
ABL Switch
R462
ABL Sw
R461 55
8 1080i
HVcc +9V 40 Y In
Signal PWB Signal PWB
PPD6 Deflection PWB LH06
TH01
DH13
FBT 5
SW
9 9
+115V RH23 CH17
10 1 Gnd
To QH01 10
RH27 To
Collector of High Voltage Stops
27K Anodes
ABL Switch Output Transistor H. Drive
PPS2 PPD2 RH29
QH03 IH01
To Focus
ABL Switch 47K
2 2 ABL Pull-Up ABL OVP
Resistors 3
RH30 7
RH28 56K CH14 DH14
ABL SWITCH
Active When Side Bars RH26
Power [ Current Path ]
Supply are Black Only 150K DP24
180K All Others RH25
PWB
DH16 RD30EB4
RH32 12K DP24
Sw +9V 18K DP26, DP27/D
6.8K RH09 CH10
Clamp 33K DP23
RH31
XRay Protect
3 3 RH24
As Brightness goes Up, ABL Voltage 30K DP24 DH15
goes Down. (Inverse Proportional) CH18 43K DP26, DP27/D HZ22-2L
PAGE 03-14
33K DP23
DP-2X ABL SWITCH FOR 4X3 DISPLAY WITH BLACK SIDE BARS MODE ONLY
SW+9V PPS2 PPD2
I401 RG58 ABL Switch

ABL Switch
DAC 2 36 2 2 Gray Side Bars Black Side Bars
ABL Switch
RC84
QH03 Off QH03 On
Power
Supply 115V
RAINFOREST IC SIGNAL PWB PWB
ABL SWITCH QH03 RH27

New for this chassis is the ability to change the brightness level of ABL SWITCH 27K
the Side Panels when watching a NTSC 4X3 image. When a 4X3 Active When Side Bars
images is displayed on a 16X9 set, the sides do not reach the are Black Only
edges. To avoid excessive ageing at the 4X3 display area, the side
panels IRE levels are raised. However, sometimes the customer RH29
may want to turn the side gray panels off. Through the Video 47K
RH28
Advanced features Menu the customer can now do this. When the QH03 56K
R745 RH30
Side panels are turned off, the overall average ABL level for the
image is reduced. To compensate, QH03 ABL Switch is added.
When the customer selects Black Side panels, the Microprocessor
I001 tells the Rainforest IC I401 via I2C communication to output a
high from the DAC2 line pin 36. This high is routed through the
PPS2 connector pin 2 on the Signal PWB to the Power Supply
PWB. Then from the PPD2 connector pin 2 on the Power Supply
PWB to the PPD2 connector on the Deflection PWB and finally to
the base of QH03 turning it On. ABL From
ABL
With QH03 turned on, the Resistor RH29 connected to the collector 3 Flyback
To PPD2 pin 3
is added to the ABL pull up circuit and the ABL level drops slightly to Pin 3
PAGE 03-15
compensate for the side panel loss of brightness.
DP-2X AUDIO VIDEO MUTE CIRCUIT EXPLANATION
(See DP-2X Series Chassis Audio Video Mute Circuit Diagram for details)
There are times in which the main picture and audio must be muted. This can be because of changing channels
where the noise between stations is unacceptable, same thing for Auto Programming channels. When the deflec-
tion circuit malfunctions, etc…
All this is done primarily to prevent damage to the CRTs or to external amplifiers or speakers connected to the
projection television.
MICROPROCESSOR OUTPUT:
The Microprocessor outputs V. Mute from pin 49 when changing channels, Auto Programming, etc… This high
is routed to the Video Mute circuit and to the Audio Mute circuit.
VIDEO MUTE PATH.

The High from pin 49 is routed to D412 to the base of Q442. The following action will be labeled MUTE ACTI-
VATION for here forward, please use the below explanation when Mute Activation is mentioned.
MUTE ACTIVATION:
When Q442 turn on, the collector pulls the base of Q441 low and turns it on. It’s collector is connected to the
HVcc 9V line through R551 and D411. When Q441 turns on, it’s collector goes high. This is routed to two
places. Through R441, D402, and R439 and into the Rainforest IC pin 24 of I401. This pin is also the same pin
that FC H Blk and FC V Blk is input. Generally this input is a positive going pulse that blanks the video during
the peak pulses. However, when the DC component is forced high by the action of Q411 turning on, this pin goes
high and mutes the output of RGB.
The other route for the high from Q411 is through R548 to the base of Q440. This transistor turns On and outputs
the high from it’s collector out it’s emitter to mute the Audio described later.
Another circuit attached to the Mute Activation circuit is AC Loss Detection.

AC LOSS DETECTION:
AC is monitored by the AC Loss detection circuit. The AC input from I903 to PPS3 pin (1) on the Power Supply
PWB is routed and rectified by D416. This charges up C561 and through D415 to charge C467. When AC is first
applied, C467 charges slightly behind C561 preventing activation of Q445. If AC is lost, C561 discharges rap-
idly pulling the base of Q445 low, however D415 blocks C467 from discharging and the emitter of Q445 is held
high. This action turns on Q445 and produces a high on it’s collector. This high is routed to the base of Q442.
See the Mute Activation circuit explained previously.
SPOT:
SPOT is generated from the deflection PWB when either Horizontal or Vertical deflection is lost. This is to pre-
vent a horizontal or vertical line from being burnt into the CRTs. See Horizontal and Vertical Sweep Loss Detec-
tion circuit and explanation and circuit diagram for details. This high is input from PPD2 pin (4), through PPS2
pin (4), D413 to the base of Q442. See the Mute Activation circuit explained previously.
H Blk Loss Det:

If the Horizontal Blanking signal is loss to the Signal PWB, Q444 will detect the loss. Normally, Q444 is sup-
plied with H. Blanking on it’s base. By the activity of the pulse charging C466, the base of Q443 and it’s emitter
are held high. If H. Blk is lost, then C466 will discharge through R558. C465 is blocked by D414 and it holds the
emitter of Q443 high. This action turns on Q443 and supplies a high to the base of Q442. See the Mute Activa-
tion circuit explained previously.
See next page for continuation of Audio Mute Circuit explanation.
PAGE 03-16
DP-2X AUDIO VIDEO MUTE CIRCUIT EXPLANATION
AUDIO MUTE PATH: Labeled as V MUTE 2:

See the Mute Activation circuit explained previously.
When Q441 collector is high, the base of Q440 is high. This turns it on and supplies a high from the emitter.
This high is routed to the following circuits;
OUT TO HI-FI MUTE PATH: Labeled as V MUTE 2:

The high from Q440 is routed to DA03 anode. Then DA01, and DA02 fire and supply the high to the bases of
QA07 and QA08. These in turn ground out the audio for Out to Hi-Fi audio output jacks.
Also, the high from the Microprocessor pin 71 to I007 (in pin 7 at 3.3V and out pin 13 at 5V) to the anode of
DA04 causes the same results.
MONITOR MUTE PATH: Shown going to the Terminal PWB. Labeled as V MUTE 2:
The high from Q440 is routed to PST2 pin 9. On the terminal board is an exact same circuit as describe in the
Out to Hi-Fi Mute Path above. So the actual circuit is not show here, just the description. The high from the
PST2 connector is then sent to the anode of DX03. Then to DX01, and DX02 fire and supply the high to the
bases of QX01 and QX02. These in turn ground out the audio to the Monitor Out jacks.
Also, the high from the Microprocessor pin 49 to I007 (in pin 3 at 3.3V and out pin 17 at 5V) to the same circuit.
CRT MUTE PATH: Shown going to the CRT PWB. Labeled as V MUTE 1:
The high from Q440 is routed to PSC pin 11. This high goes to Q8C1 base. This turns on and supplies a ground
to the following diodes, D8A3 on the Blue CRT PWB, D853 on the Green CRT PWB, D803 on the Red CRT
PWB. When the diodes are supplied with a ground on their cathodes, they remove the base voltage fro the RGB
drivers, Q8A3, Q853, and Q803 on the Blue, Green and Red CRT PWBs.
FRONT AUDIO OUT HARD MUTE PATH: Labeled as V MUTE 2:

The high from Q440 is routed to DA08. The high continues to the base of QA11. When this transistor turns on, it
supplies a Lo to pin 11 of IA03 and hard mutes the Audio Out. (Note: This is not the same thing as the Mute se-
lected from the customer’s remote. This is supplied by the Front Audio Control IC and functions in three states,
No Mute = 100%, 1/2 Mute = 50% and Full Mute = 0%. Also, the high from the Microprocessor pin 49 to I007
(in pin 3 at 3.3V and out pin 17 at 5V) to the same circuit.
FRONT AUDIO OUT MUTE and A MUTE PATH: Labeled as V MUTE 2 and A MUTE:
The high from Q440 is routed to DA05. The high continues to the base of QA19, and QA10.
When these transistor turns on, they in turn ground out the audio going into the Audio Output IC, Right audio in
pin 4 of IA03, Left audio in pin 2 of IA03
A MUTE: Also, the high from the Microprocessor pin 71 to I007 (in pin 7 at 3.3V and out pin 13 at 5V) to the
anode of DA06 and on to the same circuit.
Ft Spk Off: (Front Speaker Off) Also, the high from the Microprocessor pin 72 to the anode of DA07 and on to
the same circuit.
PAGE 03-17
DP-2X Series Chassis AUDIO and VIDEO MUTE Circuit
NOTE: FC H Blk FC V Blk

V MUTE 1 becomes V MUTE Q412 Q411
V MUTE 2 on Signal PWB 2 & 3 10V p/p R441 D402
24 I401
Then V MUTE 1 again on CRT PWB
D412 R439 Rainforest
Q445 HVcc 9V
See explanation PSC R442
AC Sig Q443 PPS2 PPD2
for details
R557 8 8 H Blk
V MUTE 1 11
Q444 R559
R560
R563
R561
CRT PWB
R555
R556
R511 D416 D415
See explanation PST2 D417
for details C465
R562 C467 Deflection
V MUTE 2 9 C561 D414
C466 R558 PWB
Terminal PWB D413
HVcc 9V 4 4 Spot
R554
JA01 R551 D411
CA03 CA04
R Right Q441 C464 R553 "SPOT"
CA08 R550
L Left Horizontal Sweep Loss Det.
QA07 DA01 DA03 Q440 Vertical Sweep Loss Det.
CA07 R510 (From Deflection PWB)
Out To
Hi-Fi RA27 DA04 See Sweep Loss Detection
R548 Q442 Circuit Diagram for details
QA08 RA28 DA02 V MUTE 2
Micro Processor
RA50 Mute = Lo
I001 QA11 11 Mute
SPK OFF DA09 RA48
Ft Spk Off 72 CA64 IA03
V MUTE 1 RA49
CA63B CA60
V MUTE 49 3 CA56
I007 17
Level 19 4 R In R Out 7
DA08 IA04 Right CA57
Shift Ft. Audio 6 2 L In L Out 12
A MUTE 71 7 13 Left QA10 CA59
A MUTE F. Spk Off DA07
RA45 FRONT L & R
V Mute 2 DA05 Audio Output
A Mute DA06 QA09
RA44
PAGE 03-18
DP-23, DP-23G, DP-26, DP-27 and DP-27D CHASSIS DVI SIGNAL PATH (Not DP-24)
All of these pins are ground
B+ IJ01 4 10 12 16 21 25
DVJ 1 2 2 1
SiI907B 28 33 35 43 45 50 PET
DVI CONN
DJ22 3 DJ21 3 DVIH
1 49 RX2- HSync 18 9 DVIH
RX2- DVIV
RX2+ 2 48 RX2+ VSync 19 11 DVIV
GND2/4 3 B+ DVIR QJ01
1 2 2 1 IOR 23 3 DVIR
RX4+ 4 26
DVIG QJ02 5
IOG DVIG
RX4- 5 DVIB QJ03
DJ24 3 DJ23 3 B+
SCL 6 1 2 2 1 IOB 31 7 DVIB
SDA 7 40
DVIDET QJ06 12
SCDT DVIDET
VSYNC 8 DJ25 3 DJ26 3
9 52 RX1- AVcc 1
RX1-
RX1+ 10 51 RX1+ AVcc 7
B+
GND1/3 11 1 2 2 1 Vcc 13 2 GND
RX3+ 12 DJ27
DJ28 DVcc 17 4 GND
RX3- 13 3 3
Vcc 22 6 GND
5V 14
GND 15 DACVccR 24 8 GND
HTPIUG 16 DACVccG 27 10 GND
RX0- 17 3 RXO- DACVccB 32
13 GND
RX0+ 18 2 RXO+ DACVcc 37
GND0/5 19 QJ08
Vcc 38
RX5+ 20
RX5- 21 DVcc 41
GNDC 22 Vcc 46 LJ15
TXC+ 23 5 RXC+ 1
Reset 39 4 IJ04 5 3 IJ07 1 SW+5
TXC- 24 6 RXC-
C1 (R) 25 DJ29
2
15 14 Reset 3 14 NC
C2 (G) 26
C3 (B) 27 15 NC
C4 (H) 28 DJ05 DJ06 LJ17
8 2 5
C5 (GND) 29
IJ02 IJ0A 1
C5 (GND) 30
NDC7002N NDC7002N 3
DJ04DJ02 7 5 6 6
SCL 4 SDA
Mode DJ01
PAGE 03-19
DP-2X COMPONENT SYNC CIRCUIT EXPLANATION
(See DP-2X Series Chassis Main/Component Sync Separation Signal Path for details)
This diagram shows the route for sync utilized when the set has selected Component inputs.
IX02 Main Y Pr/Pb Selector:

The Component inputs are Component 1 at pin 59 and Component 2 at pin 5. The Y component for NTSC is in-
put at pin 53.
Main Y Output from IX02:

The Y component from the selected source is output at pin 44. Then through QX22 to the Main Video Chroma
Y Pr/Pb Switch IZ02 pin 30 and pin 6. After internal separation, the H Sync is output at pin 17 and the V. Sync is
output at pin 15.
H. Sync from IZ02 pin 17:

This is routed through the transistor QZ14 then to the connector PST1 pin 1. From here it is split. One route is
into the PFC1 pin 8 connector on the Flex Converter U303 called M H In (Main Horizontal In). The Flex Con-
verter uses this signal for a timing signal as it performs it’s conversions.
The other route from the PST1 connector pin 1 is to pin 13 of the Sync selector IC I402. If the control line at pin
11 is high, this H. Sync is routed out pin 14 to pin 16 of the Rainforest IC I401. This sync is used if the set is re-
ceiving a true 1080i signal and the Flex Converter is bypassed.
V. Sync from IZ02 pin 15:
This is routed through the transistor QZ18 then to the connector PST1 pin 2. From here into the PFC1 connector
pin 7 on the Flex Converter U303 called M V In (Main Vertical In). The Flex Converter uses this signal for a
timing signal as it performs it’s conversions.
PinP (Sub) Y Output from IX01:

The Y component from the selected source is output at pin 50. Then through QX19 to the Sub Video Chroma Y
Pr/Pb Switch IZ01 pin 30 and pin 6. After internal separation, the H Sync is output at pin 17 and the V. Sync is
output at pin 15.
H. Sync from IZ01 pin 17:

This is routed through the transistor QZ13 then to the connector PST2 pin 28. From here it is routed into the
PFC1 pin 15 connector on the Flex Converter U303 called S H In (Sub Horizontal In). The Flex Converter uses
this signal for a timing signal as it performs it’s conversions.
V. Sync from IZ01 pin 15:
This is routed through the transistor QZ15 then to the connector PST2 pin 29. From here into the PFC1 connec-
tor pin 14 on the Flex Converter U303 called S V In (Sub Vertical In). The Flex Converter uses this signal for a
timing signal as it performs it’s conversions.
I402 Sync Selector to the Rainforest IC I401:

One route for the H. Sync for the Main Picture is from the PST1 connector pin 1 is to pin 13 of the Sync selector
IC I402. If the control line at pin 11 is high, this H. Sync is routed out pin 14 to pin 16 of the Rainforest IC I401.
This sync is used if the set is receiving a true 1080i signal and the Flex Converter is bypassed.
The other route is for Horizontal Sync from the Flex Converter U303 pin 7 of PFC2. This Horizontal Sync signal
is called HD Out (Horizontal Digital Output, meaning that the signal has gone through the Digital manipulation
within the Flex Converter). This signal is routed to pin 12 of I402. If the control line at pin 11 is Low, this H.
Sync is routed out pin 14 to pin 16 of the Rainforest IC I401. This sync is used if the set is using a signal that has
been processed by the Flex Converter.
Vertical Sync from the Flex Converter U303 to the Rainforest IC I401:
The other route is for Vertical Sync from the Flex Converter U303 pin 6 of PFC2. This Vertical Sync signal is
called VD Out (Vertical Digital Output, meaning that the signal has gone through the Digital manipulation within
the Flex Converter). This signal is routed to pin 15 of the Rainforest IC I401. This sync is used no matter what
source, because all vertical timing is the same.
PAGE 03-20
DP-2X SERIES CHASSIS MAIN/COMPONENT SYNC SEPARATION SIGNAL PATH
15 VD In
16 HD In
I401
14 Rainforest IC
Control
X
I402 Lo Hi
11 28 Sync SW
From 3 D Y/C
12 13 IZ02 3, 4, 5 IX02
4 S-In
Main Y
Main Main
YPr/Pb 2 Main Y YPr/Pb
PFC2 PFC1 PST1 Selector Selector
HD Out QZ14 D Sync2 In 6 From
M H In HD-Out
7 U303 8 1 17 H Sync QX22 Main 3 D Y/C
VD Out FC4 M V In VD-Out D Sync1 In 30 44 Y Out 2
6 7 2 15 V Sync 53 DVI Y
YOut Unit Main
QZ18 Component Y
16 5
PBOut
From 3 D Y/C Component 2 Y
18 IZ01 S-In 3, 4, 5
4 59
PROut Main Y
Sub
20 Component 1 Y
YPr/Pb 2 Sub Y
See DP-2X Chassis PST2 Selector
QZ13
Flex Converter
Video Signal Path D Sync2 In 6
S H In HD-Out QX19 Sub
15 28 17 Sub H Sync
NTSC,
S V In VD-Out D Sync1 In 30 50 Y Out 1
Component, OSD 14 29 15 Sub V Sync
Sub
QZ15
Component Y
PAGE 03-21
AUDIO
INFORMATION
DP-2X
CHASSIS DIAGRAMS
SECTION 4
DP-2X AUDIO CIRCUIT EXPLANATION
(See DP-2X Chassis Audio (Main-Terminal) Signal Path for details)
IX01 AUDIO VIDEO SELECTOR IC:

The main Audio path is delivered to the Audio/Video Selector IC IX01 to the following pins;
62 (Left) and 64 (Right): This is the Audio input from the Main Tuner U301. The integrated Tuner has an Inter-
nal Audio decoding circuit that outputs Lt (Left Total) from pin 26 and Rt (Right Total) from pin 27. The Left
continues through the PST1 connector pin 21 and the Right continues to pin 20. They arrive at IX01 pins 62 and
64 respectively.
2 (DM-Left) and 4 (DM-Right): This is the Audio input from the ATSC Tuner UD2002. The Digital Tuner has
an Internal Audio decoding circuit that outputs Lt (Left Total) from pin 10 and Rt (Right Total) from pin 9. The
Left continues through the PST1 connector pin 25 and the Right continues to pin 26. They arrive at IX01 pins 2
and 4 respectively. The Digital Module (ATSC Tuner) is only available on the DP-26 chassis).
59 (Left) and 61 (Right): This is the Audio input from Auxiliary 1 input. This audio is associated with component
input 1 and with DVI input. (DVI is not available on the DP-24 chassis).
29 (Left) and 31 (Right): This is the Audio input from Auxiliary 2 input. This audio is associated with component
input 2 which also accepts composite video on the Y jack.
16 (Left) and 18 (Right): This is the Audio input from Auxiliary 3 input, composite or S-In only.
9 (Left) and 10 (Right): This is the Audio input from Auxiliary 4 input, composite or S-In only.
23 (Left) and 25 (Right): This is the Audio input from the front Auxiliary 5 input, composite or S-In only. These
inputs are delivered through the PFT connector pins 4 and 5 respectively.
MONITOR OUTPUTS:
38 (Left) and 40 (Right): This is the Monitor Audio Outputs.
LEFT and RIGHT OUTPUTS:

43 (Left) and 35 (Right): This is the Left Total and Right Total output which represent the Audio associated with
the Main picture. The Lt and Rt represent the fact that the Audio has any Dolby ® encoding still embedded.
The outputs are then routed through the PST1 connector pins 10 (Left) and 9 (Right) to the Center Select IC I005
pins 2 and 12 respectively. I005 is responsible for selecting the audio input from the Center Jack when the cus-
tomer has set the television to operate in TV as Center Mode. The Center audio is routed to pins 1 and 13. The
control switching signal is provided by the Microprocessor I001 pin 61 through the inverter QA16 to pin 10 and
11. A low on these pins with switch to receive inputs from the main L and R and a high on these pins will place
the IC into the Center mode.
The audio from I005 leaves pin 15 Left and 14 Right and into the Audio Control IC IA01.
IA01 AUDIO CONTROL IC: MODE LOGIC

Pin 12 Pin 13
This IC is responsible for controlling the audio Surround formats as well as volume, Mode1 Mode2
bass, balance, treble and customer mute. The Microprocessor outputs I2C bus control SRS LOGIC (NJM2198) IA02
lines from pin 28 (SCL) and 31 (SDA) to pin 14 and 13 respectively. Dependant upon BYPASS (SRS OFF) L L/H
the Surround mode selected the audio is interfaced with IA02 which acts as the BBE/ SRS STEREO H L
SRS IC. The control pins for IA02 are listed in the table to the right. SRS MONAURAL H H
The Audio is output from pin 8 (L) and 23 (R) to IA04 which buffers the audio and BBE LOGIC (NJM2155) IA04
outputs on pin 6 (L) and 19 (R) to two different circuits. Primary route is to the Audio MODE LOGIC ON OFF
Output IC IA03 pins 2 (L) and 4 (R) and out pin 12 (L) and 7 (R) to the speaker plugs BBE (Pin 8) H L
PL and PR. MACH3 (Pin 11) H L
The Secondary route from IA04 is to the Out to Hi-Fi jacks.
(See the Audio Video Mute circuit for details on the Mute transistors operation and control).
PAGE 04-01
DP-2X Chassis Audio (Main-Terminal) Signal Path
SIGNAL PWB JA01
SIGNAL PWB PST1
SEL Center In
C
TV Main R I005
27 20 64 OUT
U301 Tuner Audio Hi 10
TV Main L 1
Main Tuner 26 21 62 L Y MODE 1 IA02
15 30 Left 8 BBE
Left Out 43 10 2 Lo 18 12 BBS/
R Lo 11 SRS 11 Mach3
UD2002 DM R Right Out 45 9 12 X1 MODE 2
9 26 4 Digital 14 1 Right Pin 12 Pin 13
ATSC Tuner 13 17 13
DM L Hi MODE LOGIC
10 25 2 Tuner Audio QA16 Mode1 Mode2
DP-26 ONLY
BBEout R 27 23 RIn SRS LOGIC (NJM2198) IA02
TV as Center
IX01 61 BYPASS (SRS OFF) L L/H
A/V Select =L SCL BBEout L SRS STEREO H L

QX30 I001 4 24 LIn
Aux 1 Left 28 14 SRS MONAURAL H H
59
Component 1 or BBE LOGIC (NJM2155) IA04
V1 QX31 Micro SDA
Aux 1 Right DVI (Not DP24) Tone R In 26 15 ROut
MODE LOGIC ON OFF
61 31 13
T
QA14 BBE (Pin 8) H L
o
Tone L In 5 16 LOut MACH3 (Pin 11) H L
Aux 2 Left Mach3 57
29 I
Component 2 QA13 A
V2 Aux 2 Right Composite 2 BBE 63 0 IA01 HiFi Out
31 2
Audio Control QA03
Left R
Aux 3 Left 6 1 8 L Out
16
Composite 3 IA04 Right
V3 Aux 3 Right S-In 3 19 24 23 R Out QA04 QA05
18 L
Aux 4 Left
QA07
9 QA06
Composite 4
V4 Aux 4 Right S-In 4 QA08
11 See AV Mute
Circuit Diagram PR
-
+ 7 2
PFT
4 FR (WO) Out
Aux 5 Left
4 23 CA81 4
Composite 5 See AV Mute
V5 Aux 5 Right S-In 5 Circuit Diagram QA09 FR (TW) Out
5 17
25 IA03
PL
Front Control PWB FL (WO) Out
-
+ 12 2
Monitor Out Left 2 CA76
38 4
MON See AV Mute QA10
MON Monitor Out Right Circuit Diagram FL (TW) Out
40 OUT Front Audio Out
SIGNAL PWB TA8258H
TERMINAL PWB
PAGE 04-02
DEFLECTION
INFORMATION
DP-2X
CHASSIS DIAGRAMS
SECTION 5
DP-2X HORIZONTAL DRIVE CIRCUIT EXPLANATION
HORIZONTAL DRIVE CIRCUIT DIAGRAM DESCRIPTION:

(Use the DP-2X Horizontal Drive Circuit Diagram for details)
CIRCUIT DESCRIPTION
When B+ arrives at the Rainforest IC I401 pin (19), horizontal drive is output from pin (26). The drive signal is
routed through the connector PSS2, PPD2 pin 8 to the Horizontal Driver Transistor Q709. This transistor
switches the ground return for pin (8) of the Driver transformer (T702). SW+28 volts is supplied to pin (5) and
this switching allows EMF to develop. As this signal collapses, it creates a pulse on the output pin of (T702) at
pin (4) to the base of the Deflection Horizontal output transistor Q777. This transistor provides primary switch-
ing pulses for the Deflection Transformer T701.
Q777 TRANSISTOR PRODUCES THE FOLLOWING OUTPUT PULSES;
1. The Dynamic Focus OUT Circuit to QF01: A Dynamic Focus waveform, (Horz. Parabola) is created.
This is a parabolic waveform that is superimposed upon the static focus voltage to compensate for beam
shape abnormalities which occur on the outside edges of the screen because the beam has to travel fur-
ther to those locations.
2. Horizontal Deflection Yokes drive signals. The collector of Q777 provides the drive signal for all
Horizontal Deflection Yokes.
T701 TRANSFORMER PRODUCES THE FOLLOWING OUTPUT PULSES;

• Deflection H. Pulse from pin (7): This pulse is used by;
HORIZONTAL BLANKING (H. BLK) GENERATED FROM PIN (7):

The Horizontal Pulse is also routed to the Horizontal Blanking generation transistor Q706. This transistor gener-
ates the 13V P/P called H Blk. This signal goes to the following circuits;
• To the PPD2, PPD2 connector pin 8 to pin (24) of I401 as FBP In. Here this signal is used as a comparison
signal. It is compared to the reference signal coming in at pin (16) Horizontal Sync. If there are any differ-
ences between these two signals, the output Drive signal from pin (26) is corrected.
NOTE: When a 1080i signal is input through component inputs, the Rainforest IC detects this as well
and outputs the ABL Switch signal from pin (36). (See ABL Switch Circuit Diagram for details). The
Reference signal for Horizontal Sync now becomes the Y input from component, pin (8).
• The H Blk signal is routed from here to the the Microprocessor which uses this signal for OSD positioning
and for Station Detection during Auto programming within the coincidence detector, also as a detection sig-
nal to activate the AFC Loop.
The PinP unit uses this signal for switching purposes. Like the read/write clock, positioning, etc…
• Through the PDG connector pin 14 to the Convergence circuit for correction waveform generation.
• Through CN01 to the Sweep Loss Circuit (QN01) to shut off the drive to the CRTs if Horizontal deflection
is lost.
HORIZONTAL DRIVE FOR THE HIGH VOLTAGE:
• The Horizontal Blanking signal H Blk from Q706 is also sent to the High Voltage Driver IC IH01 pin (3).
This IC uses this signal as its reference signal to produce the High Voltage Drive waveform output from pin
(1). This output is routed to the driver transistors, QH02. Then to the High Voltage Horizontal Output Tran-
sistor QH01. This transistor switches the primary of the Flyback transformer TH01. Deflection SW +115 is
sent through pin (9) and output pin (10) to the collector of the Horizontal Output Transistor QH01.
A sample of the High Voltage is output from the Flyback transformer TH01 pin (12). This voltage is sent to pin
(9) of the High Voltage Driver IC IH01. This voltage is compared to the reference voltage available at pin (12).
PAGE 05-01
DP-2X HORIZONTAL DRIVE CIRCUIT EXPLANATION
If there is a difference between the two voltages, an error voltage is generated and output from pin (10) and input
again at pin (11) where it manipulates the PWM (Pulse With Modulation) signal producing the Horizontal Drive
signal output from pin (1).
It’s important to notice that the High Voltage circuit can not function without the Horizontal Deflection circuit
providing a drive signal.
GENERAL INFORMATION:
The DP-2X deflection circuit differs from analog Hitachi projection televisions. It utilizes in a sense, two hori-
zontal output circuits. One for Deflection and one for High Voltage. This allows for better deflection stabilization
and is not influenced by fluctuations of the High Voltage circuit which may cause unacceptable breathing and
side pulling of the deflection.
PAGE 05-02
DP-2X SERIES CHASSIS HORIZONTAL DRIVE CIRCUIT
Power Power H. Def. Yoke R
To Micro. for OSD, Auto Prog, SD, AFC,
Supply PPS3 Supply
PWB HVcc 9.3V PWB H. Def. Yoke G
I401 VCC 19 9
PPD2 PPS2
H. Def. Yoke B
8 8 Osc.
SW HVcc
24 FBP In HVCO 21 3
H.Blk. X401 To Dynamic Focus QF01
Y2 In 8 1080i I910
6 6 26 H Out Through Mode
H. Sync In
2
H Out HD1 In 16
From Flex T701 Def.
Power H Pulse
Converter
Signal PWB Rainforest IC On/Off 7
8
R735 Q709 T702 2
8 4 1
R748
D709 D715 5 1 Q777
SW +28V R748
C725 Q701
SW + 115V
6
Q706 Side Pin Modulator
PPD6 TH01
H.Blk. 9 High
See Voltage and Waveform IH01 SW +115V 9
Horizontal Voltage
Chart on next page. 10
RH07 Gen Output
3 QH02
Drive QH01
PDG DH04 1
10
To Convergence
14 Com1
Circuit PPD3
RH01 RH02 Ref. V.
SW +9V 2 12 E
CN01 11 r
DH01 CN01 r
To H. Sweep Loss HV Sample
Det. Circuit QN01 10 o 9
r 12
FB In DH05 RH22
PAGE 05-03
DP-2X IH01 HIGH VOLTAGE DRIVER IC WAVEFORM AND VOLTAGES
IH01 NORMAL OPERATION:

Pin 1 = 6.80V with Color Bar,
Varies with Brightness levels. 9 10 11 12 13 14 15 16
Pin 2 = 11.72V Gnd
Pin 3 = 0.59V + REF
Pin 4 = 2.47V
+
-
Pin 5 = 1.60V -
-
Pin 6 = 10.58V -
+
Pin 7 = 0.0V
Pin 8 = 0.0V UVP OVP POUT AGC GEN UVLO
Pin 9 = 4.90V
Pin 10 = 0.03V 8 7 6 5 4 3 2 1
Pin 11 = 0.03V
Pin 12 = 4.90V
Pin 13 = 0.05V
Pin 14 = 2.02V Pin 1 12V P/P 33.75Khz
Pin 15 = 4.96V
Pin 16 = 0.0V
Pin 3 4.5V P/P 33.75Khz
Pin 4 3V P/P 33.75Khz
IH01 NOT RUNNING: NOT RUNNING EXPLANATION:

This situation can happen and possibly lead the Service Technician
Pin 1 = 12.28V off on the wrong path.
Pin 2 = 11.86V Take a quick look at the voltages for pin 3 and 14. This is the key.
Pin 3 = 3.96V These two pins tie back to the Horz. and Vert. Sweep Loss Detec-
Pin 4 = 3.5V tion Circuit.
Pin 5 = 1.089V (See page 05-05 for the Sweep Loss Detection Circuit Diagram).
Pin 6 = 0.021V If the Sweep Loss circuit is activated, it outputs a high from QN02.
Pin 7 = 0.0V This high is used to shut off the CRT to prevent CRT burn, How-
Pin 8 = 0.0V ever, the Collector of QN02 is also routed to these two pins through
diodes DN09 to pin 14 and DN10 to pin 3.
Pin 9 = 0.019V
When QN02 goes high, it drives pin 3 and 14 high which turns off
Pin 10 = 0.038V the internal oscillator of IH01 via pin 3. This action stops Horizontal
Pin 11 = 0.038V Drive to the High Voltage circuit. This action causes pin 1 to satu-
Pin 12 = 4.90V rate and it goes High.
Pin 13 = 0.05V Note that pin 14 is tied to an internal op-amp (-) leg. This cause the
Pin 14 = 4.59V output to stop. So no Horizontal Drive is allowed to pass to the out-
Pin 15 = 4.96V put amp. connected to pin 1.
Pin 16 = 0.0V
PAGE 05-04
DP-2X SWEEP LOSS DETECTION CIRCUIT EXPLANATION
(See DP-2X Sweep Loss Detection Circuit for details)

The key component in the Sweep Loss Detection circuit is QN02. This transistor is normally biased off. When
the base becomes 0.6V below the emitter, it will be turned on, causing the SW +9V to be applied to two different
circuits, the Spot circuit and the High Voltage Drive circuit.
SPOT ACTIVATION CIRCUIT

When QN02 is turned on, the SW +9V will be applied to the anode of DN11, forward biasing it. This voltage
will then pass through DN11. It will then be clamped by DN12, and arrive at pin 4 of PPD2, PPS2. It will then
be directed to the Signal PWB where it will pass through D413 and activate the Video Mute circuitry Q442 -
Q441. This is done to prevent CRT burns. (See DP-2X Audio Video Mute Circuit for details)
A control (enable) circuit for SPOT is routed from pin 5 of PPS2, PPD2 called “CUT OFF”. This will activate
when accessing certain adjustments parameters in the service mode; i.e. turning off vertical drive for making
CRT drive or cut-off adjustments. When Vertical Drive is defeated, the Vertical Sweep loss circuit would acti-
vate. Cut Off is produced from the Microprocessor I001 pin 47 and routed to QN06 to “inhibit” the Spot line
from activating and shutting off the CRTs.
HIGH VOLTAGE DRIVE CIRCUIT

When QN02 is turned on, the SW +9V will also be routed through RN15 and DN09 and applied to the High
Voltage Drive IC IH01 at pin 14. When this occurs, the IC will stop generating the drive signal that is used to
produce High Voltage via QH02, the High Voltage Driver. Again, this is done to prevent CRT burn, especially
during sweep loss.
This high is also routed through RN16, DN10 to pin 3 of IH01 which also kills the internal drive.
CONCERNING QN02
There are several factors that can cause QN02 to activate; loss of vertical or horizontal blanking.
Loss of Vertical Blanking (V Blk)

The Vertical pulse at the base of QN05 switches ON05 on and off at the vertical rate. This discharges CN03 suf-
ficiently enough to prevent the base of QN04 from going high to turn it on and activate QN02.
When the 24 Vp/p positive vertical blanking pulse is missing from CN04 to the base of QN05, it will be turned
off, which will cause the collector to pull up high because CN03 charges up through RN11. This in turn will
cause QN04 to turn on because it’s base pulls up high, creating an increase of current flow from emitter to collec-
tor and through RN09. RN08, (which is located across the emitter base junction of QN02), to the SW +9V sup-
ply. This increase of current flow through RN08 will bias on QN02 and the events described in “Spot Activation
Circuit” above will occur.
Loss of Horizontal Blanking (H Blk)

The Horizontal pulse at the base of QN01 switches ON01 on and off at the horizontal rate. This discharges CN02
sufficiently enough to prevent the base of QN03 from going high to turn it on and activate QN02.
When the 11.6 Vp/p positive horizontal blanking pulse is missing from CN01 to the base of QN01, it will be
turned off, which will cause the collector to go high through DN03, RN02 as the SW +9V charges CN02 . This
in turn will cause QN03 to turn on because it’s base is pulled up high when DN02 fires. When QN03 turns on, an
increase of current flow from emitter to collector, through RN10, and up through RN08. This increase of current
flow through RN08 will bias on QN02 and the events described in “Spot Activation Circuit” above will occur.
PAGE 05-05
DP-2X SWEEP LOSS DETECTION CIRCUIT
DN13
SW+9V
RN09
RN12 RN11
From Power
Vertical Blanking DN08 Supply Circuit
From Pin 11 I601 QN05 QN04 Diagram
RN13
V. Blk. CN03
DN06 SW+7V
CN04
RN14 DN07
DN14
24V P/P
RN18
RN02 RN08
CN02 RN03
QN02
DN03
RN10 High Voltage

DN02 Driver IC
Horizontal Blanking RN06
From Q706 Emitter IH01
QN01
DN01 QN03
H. Blk. 14 Stops
Drive
CN01 RN04 RN15 DN09
RN05 RN01
11.6V P/P
H. Blk
PPS2 PPD2
RH07
DN11 DN10
Prevents CRT Burn Stops
SPOT 4 4 3 Osc
RN16
To Q442 DN12
DN04
Signal Stops High Voltage
3of 3 Drive Signals From
See A/V being produced
MUTE when Sweep Loss is
Circuit detected.
RN17
CUT OFF 5 5 QN06
When Vertical Drive Spot Inhibit
From I001 is turned Off during
Micro adjustment, I 2C.
Pin 47
PAGE 05-06
DP-2X VERTICAL OUTPUT CIRCUIT EXPLANATION
(See the DP-2X Series Chassis Vertical Output Circuit for details)
I601 B+:
The Vertical Output IC I601 requires SW+28V to operated. This voltage is supplied from the Power Supply. The
output for the SW+28V pulse is from pin 14 of T902. This power supply is protected by E902, rectified by
D918, filtered by C929, L913, C950 and output from the PPD6 connector pin 1 and 2. It arrives at the Deflection
PWB and is routed through the Vertical B+ Excessive Current Sensor R629, Q604 to pin 10 of I601.
TRIGGER PULSE:
The Trigger pulse is routed from the Rainforest IC I401 pin 27 on the Signal PWB. It is output from the PPD2
connector pin 10, through the Power Supply PWB and then through the PPS2 connector pin 10 to the Deflection
PWB. It is then sent to the Trigger Input on I601 pin 3.
During Trace, the internal Ramp Generator circuit using C603 connected to pin 7 as the time constant begins
charging. As it charges, the Pump Up circuit is also charging from the SW+28V to C605, through pin 11 to an
internal switch of I601. When the Trigger pulse arrives (Retrace Time), the internal switch toggles over to the
output stage push pull pair inside I601, and the +28V charged capacitor C605 discharges. The output stage push
pull pair inside I601 already have +28V input from pin 10. So the output pulse from pin 1 is now near 50V p/p.
This is only needed for a short duration of time, (retrace) so the Charge Pump circuit eliminates the need for a
50V power supply.
(V BLK) VERTICAL BLANKING PULSE GENERATION:

When the Charge Pump discharges and produces the 50V p/p pulse for Vertical drive during retrace, this pulse
from pin 11 is also routed out as the Vertical Blanking pulse. It’s amplitude is around 21V p/p and is sent to the
following circuits;
• Vertical Sweep Loss detection circuit
• Convergence circuit for vertical correction waveform generation
• To the PPS2, PPD2 connector pin 12 to be sent to various circuits on the signal PWB. The Micro-
processor uses this signal to time it’s OSD.
VERTICAL OUTPUT PULSE:

The Vertical Output pulse is then routed to the Vertical Yokes generating a linear sawtooth current which moves
the beam. (Trace = from top to bottom, Retrace = from bottom to top). This linear current is generated by the
charge time constant of the vertical yokes charging C607 through the low ohm resistors R619, R620.
VERTICAL YOKE CHARGE PULSE:

The pulse generated on the positive side of C607 is also routed through the parabolic wave form generation cir-
cuit of R621, and C608 to the side pincushion circuit and to the dynamic focus circuit for corrections to deflec-
tion and focus.
The pulse generated on the positive side of C607 is also routed back to I601 pin 8 and 9. The AC component of
this signal is for vertical linearity compensation. The DC component of this signal and the DC component pro-
vided by the Vertical size pot into pin 4 are routed back to the Ramp generator circuit described above. The DC
component determines the charge time associated with the ramp generator or in other words, the Vertical height.
D SIZE SWITCH:
When Magic Focus is activated by either the Magic Focus button or customer’s menu or during service when the
sensors are initialized, Q603 receives the D Size command from the Digital Convergence Unit, UKDG pin 15 of
PDS connector. When Q603 turns on, it bypasses R611 and lowers the resistance from R607 (Vertical Size Pot)
to ground. This increases the Vertical size to allow positive contact of the light pattern hitting the sensors.
PAGE 05-07
DP-2X SERIES CHASSIS VERTICAL OUTPUT CIRCUIT
PMB
X Ray Power V+
To Micro. for OSD Positioning Protect Supply PWB 2
R626
Main V-
I401 PPS3 28V 1
PPS2 PPD2 8 Y Direct
R632 V. Def. Yoke B
VCC 55 9 D608 Q604
12 12 HVcc PMG
V.Blk. V+
HVCO 21 2
Osc. R631 C610 R627
V Drive V-
V. Sync In
1
10 10 27 VP Out
VD1 In 15 - + R629 V. Def. Yoke G
From Flex
Converter R630 0.68
Signal PWB
PMR
Power + V+
Supply I601 C604 R628 2
PWB 6 Gnd Vs 10 - L601 L602
V-
D603 1
R625 V. Def. YokeR
R622 C609
R602 V OUT 1
Trigger
3 Output D606
Input 2
D601 Stage Vs + D604 D605
C605
To Conv. -
Ramp Flyback
Circuit 7 Gen 11 D607
Gen
R605
To Vertical C603 Inverting
Input
9
Sweep Loss
Detection Circuit
5 NC R604 R617
V.Blk. Buffer
Out
8
C602 R616 R621
R606 To Side Pin
R614 R611 + + + Cushion Circuit
V OUT C606 C607 To Dynamic
- - 2200/25 - C608
Focus Circuit
Hight
R613 Adj
4
Q603 R619 R620
1.2 ohm 1.2 ohm
D Size
R607 V Size R608 R618 V.Blk.
PAGE 05-08
DP-2X SIDE PINCUSHION CIRCUIT EXPLANATION
(See the DP-2X Side Pincushion Circuit for details)
Due to the nature of deflection, the sides of the picture has a tendencies to pull in similar to an hour glass. The
Side pincushion circuit is responsible for manipulating deflection to compensate. This is accomplished by super
imposing a vertical parabolic waveform on the DC voltage utilized for Horizontal Size.
VERTICAL YOKE CHARGE PULSE: (See Vertical Output Circuit for details)
The pulse generated on the positive side of C607 is routed through the parabolic wave form generation circuit of
R621, and C608 to the side pincushion circuit.
SIDE PIN WAVE FORM GENERATION IC:

Then through R742, C702, R709 to pin 6 of I701. This is the positive leg of the internal op-amp. Also attached
to this input circuit is the Horizontal Size circuit comprised of R710, R711, R713 and clamped by D714. The
variable resistor R711 which adjust the DC level at pin 6. The negative leg of the op-amp is connected through
pin 5 to the feedback circuit from the Side Pin Cushion output circuit for stability.
The output of the DC offset voltage with Vertical parabolic wave form attached is then routed out pin 7 to the
base of Q703. This transistor has it’s emitter off set above ground by D713, R747 back to the SW +9V and
R704. This transistor drives the base of the Side Pin Cushion modulator transistor Q701. The collector of Q701
is connected to the Deflection SW +115V. The DC offset voltage and Vertical parabolic side pin cushion com-
pensation wave form is now super imposed on the SW +115V which is sent to the Deflection Transformer T701
and the Horizontal Linearity circuit C715, L703, R729 to the Horizontal Yoke returns.
D SIZE SWITCH:
When Magic Focus is activated by either the Magic Focus button or customer’s menu or during service when the
sensors are initialized, Q710 receives the D Size command from the Digital Convergence Unit, UKDG pin 15 of
PDS connector. When Q710 turns on, it bypasses R714 and lowers the resistance from the emitter of Q701 to
ground. This increases the Horizontal size to allow positive contact of the light pattern hitting the sensors.
X-RAY PROTECT:
If something should fail within the Side Pincushion circuit that could cause a CRT burn, the voltage at pin 7 of
I701 is monitored by D702. If this zener fires because the voltage at it’s cathode increases above a specified
level, D703 would forward bias and send a Shut Down command through the Protect line.
(See Deflection Protect Power Supply Shut Down Circuit Diagram for details.)
PAGE 05-09
DP-2X SIDE PINCUSHION CIRCUIT DIAGRAM
SW +115V SW +9V
D702 D703
R706 R717
X-RAY Protect
R707 C701
Q701 V Parabolic
C701 C722 R709 C702
R721 R742
SW+11V
R708
R712 R710
D701
4.39V 5.17V 5.14V
R701 8.96V 8 7 6 5
Q703
R711
I701 -
H Size
R702 + D714
R747 Adj
R704
+
R713
-
D713
R703
1 2 3 4
Sensor Initialize = Hi
Q710 Magic Focus = Hi
T701
R714 D SIZE Deflection Horizontal Driver To Q705
R715 6 7 H. Blk Generator
Q777
1 8
To H. Deflection Yokes
To H. Linearity off H. Yoke Returns

L704, L705
PAGE 05-10
C715 L703 R729
DIGITAL
CONVERGENCE
INFORMATION
DP-2X
CHASSIS DIAGRAMS
SECTION 6
DP-2X DIGITAL CONVERGENCE INTERFACE CIRCUIT EXPLANATION
See DP-2X Chassis Digital Convergence Interconnection Circuit Diagram for details.
The Digital Convergence circuit is responsible for maintaining proper convergence of all three colors being pro-
duced by the CRTs. Many different abnormalities can be quickly corrected by running Magic Focus.
The Digital convergence Interconnect Diagram depicts how the Digital Convergence Circuit is interfaced with
the rest of the Projection’s circuits. The main components and/or circuits are;
• THE DIGITAL CONVERGENCE UNIT (DCU)
• INFRARED REMOTE RECEIVER
• ON SCREEN DISPLAY PATH
• CONVERGENCE OUTPUT STKs
• CONVERGENCE YOKES
• MAGIC FOCUS SENSORS AND INTERFACE
• MICROPROCESSOR
• RAINFOREST IC (Video Processor).
• SERVICE ONLY SWITCH
• MAGIC FOCUS activation by Magic Focus Switch on Front Control Panel or customer’s Menu.
THE DIGITAL CONVERGENCE UNIT (DCU) (8 Sensor array).

The DCU is the heart of the Digital convergence circuit. Held within are all the necessary components for gener-
ating the necessary waveforms for correction, and associated memories for the adjustment data and Magic Focus
Data.
Sensors (X8)
Technician's Eye
SCREEN
Adjust through observation
M
IR
Light
RO
R
Stored during Initialize
Stored Light Sensor Data
Remote EEPROM Timing
Control 2K Bit Controller
Data Comparator Serial-Parallel

between stored data A/D Sensor PWB
and light sensor data Converter
H
R
Error Data G
Infra-Red Decoder CRT B
V
To Video Circuits Digital Cross
Via O.S.D. Hatch Gen. Timing CY CLAMP
Displays CrossHatch Controler
2nd S/H
CLAMP
1st S/H
LPF
D/A
256 Adjusted One Chip CPU
Points
Per/Color Serial/Parallel
8 bit Converter
128 Kbit X1 X6 X6 X6 X6
117 Points Per/Color
SLOW
Addressable Gate Array 4000 gates
by EEPROM Calculation of other 139 points per/color
Technician (2Kbit)
S-RAM INTERPOLATION DIGITAL
Also available; (256Kbit)
FAST CONVERGENCE
35 Adjustment Points Back Up
9 Adjustment Points CIRCUIT
117 Points Per/Color D/A Conv.

Static Centering
AC Applied, Copy from EEPROM, then caculations will be made. Time, approx. 20 sec.
Figure 1
The Block above shows the relationship of the DCU to the rest of the set. Note that the light being produced by
the CRTs is what is used by the sensors for Magic Focus. This allows the DCU to make adjustments regardless of
circuit changes, magnet influence or mechanical, by actually using the light on the screen to make judgments.
EEPROM AND SRAM SHOWN IN FIGURE 1: (8 Sensor Array).

Each color can be adjusted in any one of 117 different locations. The internal workings of the DCU can actually
make 256 adjustment points per color. These adjustment points are actual digital data stored in memory. This
PAGE 06-01
data represents a specific correction signal for that specific location. When the Service Technician makes any
adjustment, the new information must be stored in memory, EEPROM. The EEPROM only stores the 117 differ-
ent adjustment points data, the SRAM interpolates to come up the additional 139 adjustment points for a total of
256 per color. The EEPROM data is slow in relationship to the actual deflection raster change. The SRAM is a
very fast memory. So, during the first application of AC power, the EEPROM data is read and the SRAM makes
the interpolation and as long as power remains, interpolation no longer has to be made.
This can be seen during an adjustment. If the Interpolation key is pressed on the remote control, what is happen-
ing is that the SRAM must make those additional calculations beyond the 117 made by the Servicer and this is all
placed into memory.
INFRARED REMOTE CONTROL INPUT SHOWN IN FIGURE 1:

As can be seen in Figure 1, the Infrared Remote control signals actually manipulate the internal data when the
Service Only Switch is pressed on the Deflection PWB. This process actually prevents the Microprocessor from
responding to Remote commands, via a Busy line output from the DCU.
INTERNAL CONTROLLER, D/A CONVERTERS SHOWN IN FIGURE 1:

The internal controller, takes the stored data and converts it to a complicated Convergence correction waveform
for each color. The Data is converted through the D/A converter, 1st and 2nd sample and hold, the Low Pass Fil-
ter that smoothes out the parasitic harmonic pulses from the digital circuit and the output Clamp that fixes the DC
offset level.
The DC offset voltage is adjusted by several things.
• Raster Centering. The Raster Centering adjustment actually moves the DC offset voltage for Horizontal
and Vertical direction. This Offset voltage will move the entire raster Up or Down, Left or Right.
When a complete Digital Convergence procedure has been performed and the adjustment information stored in
memory by pressing the PIP Mode button twice (2), it is mandatory to run Sensor Initialization.
If Sensor Initialization is not performed, the set will not allow Magic Focus to operate. If the Magic Focus button
is pressed, the screen will display an adjustment grid instead.
This is done by pressing the PIP-MODE button on the remote once (1), then pressing the PIP CH button. This
begins a preprogrammed generation of different light patterns. Magic Focus memory memorizes the characteris-
tics of the light pattern produced by the digital convergence module. If a convergence touchup is required in the
future, the customer simply presses the Magic Focus button on the front panel or activates it from the customer’s
menu and the set begins another preprogrammed production of different light patterns. This automated process
duplicates the same light pattern it memorized from the initialization process, re-aligns the set to the memorized
convergence condition. Note that this process is using “Light” as it’s source. This is a better process than using
waveforms or voltages as it is adjusting using the actual light pattern as see by the customer.
“MAGIC FOCUS” SENSORS SHOWN ON FIGURE 1:

This process is a joint effort between the digital convergence module and 8 Photo-sensors, physically located on
the middle edges of the cabinet and the centers of the top and bottom, just behind the screen. The physical place-
ment of the sensors assures that they will not produce a shadow on the screen that can be seen by the customer.
Magic Focus is activated by pressing the Magic button inside the front control panel door or by the Customer’s
Menu. An on-screen graphic display pattern will be displayed to confirm that the automatic convergence mode
(Magic Focus) has begun.
The digital convergence module produces different patterns for each CRT, and the sensors on the side of the
cabinet pick up the transmitted light and generate a DC voltage. This voltage is sent to the DCU and converted to
digital data and compared with the memorized sensor initialization data. Distinct patterns will be generated in
each primary color. As the process continues, the digital module manipulates the convergence correction wave-
forms that it is producing to force the convergence back into the original memorized configuration.
When all cycles have been completed, the set will return to the original signal and the convergence will be cor-
rected. In most cases, activating the Magic Focus will allow the set to correct itself, without further adjustments.
PAGE 06-02
EXPLANATION OF THE DIGITAL CONVERGENCE INTERCONNECT DIAGRAM:

INFRARED RECEIVER:
During normal operations, the IR receiver directs it signal to the Main Microprocessor where it interprets the in-
coming signal and performs a predefined set of operations. However, when the Service Only Switch is pressed,
the Main Microprocessor must ignore remote control commands. Now the DCU receives theses commands and
interprets them accordingly. The Microprocessor is notified at pin 42 when the DCU begins its operation by the
BUSY line. As long as the BUSY line is active, the Main Microprocessor ignores the IR signal.
NOTE: All chassis but the DP-24 has two IR Receivers. This allows operations of remote from any angle.
NOTE: The DP-24 only has one IR Receiver.
ON SCREEN DISPLAY PATH:

MICROPROCESSOR SOURCE FOR OSD:
The On Screen Display signal path is shown with the normal OSD information such as Channel Numbers, Vol-
ume Graphic Bar, Main Menu, Service Menu, etc… sent from the Main Microprocessor pins 34, 33 and 32 to the
Rainforest IC I401 pins 37, 38 and 39. These are positive going pulses, about 5 V p/p and about 3uS in length
dependant upon there actual horizontal time for display.
DCU (Digital Convergence Unit P/N CS00591) SOURCE FOR OSD:

The DCU has to produce graphics as well. When the Service Only switch is pressed, the Main Microprocessor
knows the DCU is Busy as described before. Now the On Screen Display path is from the DCU pins 22, 21 and
20 to the Rainforest IC I401 pins 33, 34 and 35.
The output for the DCU OSD characters is output through the PPG connector pins (20 Dig Red, 21 Dig Green
and 22 Dig Blue). These are routed through their buffers (QK06 Dig Red, QK07 Dig Green and QK08 Dig
Blue) to the PPD1, PPS1 connector pins (2 Dig Red, 4 Dig Green and 5 Dig Blue). Then through their buffers,
(Q422 Dig Red, Q421 Dig Green and Q420 Dig Blue). Then it arrives at the Rainforest IC I401 at pins (35 Dig
Red, 34 Dig Green and 33 Dig Blue). When a character pulse arrives at any of these pins, the internal color amp
is saturated and the output is generated to the CRTs. Any combination for these inputs generates either the pri-
mary color Red, Green or Blue or the complementary color Red and Green which creates Yellow, Red and Blue
which creates Magenta or Green and Blue which creates Cyan.
OUTPUT STKs:
These are output amplifiers that take the correction waveforms generated by the DCU and amplify them to be
used by the Convergence Yoke assemblies for each color.
RV is Red Vertical Convergence correction. Adjust the location either up or down for Red.
RH is Red Horizontal Convergence correction. Adjust the location either left or right for Red.
GV is Green Vertical Convergence correction. Adjust the location either up or down for Red.
GH is Green Horizontal Convergence correction. Adjust the location either left or right for Red.
BV is Blue Vertical Convergence correction. Adjust the location either up or down for Red.
BH is Blue Horizontal Convergence correction. Adjust the location either left or right for Red.
CONVERGENCE YOKES:
Each CRT has a Deflection Yoke and a Convergence Yoke assembly. The Deflection manipulates the beam in
accordance to the waveforms produced within the Horizontal Deflection circuit or the Vertical Deflection circuit.
The Convergence Yoke assembly manipulates the Beam in accordance with the correction waveforms produced
by the DCU.
MAGIC FOCUS SENSORS AND INTERFACE: (8 Sensor Array).

Each of the eight photo cells, called solar batteries in the service manual, have their own amps which develop the
DC potential produced by the photo cells. Each amp is routed through the PDS1 connector and arrives at the PDS
connector on the DCU where the DCU converts this DC voltage to Digital signals. These digital signals are used
only when the Magic Focus Button is pressed and Magic Focus runs or during Initialization of the sensors.
PAGE 06-03
MICROPROCESSOR:
The Microprocessor is only involved in the Digital Convergence circuit related to disabling IR (Infrared Remote
Control Signals). When the DCU is put into the Digital Convergence Adjustment Mode (DCAM) or Magic Fo-
cus, the Microprocessor ignores IR pulses. This is accomplished by the BUSY signal from the DCU. The BUSY
signal is routed from the DCU out the PDG connector pin 19, to the PDD1 connector pin 1, then the PPS1 con-
nector pin 1 to the Microprocessor I001 notifying that the DCU is busy.
RAINFOREST IC (Video Processor).

The Rainforest IC, I401 is only involved with the Digital Convergence circuit related to OSD and Velocity
Modulation inhibit during Digital convergence OSD operation in which it inhibits the Luminance from the main
video.
SERVICE ONLY SWITCH:

The Service Only Switch is located just in front of the DCU on the Deflection PWB. If the front speaker grills are
removed and the front access panel is opened, the switch will be on the far left hand side. When this button is
pressed with the TV ON, the DCU enters the Digital Convergence Adjustment Mode.
If the button is pressed and held down with the TV OFF and the power button is pressed, the Digital Conver-
gence RAM is cleared. This turns off any influence from the DCU related to beam deflection. Magnetic centering
is performed in the mode as well as the ability to enter the 3X3, (9 adjustment points) mode.
MAGIC FOCUS SWITCH:

• Located on the Front Control panel is the Magic Focus switch. When Magic Focus is activated by the cus-
tomer pressing this switch, the DCU enters the “MAGIC FOCUS” adjustment mode described earlier.
• When the Customer presses the Magic Focus Switch, the low is sent to the Microprocessor I001 pin 45. The
Microprocessor then communicates with I007 pin 8 (Level Shift) and it outputs a low on pin 12 (Magic Sw).
This low is routed through the PPS1, PPD1 connector pin 6 to the DCU connector PDS pin 1. This starts the
Magic Focus function.
• Also the Magic Focus can be started from the Customer’s Menu. When selected by the customer, the same
communication is performed to I007 (Level Shift) and a low is sent out pin 1 to the DCU to start Magic Fo-
cus.
CONVERGENCE MUTE:
IK02 is the convergence mute IC. When the +28V line collapses when power is turned off, it’s possible that the
output STKs could be damaged. To prevent this, IK02 monitors the +28V line. If it falls too low, pin 3 will out-
put a Mute signal to pin 21 of connector PDS on the Digital Convergence Unit.
DIGICON ADJUST:
This year, the Digital convergence can be adjusted by the customer. This is accessed from the Video Menu and
selecting Magic Focus. Under the Magic Focus menu, select Manual. (See below). They have access to the 117
adjustment points for Red and Blue. (Green is fixed as reference).
However, if after adjusting using Video this process, the customer can no
longer use Magic Focus as it will Magic Focus return the set to it’s original condi-
tion.
Aligns the Red, Green, and Blue
colors to correct for Magnet
Influences.
Adjustment Mode
Auto
Manual
If you want to adjust now START
Move Sel Select
PAGE 06-04
DP-23, 23G, 26, 27 & 27D CHASSIS "DIGITAL CONVERGENCE" INTERCONNECTION CIRCUIT DIAGRAM
I001 Rainforest I401
MAG SW In
45 Magic Sw In Q417 PSC
OSD B
OSD B 34 37 OSD B B Q428
OSD G Q418 41 5 B
11 9 56 Digicon OSD G 33 38 OSD G
I007 Adj Q419
OSD R
3.3V-5V OSD R 32 39 OSD R G Q433
12 8 44 Magic Sw Out Dig OSD B Q420 42 7 G
33 Dig OSD B
Digicon
To CRTs
42 Main Dig OSD G Q421

BUSY Busy In 34 Dig OSD G R Q438
Up Dig OSD R Q422 43 9 R
IR In 35 Dig OSD R
80 IR
49 YS3 RGB
MAG SW Out
Signal PWB BUSY
5 ~ 11 Not Used PCB

BUSY PDS +28P 10 CYV+
1, 3 & 12 Gnd 18 1
PPS2 PPD2 5 BV
SK01 Service Only PDG BV + - CYV-
1 1 13 15 16 3
Sw Adj CYH+
18 UKDG IK05 11 6
Magic Focus Dig Adj
PPS1 PPD1 BH
1 13 CS00591 + - CYH-
BUSY BUSY BH
14 14 13 4
To Blue Convergence Yokes
SM09 1 1 19
5 Dig R QK06 Dig R "DCAM"
Ft. Control 2 2 20 GH 9
Digital Convergence 17 6 GH
PWB IR-In IR-In Adjustment Mode
PCG
8 3 3 17 + -
QK07 7
Dig G Dig G 6
7 4 4 21 11 N/C
Dig B QK08 Dig B 17 8 12 4 CYH+
5 5 22 Digital 10 4
PFS MAG SW 6 6 MAG SW CYH-
H Blk 14 Convergence 12
PFI
7 7 D Size 15 Unit 22 Deflection -28P
1 2 3
Stby V Blk 16 "DCU" PWB
EFI
QM07 +5V
Power From QK01 -5V 2 3
QM06 Signal Supply From IK01 +5V 4 17 8 12 4 CYV-
PWB PWB "Mounted on
1 Deflection 18 1
To Green Convergence Yokes
1 2 GV CYV+
3 PWB" GV + -
IR Out PDS1 12 16 15 16 PCR
HMO2 3 Sensor +5V IK04 CYV+
IR Receiver PWB 1 +5V Digital PDS 11 1
MAG SW RV
2 From IK01 1 RV + - CYV-
PFR GND Gnd 19 14 13 3
3 10
1 2 3
S7 4 S7 2 CYH+
9 4
EFR S6 S6 RH
5 3 RH
LED S5 S5 + - CYH-
1 2 6 4 20 6 7 6
S0 ~S7 S4 S4
IR Out 7 5 10 5
8 Total S3 S3
To Red Convergence Yokes
HMO3 3 8 6 Normal "Lo"

Sensors
IR Receiver S2 9 S2 7 Mute
S1 10 S1 8 21 3 IK02 1 +28V
S0 11 S0 9 RK22 RK23
2 RK24
S0 12 DK53
PAGE 06-05
DP-24 CHASSIS "DIGITAL CONVERGENCE" INTERCONNECTION CIRCUIT DIAGRAM
I001 Rainforest I401

MAG SW In
45 Magic Sw In Q417 PSC
OSD B
OSD B 34 37 OSD B B Q428
OSD G Q418 41 5 B
11 9 56 Digicon OSD G 33 38 OSD G
I007 Adj Q419
OSD R
3.3V-5V OSD R 32 39 OSD R G Q433
12 8 44 Magic Sw Out Dig OSD B Q420 42 7 G
33 Dig OSD B
Digicon
To CRTs
42 Main Dig OSD G Q421

BUSY Busy In 34 Dig OSD G R Q438
Up Dig OSD R Q422 43 9 R
IR In 35 Dig OSD R
80 IR
49 YS3 RGB
MAG SW Out
Signal PWB BUSY
5 ~ 11 Not Used PCB

BUSY PDS +28P 10 CYV+
1, 3 & 12 Gnd 18 1
PPS2 PPD2 5 BV
SK01 Service Only PDG BV + - CYV-
1 1 13 15 16 3
Sw Adj CYH+
18 UKDG IK05 11 6
Magic Focus Dig Adj
PPS1 PPD1 BH
9 13 CS00591 BH + - CYH-
BUSY BUSY 14 14 13 4
To Blue Convergence Yokes
SM09 1 1 19
5 Dig R QK06 Dig R "DCAM"
Ft. Control 2 2 20 Digital GH 9
17 6 GH
PWB IR-In IR-In Convergence PCG
2 3 3 17 + -
Adjustment 7
Dig G QK07 Dig G Mode 6
3 4 4 21 11 N/C
Dig B QK08 Dig B 17 8 12 4 CYH+
5 5 22 Digital
QM05 10 4
PFS MAG SW 6 6 MAG SW CYH-
H Blk 14 Convergence 12
7 7 D Size 15 Unit 22 Deflection -28P
Stby V Blk 16 "DCU" PWB
QM01 +5V
Power From QK01 -5V 2 3
Signal Supply From IK01 +5V 4 17 8 12 4 CYV-
PWB PWB "Mounted on
1 Deflection 18 1
To Green Convergence Yokes
1 2 GV CYV+
3 PWB"
IR Out GV + -
PDS1 12 16 15 16 PCR
HMO1 3 Sensor +5V IK04 CYV+
IR Receiver PWB 1 +5V Digital PDS 11 1
MAG SW RV
2 From IK01 1 RV + - CYV-
GND Gnd 19 14 13 3
3 10
S7 4 S7 2 CYH+
9 4
S6 5 S6 3 RH
LED RH + - CYH-
S5 6 S5 4 20 6 7 6
S0 ~S7 S4 S4
7 5 10 5
8 Total S3 S3
To Red Convergence Yokes
Sensors 8 6 Normal "Lo"

S2 9 S2 7 Mute
S1 10 S1 8 21 3 IK02 1 +28V
S0 11 S0 9
RK23
2
PAGE 06-06
S0 DK53 RK24
12
DP-23, DP-23G & DP-24 REMOTE CONTROL CLU-4321UG
(p/n HL01831)
POWER
ROM READ TV CBL/SAT DVD/VCR
(Read Old ROM Data)
ROM WRITE
SWAP PIP MODE

PIP FREEZE
RASTER POSITION
PIP CH
VIDEO MENU
REMOVE COLOR
INITIALIZE
ADJUSTMENT SELECT
MUTE LAST CH
EXIT
CROSSHATCH /
VIDEO
VOL CH (5 Times)
CURSOR UP
CURSOR DOWN 1 2 3
CURSOR LEFT 4 5 6 CURSOR RIGHT
7 8 9
BLUE Select
GREEN Select
13X9 Mode ANT 0 INFO
3X3 Mode (5 Times)
(5 Times)
RED Select
VID1 VID2 VID3 VID4 7X5 Mode (5 Times)
REC ASPECT VIRTUAL HD
VID5
CALCULATION
PHASE HITACHI *VCR MODE ONLY
CLU-4321UG
PAGE 06-07
DP-26 REMOTE CONTROL CLU-5721 TSI (P/N HL01821)
POWER
TV VCR CBL SAT
SOURCE WIZARD
CURSOR UP DVD AV1 AV2 AV3
CURSOR DOWN
1 2 3
7 8 9
RED (7 X 5)
RASTER PHASE
SLEEP 0 INFO
GREEN (3 X 3)
A/V NET GUIDE ASPECT
ANT C.S.
BLUE (13X9)
CROSSHATCH
U EXIT
REMOVE MEN VIDEO
COLOR
CORRECTION
VOL SELECT CH
BUTTONS
MUT T CH
SV E LAS
CS HD
SC
VID
1 5
VID
VID 4
2 VID
VID 3
CALCULATE PIP PIP CH FREEZE CENTERING

RASTER
INITIALIZE PIP ACCESS POSITION
PIP-MODE SWAP VIDEO
PIP MODE +
PIP CH
READ OLD
ROM DATA
WRITE TO PRESS (2X)
ROM
REC
PRESS
(2X)
HITACHI
CLU-5721TSI
PAGE 06-08
DP-27 & DP-27D REMOTE CONTROL CLU-5722 TSI (P/N HL01822)
POWER
TV VCR CBL SAT
SOURCE WIZARD
CURSOR UP DVD CD TAPE AMP
CURSOR DOWN
1 2 3
7 8 9
RED (7 X 5)
RASTER PHASE
SLEEP 0 INFO
GREEN (3 X 3)
C.C. A/V NET ASPECT V
ANT IRT UAL H
D
BLUE (13X9)
CROSSHATCH
U EXIT
REMOVE MEN VIDEO
COLOR
CORRECTION
VOL SELECT CH
BUTTONS
MUT T CH
SV
CS
E LAS HD
SC
VC
VID RP /T V
1 LU IDE 5
S+ GU VID
VID 4
2 VID
VID 3

RASTER
PIP-MODE SWAP VIDEO
PIP MODE +
PIP CH
READ OLD
ROM DATA
WRITE TO PRESS (2X)
ROM
REC
PRESS
(2X)
HITACHI
CLU-5722TSI
PAGE 06-09
NOTE: Aspect may not be correct but dimensions are correct.
DIGITAL CONVERGENCE OVERLAY DIMENSIONS
43 inch
OVERLAY DIMENSIONS NORMAL MODE
952
17 76.5 76.5 76.5 76.5 76.5 H. SIZE 76.5 76.5 76.5 76.5 76.5 17
25.7
34.5
69.1
69.1
69.1 R B
535
69.1
69.1 Centering Offset
69.1 PART NUMBER H312271

34.5
25.7
V. SIZE RED OFFSET = 25mm VERTICAL SIZE = 460mm

BLUE OFFSET = 30mm HORIZONTAL SIZE = 870mm
43FWX20B DP-24 Chassis
PAGE 06-10
46 inch
1018
18.2 81.8 81.8 81.8 81.8 81.8 H. SIZE 81.8 81.8 81.8 81.8 81.8 18.2
25.7
37.0
74.0
74.0
74.0 R B
573
74.0

37.0
27.5

46F500 DP-23K Chassis
PAGE 06-11
51SWX20B, 51UWX20B, 51GWX20B, 51XWX20B
1129
19.7 90.8 90.8 90.8 90.8 90.8 H. SIZE 90.8 90.8 90.8 90.8 90.8 19.7
30.5
41.0
82.0
82.0
82.0 R B
635
82.0

41.0
30.5

DP-26 & 27/27
HORIZONTAL SIZE = 1040mm
51UWX20B DP-23 Chassis

51GWX20B DP-23G Chassis
NOTE: DO NOT USE THE HORIZONTAL SIZE

MARKERS ON THE OVERLAY FOR DP-26 & 27.
THESE HAVE BEEN CHANGED. VALUE SHOWN IS CORRECT.
51SWX20B DP-27 Chassis

51XWX20B DP-26 Chassis
PAGE 06-12
57SWX20B, 57TWX20B, 57UWX02B, 57GWX20B, 57XWX20B
1262
22.0 101.5 101.5 101.5 101.5 101.5 H. SIZE 101.5 101.5 101.5 101.5 101.5 22.0
34.1
45.8
91.7
91.7
91.7 R B
710
91.7

45.8
34.1

DP-26 & 27/27/27D


MARKERS ON THE OVERLAY FOR DP-26, 27 & 27D.

57TWX20B DP-27D Chassis
PAGE 06-13
65SWX20B, 65TWX20B, 65XWX20B
1439
25.3 115.7 115.7 115.7 115.7 115.7 H. SIZE 115.7 115.7 115.7 115.7 115.7 19.7
38.6
52.1
104.6
104.6
104.6 R B
809
104.6

52.1
38.6



PAGE 06-14
ADJUSTMENT
INFORMATION
DP-2X
CHASSIS DIAGRAMS
SECTION 7
DP-2X CHASSIS ADJUSTMENT ORDER
It is necessary to follow an order when doing adjustments in the DP-2X chassis.
DP-2X SERVICE ADJUSTMENT ORDER “PREHEAT BEFORE BEGINNING”

Order Adjustment Item Screen Format Signal DCU Data
Pre HEAT (30 Minutes) Normal Mode NTSC N/A
1 Cut Off Normal Mode NTSC N/A
2 DCU Phase Data Setting Normal Mode NTSC N/A
3 Horz. Position Adj. (Coarse) Normal Mode NTSC N/A
4 Raster Tilt Normal Mode NTSC CLEAR
5 Beam Alignment Normal Mode NTSC CLEAR
6 Raster Position Normal Mode NTSC CLEAR
7 Vertical Size Adjust Normal Mode NTSC CLEAR
8 Horz. Size Adjust Normal Mode NTSC CLEAR
9 Beam Form Normal Mode NTSC N/A
10 Lens Focus Adjust Normal Mode NTSC N/A
11 Static Focus Adjust Normal Mode NTSC N/A
12 DCU Character Set Up Normal Mode NTSC N/A
13 DCU Sensor Position Normal Mode NTSC N/A
14 Convergence Alignment Normal Mode NTSC CLEAR
15 Sensor Initialize Normal Mode NTSC N/A
16 Blue Defocus Normal Mode NTSC N/A
17 White Balance Adjustment Normal Mode NTSC N/A
18 Sub Brightness Adjustment Normal Mode NTSC N/A
19 Sub Picture Adjustment Normal Mode NTSC N/A
20 Horz. Position Adjust (Fine) Normal Mode NTSC N/A
Note: To enter the Service I2C Menu;

1. Power should be Off
2. Press and Hole the “INPUT” button on the front control panel.
3. Press the “POWER ON” button while still holding the “INPUT “ button.
4. When the power on LED lights, release both buttons.
5. Use the Cursor Up/Down to navigate.
6. Use the Cursor Right/Left button to manipulate the Data Values within the Adjustment.
PAGE 07-01
DP-2X CHASSIS PRE-HEAT RUN ADJUSTMENTS
PRESET EACH 3. Focus VR on focus pack.

ADJUSTMENT VR TO Pre Set fully clockwise.
CONDITION AS SHOWN:
FOCUS VR
1. Before Pre Heat Run.
Enter I2C Service Menu.
Pre-set the Green DRV Allow set to operate at
and Red DRV to 3F. This least 30 Minutes before
is considered “Center” beginning adjustments.
position.
(With power Off, press the
INPUT button on front
panel and then press the
POWER ON button then
release. The Service Menu
is displayed.)
2. SCREEN VR ON
FOCUS PACK.
Pre Set fully counter SCREEN VR
clockwise.
Screen VR
R G B
Focus VR
R G B
FOCUS PACK
Projection Front View
RED CRT GREEN CRT BLUE CRT
PAGE 07-02
DP-2X CHASSIS CUT-OFF (SCREENS) ADJUSTMENT
ADJUSTMENT 2) Set R DRV (COOL) to 8) Repeat for the other two

PREPARATION: center data value (3F). colors.
• Pre Heat Run should be 3) Set G DRV (COOL) to 9) Exit SERVICE by press-
finished. center data value (3F). ing the cursor on remote to
• Be sure Screen Color 4) Set R, G, and B CUTOFF the left [◄ ].
Temperature setting is in (COOL) data settings to 10)Exit SERVICE MENU by
the COOL mode on Cus- [80]. pressing the MENU key
tomer’s Menu. 5) Adjust Screen VRs on Fo- on remote.
• Room Light should be cus Pack fully counter
minimal. clock wise.
6) Choose SERVICE item [1]
ADJUSTMENT of I2C ADJ. Mode. Select
PROCEDURE: CURSOR RIGHT [X] and
1) Go to I2C ADJ. Mode. the Vertical will collapses.
(With power Off, press the 7) Adjust any Screen VR.
INPUT button on front Screen VR should be
panel and then press the turned clockwise gradually
POWER ON button then until that particular color
release. The Service Menu is barely visible.
is displayed.)
Screen VR
R G B
Focus VR
R G B
FOCUS PACK
PAGE 07-03
DP-2X CHASSIS PRE-FOCUS ADJUSTMENT
ADJUSTMENT 2) Adjust the Focus VR for

PREPARATION: Red until Focus is
A) Pre Heat Run should be achieved. (A Fine Adjust- NOTE:
• PTSR connector on RED
finished. ment will be made later.)
CRT PWB.
3) Repeat for Blue and • PTSG connector on GREEN
FOCUS ADJUSTMENT: Green. CRT PWB.
1) Short the 2pin sub- • PTSB connector on BLUE
miniature connector on the CRT PWB.
CRT PWB (PTS), to
remove any color not
being adjusted and adjust
one color at a time. (The
adjustment order of R, G
and B is just an example.)
Screen VR
R G B
Focus VR
R G B
FOCUS PACK
PAGE 07-04
DP-2X CHASSIS DCU CROSSHATCH PHASE ADJUSTMENT
Adjustment Preparation: adjustment mode). *DCA stands for (Digital

• Cut Off adjustment should 6) Adjust data value using Convergence Adjustment)
be finished. the keys indicated in the
• Video Control: Brightness chart, until the data
90%, Contrast Max. matches the values indi-
cated in the chart.
Adjustment Procedure:
NORMAL MODE Exiting Adjustment Mode:
1) Receive any NTSC signal. 7) Press AV NET key on
2) Screen Format is Normal remote control.
3) Press the SERVICE 8) Press PIP MODE key
ONLY switch on the De- TWICE to store the
flection/Power PWB to information.
enter DCAM. 9) When Green dots are
4) Press the A/V NET key displayed, press the
on the Remote, Green MUTE key twice to re-
Cross hatch appears. turn to DCAM grid.
5) Then press the EXIT key.
(This is the Phase
PHASE MODE Display Format

NORMAL
ADJUST USING Address Data
Value
4 and 6 keys on Remote PH-H CD
2 and 5 keys on Remote PH-V 04
Cursor Left and Right on Remote CR-H 35
Cursor Up and Down on Remote CR-V 0A
PAGE 07-05
DP-2X CHASSIS HORIZONTAL PHASE (COARSE) ADJUSTMENT
Adjustment Preparation: 4) Mark the center of the NOTE: To enter the I2C Bus
• Video Control: Brightness Digital Convergence alignment menu, with Power
90%, Crosshatch Pattern with Off, press the INPUT button
• Contrast Max. finger. and hold it down, then press
5) Press the SERVICE the POWER button and re-
Adjustment Procedure ONLY switch to return to lease. I2C adjustment menu
NORMAL MODE: normal mode. will appear.
6) Enter the I2C Service
1) Receive any NTSC cross- Menu and select Item H
hair signal. POSI and adjust the data
2) Screen Format is NOR- so that the center of
MAL. Video matches the loca-
3) Press the SERVICE tion of the Digital Cross-
ONLY switch on the con- hatch pattern noted in step
vergence PWB and dis- {4}.
play the Digital Conver- 7) Exit from the I2C Menu.
gence Crosshatch pattern.
PAGE 07-06
DP-2X CHASSIS TILT (RASTER INCLINATION) ADJUSTMENT
Adjustment Preparation: Adjustment Procedure : BLUE:

• The set can face any direc- GREEN: 6) Remove cover or PTS
tion. 1) Apply covers to the RED short from BLUE and
• Receive the Cross-Hatch and BLUE lenses or short cover the RED CRT.
Signal the 2P Sub Mini connector Align BLUE with
• VIDEO CONTROLS: Fac- [PTS] on R&B CRT PWB GREEN.
tory Preset. to produce only GREEN. 7) [+/- 1mm tolerance when
• SCREEN FORMAT: should 2) Turn the Green deflection compared to Green]
be NORMAL mode. yoke and adjust the TILT
• The lens focus should have until the green is level.
After Completion:
been coarse adjusted. 3) [+/- 2mm tolerance]. See8) Tighten DY Yoke Screws
• The electrical focus should diagram. to 12+/-2 kg-cm.
have been coarse adjusted. 9) REMOVE ALL COVERS
• The Digital Convergence RED: or SHORTS on the PTS
RAM should be cleared. 4) Remove cover or PTS connectors.
(Turn power off, press and short from RED CRT and 10)Turn the power off.
hold the SERVICE ONLY align RED with GREEN.
switch on the Convergence 5) [+/- 1mm tolerance when
PWB, then press the compared to Green]
POWER button).
l =< 2mm
Vertical Center axis of

Cross-Hair signal
PAGE 07-07
DP-2X CHASSIS BEAM ALIGNMENT ADJUSTMENT
Preparation for adjustment: 2) Put Green (G) tube beam align- Red and Blue in the same way.
• Pre Heat, Pre-optical focus, DCU ment magnet to the cancel state 9) Red (R) focus on focus pack.
Phase Data, H. POSI Course and as shown in Figure 1. 10) Blue (B) focus on focus pack.
Raster Tilt adjustment should be 3) Turn the Green (G) static focus 11) Upon completion of adjust-
completed. VR counterclockwise all the ment, place a small amount of
• Brightness: 90% way and make sure of position white paint on the beam align-
• Contrast Max. of cross hatch center on screen. ment magnets, to assure they
• Receive cross hatch signals, or 4) Turn Green (G) static focus VR don’t move. (If available).
dot pattern clockwise all the way.
• RASTER TILT adjustment 5) Turn two Beam alignment mag-
should be finished. net in any desired direction and
• SCREEN FORMAT should move cross hatch center to posi-
tion found in step (3). (See Fig-
• be NORMAL mode.
ure 2 below).
Adjustment procedure:
6) If image position does not shift
1) Green (G) tube beam alignment
when Green static focus VR is
adjustment:
turned, adjustment complete.
Short-circuit 2P subminiature
7) If image position does move,
connector plug pins of Red (R)
repeat steps [2] through [6].
and Blue (B) on the CRT boards
8) Conduct beam alignment for
and project only Green (G).
ADJUSTMENT
Figure 1 TABS BEAM SHAPE &
PICTURE TUBE SIDE ALIGNMENT MAGNET
4-POLE BEAM SHAPE

CORRECTION MAGNET
ZERO FIELD SPACER

(NO ADJUSTMENT)
The figure shows that the long and
short knobs of the 2P magnet are 2-POLE BEAM
aligned, this is the cancel state. ALIGNMENT MAGNET
Figure 2
NOTE: This is the Centering Magnet not
the Beam Alignment Magnets.
This is just shown for reference, but the
principle remains the same.
PAGE 07-08
DP-2X CHASSIS RED AND BLUE RASTER OFF SET ADJUSTMENT
INFORMATION:
Raster Off set is necessary to conserve Memory allocation.
It is very important to remember that the Red is off-set Left of Center and Blue is off-set Right of center.
Please use the following information to accurately offset Red and Blue from center.
Also see Overlay Dimensions for further details.
Preparation for adjustment:

• With Power Off, press the Service Only switch on the Convergence PWB. While holding the Service Only
Switch down, press the Power On button and Release. DCU Grid will appear without convergence correc-
tion. NOTE: After entering DCAM, with each press of the Service Only Switch, the picture will toggle be-
tween Video mode and DCU Grid.
• Video Control should be set at Factory Preset condition.
• Static Focus adjustment should be finished.
Adjustment Procedure
1. Turn the centering magnets of Red, Green and Blue and adjust so that the center point of the cross-hatch
pattern satisfies the diagram and Offset Value Table below. (DCU data is cleared). Remember Green is
Centered. Red is to the left of Green and Blue is to the right of Green as indicated below.
• All Vertical positions are geometric center of screen.
• Parameters are +/- 2mm.
Offset Value Table
DP-2X L1 L2
43 inch 25mm 30mm
46 inch 25mm 35mm
51 inch 20mm 35mm
57 inch 20mm 35mm
65 inch 20mm 35mm
Red Blue
Geometric Vertical Center
L1 L2
Green
Geometric Horizontal
PAGE 07-09
DP-2X VERTICAL SIZE ADJUSTMENT
VERTICAL SIZE: 3) Select GREEN (A/CH) NOTE: Centering magnet

1) Receive an NTSC signal. and press the MENU but- may be moved to facilitate.
2) With Power Off, press the ton to remove Red and Distance is important, not
Service Only switch on the Blue. centering.
Convergence PWB. While 4) Adjust using R607
holding the Service Only (Vertical Size Adj. VR) to NOTE: The Vertical Fre-
Switch down, press the match marks on the Over- quency is shared between
Power On button and Re- lay. (See Figure Below) Normal and 16X9 HD
lease. DCU Grid will ap- modes.
pear without convergence
correction. NOTE: After
entering DCAM, with Alternate Method:
each press of the Service Adjust Vertical Size until the
Only Switch, the picture size matches the chart below.
will toggle between Video
mode and DCU Grid.
VERTICAL SIZE
Vertical Hash
Mark
Between the horizontal

line at the top and the
bottom.
l 5th LINE
FROM CENTER
Vertical Hash
Mark
DP-2X L=
43 inch 460 mm
46 inch 505 mm
51 inch 560 mm
57 inch 625 mm
65 inch 710 mm
PAGE 07-10
DP-2X HORIZONTAL SIZE ADJUSTMENT
HORIZONTAL SIZE: the Service Only Switch, the DCAM. (Digital Conver-
(Display Mode NORMAL) picture will toggle between gence Adjustment Mode.)
• Install the correct Overlay. Video mode and DCU Grid.
• Input an NTSC Signal. • Project only the Green NOTE: On the DP-26, DP-
• Digital Convergence RAM raster by selecting Green 27 and DP-27D DO NOT
should be cleared. With Adjustment mode and press- USE THE MARKS ON
Power Off, press the Service ing the MENU button on THE OVERLAY. The
Only switch on the Conver- remote. Horizontal Size adjustment
gence PWB. While holding has been increased by
the Service Only Switch ADJUSTMENT 20mm on the 51” and 57”
down, press the Power On 1. Adjust using R711 and 25mm on the 61”.
button and Release. DCU (Horz. Size Adj. VR) Ad-
Grid will appear without just Horizontal Size until
convergence correction. the size matches the chart
NOTE: After entering below.
DCAM, with each press of 2) Press “Power Off” to exit
HORIZONTAL SIZE
DO NOT USE HASH DO NOT USE HASH
MARKS ON: MARKS ON:
DP-26, 27 and 27D DP-26, 27 and 27D
Overlay Overlay
Hash Hash
Mark Mark
6th Line 6th Line

From l From
Center Center
Between Outside Lines
DP-2X DP-23/G, 24/K, 25 L= DP-26, DP-27/27D L=
43 inch 870 mm —
46 inch 930 mm —
51 inch 1020 mm 1040 mm
57 inch 1140 mm 1160 mm
65 inch 1300 mm 1325 mm
PAGE 07-11
DP-2X BEAM FORM ADJUSTMENT
BEAM SHAPE (FORM) 5) Also adjust the Red and Blue

Preparation for adjustment Adjustments procedure: CRT beam shapes according to
1) Green CRT beam shape adjust- the steps (1) to (4).
• IMPORTANT: Screen format ment. 6) After the adjustment is com-
should be “NORMAL“. 2) Short-circuit 2P sub-mini con- pleted, return R, G and B static
• Pre Heat, Cut-Off, Pre-optical nectors on Red and Blue CRT VRs to the Best Focus point.
focus, DCU Phase Data, H. Pos PWB to project only the Green
Course, Raster Tilt, Beam Align- beam.
ment, Raster Position, Vertical 3) Turn the green static focus VR
and Horizontal Size adjustment fully clockwise.
should be completed. 4) Make the dot at the screen cen-
• Brightness: 90%, Contrast: Max. ter a true circle, using the 4-Pole
• Input a NTSC DOT signal. magnet shown in Figure 2 be-
low.
ADJUSTMENT
TABS
PICTURE TUBE SIDE
b 4-POLE BEAM SHAPE

CORRECTION MAGNET
ZERO FIELD SPACER

(NO ADJUSTMENT)
a 2-POLE BEAM
ALIGNMENT MAGNET
Figure 1 Figure 2
PAGE 07-12
DP-2X LENS FOCUS ADJUSTMENT
Preparation for adjustment 2) (See Figure 1) Loosen the 4) After completing optical
fixing screw on the lens focus, tighten the fixing
• Receive the Cross-hatch assembly so that the lens screws for each lens.
pattern signal. cylinder can be turned. (Be 5) When adjusting the Green
• The electrical focus adjust- careful not to loosen the Optical focus, be very
ment should have been screw too much, as this careful. Green is the most
completed. may cause movement of dominant of the color guns
• Deflection Yoke tilt should the lens cylinder when and any error will be eas-
have been adjusted. tightening.) ily seen.
• Brightness = 50% 3) Rotate the cylinder back 6) Repeat Electrical Focus if
• Contrast = 60% to 70% and forth to obtain the best necessary.
focus point, while observ-
Adjustment procedure ing the Cross-Hatch.
(Observe the center of the
1) Short the 2 pin sub- screen).
miniature connector on the
CRT P.W.B. TS, to pro- • Hint: Located just below
duce only the color being the screen are the two
adjusted and adjust one at wooden panels. Remove
a time. (The adjustment the panels to allow access
order of R, G and B is just to the focus rings on the
an example.) Lenses.
FIXING SCREW
Or FIXING WING NUT
er
d
in
yl
C
ns
Le
LENS ASSEMBLY R, G, B.
Figure 1
PAGE 07-13
DP-2X STATIC FOCUS ADJUSTMENT
ADJUSTMENT FOCUS ADJUSTMENT: 2) Adjust the Focus VR for

PREPARATION: 1) Short the 2pin sub- Red until maximum Focus
• Pre Heat Run should be miniature connector on the is achieved.
finished. CRT PWB (PTS), to 3) Repeat for Blue and
remove any color not Green.
being adjusted and adjust
one color at a time. (The
adjustment order of R, G
and B is just an example.)
Screen VR
Screen VRs
R G B
Focus VR
Focus VRs
R G B
FOCUS PACK
PAGE 07-14
DP-2X CHASSIS MAGIC FOCUS “CHARACTER SET UP”
NOTE: This instruction should be 4. Press the PIP TABLE 1 DP23 DP-23K 46”
DP23G Only
applied when a new DCU is being MODE key 2 time DP23K Not 46”
replaced. to write the changed DP27 / G DP24
data into EEPROM. DP26
Adjustment Preparation: • First press, ADJ Parameter Normal Normal
1. Receive NTSC RF or Video PARAMETER ADJ.DISP 77 77
Signal. ROM WRITE ? Is DEMO WAIT 2F 2F
2. With Power Off, Press and displayed for INT. START 03 03
HOLD the SERVICE ONLY alarm. V. SQUEEZE F0 F0
button on the Convergence/ • 2nd press writes INT STEP 1 02 02
Focus PWB, then press the data into
INT STEP 2 06 06
Power On/Off and release. EEPROM. Green
INT BAR 28 25
When picture appears, release dots appear after
Service Only switch. (DCU completion of op- INT DELAY 01 01
grid is displayed without con- eration. MGF STEP 1 00 00
vergence correction data. 5. Press the MUTE MGF STEP 2 06 06
button 3 times exit MGF BAR 1B 1B
Adjustment Procedure: back to DCAM. MGF DELAY 01 01
1. Press the FREEZE key on R/ 6. Press the Service SEL. STAT. 00 00
C. (One additional line appears Only Switch to exit
LINE WID 1F 1F
near the top and bottom. from DCAM.
2. Press the PIP CH key, the ADD LINE 09 09
7. Power set off.
ADJ. PARAMETER mode is SENSOR CK 00 00
displayed as following. PORT 0 07 07
PORT 1 06 06
ADJ.PARAMETER PORT 2 05 05
PORT 3 04 04
—–> ADJ. DISP. : 77 PORT 4 03 03
PORT 5 02 02
DEMO.WAIT : 2f PORT 6 01 01
INT. START. : 03 PORT 7 00 00
V. SQUEEZE :00 AD LEVEL 03 03

CENT. BAL 00 01
E. DISPLAY 00 00
NOTE: ADJ. TIMS 60 60
Press the Cursor Left and Right
ADJ. LEVEL 05 05
Button to change the ADJ.
ADJ. NOISE 0A 0A
DISP.
ADJ. DISP Data as follows; PHASE MOT 60 60
• 77 for HITACHI H. BLK-RV 00 00
DATA VALUES CONFIRMA- H. BLK-GV 01 01
TION: H. BLK-BV 00 00
3. Use the Cursor Up and Down H. BLK-H 00 00
keys to scroll through the ADJ. PON DELAY 0C 0C
PARAMETER table. Confirm
IR-CODE 00 00
Data values in accordance with
INITIAL 50 9E 9E
TABLE 1 to the right. To
make data value changes, Press MGF 50 96 96
the Cursor Left and Right keys. CENTER 50 FE FE
STAT 50 FE FE
DYNA 50 9F 9F
PAGE 07-15
DP-2X CHASSIS MAGIC FOCUS “PATTERN SET UP”
NOTE: This instruction should 2. Press the; and Down buttons to change
be applied when a new DCU is • A/V NET key (all but DP-24) the Pattern Position Data in
being replaced. • VID2 in (CBL/SAT) (DP-24) Vertical Direction.
• The PATTERN mode is dis- 6. Set the Data Values as shown
NOTE: This instruction shows played as following. in the Table below.
how to set up the pattern position 7. Press the PIP MODE key 2
for Intellisense. Each model has 0 1 2 times to write the changed data
a specific set up pattern position. into EEPROM.
• First press, ADJ PARAME-
Adjustment Preparation: RH : 0A TER ? ROM WRITE ? Is dis-
• Receive NTSC RF or Video 7 RV : FF 3 played for alarm.
Signal. • 2nd press writes data into
• With Power Off, Press and EEPROM. Green dots appear
HOLD the SERVICE ONLY after completion of operation.
button on the Convergence/ 6 5 4 8. Press the MUTE button 3
Focus PWB, then press the times exit Pattern Mode.
Power On/Off at the same 3. Use the 6 Key to rotate Arrow. 9. Press the Service Only Switch
time, until picture appears, then Arrow rotates clockwise with to exit DCAM.
release both. (Picture is dis- each press on the 6 Key. 10. Power set off.
played without conv. Correc- 4. Use the following Keys to
tion data. Press the Service switch color of patterns.
Only button to bring up Inter- • INFO : GREEN
nal Crosshatch.) • 0 : RED
• ANT : BLUE
Adjustment Procedure: 5. Press the Cursor Left and Right
1. Press the FREEZE key on R/ buttons to change the Pattern
C. (One additional line appears Position Data in horizontal Di-
near the top and bottom. rection. Press the Cursor Up
NORMAL MODE: DP-23, DP-23G, DP-23K Not 46”, DP-26, DP-27 and DP-27G
0 1 2 3 4 5 6 7
RH 04 02 FC FE FC 02 02 02
RV 03 00 07 01 FB 01 FE 01
GH 04 00 FE 00 FE 00 02 02
GV 04 00 06 01 FC 01 FE 01
BH 06 FE FC 00 FE FE 04 02
BV 06 00 04 01 FE 01 FB 01
NORMAL MODE: DP-24 and (DP-23K 46”) DP-23 value in ( )

0 1 2 3 4 5 6 7
RH 04 02 FE 00 FE 02 04 02
RV 03 01 06 01 FC 01 FF 01
GH 04 00 FE 00 FE 00 02 (04) 02
GV 04 01 05 01 FD 01 FD 01
BH 04 FC FE 02 00 FE 04 02
BV 06 01 04 01 FF 01 FD 01
PAGE 07-16
DP-2X DIGITAL CONVERGENCE OVERLAY DIMENSIONS
43FWX20B DP-23 Only OVERLAY DIMENSIONS NORMAL MODE

952
17 76.5 76.5 76.5 76.5 76.5 H. SIZE 76.5 76.5 76.5 76.5 76.5 17
25.7
34.5
69.1
69.1
69.1 R B
535
69.1

34.5
25.7

46F500 DP-23K Only OVERLAY DIMENSIONS NORMAL MODE

1018
18.2 81.8 81.8 81.8 81.8 81.8 H. SIZE 81.8 81.8 81.8 81.8 81.8 18.2
25.7
37.0
74.0
74.0
74.0 R B
573
74.0

37.0
27.5

PAGE 07-17
51SWX20B, 51UWX20B, 51GWX20B, 51XWX20B
1129
19.7 90.8 90.8 90.8 90.8 90.8 H. SIZE 90.8 90.8 90.8 90.8 90.8 19.7
30.5
41.0
82.0
82.0
82.0 R B
635
82.0

41.0
30.5

DP-26 & 27/27


MARKERS ON THE OVERLAY FOR DP-26 & 27.

PAGE 07-18
57SWX20B, 57TWX20B, 57UWX02B, 57GWX20B, 57XWX20B
1262
22.0 101.5 101.5 101.5 101.5 101.5 H. SIZE 101.5 101.5 101.5 101.5 101.5 22.0
34.1
45.8
91.7
91.7
91.7 R B
710
91.7

45.8
34.1

DP-26 & 27/27/27D



PAGE 07-19
65SWX20B, 65TWX20B, 65XWX20B
1439
25.3 115.7 115.7 115.7 115.7 115.7 H. SIZE 115.7 115.7 115.7 115.7 115.7 19.7
38.6
52.1
104.6
104.6
104.6 R B
809
104.6

52.1
38.6



PAGE 07-20
DP-23, DP-23G & DP-24 REMOTE CONTROL CLU-4321UG (p/n HL01831)
43FDX20B, 51UWX20B, 57UWX20B, 51GWX20B, 57GWX20B
POWER
ROM READ TV CBL/SAT DVD/VCR
(Read Old ROM Data)
ROM WRITE
SWAP PIP MODE

PIP FREEZE
RASTER POSITION
PIP CH
VIDEO MENU
REMOVE COLOR
INITIALIZE
ADJUSTMENT SELECT
MUTE LAST CH
EXIT
CROSSHATCH /
VIDEO
VOL CH (5 Times)
CURSOR UP
CURSOR DOWN 1 2 3
7 8 9
BLUE Select
GREEN Select
13X9 Mode ANT 0 INFO
3X3 Mode (5 Times)
(5 Times)
RED Select
VID1 VID2 VID3 VID4 7X5 Mode (5 Times)
REC ASPECT VIRTUAL HD
VID5
CALCULATION
PHASE HITACHI *VCR MODE ONLY
CLU-4321UG
PAGE 07-21
DP-26 REMOTE CONTROL CLU-5721 TSI (P/N HL01821)
51XWX20B, 57XWX20B, 65XWX20B
POWER
TV VCR CBL SAT
SOURCE WIZARD
CURSOR UP DVD AV1 AV2 AV3
CURSOR DOWN
1 2 3
7 8 9
RED (7 X 5)
RASTER PHASE
SLEEP 0 INFO
GREEN (3 X 3)
A/V NET GUIDE ASPECT
ANT C.S.
BLUE (13X9)
CROSSHATCH
U EXIT
REMOVE MEN VIDEO
COLOR
CORRECTION
VOL SELECT CH
BUTTONS
MUT T CH
SV E LAS
CS HD
SC
VID
1 5
VID
VID 4
2 VID
VID 3

RASTER
PIP-MODE SWAP VIDEO
PIP MODE +
PIP CH
READ OLD
ROM DATA
WRITE TO PRESS (2X)
ROM
REC
PRESS
(2X)
HITACHI
CLU-5721TSI
PAGE 07-22
DP-27 & DP-27D REMOTE CONTROL CLU-5722 TSI (P/N HL01822)
51SWX20B, 57SWX20B, 65SWX20B, 57TWX20B, 65TWX20B
POWER
TV VCR CBL SAT
SOURCE WIZARD
CURSOR UP DVD CD TAPE AMP
CURSOR DOWN
1 2 3
7 8 9
RED (7 X 5)
RASTER PHASE
SLEEP 0 INFO
GREEN (3 X 3)
C.C. A/V NET ASPECT V
ANT IRT UAL H
D
BLUE (13X9)
CROSSHATCH
U EXIT
REMOVE MEN VIDEO
COLOR
CORRECTION
VOL SELECT CH
BUTTONS
MUT T CH
SV
CS
E LAS HD
SC
VC
VID RP /T V
1 LU IDE 5
S+ GU VID
VID 4
2 VID
VID 3

RASTER
PIP-MODE SWAP VIDEO
PIP MODE +
PIP CH
READ OLD
ROM DATA
WRITE TO PRESS (2X)
ROM
REC
PRESS
(2X)
HITACHI
CLU-5722TSI
PAGE 07-23
DP-2X CHASSIS READ FROM ROM NOTES
BEFORE MAKING ANY DIGITAL EXAMPLE:

CONVERGENCE ADJUSTMENTS Sometimes the Magic Focus will not run cor-
rectly and will return an error code.
Heat Run the set for at least 20 minutes.
Do not run Magic Focus before the 20 min- Sometimes after Magic Focus is run but the
utes have passed. convergence appears off after completion.
MAKE A OTHER IMPORTANT INFO:

DETERMINATION: Many times after a complete adjustment,
1) There are many situations where the digi- when initializing the Magic Focus sensors, an
tal convergence looks as thought it may error code will appear, overflow, Error 4,
need a convergence adjustment. etc…
2) Be sure that it really does before begin- When this happens, most of the time it is be-
ning. cause some critical adjustments were over-
3) READ FROM OLD ROM DATA: looked or skipped.
4) In any Hitachi Digital convergence set, the The below adjustments are very critical to the
Old ROM data can be re-read to place the complete alignment process and CAN NOT
unit into the last saved condition. This be overlooked.
could be beneficial before an attempt to
make a rather lengthily adjustment. • Vertical Size Adjustment
5) Enter the DCAM. • Horizontal Size Adjustment
• Press the Service Only switch on the De- • Red and Blue Offset Adjustment
flection PWB. • DCU Character Adjustment and data
1) To Read the Old ROM Data, press the confirmation check
SWAP button twice. • DCU Sensor Position Adjustment.
• First press: (Read from ROM?) will ap- All of the above adjustment can vary depend-
pear on screen. ant upon the Chassis used. Be sure to check
• Second press: Screen goes black, then re- the Service Manual for specifics related to
appears with green dots. values.
• Press the MUTE button to return to Digi-
tal convergence grid. • In I2C Bus adjustment: H. POSI Adjust-
ment
PAGE 07-24
DP-2X DIGITAL CONVERGENCE ALIGNMENT PROCEDURES
Complete Digital Convergence Alignment
Center the Overlay Jig geometrically on the screen
Receive any NTSC signal (Crosshair if possible)

Set SCREEN FORMAT TO NORMAL mode
Clear RAM data (DCU RAM)

Service only
switch Internal
is on the Press and hold the SERVICE ONLY
SWITCH, then press the POWER Digital "Cross
Deflection Hatch Signal"
PWB. Button and release, picture appears.
Release the SERVICE ONLY SWITCH is projected
again. DCU Grid appars.
No DCU Correction
added results in severe
pincushion distortion
Center Magnet Adjustments
Select the External Center Cross Signal

by pressing the EXIT button 5 times.
Use the Centering Align the G,R,B individual External Selected Center
Magnets closest to center crosses to their Cross with no DCU center
the Yoke respective marks on the data
Overlay using the Yoke
Center Magnets R G B
Front View Red = Left Blue = Right

R G B
Green = Center
A See Offset Chart for exact distances Page 06-09
PAGE 07-25
Static Centering Alignments (Moves Entire Raster)

Press EXIT 5 times to return to DCU Grid.
Internal Cross
Hatch Signal
selected
Press the Remote FREEZE
button (extra lines will appear
at top and bottom)
Extra Lines
appear
indicating
Raster
Mode
Remote
Adjust Color Up
Press the Remote Cursor
buttons to match the selected Adjust Adjust
Color select
Crosshatch Left
Color
Right
(red and blue) to the green.
Adjust Color Down
Align Red and Blue static centers

TO SELECT COLORS
Info : Selects GREEN
0 : Selects RED
ANT : Selects BLUE
Green should already be centered
Press the Remote

FREEZE button
to exit Raster Position.
(extra lines will disappear)
B
PAGE 07-26
B
Convergence 3x3 Point Adjustment Mode
(Green Coarse Alignment)
Press the Remote INFO

button to enter the Green
Adjustment Mode (The 3X3 Mode
can only be
Press the Remote INFO entered when
button 5 times to enter the the DCU RAM
3X3 Adjustment Mode data is cleared)
INFO Button is Green Only

used for
selecting the Press the Remote
3X3 Adjustment MENU button to
Mode (when project the green
pressed 5 tube only
times).
Remote
INFO
Use the Remote 2, 4, 5, 6 number

buttons to move the Adjustment Point Selects GREEN
location (intersection of blinking 3X3 Mode =
cursor) and the Cursor Buttons to 9 Adjustment Points
adjust the lines so that the green cross Remote
Cursor blinks hatch align

at intervals of with the Overlay (Jig)
SELECT
3 to indicate
the 3X3
Before Adjustment
Adjustment
Mode Adjusted by cursor keys
After Adjustment
Remote
2
4 5 6
Lines symmetrically
Moves location of
aligned at Adjustment
Adjustment Point
Points
(Intersection of
blinking cursor)
C
Continue on next page
PAGE 07-27
C
Before Calculation
Press the Remote VID 3 button to

Calculate points in between the
adjustment points.
Calculation averages the error between the
points to prevent "S" Distortion
Convergence 3x3 Mode (9 Point) Adjustment

(Red / Blue Coarse Alignment)
After interpolation, press the Remote0 button to select

Green always the Red Convergence Adjustment Mode
projected
Remote
Cursor blinks
RED 4 5 6
7 8 9
0
0 Selects RED
Press the Remote 2,4,5,6 buttons to move the

Crosshatch is adjustment point, and the Cursor buttons to
yellow when the red converge the selected color onto green
and green
crosshatches align
Cursor Blinks Blue
Iinterpolate as
often as
necessary
Remote
Selects ANT
Has the Blue Blue

3x3 Convergence
Mode been
aligned?
No Press the Remote
ANT button to Select
Crosshatch is cyan when the blue and the Blue Convergence
green crosshatches align Yes Adjustment Mode
White internal crosshatch

should be projected
Press Menu
Button D
PAGE 07-28
Convergence 7x5 Point Adjustment

(Green Only Alignment)
Remote
Press the Remote 0 button five 4 5 6
times to enter the 7X5 mode 7 8 9
0
If selected Color isn't already Red, it
will take 6 presses of 0 button Selects the 7X5
mode
Remote
Press the Remote INFO button
to project the green only INFO
Selects GREEN
Use the Remote Cursor and 2,4,5,6 buttons to

perform convergence point adjustment
at every other intersection
of the crosshatch
35 convergence adjustment
points in 7X5 mode Remote
Adjust Color Up
Adjust Adjust
SELECT
Color Color
Left Right
Adjust Color Down
Press the Remote VID 3 button to Calculate

points in between the adjustment points.
Note: Vid 3 on CLU4321UG
must be in VCR Mode.
E
PAGE 07-29
E
Remote
Convergence 7x5 Point Adjustment 4 5 6
(Red/Blue Alignment) 7 8 9
0
Press the Remote 0 button to project

the Red/Green Crosshatch
Press the Remote Cursor and 2,4,5,6 SELECT

buttons to perform convergence point
adjustment at every other intersection
of the crosshatch
Perform
adjustment at Cursor Blinks
every other Blue
intersection
Press the
Remote VID 3
button to
Calculate points
in between the
adjustment
Cursor blinks red points.
at intervals of 2 to
indicate the 7x5
mode Press the Remote ANT button
to select the Blue Convergence
Adjustment Mode
Has the Blue

No
7X5 Convergence Mode
been aligned? Remote
Selects
White Internal Blue ANT
Crosshatch
should be
projected Yes
Press Menu Button Selects Blue for

adjustment
F
PAGE 07-30
Convergence 13X9 Point Adjustment

(Green Only Alignment)
Press the Remote ANT

button five times to
enter the 13X9 mode
Remote
If selected Color isn't already Pressed 5 times,
Blue, it will take 6 presses Selects the ANT
of Source button 13X9 mode
Remote
Remote
Press the Remote A/CH button
INFO to project SELECT
the green only
Selects GREEN 2
4 5 6
Use the Remote Cursor and 2,4,5,6

buttons to perform convergence
point adjustment at every other
intersection of the crosshatch
117 convergence Remote

adjustment points in Adjust Color Up
13X9 mode
Adjust Adjust
SELECT
Color Color
Left Right
Adjust Color Down

Press the Remote VID 3 button to

Calculate points in between the
adjustment points. G
PAGE 07-31
Convergence 13X9 (117 Point) Remote

4 5 6
Adjustment (Red/Blue Alignment) 7 8 9
0
Press the Remote " 0 " button to enter RED Adjustment Mode
and to project the Red/Green Crosshatch
Press the Remote Cursor and

2,4,5,6 buttons to perform
Perform convergence point adjustment at
adjustment at every intersection of the
every crosshatch Cursor Blinks Blue
intersection
Press the
Remote VID 3
button to
Calculate points
in between the
adjustment
Cursor blinks red points.
indicating the
13X9 mode
Note: Vid 3 on Press the Remote ANT button
CLU4321UG to select the Blue Convergence
Remote
must be in Adjustment Mode
Adjust Color Up
VCR Mode.
Adjust Adjust
Color Color Remote
SELECT
Left Right
Has the Blue ANT
13X9 Convergence No
Adjust Color Down Mode been
aligned?
White Internal Selects Blue for
Crosshatch adjustment
should be
projected
Yes
Press the Menu Button

to Display all colors
H
PAGE 07-32
Store New Convergence Data in ROM
Press the Remote PIP MODE

button twice to save the data to
ROM mode = STORE
ROM WRITE?
1 2
This screen is projected at the first

press of PIP MODE button
3 Screen goes blank for several

seconds at the second push of
the PIP MODE button
!!!! WARNING !!!!

Sensor Initialization must be done
after a Write to ROM, (STORE) in
This screen appears with a series of order for MAGIC FOCUS to operate.
green dots indicating a successful If this is not done, when HD FOCUS
Write to ROM or Store. is run, a single Cross Hire will be
Note: If Red dots appear, retry the displayed.
process. If Red dots appear the Return to the Digital Conv.
second time, replace the Digital Adjustment Mode and Initialize the
Convergence module. Sensors.
Press the Remote MUTE button to

return to the Digital Convergence
Adjustment mode
I
PAGE 07-33
Magic Focus Sensor Initialization
Press the Remote PIP MODE button once
1 PIP PIP CH FREEZE
ROM WRITE?
PIP MODE SWAP VIDEO
Again the screen projects

ROM WRITE at the first
press of PIP MODE button
Press the Remote PIP CH button to

begin the Initialization Mode
This screen appears with a series of

green dots indicating successful
sensor Data Initialization
2
INITIAL:N
3
Screen projects different
light patterns during the
Initialization Mode
Press the MUTE Button to return to Crosshatch.

Finished with Digital Convergence Setup for NORMAL mode.
Press the Service Only Switch to Exit to Normal Mode
CONVERGENCE ADJUSTMENT OPERATION COMPLETE
PAGE 07-34
Convergence Touchup Overlays NOT required!
Convergence Point Adjustment.

NTSC (Normal).
Enter the Service Mode by pressing the Service Only Switch on Power/Deflection PWB.
Press "0" five times to select the 7X5 Mode

Press "ANT" five times to select the 13X9 Mode
Note: 3X3 mode can not be entered without clearing RAM data.
Cleared RAM data mode can be entered if necessary.

Clear RAM data by pressing and holding the Service Only button, then press the
Power button. Press the Service Only switch again to display the DCU Grid,
then Read the Old ROM data. (SWAP pressed twice)
Press the MENU button to Remove colors not being adjusted.
Press 2, 4, 5, 6 buttons to move Adjustment Point

Press Cursor Up / Down / Left / Right to Adjust Convergence
When adjustment is complete, STORE the New

DATA by pressing the PIP MODE button twice.
Press the MUTE button to return to DCAM grid.
After Storing, initialize the sensors by pressing the PIP MODE button ONCE
and then press the PIP CH button.
Press the MUTE button to return to DCAM grid.
See "Complete Digital Convergence Alignment procedure" for more details.
Press the Service Only Switch

to Exit DCAM mode.
PAGE 07-35
MAGIC FOCUS ERROR CODES FOR THE DP-2X CHASSIS
CONVERGENCE ERRORS:
If an error message or code appears while performing MAGIC FOCUS or initialize (PIP MODE and PIP CH in
Digital Convergence Adjustment Mode, follow this confirmation and repair method.
1) Turn on Power and receive any signal.
2) Press the Service Only Switch on the Convergence Output PWB.
3) Press SWAP and then the PIP CH buttons on the remote control.
4) Error code will be displayed in bottom right corner of screen.
5) If there is no error, and INITIAL OK will appear on screen.
ERROR!! CONNECT 1! Error Message

Error Code
X No. 1 3 Sensor Position
6) Follow repair table for errors.

ERROR!!.
Application
Error Error
Code Display Countermeasure Initialize Magic
Code Focus
1 VF Error Replace DCU X X
2 Connect 1 1. Darken Outside Light

*2 2. Placing of Sensor
3. Is pattern hitting sensor?
4. Check connection and solder bridge of sensor
5. Replace Sensor. X — SENSOR POSITION
6. Replace Sensor PWB.
7. Sensor Connector check. 0 1 2
8. Replace DCU.
9. Adjustment check (H/V size, centering). 7 3
3*2 A/D Level Same as Error Code 2 X X
6 5 4
4 Over Flow 1. Check the placement
2. Adjustment check (H/V size, centering).
X X
3. Conv. Amp. Gain check*1 (check resistor values
only)
5 Convergence Same as Error Code 4 X X
7 Operation Same as Error Code 4 — X
9 Connect 2 Same as Error Code 2 X X
10 Noise Input strong field. Strong signal. Check the wiring of X X

connector between sensor and DCU
11 Sync Input strong field. Strong signal. Check the wiring of X X

connector between sensor and DCU
*1 = RK 42, 46, 50, 54, 58, 62 check these resistors. *2 = Sensor Position
PAGE 07-36
DP-2X BLUE DE-FOCUS ADJUSTMENT
Adjustment Preparation: Adjustment Procedure 1mm on each side equal-

ing 2mm total. See figure
• Video Control: Brightness 1) Receive any NTSC cross- Below.
90%, Contrast Max. hatch signal.
• SCREEN FORMAT should 2) Turn the B FOCUS VR
be PROGRESSIVE mode. fully clockwise.
3) Adjust BLUE defocus ac-
cording to the following
specifications.
Blue Defocus “Sticking Out”
Center of Blue crosshatch line Screen VR
Screen VRs
R G B
Focus VR
Focus VRs
R G B
FOCUS PACK
PAGE 07-37
DP-2X WHITE BALANCE and SUB BRIGHTNESS ADJUSTMENT
Adjustment Conditions: that input using the VID but- remote to Exit Service
• Cut Off and Blue Defocus tons on the remote or front Menu.
must be complete. control panel.
• High brightness white balance 5) Turn the Brightness and Remember: When adjusting the
• Low brightness white balance Contrast OSD all the way up. Screen controls. After the Cut
6) Enter the Service Menu Off adjustment has been com-
Screen adjustment VRs on Fo- again. pleted, never adjust the controls
cus Block 7) Make the whites as white as clockwise. Always adjust
Drive adjustment performed us- possible using the Red DRV counter clockwise. This length-
2
ing I C Bus Alignment within (Cool) and Green DRV ens tube life.
Service Menu. (Cool) Drive adjustment
within I2C Service Menu . Also, do not use the Focus
Preparation for adjustment (10800K). X=0.278 Block adjustments, use I2C R, G
• Start adjustment 20 minutes or Y=0.280. and B Cutoff adjustments.
more after the power is turned 8) Set the Brightness and Con- Green is reference, do not ad-
on. trast to minimum. just.
• Turn the brightness and black 9) Adjust the low brightness
level OSD to minimum by re- areas to black and white, us-
mote control. ing screen adjustment VRs
• Receive a tuner signal, (any (red, green, blue) on the Fo-
channel, B/W would be best). cus Block assembly. (10800
• Set the Green and Blue drive K)
adjustment within I2C Service 10) Check the high brightness
Menu to their Data Centers whites again. If not OK, re-
(3F). peat steps 6 through 9.
• R, G, and B Cutoff should be 11) Press the MENU key on
set to (7F).
• Set Color Temperature to
COOL on Customer’s Menu. Screen VR
Screen VRs
Adjustment procedure R G B
Focus VR
Sub Brightness:
1) Go to I2C ADJ. Mode. With Focus VRs
power Off, press INPUT and R G B
POWER buttons at the same FOCUS PACK

time, then release. Service
Menu is displayed. Projection Front View
2) Adjust the Sub Brightness
Number [2] SUBBRT using RED CRT GREEN CRT BLUE CRT
I2C Bus alignment procedure

so only the slightest white
portions of the raster can be
seen.
3) Exit Service Menu by press-
ing MENU button.
4) Input a gray scale signal into
any Video input and select
PAGE 07-38
DP-2X WHITE BALANCE ADJUSTMENT FLOW CHART
START
CUT OFF ADJUSTMENT
BLUE DEFOCUS ADJUSTMENT
SUB BRIGHT ADJUSTMENT
ADJUST Hi LIGHT W/B

Repeat two or
three times
ADJUST Lo LIGHT W/B until no
adjustment is
necessary.
SUB BRIGHT ADJUSTMENT
CHECK If NOT OK
Lo LIGHT W/B
Hi LIGHT W/B
If OK
FINISH
PAGE 07-39
DP-2X SUB PICTURE AMPLITUDE ADJUSTMENT
Preparation for Adjustment Adjustment Procedure

Enter I2C adjustment Menu.
Press Menu and scroll through
[a] Sub Brightness adjust- 1) Go to I2C adjustment
pages until TA1270-M appears.
ment should be finished. Mode.
[b] Start adjustment 20 min- 2) Press “MENU” on remote
utes after the power is to scroll through adjust- ADJUST MODE
turned on. ment pages, until TA1270-
TA1270-M
[c] Condition should be set as M appears at the top of the SUB CONT (TV-S) **
follows: page. OSD POSITION
AFC/CLOCK TEST
[d] Contrast = MAX 3) Go to SUB CONT (TV-S) MEMORY INIT
[e] Brightness = Center 4) Press PIP and PIP Mode I2COPEN
IR BLASTER
[d] PIP mode should be in on remote control,
SPLIT mode. TA1270-M changes to
[e] Receive ANT A NTSC TA1270-S. Press PIP button and
PIP Mode button.
white signal, for the Main 5) Observe P852 on the CRT
Picture and the Sub- PWB and change the
SPLIT
Picture. TA1270-S “SUB CNT”
[f] Connect Probe on the I2C data so that the ampli- MAIN SUB
P852 (CRT PWB — tude of the Sub Picture is ANT A ANT A
Green) to check sub- the same level as that of
picture amplitude. the main picture. Shown
below.
6) Exit Service Menu.
1H
Main Picture White Sub Picture White Should Match Main
Adjust SUB CONT (TV-S) until peak white of

PinP matches peak white of the main picture.
PAGE 07-40
DP-2X HORIZONTAL POSITIONS (FINE) ADJUSTMENT
Adjustment Preparation: 4) Exit from the I2C Menu. NOTE: To enter the I2C Bus
• Video Control: Brightness alignment menu, with Power
90%, 1080i 16X9 Standard Mode Off, press the INPUT button
• Contrast Max. Adjustment: and hold it down, then press
the POWER button and re-
Adjustment Procedure 5) Receive any 1080i (2.14H) lease. I2C adjustment menu
16X9 Standard Mode: signal. will appear.
6) Change Screen Format
1) Receive a 16X9 Standard 16X9 Standard mode.
crosshair signal. 7) Power the Set Off.
2) Screen Format is NOR- 8) Enter the I2C Bus align-
MAL. ment menu and select Item
3) Enter the I2C Bus align- [9] H POSITION
ment menu and select Item 9) Adjust the data so that the
[9] H POSITION and ad- left and right sides are the
just the data so that the left same size..
and right sides are the 10)Exit from the I2C Menu.
same size. 11)Turn the Power Off.
16X9 NORMAL MODE: 1080i STANDARD MODE:

Balance left and right side display position. Balance left and right side display position.
PAGE 07-41
DP-2X MAGNET AND YOKE LOCATION
DP-2X MAGNETS
Adjustment Points
1 2 3
FRONT
RED GREEN BLUE

CRT CRT CRT
4
4 6
4
5
5
5
(1) Centering magnet RED (5) Beam Alignment magnets

(2) Centering magnet GREEN (6) Focus Block Assembly
(3) Centering magnet BLUE RED, GREEN & BLUE
(4) Beam Form Magnets FOCUS CONTROLS
Also: SCREEN CONTROLS
for RED, GREEN & BLUE
PAGE 07-42
MISCELLANEOUS
INFORMATION
DP-2X
CHASSIS DIAGRAMS
SECTION 8
DP-23 / 23G REAR PANEL
51UWX20B, 57UWX20B DP-23 CHASSIS

51GWX20B, 57GWX20B DP-23G CHASSIS
ANT A
DVI-HDTV
Pr Pb Y
INPUT 1
To R (MONO/L)
Converter AUDIO
Pr Pb Y/VIDEO
ANT B INPUT 2
R (MONO/L)
AUDIO
R (MONO/L) VIDEO S-VIDEO

INPUT 3
AUDIO
TO HI-FI
CENTER
IN INPUT 4
R L VIDEO S-VIDEO
MONITOR
L
OUT
AUDIO
R
PAGE 08-01
DP-24 REAR PANEL
43FWX20B DP-24 CHASSIS
ANT A
Pr Pb Y
INPUT 1
To R (MONO/L)
Converter AUDIO
Pr Pb Y/VIDEO
ANT B INPUT 2
R (MONO/L)
AUDIO

INPUT 3
AUDIO
TO HI-FI
CENTER
IN INPUT 4
R L VIDEO S-VIDEO
MONITOR
L
OUT
AUDIO
R
PAGE 08-02
DP-26 REAR PANEL
65XWX20B, 57XWX20B and 51XWX20B
1 2 9 7 10 11
ANT A
DVI-HDTV
Pr Pb Y OPTICAL OUT
Digital Audio
INPUT 1
To R (MONO/L)
Converter AUDIO IEEE 1394
Pr Pb Y/VIDEO
ANT B INPUT 2 Multi Media Card

R (MONO/L)
AUDIO

INPUT 3
AUDIO
TO HI-FI
CENTER INPUT 4
IN ANT C
(ATSC IN)
IR
Blaster R L VIDEO S-VIDEO
MONITOR
L OUT
AUDIO
8 4 5 3 6 1 12
PAGE 08-03
DP-27 / 27D REAR PANEL
51SWX20B, 57SWX20B, 65SWX20B DP-27 CHASSIS

57TWX20B, 65TWX20B DP-27D CHASSIS
ANT A
DVI-HDTV
Pr Pb Y
INPUT 1
To R (MONO/L)
Converter AUDIO
Pr Pb Y/VIDEO
ANT B INPUT 2
R (MONO/L)
AUDIO

INPUT 3
AUDIO
TO HI-FI
CENTER
IN INPUT 4
IR
BLASTER R L VIDEO S-VIDEO
MONITOR
L
OUT
AUDIO
R
PAGE 08-04
DP-2X SIGNAL PWB
PJIG PRST PFH1 PFH2

EH7P PH2P PH10P EH2P
I401
I001
IA03
DIGITAL
TERMINAL MODULE
PWB DP-26 Only
FLEX
CONTROL
MAIN PinP
TUNER TUNER PIP
U303
DVI
PWB
DP-23/G
DP-26
DP-27/D
U301 U302
REAR
VIEW
PAGE 08-05
DP-2X DEFLECTION PWB
CONVERGENCE
V Size Adj SERVICE SWITCH
H Size Adj SK01
1 1 6
PPD1 11
R711 R607 PADJ
7
1 IK01
PPD2 I601 QK01
12 1 DIGITAL
CONVERGENCE
PDF1
1 6 UNIT
1
UKDG
PPD3
1 PDS1
7 MB MG MR
1
PPD6 QF01
T701
10 PCR
RED
D708 Q777
IK04
T702
RH17
HV ADJ PCG
DO NOT GREEN
ADJ. TH01
FLYBACK
IK05
M62501P
IH01
CH16
PCB
BLUE
QH01
PAGE 08-06
DP-2X POWER SUPPLY PWB
D928
= GREEN or RED LED

B+
PPD1
PPS1
D940
S903
PPS2
PPD2
+28V
PPS3
E906
PPD3
D964 REG
+6V SW
SW +9V
PPS4
AUDIO SW
PPD6
DM SW
S902
PPS5
S906 E907
S905 B+
PDC1
D965 +35 SW
PPS7
AUDIO E904
+29V 12WX2 E902
+7V
+39V 20WX2 +28V E905
+220V
E912 E903
DM+10V E909 -7V
+10V
E901
E911 PRO -28V
I905
T901 T902
Switching Switching
Transformer I904 I903 Transformer
FB ACK I906
FB
I901 I902 D915
F903
DEF POWER
FUSE
F902
FUSE
D901
D902
PPS6
DEF SW BACK
COVER
F901
FUSE S901 SIDE
1 2
PAGE 08-07
DP-2X CRT PWBs
P802
(Cathode)
RED
P801
SCREEN ADJ. VR
1 E801
FOCUS ADJ. VR
GND
P852
FOCUS PACK (UFPK)

(Cathode) B B
GREEN
G G
P851
1 E851
R R
GND
3
FOCUS PACK
P8A2
(Cathode)
BLUE
P8A1
1 E8A1
GND
PAGE 08-08
EF1
MAGIC VOL- VOL+ CH- CH+ INPUT/ MENU
S V L R FOCUS EXIT SELECT
PFR
EFR
POWER
POWER DIMMER
LED CONTROL
PF1 LIGHT RECEIVER
PFT PFS
REMOTE CONTROL
IR RECEIVER
DP-X ALL BUT DP-24 FRONT CONTROL PWB
PAGE 08-09
DP-24 FRONT CONTROL PWB
REMOTE DIMMER
CONTROL CONTROL
RECEIVER LIGHT RECEIVER
POWER
LED
POWER
INPUT/ MENU
EXIT SELECT VOL- VOL+ CH- CH+
S V L R
MAGIC FOCUS
PAGE 08-10

Hitachi 51F500

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Dec 2004 (ver g) Training Materials Prepared by: ALVIE RODGERS C.E.T.

2002 and 2003

DP-27D 57TWX20B 16X9

DP-26 65XWX20B 16X9

DP-24 43FWX20B 16X9

DP-23G 57GWX20B 16X9

DP-23K 46F500 16X9

DP-23 57UWX20B 16X9

CONTENTS... 2002 DP-2X Chassis Projection Television Information

SECTION (2) MICROPROCESSOR INFORMATION:

SECTION (3) VIDEO CIRCUIT INFORMATION:

Continued on Next Page

Table of Contents Page 1 of 4

SECTION (4) AUDIO CIRCUIT INFORMATION:

SECTION (5) DEFLECTION CIRCUIT:

SECTION (6) DIGITAL CONVERGENCE CIRCUIT INFORMATION:

SECTION (7) ADJUSTMENT INFORMATION:

Continued on Next Page Table of Contents Page 2 of 4

◊ DIGITAL CONVERGENCE ALIGNMENT PROCEDURE ------------------------------ 07-25

Continued on Next Page

Table of Contents Page 3 of 4

SECTION (8) MISCELLANEOUS INFORMATION:

SECTION (9) THINGS YOU SHOULD KNOW / SERVICE BULLETINS / ETC….:

Table of Contents Page 4 of 4

THIS POWER SUPPLY RUNS ALL THE TIME:

B+ GENERATION FOR THE LOW VOLTAGE POWER SUPPLY DRIVER IC:

D904 Start Up Run

D901 R907 D905

D901 R907 Start Up D905 Run

C904 Cold Ground from

Relay Controls Circuit Diagram explanation:

RELAYS ENERGIZED BY Q907 (DP-23, DP-23G, DP-24, DP-27 and DP-27D:

DP-26 ONLY: RELAYS ENERGIZED BY POWER _1 and POWER _2:

Power _1: (High when the Set is turned On.)

RELAYS ENERGIZED BY Q907: Activated by Power _1

RELAYS ENERGIZED BY Q909: Activated by Power _2

TIMER (Unattended Recording) OPERATION:

MODE POWER _1 POWER _2

T901 S-902 Audio Power Sby 5V comes from I909 pin 2

Control +6V S-903 SW +6V Q903

Low Voltage Power Supply Shut Down Circuit Diagram explanation:

POWER SUPPLY SHUTDOWN PHOTO COUPLER I905 EXPLANATION

VOLTAGE LOSS or SHORT DETECTION

(Continued on page 10)

VOLTAGE TOO HIGH DETECTION Any Positive

NEGATIVE VOLTAGE LOSS DETECTION

HOT GROUND SIDE SHUT DOWN SENSING CIRCUITS. (Specific to I901).

LATCHED SHUT DOWN MONITORS: (AC must be removed to recover).

DP-27 SHUT DOWN CIRCUIT:

Q903 Relay Inhibit Activation.

(Continued on page 12)

SW –28V Loss Detection

From the Deflection Circuit PPD3 connector pin 6.

SOME SHUTDOWN CIRCUITS ARE DEFEATED IN STANDBY MODE. (Set Off).

B+ GENERATION FOR THE LOW VOLTAGE POWER SUPPLY DRIVER IC:

Hi-Voltage Power Supply Circuit Diagram explanation:

TURNING ON THE SW +115V POWER SUPPLY:

B+ GENERATION FOR THE HIGH VOLTAGE POWER SUPPLY DRIVER IC:

C927 R943 R942 Deflection 10 SW +115V

D925 D927 Cold Ground from

Additional Power Supply Shut Down Circuit Diagram explanation:

SW +115V EXCESSIVE CURRENT DETECTION

NEGATIVE VOLTAGE LOSS DETECTION

VOLTAGE TOO HIGH DETECTION