Reference Generation for A/D Converters
Frank Ohnhauser*, Texas Instruments Dt. GmbH, Erlangen, Germany
Mario Huemer, Klagenfurt University, Austria
An Analog-to-Digital Converter (ADC) compares the input
voltage Vin with a reference voltage REF to convert it into a digital
word. The reference source must be able to drive the ADCs
reference input; it needs to provide low noise, should be
adjustable, stable over temperature and supply voltage and
should not require external components. A novel scheme was
developed and implemented in a 12bit 2MSPS SAR converter.
Index Terms—Analog-digital conversion, Digital-analog
conversion, Integrated Circuit
I. INTRODUCTION
Many ADCs have a reference source on chip. This reference
needs to recharge internal capacitors of the converter within
less than a clock cycle. Two general schemes are in use. Some
products provide an internal buffer, so that the reference input
is high impedance (Fig. 1a). This buffer needs to have a wide
bandwidth at low noise and will therefore consume a
significant amount of power. The second solution (Fig. 1b)
requires a large external capacitor CREF, which provides the
charge for the internal capacitors of the ADC. This solution
relaxes the settling requirements of the amplifier with respect
to bandwidth and noise. Unfortunately, most amplifiers and
references become unstable when driving large capacitors.
Also, applications often scale the reference voltage to adjust
the input voltage range. If the reference is externally adjusted
with a resistive divider, then the input impedance is getting too
high, so that an additional amplifier is required (see Fig. 1b)
and the solution gets more expensive. Both solutions are not
satisfying. The following chapters will discuss the
requirements to the reference voltage and introduce a new
scheme, which is implemented inside a new 2MSPS, 12bit
SAR ADC that provides a 5V input range.
Internal Reference REFOUT
REFIN
ADC
a) Integrated Circuit with
internal reference buffer 0V
Internal Reference REFOUT
ADC REFIN
b) Circuit with external capacitor CREF
0V
Fig. 1. Typical reference strategies with external reference adjustment
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II. REFERENCE REQUIREMENTS OF THE ADC
Delta-Sigma (∆Σ) ADCs have feedback capacitors from the
digital output to the integrators to add or to subtract charge,
which is provided from the reference. Converters based on
successive approximation (SAR) have a capacitive digital-to-
analog converter (CDAC), which is controlled by switching
these capacitors between REF and ground. Finally, pipeline
converters are subtracting REF from the input voltage in all
stages, where Vin>REF. For all ADC types, the capacitors need
to be recharged within less than one clock cycle and the
reference input must be fast enough to provide this charge.
Assuming that the settling of the voltage across the capacitor
VCAP is exponential and that the error VCAP -REF has to be less
than half an LSB then the bandwidth of the reference driver
can be calculated to [1]:
1 ln( 2 ) ⋅ ( n + 1 ) (1)
f − 3 dB = >
2π ⋅τ 2π ⋅ T s
TS is the settling time, which typically is half a clock cycle, and
n equals the resolution of the converter. A 2MSPS, 12 bit SAR
ADC typically requires 16 clock cycles per conversion
(fclk=32MHz). The available settling time for the reference is
TS=15.6ns, so that f-3dB=92MHz. The required bandwidth can
only be achieved with high power consumption. The amplifier
further needs to provide low noise, which couples directly into
the signal path. The total peak-to-peak noise of a 12 bit
converter can be estimated to ±4-times (=8-times) the rms-
voltage, which should be less than a least significant bit (LSB).
Less than half an LSB should be considered for the noise of
reference buffer vnref. The transfer function of the amplifier can
be assumed to be a first order low-pass filter. Noise above f-3dB
is suppressed, but not eliminated. The effective bandwidth for
noise is f = π f (also see section V.), so that the
eff − 3 dB
2
maximum noise density v nref ⋅ ∆ f
−
1
2 can be calculated to
v nref 0 . 5 ⋅ LSB 0 . 61 mV nV
(2)
= = = 6 .3
∆f π π Hz
8⋅ f − 3 dB 8 92 MHz
2 2
n+1
If a capacitor CREF>2 ·CCDAC is placed between the reference
amplifier and the ADCs reference input, then REF will not
drop more than half an LSB during the conversion. The
external capacitor needs to be recharged within one conversion
cycle, which for a 12 bit converter often is 16 clock cycles
TCLK. Furthermore, the voltage does not have to resettle to a 12
bit resolution (TS=9τ, see equation (1)), because the voltage
drop already is below 0.5·LSB (TS<1τ). The bandwidth of the
reference input can be reduced by a factor of
355
 16 ⋅ Tclk 9 ⋅ τ
f = ⋅ = 288 and will make the CDAC noise REF
0.5 ⋅ Tclk 1 ⋅ τ 0V
insignificant compared to other noise sources.
Due to the power saving and the better noise performance, the
solution with external capacitor should be chosen. However,
this adds several requirements to the reference buffer. Beside
the stability issue, the buffer must have a good load regulation,
because it has to provide the code dependent current into
REFIN without changing the voltage more than half an LSB, DAC
because the code dependency will cause linearity errors. 0V
In the example of the 2MSPS, 12 bit SAR converter, the total
Fig. 3. String DAC architecture
ADC capacitance CADC is 6pF, the maximum current IREF can
be calculated to:
∆QREF I REF IV. NEW REFERENCE CONCEPT ADDING A DAC
C ADC = = ⇔ I REF = C ADC ⋅ REF ⋅ f conv = 30 µA
REF REF ⋅ f conv The voltage divider is realized with a programmable internal
The load regulation of the buffer has to be better than: digital-to-analog converter (DAC). The best fitting architecture
dREF 0 . 5 ⋅ LSB mV (3) is a string DAC, which is a resistive voltage divider [2].
< = 20 Switches are placed at each interconnection of the resistors, so
dI REF I REF , max mA
that the voltage of interest can be chosen (Fig. 3).
Resistors typically show a severe temperature coefficient, but
III. REFERENCE REQUIREMENTS OF THE in this case, only the resistor matching is important, so that the
APPLICATION temperature drift of the DAC output remains low.
A typical application has its specific input voltage range. As there is no DC current through the switches, the differential
Optical encoders, which are often used for position non-linearity (DNL) of the DAC is also purely dependent on
measurements in electrical motor control, have an output range the resistor matching and on the layout of the interconnections.
of 1Vpp. The same application might also use resolvers, which A good DNL is important in this application, so that the
have an output voltage range of ±2.5V around a common mode reference can be adjusted without gaps.
voltage that often is identical to the reference. The input range The voltage coefficient of the resistors and the layout might
of the ADC is often adjusted to the needs of the application by generate some integral linearity errors. In most applications,
dividing the reference voltage externally (Fig. 1). the gain is calibrated. If calibrated, then the DAC can be
The reference divider will increase the input impedance of the readjusted until the ADCs input range fits the applications
reference, which must remain below the load rejection needs. An integral linearity error is therefore less critical.
calculated in equation (3). The divider can therefore only be The output of the DAC can now be buffered with an on-chip
implemented, if its output is buffered with an additional amplifier, which was already required for the reference output
amplifier. Such amplifiers, which can drive a capacitive load, without the string DAC. However, the amplifier needs to be
are adding essential costs to an application. The concept of Fig. modified, because it has to be insensitive to external capacitors
1a would be preferred. even with some lead inductance being in series.
The new reference architecture (Fig. 2) will satisfy all
requirements by adding the divider and the buffer inside the V. NOISE ADDED BY THE DAC
converter. The reference output is adjustable and no external
Unfortunately, resistors are adding thermal noise to the
components are required beside CREF.
electrical circuitry, which will couple into the ADCs signal
path. The noise [3] of resistors is given to
REFOUT vn2 = 4kTRDAC ∆f (4)
Internal
Reference T is the absolute temperature, k the Boltzmann constant
(1.38·10-23JK-1), RDAC the output resistance of the string DAC
and ∆f the effective noise bandwidth. Reducing the resistance
DAC could lower the noise, but would generate a higher current
REFIN through the string DAC and add power dissipation. Therefore,
ADC CREF the bandwidth needs to be limited to minimize the noise of the
DAC. A capacitor CDAC has to be placed at the output of the
0V DAC, which forms a pole at the output with the -3dB
frequency being
Fig. 2. New reference architecture with internal DAC and buffer
1 (5)
f − 3 dB =
2π ⋅ R DAC ⋅ C DAC

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 the input stage of the amplifier (Fig. 5) in eight differential
v n2 Distribution of thermal noise pairs and connecting them either to the upper or the lower
∆f terminal of the resistor of interest [4]. If the three LSBs for
example are programmed to 011, then three of the eight
differential pairs are connected to the higher voltage side of the
f chosen resistor, the other five differential pairs to the lower
voltage side.
Transfer Function of a low-pass filter FRC(f)
Fig. 5 further shows a NCH and a PCH input stage. This is
0dB
f-3dB f necessary as the analog supply AVDD can drop all the way to
2.7V. A rail-to-rail amplifier is required, as the DAC output
can be varied from 0.2V to 2.5V. Rail-to-rail amplifiers
typically change the input stages over a certain input voltage
v n2 Filtered noise distribution range. Within this range, the transfer function is very non-
∆f linear due to the different offsets of the two differential pairs.
Due to this effect, the power supply rejection and therefore
v n2
noise rejection are also very poor within this voltage range.
As the noise of the ADC is more important than the linearity of
f-3dB f the DAC, the amplifier changes the input differential pair at a
Fig.4. Effective noise bandwidth particular code 508 controlled by the signals range and xrange.
A systematic offset is added to ensure that rather an overlap
Fig. 4 shows that noise above f-3dB is suppressed, but not instead of a gap is generated in the transfer function of the
eliminated. Integrating the transfer function FRC(f) will result in DAC.
an effective bandwidth of The 7bit resistor string with 128 resistors, the respective
π 1 (6) switches and the output capacitors is optimized in size. It only
∆ f = ∫ F RC ( f ) df = f − 3 dB = consumes 100x300µm, which is less than 1% of the total die
2 4 ⋅ R DAC ⋅ C DAC
size. The layout of the DAC is shown in Fig. 6.
The noise contribution of the string DAC can therefore be
summarized to
kT (7)
v n = 4 kTR DAC ∆ f =
C DAC
The same noise equation is valid for the sampling process of
the ADC. CDAC has to be designed essentially larger than the
sampling capacitor of the ADC to make the DAC noise
insignificant. Fortunately, the reference is a constant voltage,
so that the voltage coefficient of the capacitor is uncritical.
A high density gate capacitor (Poly-NWell, 2 . 5 fF ) can be
µm 2
used for CDAC, while the sampling capacitor of the ADC
requires a material with low voltage coefficient like Poly-Poly
or Metal-Metal capacitors, where the capacitive density is only
fF or less. In addition, the layout can be implemented
0 .8
µm 2
very area efficient, because CDAC does not have to match to
other capacitors like the sampling capacitor does. In the
particular 12bit design, CDAC was chosen to 20pF, while the
Fig. 5. Amplifier input stage with 3 bit interpolation
sampling capacitor is only 2pF. Furthermore, the ADC has two
sampling capacitors, one for the positive input and one for the
negative input, so that the sample noise vnsamp=64.3µVrms. If
the DAC noise is added geometrically to the sampling noise,
then the sum is vnsamp+DAC=65.9µVrms. It can be seen that the
DAC noise is indeed insignificant.

VI. IMPLEMENTATION OF THE DAC

A 10bit string DAC was implemented with an interpolating
topology, where the seven most significant bits (MSB) are
Fig. 6. Layout of the string DAC
generated with a resistor string and the 3 LSBs by separating

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 The particular CMOS process includes thin-film resistors,
Load Rejection
which provide an excellent voltage and temperature coefficient. 2 .50 0 6
The resistor size was chosen to 5kΩ, so that the total size of the 2 .50 0 4

REF in V
string adds to 640kΩ. This forces a DC current of only 4µA out 2 .50 0 2 5V
of the bandgap circuitry. 2 .5 3.3V
If the bandgap is assumed to an ideal voltage source, then the 2 .4 9 9 8 2.7V
maximum output resistance occurs at code 512, where 320kΩ 2 .4 9 9 6
are connected from the DAC output to the bandgap and the -2 -1 0 1 2

same resistance to ground. The output impedance results in 160 IREF in mA

kΩ.
Fig. 8. Reference voltage versus output current
The output impedance generates a time constant of 3.2µs
together with the capacitance of 20pF for the noise reduction.
The settling time for 12 bit accuracy is in the range of 30 µs. Parameter Typical Value Typical Value Unit
This settling time is insignificant, if compared to the settling New Design Previous Design
time of the amplifier. If a 500nF capacitor has to be charged to Speed 2 0.5 MSPS
2.5V with a current of roughly 2.5mA, then the amplifiers SNR 73 72.5 dB
settling time can be estimated to
C ⋅ ∆V 500 nF ⋅ 2 . 5V DNL ±0.2 ±0.5 LSB
∆t = = = 500 µ s (8)
I 2 . 5 mA INL ±0.25 ±0.5 LSB
IVDD 6.5 5 mA
VI. RESULTS
dREF/dT 10 20 ppm
The linearity of the DAC is shown in Fig. 7. The transfer Table 1. ADC Performance (for two simultaneous sampling ADCs and
function is very smooth beside the intended overlap at code reference circuitry)
508. Fig. 8 illustrates the load rejection of the amplifier. It was
Noise, linearity and power consumption of the new ADC prove
designed to 200 µV , so that the reference can also be utilized the advantage of the new concept. Table 1 compares the new
mA
concept of the 2MSPS product with the old approach inside the
by other circuits like instrumentation amplifiers that might be
500kSPS ADC. The higher current consumption is mainly
used in the application to adjust signal levels.
generated by the faster digital circuitry.
The new reference concept of Fig. 2 was implemented in the
2MSPS, 12 bit SAR converter. High-speed SAR ADCs often
VII. CONCLUSION
have a dynamic error correction implemented to relax the
settling requirements of the reference and of the internal A novel reference architecture was developed, which satisfies
comparator. Such schemes require a digital adjustment of the the requirements of both, the low-cost and adjustable approach
converters output, so that the output data has to be read after for the application and the high-performance and low power
the conversion or during the next conversion. approach for the design. The possibility to adjust the reference
This SAR converter has a serial output and the application output is realized by adding a string DAC between the bandgap
requires that the data is read during a running conversion. Later output and the reference output amplifier. Noise, drift and the
dynamic adjustments are not possible, so that this converter has chip area of the DAC can be neglected.
the conventional settling requirements. Results show that the linearity and the noise performance
The SAR converter is furthermore replacing a 500kSPS 12bit improve, even that the conversion rate was increased by a
SAR ADC, which was implemented on a similar 0.6µm CMOS factor of four. The current consumption remained stable dispite
process. The older version had a reference input buffer as the increased conversion rate and the added functionality.
shown in Fig. 1a. Furthermore, the supply voltage on the new design can go as
low as 2.7V, so that the power consumption can be
significantly lower than in the previous design.
Integral and Differential Non-Linearity of the DAC
2 .0 0 0 [1] F. Ohnhauser, “Piloter l’entrée de reference d’un CAN a approximations
Linearity (LSB)

1.0 0 0 successives”, Electronique, 11/2003

INL [2] W. Rempfer, “Digital-to-Analog Converters”, US Patent 5,396,245, 1995
0 .0 0 0 [3] P. R. Gray, R. G. Meyer, “Analysis and Design of Analog Integrated
DNL Circuits”, John Wiley & Sons Inc, 1993, ISBN 0-471-57495-3
-1.0 0 0
[4] A Yilmaz, “LSB Interpolation Circuit and Method for Segmented D/A
-2 .0 0 0 Converter”, US Patent 6,246,351, 2001
2 50 3 50 4 50 550 6 50 750 8 50 9 50
Code

Fig. 7. Differential Non Linearity

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