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COMPUTER ORGANIZATION AND ARCHITECTURE

SUBMITTED BY:-

NAME :- SHYAM SUNDER

ROLL_NO:-RE3004B69

Class: MCA- M.tech

Section: E3004

Batch: G2

Course No: CAP11

Course Title: COMPUTER ORGANIZATION
AND ARCHITECTURE

SUBMITTED TO:-

RICHA MALHOTRA
 Part – A

Q1: The access time of cache memory is 100 ns and that of main memory is 1000 ns. If cache hit
ratio is 0.85, determine the effective access time of the system.
Answer:-
Access time of cache memory :- 100
Main memory :- 1000
Hit ratio :- 0.85
Hit missed by cache memory :- 0.15

Effective Access time of the system is :- 0.85*100+0.15*1100

85+165
250ns

Q2: A digital computer has memory unit of 64K x 16 and cache memory of 1K words. If direct
mapping policy is used, determine the number of bits in:
(a) Main Memory address
(b) Cache Memory address
(c) Tag and Index fields
Answer:-
(a) Main Memory address

Memory unit of 64K*16 capacity means 64 K = 26 * 210 = 216

i.e. 16 bit address and 16 bit data lines are needed
6 bits 8 bits 2 bits = 16 bits

TAG BLOCK WORD

(b) Cache Memory address

28=256 blocks of four words each accommodate.

(c) Tag and Index fields

Tag=6 bits
Index= 10 bits
Q3: Direct Memory access is an efficient way of implementing I/O transfer. Prove that point by
giving importance of DMA
Answer:-
The transfer of data between a fast storage device such as magnetic disk and memory is often
limited by the the speed of the CPU. Removing the CPU from the path and letting the peripheral device
mange the memory buses directly would improve the speed of transfer. This transfer technique is called
direct memory access(DMA). During DMA transfer, the CPU is idle and has no control of the memory
buses. A DMA controller takes over the buses to manage the transfer directly between the I/O device and
memory.
The CPU may be placed in an idle state in a variety of ways. One common method extensively used
in microprocessors is to disable the buses through special control signals.
Bus Signal:- CPU that facilitate the DMA transfer. The bus request input is used by the DMA
controller to request the CPU to relinquish control of the buses. When this input is active, the CPU
terminates the execution of the current instructions and places the address bus, the data bus, and the
read and write lines into a high impedance state. The high impedance state behaves like an open circuit,
which means that the output is disconnected and does not have a logic.
Bus Grant:-
Part - B

Q4: Differentiate between synchronous and Asynchronous data transfer techniques along with
the circumstances in which each can be used.
Answer:-
Synchronous:-
In synchronous transmission, the units share a common clock frequency and
bits and transmitted continuosly at the rate dicatated by the clock pulses. In long distant serial
transmission, each unit is driven by a separate clock of the same frequency. Synchronization
signals are transmitted periodically between the two units to keep their clocks in step with each
other. Synchronous transmission does not use start stop bits to frame characters and therefore
makes more efficient use of the communication link. High speed devices use synchronous
transmission to realize this efficiency. The modems used in synchronous transmission have
internal clocks in the transmitter and receiver modems remain synchronized at the times.
Asynchronous:-
In Asynchronous transmission, binary information is sent only when it is available and the line
remains idle when there is no information to be transmitted. This is in contrast to synchronous
tramission, where bits must be transmitted continuosly to keep the clock frequency in both units
synchronized with each other. A serial asynchronous data transmission technique used in many
inter-active terminals employs special bits that are inserted at both ends of the character code.
With this technique, each character consists of three parts: a start bit, the character bits, and stop
bits. The convention is that the transmitter rests at the 1- state when no characters are
transmitted. The First bit, called the start bit, is always a 0 and used to indicate the beginning of a
character. The last bit called the stop bit is always a 1.

Q5: Write a program in assembly language to perform data transfer from registers and memory.
Answer:-
Introduction
A processor can directly execute a machine language program. Though it is possible to program directly
in machine language, assembly language uses mnemonics to make programming easier.
An assembly language program uses mnemonics to represent:
1.Symbolic instructions and
2.The raw data that represent variables and constants.
A machine language program consists of:
1.A list of numbers representing the bytes of machine instructions to be executed
2.Data constants to be used by the program.
4.2 Assembly language syntax
An assembly language program consists of statements. The syntax of an assembly language program
statement obeys the following rules:
• Only one statement is written per line
• Each statement is either an instruction or an assembler directive
• Each instruction has an op-code and possibly one or more operands
• An op-code is known as am nem onic
• Each mnemonic represents a single machine instruction
• Operands provide the data to work with

4.3 Program Statement:

The general format for an assembly language program statement is as follows:
Name mnemonic operand (destination), operand (source); comment

Program in Assembly language

The hello world program in Assembly
.model small
.stack 200
.data
greeting db 'hello world !',13,10,'$'
.code
mov ax,@data
mov ds,ax
mov ah,9
mov dx,offset greeting
int 21h
mov ah,4ch

Q6: List various addressing modes available in latest Pentium processors.