FIFO APPLICATIONS

GUIDE

September 1999

1
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 TABLE OF CONTENTS

TITLE APPLICATION PAGE

NOTE NUMBER
FIFO Family & Part Number Application Note Cross Reference Table 5

Introduction to FIFO Memories 7

CUSTOMER SPECIFIC APPLICATION NOTES

PCI Bus
Prototyping System/ Algorithm Accelerator Utilizing the IDT72V36110 AN-243 11

HDTV & Image Processing

Application of the IDT72V2113 High Density FIFO within an HDTV Encoder AN-244 15

Medical Equipment
Application of the IDT72V2105 FIFO within an X-Ray Image Processing System AN-245 17

GENERAL APPLICATION NOTES

SuperSync II Mid-Bus FIFO - The Solution to High Density FIFO Requirements AN-242 25
within 36 Bit Bus Applications

Operating FIFO's on Full and Empty Boundary Conditions TN-08 27

Cascading FIFO's or FIFO Modules TN-09 29

Width Expansion of SyncFIFO's AN-83 32

Using IDT SyncFIFO's as Parallel Data Delay Lines AN-122 37

Serial Programming of SuperSync FIFO Flag Offsets: A State Machine Approach AN-130 42

Dual SyncFIFO Applications using the IDT728x1 and IDT728x5 AN-134 59

ADDITIONAL INFORMATION
Thermal Performance Calculations for IDT's Packages 73

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 1999 Integrated Device Technology, Inc.
4
 Application Note and FIFO Device
Cross Reference

FIFO FAMILY PART NUMBER DESCRIPTION APPLICATION PAGE

NOTE #

SUPERSYNC II 72V36110 PCI BASED ALGORITHM ACCELERATOR AN-243 11

SUPERSYNC II 72V2113 HDTV ENCODER SYSTEM AN-244 15

SUPERSYNC II 72V2105 X-RAY IMAGE PROCESSING AN-245 17

SUPERSYNC II 72V3660/3670/3680 36 BIT MID-BUS REPLACES SUPERSYNC AN-242 25

3690/36100/36110

SUPERSYNC 72V255LA/V265LA SERIAL PROGRAMMING OF FLAG OFFSETS AN-130 42

72255LA/265LA
72V261LA/V271LA
72261LA/271LA

SYNCFIFO 72V2X5/ 722X5 WIDTH EXPANSION OF SYNCFIFO'S AN-83 32

72V2X1/ 722X1

SYNCFIFO 72V2X5/ 722X5 USING SYNCFIFO'S AS PARALLEL DATA AN-122 37

72V2X1/ 722X1 DELAY LINES

DUAL SYNCFIFO 72V8X5/728X5 DUAL SYNC FIFO APPLICATIONS AN-134 59

72V8X1/728X1

ASYNC FIFO 7201 - 08 SYNC FIFO OPERATION AT THE FULL & TN-08 27
EMPTY BOUNDARY CONDITION

ASYNC FIFO 7201 - 08 CASCADING ASYNC FIFO'S TN-09 29

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 1999 Integrated Device Technology, Inc.
6
 An Introduction to FIFO Memories
and their Applications
FIFO Memories
A FIFO is used as a "First In-First Out" memory buffer between two
asynchronous systems with simultaneous write and read access to and
from the FIFO, these accesses being independent of one another. Data
written into a FIFO is sequentially read out in a pipelined manner, such
that the first data written into a FIFO will be the first data read out of the
FIFO. So, the fundamental architecture of a FIFO has an input (write)
port, and an output (read) port. Each port has its own, associated pointer
which points to a location in memory, after a FIFO reset both write and
read pointers will be at the first memory location within the FIFO. Every
write operation will cause the write pointer to increment to the next
location in memory, similarly every read operation will cause the read
pointer to increment to the next location in memory. FIFO write and read
operations will loop in a circular fashion, from the last memory location to
the first memory location without the need for any kind of read or write
pointer reset.
FIFO status flag outputs are a function of the comparison of the
respective write and read pointers. A FIFO will always have some status
flag outputs; at least a flag that indicates the empty condition and a flag
that indicates the full condition. An empty flag is asserted when the FIFO
memory is empty. This is generated by the comparison of the write and
read pointers and results in the number of memory locations between
them being zero, (i.e. when they are at the same memory location). A full
flag is asserted when the FIFO memory is full. This is generated by the
comparison of the write and read pointers results in the number of
memory locations between them being the maximum FIFO depth, the
write pointer is 'D' locations ahead of the read pointer, where D is the
FIFO depth. Note, a FIFO that is full cannot be written in to and a FIFO
that is empty cannot be read from.
IDT FIFO's can be either Synchronous or Asynchronous, the
fundamental difference between the two being the presence of clock
inputs on the Synchronous FIFO's, the Asynchronous FIFO's have no
clock inputs. The entire operation of a Synchronous FIFO is dependent
on the application of a either a write clock signal or read clock signal. IDT
offers a wide variety of FIFO's available in many densities providing
various widths and depths. Data bus widths vary from 1 bit to 72 bits and
FIFO depths vary from 64 to 512,000. IDT's range of FIFO's also
includes many different grades of performance and feature offerings. IDT
FIFO's are available as Uni-directional devices (where data flow through
a FIFO is in one direction only), or Bi-directional (data can flow in both
directions through the FIFO). IDT provides specialty FIFO's which
include 'Parallel-to-Serial' and 'Serial-to-Parallel' FIFO's. Here the data
input to, or the data output from a FIFO can be either a parallel data
bus or serial bit stream.
IDT's FIFO Family Tree
IDT has three main FIFO families, Asynchronous FIFO's, Synchro-
nous FIFO's (both families being Uni-Directional) and Bi-Directional
Synchronous FIFO's. Asynchronous FIFO's have no clock input for either
the read or the write operations. Data is written into or read from the
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 1999 Integrated Device Technology, Inc.
FIFO based on an Asynchronous edge triggered input. Asynchronous
FIFO's do not offer the same level of performance or feature set as the
Synchronous FIFO families, but due to their simplicity they are still
commonly used. They have densities up to 512Kbits. Asynchronous
FIFO's are Uni-Directional.
The Synchronous FIFO family has seen a number of developments
over the years. The first Synchronous FIFO family, SyncFIFOTM , has
improved performance and some added features when compared to the
Asynchronous FIFO's, but has the main difference of read and write
clock inputs. IDT's SyncFIFO's have maximum clock speeds of 100MHz
and a maximum density of 64Kbits. IDT also has the SuperSyncTM
FIFO, which offers better performance and added features when
compared to SyncFIFO's. SuperSyncTM FIFO's are available in speeds
up to 100MHz and densities up to 4Mbits. IDT's latest and industry
leading FIFO is the SuperSync IITM family. This again has improved
performance and added features when compared to SuperSyncTM
FIFO's. Supersync IITM offers speeds up to 133MHz, densities up to
4Mbit and the most comprehensive set of FIFO features to date. This
family has an architecture and packaging selection that will allow the
family to be further developed in terms of speed, density and features.
In the future we expect to achieve speeds up to 200MHz and 18Mbit
density with the continued development of SuperSync IITM FIFO's .
These FIFO's are all Uni-Directional.
The final family are the Bi-Directional FIFO's. These are capable of
36 bit bus widths with Bus Matching options. This family also includes
the TripleBusTM FIFO, which connects two 18 bit wide Uni-Directional
ports (one is an input port, the other an output port), to a single 36 bit
wide Bi-Directional port.
As mentioned above, IDT's latest FIFO family is the industry leading
SuperSync IITM. This family of FIFO's offers three groups, 'Narrow Bus'
(x9/ x18 bus width), 'Mid Bus' (x36) and the 'Extended Bus' (x72).
SuperSync IITM offers the best FIFO performance and also offers many
features that are common to all groups. Newly added features on the
SuperSync IITM FIFO's include:
a) Bus Matching, the FIFO input and output bus widths can be different;
b) Endian control, to determine the byte arrangement during Bus
Matching; c) Eight programmable flag default values, are selected
during Master reset; d) Retransmit with zero latency;
e) Synchronous or Asynchronous programmable flag operation;
f) Serial or parallel loading of the flag offsets. Default values are also
available.
Also, the 'Extended Bus' FIFO will introduce some new features to FIFO
devices, these include:
i) Separate clock input for serial flag offset loading;
ii) JTAG - provides 'Boundary Scan' of the FIFO;
iii) Synchronous output enable, synchronized to the read clock;
iv) 256 pin, fine pitch BGA package.
IDT selects leading edge, industry standard semiconductor pack-
ages. Packaging types include standard plastic DIP and CERDIP,
surface mount ceramic LCC, PLCC, SOIC, TQFP and STQFP. IDT's
package development is committed to board space saving packages,
this is highlighted in the SuperSync IITM family of FIFO's, where 80 pin
and 128 pin TQFP packages are used. This family will also include a
256 pin fpBGA (fine pitch BGA) package for its 72 bit wide device, for
the first time in a FIFO, this device will include JTAG, this allows for
the implementation of a Boundary Scan function. Dual packaging for
FIFO's is also available. Here, two discrete FIFO's are packaged
together to save board space. IDT FIFO's are available with standard
power supply voltages of 3.3V and 5V. Also, Industrial, Military and
Commercial temperature grades are available.
IDT is committed to supplying the communication and networking
communities with high performance, feature rich FIFO products. IDT
strives to provide the highest level of product support and customer
service, FIFO product development includes a large degree of
feedback, which takes into consideration customer needs and future
needs. With the continued development of IDT FIFO products and in
particular the SuperSync IITM family, the future offerings of IDT FIFO's
look very exciting.
General FIFO Applications
The sequential operation of a FIFO is particularly useful for
performing any number of system level functions that include, Packet
Buffering, Frequency Coupling, and Bus Matching.
Packet Buffering – Data written into the FIFO can be stored until
the system on the output of the FIFO is ready to accept the data.
Here data input to a FIFO from a digital source are buffered until the
receiving network is ready to read the data. This is particularly useful
in network switching or routing arrangements where several FIFO’s
have discrete input busses, but all FIFO outputs are connected to a
common bus. The outputs of the FIFO’s are ‘polled’ for data by the
receiving system.
Frequency Coupling – Data may need to be transferred from one
frequency domain to another. That is, data may be transmitted from a
digital system running on a particular clock frequency and received
by a system running at a different frequency. Here the FIFO provides
frequency coupling, taking data in at one rate and outputting it at
another. The input and output data rates of the FIFO being controlled
by the discrete Read and Write clock signals.
Bus Matching – Data transfer may need to take place between
separate digital domains with different bus widths. Here the FIFO acts
as a bridge between the domains, channeling the data from the input
of a particular bus width, to the output with another bus width. Bus
matching is a feature that is easily setup on the SuperSync IITM family
of FIFO's. All IDT FIFO's can be easily cascaded to provide greater
depth and expanded in width to give wider data busses.
This Application Guide will show some typical customer FIFO
applications, as well as provide some useful FIFO Application Notes.
The guide will continually be updated and added to, and later versions
published.
A Brief History of IDT FIFO's
In the early 1980s, FIFOs were nothing more than a bank of
parallel shift registers, 4 or 5 bits wide and 8 to 64 nibbles deep.
Within these FIFOs, data ripples from one register to the next, and
the FIFOs thus suffered from long data latency.
By replacing the registers with dual-ported memory cells, FIFO
8
vendors boosted densities and reduced latencies. The FIFO’s internal
counters kept track of the location that was being written to and the
location that was available to be read. FIFO control logic used the
status of the counters to provide flag information. With this approach,
data written into the FIFO became available for reading almost
immediately, and the size of the memory array was independent of the
FIFO’s throughput.
Designers found that when using these faster devices, it was difficult
to take full advantage of the memory capacity because the FIFO offered
only full and empty flags. The addition of a programmable flag function
allowed designers to set the exact full/empty points needed to compen-
sate for system pipeline delays. If a system requires three clock-cycle
delays to recognize a flag, for example, the flag could be programmed
to full minus 3 or empty plus 3. Programmable flags therefore increase
performance and simplify system design.
To accommodate a wider variety of applications, today’s FIFO
architectures offer features such as bus matching; mark and retransmit;
serial load of programmable flag settings; and partial reset — all IDT
innovations. To save board space, IDT also offered the first bidirectional
FIFOs by putting two back-to-back FIFOs in one package.
Increases in system speeds have required more dramatic architec-
tural changes. For example, a synchronous interface (also introduced
by IDT) moves data in or out only on a clock edge rather than on an
asynchronous read or write enable signal. The synchronous interface
eases the interface timing and signaling requirements, as well as
improving the device cycle time.
System speed increases and the need to interconnect systems that
run at radically different speeds have also resulted in the need for
higher-capacity FIFOs. Because the use of 6- or 8-transistor dual-port
memory cells limits FIFO capacity, some FIFOs have moved to 4-
transistor single-port SRAM cells. Known as SuperSync devices, these
FIFOs outwardly function like any other FIFO but offer capacities as
high as 4 Mbits. Internally, SuperSync FIFOs still use small blocks of
dual-ported memory to decouple the inputs and outputs from the main
bank of single-ported SRAM blocks. These FIFOs use complex internal
state machines to monitor counters for multiple memory boundaries,
two variable clock boundaries (read and write), the state of the flag
logic, and pointers for the retransmit function, all of which is transparent
to users.
Even more complex FIFO architectures will further improve speed,
latency, and capacity without major cost increases. One such architec-
ture, known as SuperSync II from IDT, employs small three-port
memories to implement the traditional FIFO input and output along with
Customer Specific
Application Notes

9
 CUSTOMER SPECIFIC APPLICATION NOTES

PCI Bus
Prototyping System/ Algorithm Accelerator Utilizing the IDT72V36110 AN-243 11

HDTV & Image Processing

Application of the IDT72V2113 High Density FIFO within an HDTV Encoder AN-244 15

Medical Equipment
Application of the IDT72V2105 FIFO within an X-Ray Image Processing System AN-245 17

10
 Application of the IDT72V36110 FIFO APPLICATION
within a Prototyping System/Algorithm NOTE
Accelerator. Utilizing a PCI Based AN-243
Architecture.

Features of Report
♦ This application utilizes the IDT72V36110, 128K x36 FIFO
♦ Bus Matching is performed – a 32 bit PCI bus is connected to a
16 bit data bus
♦ Frequency Coupling is utilized, WCLK and RCLK are at
differing speeds
Overview
The FIFO’s are used to buffer data going to and from a PCI bus to
the PRPB (PCI-based Rapid Prototyping Board), data processing
system, this system is actually an “Algorithm Accelerator” based on the
RPP (Rapid Prototyping Platform), which is a product of the system
developer. A typical application would be to run a complex DSP type of
algorithm, such as vocoders and modems.
This application shows how an IDT FIFO in conjunction with a PLD
device is used to implement a PCI bridge. This offers a solution over
using conventional PCI bridge devices which would limit the functional-
ity of this application. This application is a computationally intensive
application, requiring high intensity data transfer flow between the
processing system and the PCI bus, therefore a large FIFO buffer is
required, this is typical of many DSP type applications. A standard PCI
bridge chip, such as the PLX 9080 device has a relatively shallow FIFO
memory, 32 bits wide by 32 long words deep. The IDT72V36110 FIFO
provides a 128K deep FIFO memory, which is adequate for this
application.
Introduction
The hardware Rapid Prototyping Platform (RPP) attempts to bridge the
concept with implementation. It provides a metric for gross decision-
making—on such aspects as the feasibility of the scheme’s complexity and
the partitioning between the hardware and firmware boundaries. For a given
algorithm say there are certain tasks that are time critical and require
enormous computations, like codebook search in the voice processing, it
would be ideal to relegate these types of duties to the hardware where as
other functions of the vocoder can be carried out by firmware. The hardware
can concurrently search for the best or optimal vector while say the gain
shape of the vector can be estimated by firmware since the estimate
involves variable parameters only some of which are used at a given
instance, this would be ideal to implement by firmware. The other metrics
are traditional such as power consumption and cost to implement a function
etc...The RPP is also an algorithm accelerator that is flexible,

FIGURE 1. PRPB BLOCK DIAGRAM

PC I B u s
Bi-directional
Parallel
Port
16
FIFO 1
External Processor Control 32
Signals M odule and Data
Interface 16 Interface
FIFO 2

Low-Skew Clock s

Skew Control
External Recovered
Bus Clock
Clock Clock
Reference Distribution
+2.5V +3.3V
P LL

+2.5V
Power Distribution
+3.3V

JUNE 1999
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 1999 Integrated Device Technology, Inc. DSC-2679/7
 IDT APPLICATION NOTE AN-243
expandable, and portable. Simulated impairments may be encoded into the
test bed and run in real-time. The processed data may then be stored for
other post-processing or displayed for prompt visual inspection, such as
during an onsite customer’s demonstrations.
The PCI-based Rapid Prototyping Board (PRPB) consists of several
logical entities as shown in Figure 1. The Processing Module (PM) contains
all the array of processors with their associated memory support. The PM
may be configured to provide a customized processor through the PCI bus.
The actual data that the PM needs to process and the manipulated data after
being processed both travel through the PCI bus. The Control and Data
Interface (CDI) primary responsibility, then, is to transfer data from and to the
host’s PCI bus while also providing the necessary board’s administrative
controlling logic. The Clock Distribution (CD) network ensures that the
devices within the PM and the CDI receive clocking with no skew and at the
proper frequency. The Power Distribution (PD) provides the power supply
conditioning throughout the PRPB. The CD network comprises of a 'Skew
Control' element and a PLL (Phase Lock Loop), the PLL can be set-up for
any frequency up to 160MHz as required by the different processor modules
that can be tested.
Application of FIFO
From Figure 2 we can see that the FIFO provides data buffering
between the PCI bus and the processors, the FIFO is performing both Bus
Matching and Frequency Coupling. The FIFO on the board is used largely
to benefit from its ability to pass data between the two data buses that are
asynchronous from each other. This is particularly useful when passing
data between two systems, each operating at different frequencies, the
incoming data needs to by synchronized to the local clock before use.
Therefore by passing the data through the FIFO stage the synchronization
is done automatically. In the current design this feature is particularly useful
to synchronize data coming of the PCI bus to the board or system clock prior
to distributing the data to Processing Element. The FIFO’s used on the
board are two unidirectional FIFO devices, the IDT72V36110 which are
128K x 36. One FIFO provides link from PCI world to the board and the other
from the board to PCI world. The FIFO also has a flexible x36/x18/x9 bus
matching feature on both the read and write ports of the device.
The device can be operated in two modes, Standard IDT mode or First
Word flow through (FWFT) mode. The FIFO F1 connects Processing
Element to PCI Interface, which is used to transfer input data to the

FIGURE 2. CONNECTION DIAGRAM

ID T 7 2V 3 61 1 0

F IF O 1

D 18 - D 3 3
32
PC I Bus
D 0 - D 15
33 M H z 16

Q 0-Q 15 I/P
P o rt
W CLK RCLK
33 M H z 66 M H z

32 ID T 7 2V 3 61 1 0
PC I P ro c es sin g
In terfa ce E le m e n t
F IF O 2

Q 18 - Q 33
32
Q 0 - Q 15
16
O /P
D 0-D 15 P o rt
ALTERA
RCLK W CLK
10 K 10 0 A 33 M H z 66 M H z

12

processing array. The FIFO F2 connects PCI Interface to Processing
Element which is used to transfer processed data to the PCI bus or external
world. Figure 3 shows the block diagram of such a connection and logical
signal flow between FIFO’s, Processing Element and PCI Interface. The
control signals can be say classified as those related to read/write signals
and status monitoring signals and other control signals related to bus
matching. The Processing Element generates all the read signals for FIFO
F2, including the clock signal. All the status monitoring signals such as FIFO
empty, FIFO partially empty signals or re-transmit signals are monitored by
Processing Element. It also generates the appropriate write signals for
FIFO F1, including the write clock signal. All status monitoring signals such
as FIFO full, FIFO partially full are controlled by Processing Element.
Conversely on the other side, the PCI Interface generates write related
signals for FIFO F2 and read signals for FIFO F1. However both the read
and write clocks are generated by the Injection Lock Loop (ILL), rather than
fed from the PCI clock. Since the PCI Interface does not have a local PLL
and the clock can only be taken out via a flip flop there by the frequency at
which FIFO can operate is PCI clk /2 , i.e at 16.66 MHz (given that PCI clock
operates at 33MHz). Thereby the through put of the FIFO is effected, so in
order to maintain at least PCI clock rate the clock to the FIFO’s from PCI
Interface end comes from the Injection Lock Loop, (which runs at 33MHz)
. All the bus matching related signals and internal programmable registers
are controlled by the PCI Interface. The FIFO’s are reset from the PCI
Interface via the master reset signal.
The clock frequency between the FIFO and the PCI bus is 33MHz, the
frequency between the FIFO and the Processor Module is variable, but will
be less than 100MHz. This is Frequency Matching, the PCI bus runs at
33MHz into one port clock of each FIFO, the other clock of each FIFO is
typically running at twice the PCI frequency, around 66MHz.
Bus Matching
The bus matching feature of the FIFO is particularly useful in connecting
data buses of uneven width. This feature is used to match the data bus of
the PCI world and the data bus to the processing array. There are two
reasons to for bus matching.
BUS MATCHING SIGNAL FOR FIFO F1 (PCI TO PROCESSING ELEMENT)
BM IW OW WRITE PORT WIDTH
H L H X 36
BUS MATCHING SIGNAL FOR FIFO F2 (PROCESSING ELEMENT TO PCI)
BM IW OW WRITE PORT WIDTH
H H L X 18
13
IDT APPLICATION NOTE AN-243
The data coming from the PCI bus is a burst of 32 bit words. The data
for the application does not require high bandwidth, thereby the Processing
Element side does not require such a high bandwidth of data bus. So there
is no need to connect all 36 bits of bus on the output or input side of the FIFO
on the Processing Element side. Translation of the 36 bit word to smaller
word sizes is performed by the FIFO thereby shifting the burden away from
the PCI Interface to the FIFO. There is a provision on the FIFO to select
which part of the small word can be shifted out first, Endian Control. FIFO
F1 passes data from the 32 bit PCI bus to the Processor Module, therefore
its input port bus width is set-up for x36 and its output port width is x18. FIFO
F2 takes data from the Processor Element and passes it to the PCI bus,
therefore its input port is set-up for x18 and its output port is x36. The data
from the processing array side can be read or written at twice the rate of the
PCI bus and thereby maintain the throughput. The 32 bit word from the PCI
bus is buffered in the PCI Interface and moved to the 36 bit input data bus
to the FIFO (the upper 4 bits can be zero). The FIFO splits the word into two
18 bit words and can be read on the 18 bit output data bus whose clock
frequency can be different to the PCI clock frequency. Similarly two 18 bit
words are written into the FIFO prior to reading the 36 bit word. The settings
for the bus matching signal for current configuration are tabulated below.
For other bus configuration matching set ups refer data sheet for
IDT72V36110.
The signal BE is used to select which half of the word needs to be read
first during the read cycle . During reset if FIFO finds BE to be Low then Big
Endian format is used if BE is high than little Endian format is used.
The 36 bit word can only be read after both the 18 bit words have written.
This can be checked by sampling the Empty Flag. The empty flag will be
asserted until both the 18 bit words are written, only after that it will be de-
asserted.
READ PORT WIDTH
X 18
READ PORT WIDTH
X 36
 IDT APPLICATION NOTE AN-243

FIGURE 3. CONNECTION DIAGRAM

33M H z (R ef)
CL K
RS T #

B E#
PR S # FF1BE # IN TA #
OW
SE N # FF1O W
IW
IP FF1IW GN T#
BM
HF# FF1BM
PFM
RM FF1PFM RE Q #
M R S#
FF1M RS#
LD#
FF1L D# AD[31 :0 ]
FS EL1 FF1FSE L1
FS EL0 FF1FSE L0 C/ BE#[3:0]
FF1 RT# RT# FW FT/SI
FF1FW F T/SI
FF 1O E# O E# PAF #
FF1PAF #
FF1EF# EF # FF#
FF1FF#/IR # P AR
FF1 PAE# P AE # W EN#
FF1W EN# FR A M E#
FF1 REN# RE N # W C LK
from IL L TR DY #
FF1 RC LK RC L K
IR DY #
D0-D35
FF1Q[0 :17 Q0- Q17 FF1D[0 :35 ]
ST O P#
DE VS EL#
Processing ID S EL
FIFO F1
IDT7 2V36 110
Elem ent
BE # FF2BE # PE R R #
PR S # OW FF2O W SE R R #
SE N # IW FF2IW
IP BM FF2BM
PR SN T1#
HF# PFM FF2PFM GN D
RM
M R S# FF2M RS#
PR SN T 2#
LD# FF2L D# Vc c
FS EL1 FF2FSE L1
TD I TD I
FS EL0 FF2FSE L0
FW FT/SI FF2FW F T/SI TD O
TD O
O E# FF2O E# TCK
FF2PAF # PA F#
EF# FF2EF#/OR # TMS
FF2FF# FF#
P AE # FF2 PAE# TR ST#
FF2W EN# W EN#
W C LK RE N # FF2RE N#
FF2W C LK
from IL L RE Q6 4#
RC LK
RT# FF2RT#
AC K64#
FF2 D[0 :17 ] D0-D17 Q0- Q35 FF2Q[0 :3 5]

FIFO F2
IDT7 2V36 110
AL TER A
10K 100 PLD

PCI in ter fac e

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14
 APPLICATION
Application of the IDT72V2113 FIFO NOTE
within an HDTV Encoder AN-244

Features of Report
♦ This application utilizes the IDT72V2113, 512K x9 FIFO
♦ FIFO’s are used at numerous points within the design
♦ Frequency Coupling is utilized, WCLK and RCLK are at
differing speeds
♦ The FIFO operates in First Word Fall Through mode
♦ Depth Expansion is performed
Overview
The system described is an HDTV encoder. Within this system an
input video stream is compressed using MPEG2 and output as com-
pressed HDTV video. The FIFO’s are used at various points within the
path, mainly to provide frequency coupling. The FIFO’s are setup in both
x9 and x18 configuration and are typically connected in banks to give
depths of 1Meg. The FIFO’s write and read clocks vary from 27MHz up
to 74MHz. Read and write operations are performed on the FIFO
simultaneously.
Application
The recent introduction of High Definition Digital Television (HDTV)
by U.S. major broadcasters created the need for very high performance
infrastructure equipments such as audio and video compressors.
Compression of the digital video pixel data, coupled with higher order
modulation techniques, is necessary to fit the HDTV broadcast signal
within the FCC allocated spectrum. The relatively high pixel sample
rates and picture density, (compared with a conventional, digitized NTSC
format television signal), leads to demanding requirements for data
buffering and storage in a HDTV compressor. This is particularly true in
the case of equipment used at the network broadcast centers, where the
highest possible picture quality (and in turn, a high number of bits per
compressed picture frame) must be maintained, because a signal may
undergo several concatenations of encoding and decoding by affiliate
stations prior to delivery to the home. A block diagram of a HDTV video
encoder section is shown in Figure 1. Please refer to Table 1 for
corresponding read and write clock frequencies for the FIFO's shown in
Figure 1.
In order to compress the raw digitized video data using the
Advanced Television Standards Committee (ATSC) specified MPEG-2
algorithm, it is first necessary to capture a field or frames worth of active
video pixel data (data in the equivalent of the horizontal and vertical
blanking regions is not used here). At this time, there are two broadcast
standards preferred for prime time HDTV. There is an interlaced format
carrying 1920 horizontal pixels by 1080 lines in two fields of 540 lines at
60 fields per second called the 1080i format. There is also a progressive
format carrying 1280 pixels by 720 lines at a 60 frame per second rate.
In both formats, 20 bit pixel data (10 luminance and 10 chrominance) is
sampled at 74.25MHz. Thus, a field or frame buffer must be capable of
holding over 20Mbits in the case of 1080i, and must maintain sustained
write speeds of 74.25MHz during the active video scan time. This is
over three times the depth required for conventional NTSC field buffers
at a sample rate 2.75 times faster. Specialized DRAM based field buffer
FIFOs typically used in the video industry do not have the required
depths, are difficult to cascade, and cannot meet the speed require-
ments.

FIGURE 1. SYSTEM BLOCK DIAGRAM - HDTV VIDEO COMPRESSOR

MPEG-2
FIFO
(8 L UMA ) COMPRESSOR
(8 CHRO M A)

16
SMPTE-292M VIDEO 9 PARALLEL
Bit Stream FIFO
PARSER PROCESSORS
(Video In)
VIDEO CA PTURE
BOA RD

MPEG-2
FIFO
COMPRESSOR

TILE OUTPUT Compressed

FIFO FIFO
STITCHING PROCESS HDTV Video

JUNE 1999
15
15

 1999 Integrated Device Technology, Inc. DSC-2679/7
 IDT APPLICATION NOTE AN-244

Table 1. Respective FIFO WCLK and RCLK Frequencies:

Video Parser è FIFO è MPEG-2 WCLK=74.25MHz; RCLK=63MHz

MPEG-2 è FIFO è Tile Stitching WCLK=63MHz; RCLK=54MHz
Tile Stitching è FIFO è Output Process WCLK=54MHz; RCLK=27MHz
Output Process è FIFO WCLK=27MHz; RCLK=27MHz

A cascade of IDT’s SuperSync II FIFOs proved to ideally satisfy the
requirements. As shown in Figure 2, the pixel data can be logically
partitioned into luminance and chrominance channels and stored
separately for ease of processing. Thus, two banks of 10Mbits, or
1Mword each is required to completely hold one 1080i field. A depth
cascade of two IDT72V2113 parts at 512K words each is sufficient to
meet the depth requirements. Next, the word width of 10bits must be
satisfied. While width expansion using SuperSync II FIFOs is easily
accomplished by additional parts, it is desirable to reduce system parts
count. In this case, we recognize that the MPEG-2 algorithm only
operates on 8-bit data samples, so the original 10-bit pixel data may be
rounded to 8 bits, fitting nicely into 9-bit wide FIFOs.
In Figure 1, a number of parallel MPEG-2 processors are shown,
each of which compresses a tile of the larger HDTV picture. These tiles
must be “stitched” together in a manner which allows for seamless
motion of objects between tiles. SuperSync II FIFOs may be exploited
here for their depth, comparatively low parts count, and high speed
access to accommodate bursty data from the compression engines.
Similarly, fast access FIFOs are required to act as rate buffers between
the picture processing block and the final output processing which may
operate at disparate clock rates. The final output processing block in
Figure 1 forms the Video Elementary Stream, or VES, which includes
higher level MPEG-2 required syntax elements such as presentation
time stamps, used at the receive end of the broadcast chain to lip sync
audio and video. The VES will be multiplexed with other bit streams
such as Dolby AC-3 encoded audio, user data, and identification tables
in a broadcast grade HDTV encoder to form a final transport stream for
delivery to an RF modulator. While the read/write access requirements
for the final output FIFO are low compared to the up-stream signal
processing, the depth requirements of this FIFO can be very large.
Once again, depth cascaded SuperSync II FIFOs are employed because
their industry leading 4Mbit density provides a significant parts count
reduction over alternative implementations.

FIGURE 2. HDTV FIELD/ FRAME BUFFER

72V21 13 72V21 13
512K x9 512K x9
8 8 8
LUM A D0- Q 0- D0- Q 0- LUM A
DATA IN D7 Q7 D7 Q7 D A TA O UT

EM PT Y IR OR IR OR FU LL
W R IT E EN AB LE WEN REN WEN REN REA D EN AB LE

W RITE CL O C K W CLK RCLK W CLK R C LK REA D C LO CK

72V21 13 72V21 13
512K x9 512K x9
CHRO M A 8 8 8
D0- Q 0- D0- Q 0- CHRO M A
DATA IN D7 Q7 D7 Q7 DATA O UT

OR IR

WEN REN WEN REN

W CLK RCLK W CLK R C LK

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16
 Application of the IDT72V2105 FIFO
within an X-Ray Image Processing
System
Features of Report
♦ This application utilizes the IDT72V2105, 256K x18 FIFO
♦ Illustrates a deep FIFO requirement - 1.5M depth
♦ FIFO depth expansion is performed
♦ Frequency Coupling is utilized, WCLK and RCLK are at
differing speeds
♦ Contains an analysis of FIFO depth based on input and
output data rates and packet size
♦ FIFO is used in First Word Fall Through mode
Overview
The system described In this report is used for predevelopment of
image processing algorithms, which enables testing of algorithms in real
time with a software only implementation directly connected to an X-ray
system. The system is made of 2 elements, the I/O element and the
Processing element, the IDT FIFO’s are used in the I/O element. The I/O
element is bi-directional, within a given system there will always be an I/
O at the front end (set-up for input) and one at the back end (set-up for
output). In between there can be 1-8 Processing elements. Data is input
from a detector system and processed by the Processing Elements. data
is then output from the back end one of the final Processing Element to a
display system.
Previously, an I/O element in this design had two IDT72255 FIFO’s
(18kx18) connected “anti-parallel” to create a bi-directional FIFO
between an image detector/display system and a DSP system (SHARC
– Super Harvard Risc Computer). The main task of the FIFO’s was de-
coupling of the clock domains (detector/display system and DSP
system), a FIFO being ideal for this task. To adapt to the introduction of
an upgraded detector, producing an image peak data rate up to 100 MB/
sec., the system needed extra memory in the DSP section to buffer
image data in order to have the DSP’s processing near to 100% of the
available time. This would require a 1.5 M x 18, preferably dual ported
memory, running at 20 nsec cycles.
The IDT72V2105, 256K x 18 FIFO was utilized to provide this depth.
This FIFO is pin and functionally compatible to the smaller density
72V255 FIFO. A total 6 of these devices connected in depth expansion
and two Altera PLD’s are used to implement the bi-directional ports
between the detector/display-IO and SHARC-IO. The PLD's here select
input or output of the FIFO’s to set the data direction.
Details of Application
This report specifies the design of the hardware modules of the
multiprocessor-based real-time digital image processing subsystem for
dynamic or static x-ray . The system is built of two basic hardware
modules: the I/O Module and the Processing Module. Each basic module
is placed on a discrete board. Both boards may be supplemented by
add-on boards for special functions. Any number of the two basic
17
 1999 Integrated Device Technology, Inc.
APPLICATION
NOTE
AN-245
modules - within physical limits - can be combined in order to meet the
processing and data I/O requirements of the target application. Typically
a processing pipeline structure of the modules is applied.
The I/O module can be configured as image data input or as image
data output. Hence, it is typically placed at the beginning and at the end
of the pipeline. The module communicates with the system host via a
bidirectional control interface and with the image data source/ destina-
tion. The communication in between all boards of the system is always
done via dedicated SHARC links (Super HArvard Risc Computer),
which is the ADSP21060 floating point DSP by Analog Devices.
The Processing Modules perform their function on the data derived
from the input I/O Module and pass the data to the subsequent
Processing Module in the processing pipeline or, for the last processing
module, to the output I/O module. The maximum number of Processing
modules within an input and output is 8, so we can have 8x12=96
SHARCs for image processing. The number of DSP’s used is deter-
mined by the required processing power.
I/O Module
The I/O Module performs all image data input or output from/to the
system and the communication with the host. Its major tasks are:
In Input Mode: it receives the image data stream coming in from the
image data source - e.g. a detector system – and performs a data
distribution to the subsequent DSP processing nodes located on the
Processing Modules.
In Output Mode: it performs collection of the processed image data
from the processing nodes and the transmission to data destination e.g.
a display system.
In both modes the I/O Module performs a decoupling of the image
data streams between the image source, the processing unit and the
image destination utilizing a FIFO's functionality.
The I/O module also performs the control interfacing to the host of
the system. At first the commands coming from the host are responded
to on interface level. Then they are passed to the command destination
using the same data paths through the pipeline as the image data using
the Message Passing mechanism. Any answer from the destination
node to the host goes again via an I/O Module.
The I/O Module includes a Generic Image Data Interface, (GIDI). As
mentioned above, an application dependent image data interface can
be added as an add-on board.
Refer to Figure 1 'Block Diagram - I/O Module', this shows data
interface elements bridging between the GIDI and DSP nodes. Here the
data interface section utilizes 72V2105 FIFO's (connected in depth
expansion) to buffer data that passes in both directions between the
GIDI and DSP nodes. More detail is gived in the remainder of this
report.
JUNE 1999
DSC-2679/7
 IDT APPLICATION NOTE AN-245
FIGURE 1. BLOCK DIAGRAM - I/O MODULE
D a ta Inte rfac e Im a ge D ata Inte rfa c e D a ta Inte rfac e

D a ta Port G e ne ric Im a ge D a ta Int e rfa c e D a ta P ort

FIF O D a ta I/F D a ta I/F FIF O

Signa l D os e
B us C on trol

D S P B lo c k 0 D S P B lo c k 1

H os t H os t
Inte rfa c e Inte rfa c e
1
0
(S C S I)
(SC SI)

Sha rc Lin k 0 ..5 S ha rc Lin k 0 ..5

Generic Image Data Interface Protocol for GIDI in Output Mode.

The Generic Image Data Interface (GIDI) is a 32 bit high speed image
data port connected to the two busses of the SHARC DSP nodes on the
I/O Module. The GIDI is divided into two channels, each channel includes
16 bits of pixel data and 10 control signals. Each channel can be used as
input or output. However, in this system, both channels operate in the
same direction always. The mode of operation depends on the input/
output function of the I/O Module selected via SHARC DSP software.
Protocol for GIDI in Input Mode.
Refer to Figure 2 'Detailed Diagram of GIDI & Data Port Interface'. An
I/O channel is set to INPUT mode by setting Direction_x to LOW.
Img_End_x will be set inactive by the DSP to initiate an image input (or
output run). The 'Data Port Interface' consists of the Altera PLD and a
bank of IDT FIFO's. The interface (FIFO) will set /IR_x to indicate that it
is ready to accept data. A data word is written into the interface when /
IR_x and /WEN_x are active during the rising edge of CLOCK_x. When
the last data word is read by the DSP from the FIFO, Img_End_x is
asserted again to indicate that the image is complete. In input mode, the
FIFOs will request more data then the DSP is going to read at this
moment. This data has to be flushed from the FIFO to the DSP before
the next image starts. The image source must be capable of handling
this additional request. The /PAF_x signal can be used to prevent an
input overflow. The DSP software has to react within the time the data
source takes to fill this buffer space. Writing into the interface can be
stopped or slowed down until /PAF_x is de-asserted. Note the /OE_x
must be high when the GIDI operates as input.
An I/O channel is set to OUTPUT mode when Direction_x is set
HIGH. Img_End_x will be set inactive by the DSP to initiate an image
input (or output run). The interface (FIFO) sets /OR_x as soon as image
data is available for output. A data word is read from the interface when
/OR_x and /REN_x are active during the rising edge of CLOCK_x.
When the last data word is read from the interface, Img_End_x is
asserted to indicate that the image is complete. The /PAE_x signal can
be used to prevent an input underflow. The DSP software has to react
within the time the data source takes to empty this buffer space.
Reading from the GIDI can be stopped or slowed down until /PAE_x
becomes de-asserted again. The /OE_x signal can be used to prevent
bus collision when the GIDI changes direction.
I/O FIFO's
Three FIFOs per input channel are implemented in order to decouple
the DSP system clock from the external data clocks. See also Fig. 1
and Fig. 2. The FIFOs allow the system to relax data bursts at the input
or output, thereby yield an optimized load for the processors. A
calculation for the most demanding mode allows us to determine a
minimum FIFO capacity that is required to bridge the data gap between
two successive images.
Image size: 4.62 Mpix
Image speed: 7.5 Img/sec
Clock rate: 50 Mpix/sec.

18
 IDT APPLICATION NOTE AN-245

TABLE 1. SIGNALS ASSOCIATED WITH THE GIDI CHANNELS

Channel_0 includes DATA(15..0) for pixel data and control signals: Channel_1 includes DATA(31..16) for pixel data and control signals:
CLOCK_0 Continous clock input range 100 kHz up CLOCK_1 Continous clock input range 100 kHz up to
to 40 Mhz. 40 MHz. (equal rate as CLOCK_0)
Direction_0 Input/Output mode selection; Direction_1 Input/Output mode selection. Should not be used
to be selected during system startup only. dynamically.
Img_End_0 End of Image controlled by DSP Img_End_1 End of Image controlled by DSP
/OE_0 Image data DATA(15..0) outputs enable /OE_1 Image data DATA(15..0) outputs enable
/OR_0 FIFO Output Ready /OR_1 FIFO Output Ready
/PAE_0 FIFO buffer Almost Empty /PAE_1 FIFO buffer Almost Empty
/REN_0 Read Enable /REN_1 Read Enable
/IR_0 FIFO Input Ready /IR_1 FIFO Input Ready
/PAF_0 FIFO bufferAlmost Full /PAF_1 FIFO buffer Almost Full
/WEN_0 Write Enable /WEN_1 Write Enable
DREQ_0* DMA Request DREQ_1 DMA Request
DACK_0* DMA Acknowledge DACK_1 DMA Acknowledge
Note: * The GIDI provides extra signals to handle DMA transfers. These signals may be used to simplify the handling of devices supporting DMA placed on the adapter module.

TABLE 2. SIGNALS REQUIRED FOR IMAGE INPUT & OUTPUT

Channel_0 input Channel_1 input Channel_0 output Channel_1 output
Direction_0 =low Direction_1 =low Direction_0 = high Direction_1 = high
Img_End_0 Img_End_1 Img_End_0 Img_End_1
DATA(15..0) DATA(31..16) DATA(15..0) DATA(31..16)
/WEN_0 /WEN_1 /REN_0 /REN_1
/IR_0 /IR_1 /OR_0 /OR_1
/PAF_0 /PAF_1 /PAE_0 /PAE_1
/OE_0 = high /OE_1 = high /OE_0 = low /OE_1 = low

Optimized FIFO capacity must be: 4.62 – (4.62)2 * 7.5 / 50 = FIFO access from the GIDI Interface.
1.42 Mpixels The GIDI Interface control is implemented in the GIDI_IF-EPLD. The
(A derivation is provided at the end of the report). EPLD is located between the image data I/O and the FIFO. It manages
the FIFO read and write access. The GIDI interface supports one cycle
FIFO Clock Speeds: accesses to or from the FIFOs.
When the FIFO is at the input to a system:
WCLK = 0 – 40MHz and RCLK = 25MHz FIFO access from the Data Port Interface
The data port interface is a memory mapped I/O system towards the
When the FIFO is at the output of a system: FIFO and the data port. It monitors the FIFO flags, supports the I/O from
WCLK = 25MHz and RCLK = 0 – 40MHZ and to the FIFOs and to/from the data port connector.

19
IDT APPLICATION NOTE AN-245
FIGURE 2. DETAILED DIAGRAM OF GIDI & DATA PORT INTERFACE
/ir_0 GIDI_IF DATA PO RT
/paf_ 0
/we n fifo_data_out[15..0]
ALTERA EPLD ALTERA EPLD
clock_0
EPM EPM
7128SQC100-7 7256TQC208-7
data[15..0]
fifo_data_in [15..0]
sharc_bus_0
clock_0
/or_0
/pae_0
ren/
oe/

G
E FIFO 0..2 fifo_data_out[15..0]
N
E
R
Bank of 3
I
fifo_data_in[15..0]
C IDT72V2105
256K x 18
I
M
A fifo_flags_0
G fifo_flags_1
E
im age_end_0
direction
D
A
T
A
/ir_0
GIDI_IF DATA PO RT
I /paf_0

N /wen fifo_data_out[15..0]
clock_0 ALTERA EPLD ALTER A EP LD
T
E EPM EPM
data[15..0] 7128SQC100-7 7256TQC208-7
R
F fifo_data_in [15..0]
A clock_0 sharc_bus_1

C /or_0
E /pae_0
ren/
oe/

FIFO 0..2 fifo_data_out[15..0]

Bank of 3
IDT72V2105 fifo_data_in[15 ..0]
256K x 18

fifo_flags_0
fifo_flags_1

im age_en d_0
direction

20
 IDT APPLICATION NOTE AN-245

FIFO Depth Derivation

C = Image size: 4.62 Mpix
Refer to Figure 3 'Input and Output Data Rate'. The FIFO data
v = Image speed: 7.5 Img/sec
contents will increase according to the slope r of the solid line. At input
r = Clock rate: 50 Mpix/sec.
speed r, an image size C is written into the FIFO after C/r seconds.
When the image speed is v, the next image input will start after 1/v
FIFO Capacity = C – x.
seconds. At this time the FIFO has to be read empty! Now we can draw
a (dashed) line, that represents the continuous readout speed with slope
x = (C*v ) * C/r = C2 * v / r
C*v. The distance between the lines represents the amount of data in
the FIFO at any time. The FIFO is maximum filled at time C/r. It is now
FIFO Capacity = C – (C2 * v / r) = 4.62 – ((4.62)2 * 7.5 / 50) = 1.42
obvious, that the required fifo capacity is defined by C – x
Mpixels.
(Note that C*v must be less then the SHARC bus speed)

FIGURE 3. INPUT AND OUTPUT DATA RATE

Accum ulated
C *v
data

r
Next image
x

0 C /r 1 /v Tim e

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21
22
General Application
Notes

23
 GENERAL APPLICATION NOTES

SuperSync II Mid-Bus FIFO - The Solution to High Density FIFO Requirements AN-242 25
within 36 Bit Bus Applications

Operating FIFO's on Full and Empty Boundary Conditions TN-08 27

Cascading FIFO's or FIFO Modules TN-09 29

Width Expansion of SyncFIFO's AN-83 32

Using IDT SyncFIFO's as Parallel Data Delay Lines AN-122 37

Serial Programming of SuperSync FIFO Flag Offsets: A State Machine Approach AN-130 42

Dual SyncFIFO Applications using the IDT728x1 and IDT728x5 AN-134 59

24
 SuperSync II Mid-Bus FIFO
The Solution to High Density FIFO
Requirements within 36 bit
Bus Applications
IDT72V3660-110 MID-BUS FIFO:
The IDT72V3660-36110 Mid-Bus FIFO can be configured as 36 bit wide
input/ouput busses, with word depths from 4K to 128K. Both Read and
Write clock frequencies up to 100MHz can be applied. The Mid-Bus series
of FIFO's is the ideal FIFO for applications requiring a deep FIFO for 36 bit
wide busses. Where previously one may have performed width expansion
of two IDT72V255LA-65LA SuperSync FIFO's to obtain FIFO depths up to
16K with a bus width of 36 bits, this can now be much more easily achieved
using the new SuperSync II Mid-Bus device. Figure 1 below shows the basic
connections to the Mid-Bus FIFO.
The IDT72V255LA is an 8Kx18 FIFO, the IDT72V265LA is a 16Kx18
FIFO, both are capable of 100MHz operation. Two of these devices can be
configured in Width Expansion to give x36 bit bus width, (provided it is the
same part, giving the same depth). For a 36 bit application where two
IDT72V255 devices would have previously been the solution, the
IDT72V3670 should now be applicable. The V255 and V3670 options both
provide 8K depth. In contrast, a V265 combination should now be replaced
by an IDT72V3680, both options here providing 16K depth.
ADVANTAGES:
The advantages of using the SuperSync II family of Mid Bus devices
over the SuperSync, 72V255LA/265LA parts are:
♦ Reduction in cost and board space used
♦ Reduced Power consumption
♦ No need for Width Expansion
♦ One device can provide a 36-bit bus width with a depth of
4K up to 128K
♦ A single 72V3670 can replace two 72V255LA parts
(or a 72V3680 can replace two 72V265LA's)
♦ No External Flag Logic is required
♦ No reduction in operating speed, capable of 100MHz
APPLICATION
NOTE
AN-242
Easy to Implement
When comparing the implementation of the new SuperSync II, Mid-Bus
FIFO to the older SuperSync IDT72V255-65LA in a system design, there
are a number of advantages that should make the Mid-Bus the natural
choice. The first advantage offered by the new Mid-Bus FIFO is that the
need for width expansion is removed. The Mid-Bus FIFO's are 36 bit wide
devices, the V255/265 parts are 18 bit wide and therefore 36 bit bus
applications required 2 of these devices to be connected in Width Expan-
sion mode. Please refer to Table 1 for a diagram showing the width
expansion arrangement.
No Glue Logic
From the diagram we can also extract a second advantage offered by
the new mid-bus. When performing width expansion there are now 2
devices both possessing discrete status flag outputs, in particular the empty
and full flags. Due to possible timing conflicts between the 2 devices, the
actual empty or full flag status must be a 'composite' of the flag outputs from
both devices, FIFO #1 and #2. Hence, added external logic gates are
required to provide the composite signal. (The gate logic shown is either an
'AND' gate or an 'OR' depending on whether IDT standard mode or FWFT
of operation has been selected). These added gates obviously introduce
added cost, increased power and may take up circuit board real estate.
When designing in the Mid-Bus there is only one empty or full flag signal to
consider, there is no need for composite signals and therefore external
logic.
Low Power
This brings us to a third and often critical point when designing the FIFO
into a system, and that is power consumption. The Mid-Bus FIFO con-
sumes less power even when compared to a single V255/265 device. The
Mid-Bus part has an Icc1 maximum rating of 40mA (when operated at
20MHz, 3.3v Vcc). The V255/265 parts are rated at 55mA. Therefore when
2 of these are connected in width expansion a total Icc1 maximum of 110mA
is obtained. So, within a given 36 bit bus application if two V255/265 devices
are used there is a increase in Icc1 maximum of 70mA.

MID-BUS DIAGRAM
36 36
Data Input Bus D0-D35 Q0-Q35 Data Output Bus

Write Clock WCLK RCLK Read Clock

Write Enable WEN REN Read Enable

Load LD OE Output Enable
Full Flag/ Input Ready FF /IR EF/OR Empty Flag/ Output Ready

Programmable Almost Full Flag PAF PAE Programmable Almost Empty Flag
ID T72V3660-
ID T72V36110
(4K x36 to 128K x36)

Figure 1. The IDT72V3660-110 - 36 bit FIFO

JUNE 1999
25
 1999 Integrated Device Technology, Inc. DSC-2679/7
 IDT APPLICATION NOTE AN-242
Cost & Board Space Reduction There are also some added benefits with the SuperSync II devices
As previously mentioned, two other advantages offered when using the compared to the IDT first generation SuperSync. These include Zero
Mid-Bus FIFO as opposed to the V255/265 devices are the reduction in cost Latency Retransmit, when a retransmit operation is performed the first word
and PCB real estate consumed by the FIFO. Refer to Table 1 for a price to be retransmitted appears on the output immediately. Reduced first data
comparison. word latency, this is the time taken for the first word written to an empty FIFO
With regards to the board space, the Mid-Bus FIFO's are available in a to appear on the output. The SuperSync II family is setting the future of IDT
128 pin TQFP package with a footprint area of 280mm2, the V255/265 are FIFO's, along with all of the benefits mentioned above, the SuperSync II
available in a 64 pin TQFP packages which have an area of 196mm2, offers a road map that includes faster and deeper FIFO's, with many added
therefore 2 devices (required for width expansion) gives a total area of features.
392mm2.
Further Advantages & Benefits
Some further advantages offered by using the Mid-Bus include greater
noise immunity. The Mid-Bus device utilizes a 128 pin TQFP package which
includes additional ground and Vcc lines. Extra pins also allow for the future
development of the SuperSync II family of FIFO's eventually leading to
deeper parts with greater bus widths and faster operating speeds.

TABLE1: COMPARISON OF THE FIFO OPTIONS

IDT72V3660-110 2 x IDT72V255/65LA
(8K x36 to 16K x36)
(4K x36 to 128K x36)

WCL K PAE

WEN RCL K
36 36 LD REN
Da ta Inp ut B us D0 -D 35 Q 0-Q 35 Da ta Output B us V255/265
PAF FIFO#1 OE
W rite Clock W CLK RC LK Re ad Cloc k FF/IR EF/OR
W rite E nable WEN REN Re ad Enable 18 18
D0-D17 Q0-Q17 36
Lo ad LD OE O utpu t Enab le 36
Full F la g/ Inp ut R ea dy FF/I R EF/O R Em pty Fla g/ O utp ut R ead y 18 18
Data Input D0-D17 Q0-Q17 Data Output
Progr am m able Alm ost Full Flag PAF PAE Program m able Alm ost E mp ty Flag Bus
Bus
WCL K RCL K
IDT72V3660-
IDT72V36110 WEN REN
V255/265
(4K x36 to 128K x36) OE
LD FIFO#2
PAF PAE
FF/IR EF/OR

GATE GATE
Full Flag/ Input Ready Empty Flag/ Output Ready

64 % POWER SAVING
IDT72V3660-110, Icc1 = 40mA 2 x IDT72V255-265LA, Icc1 = 110mA

15% PRICE SAVING

IDT72V3660-110 30 % BOARD SPACE SAVING IDT72V255/65LA

68-Pin
PLCC TOTAL AREA = 280mm2 TOTAL AREA =
392mm2
68-Pin
PLC
C
+ 68-Pin
PLC
C

128 - pin TQFP 6 4-pin TQ FP 6 4-pin TQ FP

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26

Operating FIFO's on Full and Empty
Boundary Conditions
The IDT7201, IDT7202, IDT7203 and IDT7204 (512 x 9, 1,024 x 9, 2,048
x 9 and 4,096 x 9) FIFOs have only four control lines: Read, Write, Reset and
Retransmit. The focus of this tech note is the relation of the Read ( R ) and
Write ( W ) lines to the FIFO’s empty and full conditions.
These high-speed FIFOs can perform asynchronous and simultaneous
read and write operations. R and W assert and deassert the Empty Flag
( EF ) and Full Flag ( FF ).Therefore, special conditions exist when a full
FIFO continues to be written to and a read operation takes place. Also,
special timings occur when an empty FIFO continues to be read to and a
write operation takes place. These operations are called the FIFO boundary
conditions.
Read and Write increment the read and write pointers on their respective
rising clock edges.The read and write pointers affect the Empty Flag and Full
Flag counters.The Empty Flag timings are shown in Figure 1. When the
FIFO has only one word in it, the falling edge of R causes EF to be asserted.
After the clock cycle is completed ( R goes HIGH again), EF will remain
asserted and the internal read counter is not affected by subsequent read
cycles. EF is deasserted by the next rising edge of W , after which another
read pulse can be applied to do a read operation. In asynchronous systems,
read and write operations take place at any time; EF is set by one signal and
deasserted by another asynchronous signal.
When R is being clocked on an empty FIFO, the outputs will be in high-
impedance. If a write operation is performed during asynchronous read
cycles, a possible violation of the read pulse width minimum can occur, as
shown in Figure 2. EF is deasserted, but there is an insufficient read pulse
minimum width. To prevent the minimum read pulse width violation, initiate
a read operation only after EF is HIGH, or guarantee a long enough read
pulse width minimum time. A violation of the timing causes an internal glitch
on the FIFO Read which can cause the read pointer to be “out of sync”. Then
the data inside the FIFO may be scrambled or may be garbage. The Empty
Flag and Full Flag counters may also be upset by the internal glitch, which
upsets FIFO memory usage. The only way to recover from this violation is
to do a master reset.
tREF
EF
Figure 1. Empty Flag from Last Read to First Write
FAST is a trademark of Fairchild Semiconductor Co.
27
 1999 Integrated Device Technology, Inc.
TECHNICAL
NOTE
TN-08
A similar situation arises at the full FIFO boundary condition. When the
FIFO is one word from being full, the falling edge of W causes the FF to
be asserted. After the write cycle is completed ( W goes HIGH again), FF
will remain asserted and the internal write counter is not affected by
subsequent write cycles. The FF flag is deasserted by the next rising edge
of R , as shown in Figure 3, after which another write pulse can be applied
to do a write operation.
When the FIFO is full and W is being clocked, data sent to the FIFO will
be ignored and the write pointer will not incre-ment. Here, as in the earlier
case, if these write cycles are asynchronous during a read operation, a
possible violation of the write pulse width minimum can occur, as shown in
Figure 4. Here, FF is deasserted but a sufficient write pulse minimum width
is not met. To prevent the problem, initiate a write operation only after FF
is HIGH, or guarantee a long enough write pulse width minimum time. A
violation of the timing causes an internal glitch on the FIFO write line. This
can cause the write pointers to be “out of sync” where the data inside the
FIFO may be scrambled or may be garbage. The Empty Flag and Full Flag
counters may also be upset by the internal glitch. Again, the only way to
recover from this condition is to do a master reset.
In summary, these FIFOs are designed to transfer only valid data from
input to output. To ensure that valid data is written into and read from,
empty and full FIFOs handshake through the flag mechanism. When there
is no output data available, the reading side must wait until the end of a
write. In a full FIFO, the writing side must wait for the reading side to create
an “empty” location. Incomplete read and write cycles can not only
invalidate data, but can cause the pointers to be out of synchronization,
requiring a master reset to renew data transfer.
This read pulse is ig nore d by the FIFO
tWEF
March 1999
DSC-4307
 IDT TECHNICAL NOTE TN-08

This read pulse is ignored by the FIFO

EF External
to FIFO
t1
R
R (Internal)
INTERNAL READ (1)
EF EF (Internal)
NOTES:
1. Pulse within the FIFO used to clock the write pointer and the Empty and Full Flag counters.
2. If t1 < tRPW (minimum read pulse width low), then the read pointer, Empty Flag and Full Flag counters may be out of sync. See Figure 15 of IDT7201/7202LA data sheet.
Figure 2. Violation of tRPW During Boundary Conditions

This write pulse is ignore d by the FIFO

W

R
tWFF tRFF

FF

Figure 3. Full Flag from Last Write to First Read

This write pulse is ignored by the FIFO

FF
t1
W W (Internal)
INTERNAL WRITE (1)
FF FF (Internal)
NOTES: External
to FIFO
1. Pulse within the FIFO used to clock the read pointer and the Empty and Full Flag counters.
2. If t1 < tWPW (minimum write pulse width low), then the write pointer, Empty Flag and Full Flag counters may be out of sync. See Figure 16 of IDT7201/7202LA data sheet.
Figure 4. Violation of tWPW During Boundary Conditions

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28

Cascading FIFOs or FIFO
Modules
by Suneel Rajpal and Frank Schapfel
The IDT7200/7201/7202/7203/7204/7205/7206/7207/7208 are high-
speed 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768
x 9 and 65,536 x 9 FIFOs, respectively, that can be cascaded to form even
deeper FIFOs. This tech note explains how these FIFOs are cascaded.
A cascaded FIFO configuration of 512 x 9 FIFOs is shown in Figure 1.
The FL pin (First Load) of the first FIFO to be loaded after a reset is tied to
ground. The other FIFOs have their FL pin tied to VCC. After a reset
operation, the first 512 writes occur in the first FIFO. During these write
operations, the XO (Expansion Out) and XI (Expansion In) lines are high.
On the 512th write, a pulse is created on the XO line following the Write (
W ) line. The pulse informs the second FIFO that is going to receive the next
word. It also informs the first FIFO that its write pointer will no longer
increment due to an internal evaluation of the XO line. The XO line of the
first FIFO is connected to the XI line of the second FIFO. The XO of the
second FIFO is connected to the XI of the third, and so on. The XO of the
last FIFO is connected to the XI of the first FIFO. A typical XO operation
of 2,048 writes after a reset is shown in Figure 2.
The same procedure holds true for read operations. During the 512th
read operation after a reset, another pulse will be created on the XO line
following the Read ( R ) line. This pulse will inform the second FIFO that it
will be read from on the next cycle (provided it is n’t empty). Also the first
FIFO’s read pointer will not increment until it receives a second pulse on its
XI line.
Figure 3 shows the XO and XI relationship to read and write. The XO
pulses are transferred to the XI of the next level of FIFO. The first pulse
transfers write pointer control and the second transfers read pointer control.
There is an important advantage to this method expansion. A word written
to the FIFO after a master reset is immediately available at the FIFO output.
A read cycle can be initiated as soon as the Empty Flag ( EF ) is unasserted.
This is called zero fall-through time. Earlier shift register-based FIFOs have
a fall-through time in the µsec range.
To take full advantage of this unique expansion feature, some design
precautions must be observed. Since a pulse on XI activates read or write
operations of the FIFO, they must be relatively free from cross-talk noise.
A long trace from the XO of the last FIFO to the XI of the first FIFO is a
potential source of cross-talk noise. To prevent noise spikes from altering
the XI input on this and other XO to XI interconnects, a small capacitor
in the 22pF to 47pF range should be inserted between the XI inputs and
ground.
29
 1999 Integrated Device Technology, Inc.
TECHNICAL
NOTE
TN-09
Another important point is how to handle flags in the expansion mode.
To create the composite Full Flag, tie the four individual FIFO Full Flags (
FF ) to an OR gate. The composite EF is created similarly. This additional
logic is shown in Figure 1.
To create intermediate flags using the individual Full and Empty Flags
is more tricky, but can be done. For example, an attempt to create a
composite Half-Full Flag ( HF ) is described here. Let us define Flag f1 as
when any two FIFOs are full and at last one other FIFO is not empty.
Boolean Equation for f1:
f1 = FF1.FF2(EF3 + EF4 ) +
FF2.FF3(EF1 + EF4 ) +
FF3.FF4(EF1 + EF2 )
FF4.FF1(EF2 + EF3 )
FFi = Full Flag of FIFOi
EFi = Empty Flag of FIFOi
In one extreme case, f1 is asserted when there is 1,500-1 words in the
FIFO array. The first two FIFOs are full, with 512 words in each, and the
third FIFO has 511 words. Another extreme case is when two FIFOs are full
and the third FIFO has only one word. Therefore, Flag f1 is only a range of
words where the half-full condition exists, from 1,024+1 to 1,500-1
words in the array. It may not be used as a half-full indicator, because the
FIFO array may be almost 3/4 full before Flag f1 is asserted.
As shown in Figure 4, an empty FIFO array has a word written to it and
then read from it. Then, 1,500-1 words are written to the FIFO array. The
write pointer is on the last word of the third FIFO. Only at this time is Flag
f1 asserted, while the FIFO array has 1,500-1 words in it. Intermediate flags
like f1, generated from Boolean Equations, can only provide a range of
values when f1 is to be asserted. A precise position for f1 cannot be
determined. If Boolean Equations are used to generate intermediate flags,
consider all the different locations of the read and write pointers which may
assert or deassert at a particular condition.
March 1999
DSC-4410
 IDT TECHNICAL NOTE TN-09

COMPOSITE FF COMPOSITE EF
XO
FF EF
DO-8 QO-8
#4 FL VCC
XI

XO
FF EF
DO-8 QO-8

#3 FL VCC
DATA IN XI DATA OUT
0-8 0-8
XO
FF EF
DO-8 QO-8

#2 FL VCC
XI

XO
FF EF
DO-8 QO-8
#1
XI FL GND

NOTE:
Read, Write and Reset controls go to all four FIFOs. TN-09 drw 01
Figure 1. Four Cascaded 512 x 9 FIFOs

512th WRITE 1,024th WRITE 1,536th WRITE 2,048th WRITE

XO (FIFO 1)

XO (FIFO 2)

XO (FIFO 3)

XO (FIFO 4)

TN-09 drw 02

NOTE:
Read line is assumed to be HIGH in this example
Figure 2. The XO XI Timing Pulse for 2,048 Writes and Zero Reads
XO/XI

30
 IDT TECHNICAL NOTE TN-09

512th W RITE 1,024th WRITE

512th READ 1,024th READ

R

XO (FIFO 1)
1 2

XO (FIFO 2) 3 4
TN-09 drw 03
NOTES:
1. Pulse 1 is created by the 512th write pulse; it is a delayed write pulse.
2. Pulse 2 is created by the 512th read pulse.
3. Pulse 3 from FIFO 2 is created by the 1,024th write pulse.
4. Pulse 4 is created by the 1,024th read pulse.
5. XO (FIFO 3) and XO (FIFO 4) are not shown, but they follow the same pattern.
6. XO (FIFO 4) will be created by the 2,048th write pulse and later by the 2,048th read pulse, thereby transferring pointer control back to FIFO 1.
Figure 3. The XO and XI PulseTimings

#4 #4

2 WRITE POINTER
#3 #3

WRITE POINTER 1

#2 #2

#1 #1

READ POINTER READ POINTER

TN-09 drw 04

Case 1: In the cascaded FIFO arrangement, the write pointer has just written to FIFO #3 Case 2: The FIFO array is half-full at arrow at Note 1, but f1 will not be asserted until the
and the flag defined by the f1 equation would be asserted at the half-full point. last write into FIFO #3 or until the FIFO array is almost 3/4 full or at arrow 2.
Figure 4. The Behavior of the f1 Flag for Different Cases

31
 Width Expansion Of SyncFIFOs Application
(Clocked FIFOS) Note
AN-83

by Rob De Voto
INTRODUCTION
The performance requirements of today’s systems are continually
reaching to new heights. In response to needs for higher performance, IDT
has introduced a family of First-In-First-Out (FIFO) buffers which are ideally
suited for system speeds of 25MHz or greater. The synchronous interface
of this family of Clocked FIFOs offers several advantages over the tradi-
tional IDT720X Series of FIFOs:
a) speed (data transfer rates of up to 67MHz;
b) free running clock control simplifies system design.
The Clocked FIFO family includes x8-bit, x9-bit, and x18-bit parts in a
wide range of densities. To accommodate system requirements beyond
this product family, the FIFOs can be easily expanded in width and depth.
The purpose of this Application Note is to discuss design considerations
and recommendations when designing with SyncFIFOs (Clocked FIFOs) in
Width Expansion.
SKEW TIMING
The inherent advantage of FIFO buffers is the ability to buffer data
between two mismatched systems or subsystems. Inherent to an interface
between two asynchronous systems is the issue of synchronizing events on
one side with respect to events on the other.
For the Clocked FIFOs, internal logic is used to synchronize the status
flags to either the Write Clock (WCLK) or the Read Clock (RCLK). A skew
time is specified which deter-mines if sufficient time has been allowed for the
flag to be updated in the current clock cycle. If the skew timing is not met,
an extra cycle is required to update the flag.
WIDTH EXPANSION
When using the Clocked FIFOs in Width Expansion, the control signals
of all parallel FIFOs should be connected together to maintain concurrent
operations on all devices. The recommended flag output circuitry is shown
in the following section.
DESIGN CONSIDERATIONS
Inherent to all Clocked FIFOs is the concept of skew timing. In reality, the
skew timing of individual devices may vary by a small amount. For example,
the tSKEW1 minimum spec for the 20 ns speed grade of the IDT72211 (512
x 9-Bit) equals 8ns. For two devices in width expansion, the actual tSKEW1
of FIFO#1 may equal 7.2ns and the actual tSKEW1 of FIFO#2 may equal
7.4ns.
This small variation in the actual timing of the devices may cause the
flags of the parallel devices to be de-asserted in different cycles. For
example, if the tSKEW1 timing of the system happens to be 7.3ns on the
edge which is de-asserting the EF, then the EF of the two FIFOs will be de-
asserted on different clock cycles.

tCLK
tCLK H tCLK L

W CLK

tDS tDH

DO - D7

DATA IN V ALID
tENH
tENS

WEN NO O PERAT ION

tWFF tWFF

FF
tSKEW (1)

RCLK

REN

NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 1. Skew Timing
April 1999
32
 1999 Integrated Device Technology, Inc. DSC-2649
 IDT APPLICATION NOTE AN-83

R ESET ( RS) R ESET ( RS)

D ATA IN (D ) 2x x x

R EAD CLOCK (R CLK)

W RITE C LO CK (W CLK)
R EAD EN ABLE ( REN)
W RITE EN ABLE ( WEN)
OU TPUT EN ABLE ( OE )

ID T ID T
Clocked Clocked
FIFO FIFO

x x D ATA O UT (Q) 2x

Figure 2. Block Diagram Showing the Control Signals of a SyncFIFO (Clocked FIFO) in a Width Expansion Configuration

In this situation, if REN is asserted to begin read operations when the
EF of FIFO#1 is de-asserted but the EF of FIFO#2 is not de-asserted, then
data on the outputs (Q) of the two devices will not be aligned. In other words,
data from FIFO#2 will have a one location lag behind data from FIFO#1.
SOLUTION AND RECOMMENDATION
There are two solutions to the situation described.
1. Composite Flag. Monitor the EF from all FIFOs in Width Expansion.
A read operation (REN = low) can begin only when the EF from all devices
have been de-asserted. This is the recommended solution.
2. Use the Almost Empty Flag (AE) to begin read operations. De-
assertion of AE may exhibit the same skew affect as the EF (see next
section), however, using AE does not jeopardize data integrity.
EXCEPTION
The exception to the skew affect is the Programmable Almost-Empty
Flag (PAE), the Programmable Almost-Full Flag (PAF), and the Half-Full
Flag (HF) on the IDT722X5 family (x18 SyncFIFOs). These flags are not
synchronized with respect to any one clock. In other words, they are
asserted and de-asserted with respect to different clocks. In this case, there
is no skew timing (tSKEW1). The monitoring of only one device in Width
Expansion is adequate for these flags.

OTHER FLAGS
This skew affect also applies to the Full Flags (FF) of all the Clocked
FIFOs (x8, x9 and x18 SyncFIFOs), the Almost-Empty Flag (AE) and
Almost-Full Flag (AF) for the IDT72XX0 family (x8 SyncFIFOs), and the
Programmable Almost-Empty Flag (PAE) and Programmable Almost-Full
Flag (PAF) for the IDT72XX1 family (x9 SyncFIFOs). The solution for
these flags is identical to those outlined above. In summary, use composite
flag, i.e. monitor the flags from all devices.

33
IDT APPLICATION NOTE AN-83

W CLK
tDS

D ata Input (D ) D0 (first valid w rite) D1 D2 D3

tE NS

WEN

tS K E W 1

R CLK

EF tRE F

REN

tA tA

D ata Output (Q ) D0 D1

tO LZ
tO E

OE

Figure 3. Skew Timing for FIFO#1

W C LK
tDS

D ata Input (D ) D0 (first valid w rite) D1 D2 D3

tE N S

WEN

tS K E W 1

R CLK

EF tRE F

REN

tA

D ata Output (Q) D0

tO LZ
tOE

OE

Figure 4. Skew Timing for FIFO#2

34
 IDT APPLICATION NOTE AN-83

RESET ( RS ) RESET (RS )

DATA IN (D) 2x x x

READ CLOCK (RCLK)

W RITE CLOCK (W CLK)
READ ENABLE ( REN )
W RITE ENABLE (WEN )
OUTPUT ENABLE ( OE )

IDT
Clocked
FULL FLAG ( FF ) #1 FIFO #1
EMPTY FLAG (EF ) #1
FULL FLAG ( FF ) #2
IDT EMPTY FLAG ( EF ) #2
Clocked
x FIFO #2 x DATA OUT (Q ) 2x

Figure 5. Recommended Block Diagram of Width Expansion using Composite Flags

W C LK
tDS

Data Input (D) D 0 (first valid w rite) D1 D2 D3

tEN S

WEN

tSKEW 1 two cycle s

RC LK

EF tRE F

tEN S

REN

tA

Data Output (Q ) D0

tOLZ
tOE
OE

Figure 6. Waiting Two Clock Cycles after Flag Assertion

35
IDT APPLICATION NOTE AN-83

tC LKH tC LKL

W CLK

tEN S tEN H

WEN

tPAE

PAE n + 1 w ords n words in FIFO

in FIFO

tP AE

RCLK

tEN S

REN

Figure 7. Programmable Flag Timing for the IDT722X5 Family (x18 SyncFIFOs)

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36
 Application
Using IDT SyncFIFOs as Note
Parallel Data Delay Lines AN-122

By Gary Prelesnik and Kim Goldblatt

INTRODUCTION
bit wide buffering for delays of 59, 251, 507, 1019, 2043, and 4091 clock
There are many applications in today’s high speed designs for a data
cycles. Even more flexible is the IDT722x1 family, which provides 9-bit wide
buffering device that will delay a parallel data stream for a known and
buffering for delays from three to 4096 clock cycles. The new dual FIFO
constant period of time.
family, IDT728x1, can easily be configured as an 18-bit buffer for delays
In networking applications it is very common to pull addressing informa-
from 3 to 4096 clock cycles. The IDT722x5LB is an 18-bit wide FIFO family
tion (whether source or destination) from a header block and determine if
that, by virtue of its easy multiple device depth expansion capability, offers
that data packet should be kept, discarded, or passed on to the next node.
longer delays than any lone SyncFIFO can provide. Delays achievable for
In today’s emerging standard of ATM, VCIs (Virtual Channel Identifiers) and
each device type are summarized in Table 1.
VPIs (Virtual Path Identifiers) must be assigned to set up the proper physical
In all cases, the Read and Write Clock pins ( RCLK , WCLK ) are both
connection of a data path. To perform these operations, the incoming data
connected to the clock source for incoming data. The Programmable
stream must be delayed for a period of time. The magnitude of the delay
Almost Full Flag ( PAF ) or Almost Full Flag ( AF ) is tied to the Read Enable
is design-dependent and variable.
( REN ) pin as shown in Figure 1. For devices that have programmable
Digital filtering applications need the same type of delay function for
flags, the value written to the Full Offset Register will determine the number
processing pixel streams. The standard line contains 910 pixels. By
of clock cycles by which the data will be delayed, input to output.
delaying the data stream in increments of 910 and feeding these tap-off
During normal operation, the Write Enable pin(s) must be kept active
points to a digital filter, an effective vertical filter can be constructed.
LOW continuously to achieve the desired constant data delay. It is important
These are only two brief examples of the many potential uses for a
to note that the Write Enable pin(s) cannot be tied directly to ground, as
parallel data delay buffer. This application note will look at how IDT Parallel
there is a reset requirement for all the REN and WEN control lines to be
Clocked FIFOs can be used to implement this function at high speeds.
active HIGH for a minimum of one clock cycle after the rising edge of reset.

GENERAL INFORMATION USING THE IDT722X0 FAMILY

With the large selection of clocked FIFOs that IDT offers, many different The IDT722x0 family has 8-bit input and output ports. These devices
data delay applications can be realized. The IDT722x0 family provides 8- offer depths of m = 64, 256, 512, 1024, 2048, and 4096 words. These FIFOs

SYST EM CLOCK

DATA IN W CLK RCLK

DATA OUT
D0 - D8 Q0 - Q 8
W RITE ENABLE 1
WEN1 OUTPUT ENABLE
OE
W RITE ENABLE 2/LOAD
W EN2/LD

IDT
72421/72201/72211/
72221/72231/72241

RESET FULL FLAG

RS FF
EMPT Y FLAG
EF
PAF PAE PROG RAMM ABLE ALMOST EMPT Y

REN1 REN2

3080 drw 01

Figure 1. The IDT722x1 SyncFIFO used as a 9-bit delay element

March 1994
37
 1999 Integrated Device Technology, Inc. DSC-3080
 IDT APPLICATION NOTE AN-122

CHARACTERISTICS OF IDT SyncFIFOS USED AS DELAY ELEMENTS

Maximum Programmable
Clock Rate 1 Fixed Delay Delay Range Default Delay2
FIFO Size (MHz) (Clock CYC.) (Clock CYC.) (Clock CYC.)
72420 64 x 8 83 59 — —
72200 256 x 8 83 251 — —
72210 512 X 8 83 507 — —
72220 1024 x 8 83 1019 — —
72230 2048 x 8 83 2043 — —
72240 4096 x 8 83 4091 — —
72421 64 x 9 83 — 3 to 63 59
72201 256 x 9 83 — 3 to 255 251
72211 512 x 9 83 — 3 to 511 507
72221 1024 x 9 83 — 3 to 1023 1019
72231 2048 x 9 83 — 3 to 2047 2043
72241 4096 x 9 83 — 3 to 4095 3970
72205 256 x 18 31 — 2 to 254 251
72215 512 x 18 31 — 2 to 510 507
72225 1024 x 18 31 — 2 to 1022 1019
72235 2048 x 18 31 — 2 to 2046 2043
72245 4096 x 18 31 — 2 to 4094 4091
72801 256 x 9 x 2 66.7 — 3 to 255 251
72811 512 x 9 x 2 66.7 — 3 to 511 507
72821 1024 x 9 x 2 66.7 3 — 3 to 1023 1019
72831 2048 x 9 x 2 66.7 3 — 3 to 2047 2043
72841 4096 x 9 x 2 66.7 3 — 3 to 4095 4091
NOTES 3080 tbl 01
1. Applies only to the data delay application.
2. Delay achieved with programmable flag default settings following reset.

have AE and AF flags fixed at the Empty+7 and Full-7 locations, respec-
tively. When used as a delay buffer, these FIFOs provide delays of m = 5
clock cycles. For a greater choice of delays, the IDT722x1 family is
recommended.
USING THE IDT722X1 FAMILY
The IDT722x1 family has 9-bit input and output ports. These devices offer
depths of m = 64, 256, 512, 1024, 2048, and 4096 words. These FIFOs have
programmable AE and AF flags that give the designer the ability to program
delay values in increments of the clock cycle time. A PAF offset value of 3
produces the longest delay.
The PAF will go LOW when the FIFO reaches the AF condition. This is
defined by the value in the Full Offset Register. Since the value in the register
defines the number of locations from the flag assertion to the full condition,
and the delay value is actually the number of locations from empty to flag
assertion, a small calculation must be made to achieve the be used to
calculate the correct offset value. This is accomplished by taking the
maximum FIFO size, subtracting the number of clock delays desired, then
adding two to this value. The two is added to account for the one cycle delay
from last write to flag assertion, plus one cycle for REN set up time. The
following equation can be used to calculate the Full Offset Register value for
the 722x1 and 728x1 families:
F=m-D+2
Where: F = Full Offset Register value
m = Maximum FIFO depth
D = Desired delay value (in increments of clock periods)
The FIFO can be configured for loading programmable offsets by
holding the Write Enable 2/Load (WEN2/LD) LOW at reset, then bringing
it HIGH for normal operation. Following this operation, the LD function is
active. When the WEN1 AND WEN2/LD pins are held LOW on the rising
edge of the write clock, the PAE and PAF offsets will be loaded on four
consecutive Write Clock edges. Please refer to the relevant data sheets for
more information on programming offset registers.
Following reset, the offset registers are set to default values; this may
simplify some designs. Table 1 shows the delays achieved for the default
settings of various IDT FIFOs. Perhaps the greatest advantage of using
the 722x5LB as a delay element is that composite depths greater than
4096 words can be achieved simply by daisy-chaining devices. Expand-
ing depth allows longer delays than can be achieved with a single
SyncFIFO. Depth expansion is explained further in the 722x5 data sheet.
By tying the corresponding control signals for the A and B FIFO together,
a single 18-bit wide FIFO can be constructed with the same timing and
functions as the 9-bit wide family. This device type, along with the IDT722x1,
can operate as a delay element at higher frequencies than the IDT722x5
family, which will be discussed in the timing analysis section.
USING THE IDT722X5 FAMILY:
The IDT722x5 family of 18-bit wide FIFOs can be used in delay

38

applications at clock speeds of 31MHz or less. This family also has
programmable AE and AF flags that give the designer the ability to
program delay values in increments of the clock cycle time. Compared to the
722x0 and 722x1 families, the 722x5 PAF flag asserts one WCLK cycle
earlier; therefore, delays achieved for a given PAF offset value will be one
clock cycle shorter. A PAF offset value of 2 produces the longest delay. The
minimum possible delay for the 722x5, when the Full Offset Register is set
to all 1’s, is two clock cycles. Default values are also available as listed in
Table 1.
USING THE IDT728X1 FAMILY:
The latest addition to the IDT clocked FIFO family is the Dual SyncFIFO,
IDT728x1. This family is functionally equivalent to two IDT722x1 FIFOs in
a space-saving TQFP package. The Full Offset Register value needed to
produce a given delay can be calculated using the same equation as for the
722x1 family. (See the preceding section.) Since all data and control
lines for each nine bit slice are brought outside the part, these devices can
be configured for a variety of applications. Figure 2 shows the desired
connections for an 18-bit wide delay buffer.
The following equation can be used to calculate the Full Offset Register
value for a single 722x5:
F=m-D+1
Where: F = Full Offset Register value
m = Maximum FIFO depth
D = Desired delay value (in increments of clock periods)
Perhaps the greatest advantage of using the 722x5LB as a delay
element is that composite depths greater than 4096 words can be achieved
simply by daisy-chaining devices. Expanding depth allows longer delays
than can be achieved with a single SyncFIFO. In order to ensure that once
the PAF flag goes LOW, it will stay LOW, regardless of read and write
pointer movement among the FIFOs, a flip-flop needs to be inserted
between PAF and REN. Refer to Figure 3. Depth expansion is explained
further in the 722x5 data sheet.
9
IDT APPLICATION NOTE AN-122
The following equation can be used to calculate the Full Offset Register
value for the 722x5 in depth expansion:
F=m-D+2
Where: F = Full Offset Register value
m = Maximum FIFO depth
D = Desired delay value (in increments of clock periods)
TIMING ANALYSIS
When using the PAF or AF flag as the Read Enable control, the delay
from the write clock rising edge to the deassertion of the flag plus the read
enable set up time must be less than one clock cycle. This will ensure that
one word of data will be read out for every clock cycle. In this way the data
delay will be accurate.
As an example, let’s look at the IDT72241L15 9-bit FIFO. The Write
Clock to Programmable Almost Full (tPAF) parameter is specified at a
maximum of 10ns, and the Read Enable Setup time (tENS) is specified at
a minimum of 4ns. A 15 ns period will guarantee a valid read on every rising
Read Clock edge with a one nanosecond margin. This scenario allows a
maximum shift frequency of 66.6 MHz.
The IDT728x1 Dual SyncFIFOs have timing parameters similar to the
IDT722x1 9-bit FIFOs. For all speed grades, The sum of tPAF and tENS
determine the minimum clock cycle time for the delay element application.
As a second example, let’s consider the IDT72245LB15 18- bit wide
FIFO. The t PAF parameter is specified at a maximum of 28 ns, and the
tENS is specified at a minimum of 4ns. A 15ns speed grade device, running
at maximum frequency, would not be suitable since the 15ns cycle time is
not large enough to accomodate the PAF response time plus the REN set
up time. However, at a 32 ns clock period or slower, this same device can
meet the timing constraints and offer predictable data delays.
BOUNDARY CONDITIONS
For those FIFOs possessing a programmable PAF, the shortest delay
can be achieved by programming the offset register with the largest

RES ET

RSA
D B0 - RSB
D ATA IN 18 9 D A0 - D A8 DB8
FIFO B
25 6 X 9
W C LKA W C LKB 51 2 X 9
R CLKA 10 24 X 9
C LO C K R CLKB 20 48 X 9
W R ITE EN ABLE WENA1 WENB1 40 96 X 9
W R IT E EN AB LE/LO AD WENA2 /LD A 2WENA2 /LD B
FIFO A
256 X 9 OEA OEB O U T PU T EN ABLE
512 X 9
PFA PR OG RAM M ABLE ALM O ST FU LL F LAG
10 24 X 9
20 48 X 9 RENB1 R EAD EN AB LE
40 96 X 9
RENA1
RENA2
RENB2

QA0 - Q A8 QA0 - Q A8

9
9 18 D AT A OUT

3 08 0 drw 0 2

Figure 2: The IDT784x1 Dual SyncFIFO used as an 18-bit delay element

39
 IDT APPLICATION NOTE AN-122
possible value; i.e. all ones. Under this condition, the 722x1 family will
produce a three cycle delay, and the 722x5 will produce a two cycle delay.
These delays can be accounted for as follows:
1) A one cycle delay from write to PAF flag (for 722x1 and 728x1
families only), plus
2) A one cycle delay for REN set up time (for the 722x1, 728x1 and
722x5 families), plus
3) A one cycle delay for data access time (for the 722x1, 728x1 and
722x5 families).
Figure 4 details the minimum delay timing for the 722x1 and 728x1
families.
Though it is possible to program the Full Offset Register with all zeros,
the minimum permissible value to realize a delay line application is 3 for the
722x1 and 7228x1 families, and 2 for the 722x5 family. This will account for
the three latency factors just explained, plus the time required to keep the
Full Flag (FF) inactive. If 0, 1, or 2 is written in the offset register, FF will be
activated before the PAF flag is recognized, as shown in Figure 5. Any
attempted writes will be prohibited while FF is active, thus corrupting the
incoming data stream.
SUMMARY
IDT’s high-performance SyncFIFOs, comprising the 722x0, 722x1,
728x1 and 722x5 families, are most commonly used as elastic buffers
matching two busses operating at different data rates. The foregoing
discussion show they may also be used to delay parallel data, an increas-
ingly important function for many of today’s high speed designs. Up until
now, devices designed for the exclusive purpose of delaying parallel data
have been unable to operate at frequencies much higher than 20MHz.
However, IDT SyncFIFOs have the capability to operate at clock
frequencies as high as 83MHz. Furthermore, these clocked FIFOs can be
programmed to produce a wide range of parallel data delays. For a single
device, anywhere from 2 to 4096 clock cycles of delay are realizable. Since
the 722x5 family is readily depth-expanded, even larger delays can be
attained. All IDT SyncFIFOs can be width-expanded, thus the data path
width that can be delayed has no upper limit. In conclusion, IDT SyncFIFOs
provide a higher level of performance for data line delay applications than
has previously been available.

WXI RXI
WCLK RCLK
WEN OE
RS REN
LD RS
Dn IDT Qn
FIRST
722x5LB
LOAD
FL PAF
WXO RXO

WXI RXI
SYSTEM CLOCK WCLK RCLK
WRITE ENABLE WEN OE OUTPUT ENABLE
RESET RS REN
LOAD LD RS RESET
DATAIN Dn IDT Qn DATAOUT
FIRST
LOAD 722x5LB
VCC FL PAF
WXO RXO

WXI RXI
WCLK RCLK
WEN OE
RS REN
LD RS
Dn Qn
FIRST IDT
READ
LOAD 722x5LB CLR CLK
VCC FL PAF ENABLE
D Q
WXO RXO

3080 drw 03

Figure 3: A depth expansion of the IDT722x5 used as a delay element

40
 IDT APPLICATION NOTE AN-122

CYCLE 1 CYCLE 2 CYCLE 3

W CLK = RCLK

tEN S

WEN1

tEN H

D0 - D 8 W0 W1 W2 W3 W4

t PAF

t ENS
PAF = REN1
t DS
tA tA
Q0 - Q8 W0 W1

3080 drw 04
WEN2 = HIGH, REN2 = LOW, OE = LOW)
(WEN2
Figure 4: The three cycle minimum delay as it applies to the 722x1 and 728x1 families.

CY C LE m - 3 CY C LE m - 2 CY C LE m - 1 CY C LE m CY C LE m +1

W C LK = RC LK

WEN1 LOW

t EN H

D0 - D8 W m -3 Wm - 2 Wm - 1 Wm Wm + 1
t W FF

FF
t PA F A ssertion of FF if 0, 1, or 2
program m ed into Full Offset R egister
t EN S
PAF = REN1

tA
Q 0 - Q8 W0 W1

308 0 drw 05

WEN2 = HIGH, REN2 = LOW, OE = LOW, m = maximum FIFO depth in number of words )
(WEN2
Figure 5: Maximum data delay timing as it applies to the 722x1 and 728x1 families.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or (408) 727-6116 e-mail: fifohelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 330-1753
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
41
 Serial Programming of SuperSync FIFO Application
Flag Offsets: Note
A State Machine Approach AN-130

by Kim Goldblatt
INTRODUCTION
This application note describes a state machine approach to serially
programming the partial flags on SuperSync FIFOs. Up until recently,
programmable flags on most FIFOs were programmed using parallel data
inputs. In systems where the FIFO data inputs share a common bus with
other devices, this method is not always convenient since it can tie up the
bus at the time of system reset. In such situations, serial programming
allows partial flags to be configured without having to use the bus. Recog-
nizing this advantage, IDT is now offering serial programming on high speed,
exceptionally deep First-In-First-Out memories called SuperSyncs. There
are four SuperSyncs now available: the IDT72261 (16,384 words deep x
9 bits wide), the IDT72271 (32,768 words deep x 9 bits wide), the IDT72255
(8,192 words deep x 18 bits wide), and the IDT72265 (16,384 words deep
x 18 bits wide).
The following discussion will show how a state machine can be de-
signed that can serially load as many as 30 flag offset bits into a SuperSync
FIFO at a maximum shift frequency of 100MHz. The state machine is
designed using the ABEL language and will fit into a single 20V10 PAL.
THE SUPERSYNC SERIAL LOAD
FEATURE
Figure 1 shows the architecture of the IDT72261/72271 SuperSyncs.
Figure 2 gives the architecture of the IDT72255/72265 SuperSyncs. The
only differences between these two devices are the data path width (9 bits
for the former, 18 bits for the latter) and the internal flag offset register
organization. Figure 3 illustrates the IDT72261/72271’s four registers:
PAE LSB (8 bits), PAE MSB (6 bits for the IDT72261, 7 bits for the
IDT72271), PAF LSB (8 bits), and PAF MSB (6 bits for the IDT72261, 7
bits for the IDT72271). Therefore, for the IDT72261, these registers amount
to a total of 30 bits that can be serially loaded; for the IDT72271, the total is
28 bits. Figure 4 illustrates the IDT72255/72265's two registers: PAE and
PAF (each register is 13 bits for the IDT72255, 14 bits for the IDT72265).
Therefore, for the IDT72255, these registers amount to a total of 26 bits
that can be serially loaded; for the IDT72265, the total is 28 bits. (Consult
the respective SuperSync data sheets for further information).
Note that SuperSyncs have two programmable flags: the Program-
mable Almost-Empty (PAE) flag and the Programmable Almost-Full (PAF)

D 0-D 8
WEN WC LK LD SEN

INPUT R EGISTER OFFSET REGISTER

FF /IR
PAF
WR ITE CON TROL FLAG EF/ OR
LOGIC LOGIC PAE
HF
RA M AR RA Y FW FT/SI
16,384 x 9
32,678 x 9
WR ITE POIN TER READ POIN TER

READ
CON TROL RT
LOGIC
OUTPUT R EGISTER

MRS
RESET LOGIC RC LK
PRS
REN

FS TIMING
Q 0 -Q 8
OE 3144 d rw 01

Figure 1. The IDT72261/72271 SuperSync FIFO Architecture

42
 1999 Integrated Device Technology, Inc.
 IDT APPLICATION NOTE AN-130

D 0-D 17
WEN WCLK LD SEN

INPUT REGISTER OFFSET REGISTER

FF /IR
PAF
WRITE CONTROL FLAG EF/ OR
LOGIC LOGIC PAE
HF
R AM A RR A Y FWFT/SI
8,19 2 x 18
16 ,3 84 x 18
WRITE POINTER
READ POINTER

READ
CONTROL RT
LOGIC
OUTPUT REGISTER

MRS
RESET LOGIC RCLK
PRS
REN

FS TIMING
Q 0 -Q 17
OE 31 44 d rw 0 2

Figure 2. The IDT72255/72265 SuperSyncFIFO Architecture

flag. The switching threshold for each of these flags can be set for any
degree of fullness. Therefore, the deeper the FIFO, the greater the num-
ber of offset bits necessary to specify the programmable flag threshold.
Selection of the flag programming mode, serial or parallel, takes place
during Master Reset, according to the level of the Load (LD) line during the
deassertion of the Master Reset (MRS) line. A LOW on LD selects paral-
lel loading. A HIGH on LD selects serial loading. The same LD line also
selects one of two default flag offsets: 127 words from the empty boundary
for PAE, from the full boundary for PAF; or 1,023 words from the empty
boundary for PAE, from the full boundary for PAF. After Master Reset,
the programmable flags operate at the default values until programming (if
necessary) takes place. Refer to Figure 5 for details on the Master Reset
timing.
The SuperSync FIFO is capable of operating in two different modes of
timing: IDT Standard and First Word Fall Through. These modes are se-
lected only during Master Reset, according to the level of the First Word
Fall Through/Serial In (FWFT/SI) line at the deassertion of MRS. A LOW
on FWFT/SI selects IDT Standard Timing. A HIGH on FWFT/SI selects
First Word Fall Through Timing. Serial programming can be performed in
either mode. (Consult the data sheets for more information.)
Four SuperSync pins are used to carry out serial programming: Serial
Enable (SEN), LD, FWFT/SI, and Write Clock (WCLK). Following Master
Reset recovery, as long as SEN and LD are held LOW, flag offsets can be
clocked into FWFT/SI, one bit for every rising edge of WCLK. SuperSync
serial load timing is shown in Figure 6.
A SINGLE PAL STATE MACHINE
SOLUTION
The question arises: How should the designer implement the serial
load function in a real-world application.
To take full advantage of the serial programming feature’s benefits, a
serial boot circuit should be interfaced to the SuperSync FIFO so as to be
completely independent of a system’s bus and processor, which are then
free to perform other functions. Of course, the principal goal is to provide
a serial bit-stream. However, it would be convenient if the circuit could
perform other initialization tasks such as selecting serial programming
and choosing the timing mode (IDT Standard or First Word Fall Through).
What kind of external logic should be used? The implementation
should occupy as little board space as possible. Incorporating the re-
quired serial loading functions into a single chip is desirable. Low device
cost and an ability to efficiently realize small state machines make pro-
grammable logic an ideal choice. Of course, in order for such devices to
operate as synchronous machines, registered outputs are necessary. The
most demanding conditions of a SuperSync serial load application would
require a programmable device to serially shift out the maximum pos-
sible number of offset bits (30 bits for the IDT72271) at the highest allow-
able frequency (100 MHz). The complete design example that follows
will show how a single 20V10 PAL can be used to accomplish not only
this task, but also generate signals to select serial loading and the timing
mode during Master Reset.

43
 IDT APPLICATION NOTE AN-130

TIMING CONSIDERATIONS
The serial load design will be simpler if it can operate at the system
clock frequency without having to divide down the rate. Fortunately, 20V8
PALs are now available that can run at 100MHz.
When selecting the appropriate PAL speed grade, another criterion
needs to be met: the maximum clock-to-output delay (tCO) of the PAL plus
the minimum data setup time (tDS) of the SuperSync FIFO must be less
than the minimum cycle time of the clock:
tCO (max. for PAL) + tDS (min. for FIFO) < TWCLK (min.)
Since the minimum set up time for all SuperSync data and control
inputs is 3.5 ns (10 ns speed grade), the time remaining in a 10 ns clock
period for the PAL clock-to-output delay is 6.5 ns. An example of a PAL
that can meet these timing requirements is the Lattice GAL22V10C (7 ns
speed grade). This device has a clock-to-output time of 4.5 ns. This
device can easily run at 100MHz clock frequency.

72261  16,384 x 9-B IT 72271  32,768 x 9-BIT

8 7 0 8 7 0
EMPTY OFFSET (LSB) REG. EMPTY OFFSET (LSB) REG.

DEFAULT VALUE DEFAULT VALUE

07FH if LD is LOW at Master Reset 07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset 3FFH if LD is HIGH at Master Reset

8 5 0 8 6 0
EMPTY OFFSET (MSB) REG. EMPTY OFFSET (MSB) REG.

00H 00H

8 7 0 8 7 0
FULL OFFSET (LSB) REG. FULL OFFSET (LSB) REG.

DEFAULT VALUE DEFAULT VALUE

07FH if LD is LOW at Master Reset 07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset 3FFH if LD is HIGH at Master Reset

8 5 0 8 6 0
FULL OFFSET (MSB) R EG. FULL OFFSET (MSB) R EG.

00H 00H

3144 drw 03 a 3144 drw 03 b

Figure 3. The IDT72261/72271 Offset Register Architecture

72255  8,192 x 18-BIT 72265  16,384 x 18-BIT

17 12 0 17 13 0
EM PTY OFFSET REGISTER EM PTY OFFSET REGISTER

DEFAU LT V ALUE DEFAU LT V ALUE

07FH if LD is LOW at M aster Reset, 07FH if LD is LOW at M aster Reset,
3FFH if LD is HIGH at M aster R eset 3FFH if LD is HIGH at M aster R eset

17 12 0 17 13 0
FULL OFFSET REGISTER FULL OFFSET REGISTER

DEFAU LT V ALUE DEFAU LT V ALUE

07FH if LD is LOW at M aster Reset, 07FH if LD is LOW at M aster Reset,
3FFH if LD is HIGH at M aster R eset 3FFH if LD is HIGH at M aster R eset

3144 d rw 04a 3144 d rw 04b

Figure 4. The IDT72255/72265 Offset Register Architecture

44
 IDT APPLICATION NOTE AN-130
serial loading. The name for this PAL signal will be WCLK_IN. A LOW on
DEFINING THE PAL’S FUNCTION MRS will be used to initialize the PAL to a known state. Another PAL
Considering our present design goals and what we already know about
input, can be set aside for this purpose and called MRS_IN.
the SuperSync serial port, it is now possible to define the PAL signals
One PAL output can be used to select the timing mode (IDT Standard
(Figure 7) and how they connect to the FIFO.
or FWFT) and also to send out a serial train of offset bits, since both these
In most applications, the flag offsets will be loaded once, shortly after
functions are multiplexed together on the same SuperSync input pin, FWFT/
Master Reset, in one, continuous stream of bits. Since the act of loading
SI. This PAL output, called SER_OUT, will be connected directly to FWFT/
offsets logically follows the selection of programming method (serial or par-
SI. During Master Reset, the PAL can be programmed to present a HIGH
allel) and timing mode (IDT Standard or FWFT), it makes sense to incorpo-
on SER_OUT to configure the SuperSync for First Word Fall Through
rate these Master Reset configuration activities together with a state ma-
mode, a LOW for IDT Standard Mode. After Master Reset, offset bits,
chine for the serially generating offsets–all in the same PAL.
likewise programmed into the PAL, will be clocked out on SER_OUT in
First, consider what kind of signals need to be assigned to the PAL
sequence, one bit for every rising edge of WCLK.
pins. Since PALs are available that can operate at frequencies of 100
In many designs, offset registers are programmed once but never
MHz, the SuperSync WCLK line, even when running at maximum fre-
read. In such cases, the SuperSync’s LD line is set HIGH during Master
quency, can be connected directly to the PAL clock input to synchronize
Reset to select the serial programming method and set LOW during serial

t RS
MRS

tRS S tRSR

REN

tRSS tRSR

WEN

tFW FT tRSR
FW FT/SI

t RSS tRSR

LD

tRSS

RT

tRSS

SEN
tRSF
If FWFT = HIG H, OR = HIGH
EF /OR If FWFT = LO W, EF = LOW
tRSF
If FWFT = LOW , FF = HIGH
FF / IR If FWFT = HIG H, IR = LOW

tRSF

PAE

tRSF

PAF , HF

tRSF
OE = HIGH
Qn
3144 drw 05
OE = LOW

Figure 5. SuperSync Master Reset Timing

45
 IDT APPLICATION NOTE AN-130

WCLK

t EN S t EN H ttEN
EN H
H

SEN

t LD S t LD H ttLD
LD H

LD
tDS

EMPTY OFFSET (LSB) EMPTY OFFSET (MSB) FULL OFFSET (LSB) FULL OFFSET (MSB)

BIT 0 BIT 7 BIT 0 BIT X (

(1) BIT 0 BIT 7 BIT 0 BIT X (1)
(
SI 1 1
3144 drw 06
) ) 3144 drw
NOTE: 06
1. X = 4 for the IDT72255.
X = 5 for the IDT72265 and IDT72261.
X = 6 for the IDT72271.
Figure 6. SuperSync Serial Load Timing (IDT Standard and FWFT modes)

System C lock
ID T72271

Supersync
Lattice FIFO
G A L22V10

U W CLK_IN
Q CLK W CLK
V LD_OUT
Q Q LD
W SEN_OUT
Q Q SEN
State
Variables X SER_OUT
Q Q FW FT/SI
Y M RS_IN
Q I MRS
Z
Q

System Reset

3144 d rw 07

Figure 7. Connections Between the PAL and the FIFO

loading to access the offset registers. It is not used for any other purpose.
The PAL output called LD_OUT will be used to drive LD. The FIFO’s
SEN also needs to be HIGH during Master Reset and LOW during serial
loading; however, since these two lines have different hold time require-
ments, a separate PAL output, called SEN_OUT, will be designated to
drive SEN.
In the event an application requires it, the offset values can be ac-
cessed once they have been programmed in by setting REN and LD
LOW; then the contents of the offset registers will be displayed on the
data outputs, one register for every rising edge of RCLK, starting with the
PAE LSB register and ending with the PAF MSB. In this case, LD and
SEN must be driven separately–by dedicated PAL outputs. This is an
additional function that can be incorporated into the PAL if necessary.
Figure 8 shows that six registered outputs have been set aside for use
as state variables. They are called U, V, W, X, Y, and Z. These lines,
taken together, with U as the most significant bit and Z as the least signifi-
cant bit, represent a binary code for identifying states. For example, states
S0, S1, and S2 correspond to 000000, 000001, and 000010 respectively.
Using six variables, it is possible to design a state machine that has 26 =
64 different states. The design illustrated in the next section uses only 33
states, but still requires all six variables.
Counting all the PAL output functions assigned yields a total of nine.
A 22V10 PAL, which has 10 registered outputs, would be a suitable device
for this application.

46
 IDT APPLICATION NOTE AN-130
DESIGNING THE STATE MACHINE
FO RC E 0/1/X S0 MRS = 1
Configuring the FIFO at Master Reset and serial loading of the pro- R ESET FO RC E 1/1/FW F T
grammable flag offsets are both accomplished in the state diagram shown MRS = 1, FO R C E 0/1/X H IG H

in Figure 8. A working PAL program for this state machine, written in the MRS = 0
NO OP
ABEL language, is provided at the end of this application note. MRS = 0 FO RC E 1/1/FW F T

The first states, S0, S1, and S2 are required for FIFO configuration FO RC E 1/1/FW F T
S1
during Master Reset. Following PAL power up, if MRS_IN is HIGH, the FO RC E 1/1/X
R ESET
MRS = 0
FO RC E 1/1/FW F T
machine will begin operation in S0 and wait for the falling edge of a reset LO W

pulse. If MRS_IN is LOW, the machine will begin operation in S1 and wait
MRS = 1
for a rising edge on MRS_IN. (Refer to the following section, entitled “Power FO RC E 1/1/FW F T
Up Considerations” for more information on PAL initialization.)
The combined function of S0 and S1 identifies the profile of a negative- S2
R ESET
going pulse on MRS_IN. These states set the PAL outputs, LD_OUT, R ECO VERY
SEN_OUT, and SER_OUT, at logic levels appropriate for configuring the
SuperSync FIFO during Master Reset. LD_OUT (LD on the FIFO) is forced FO RC E 0/0/SI

HIGH to choose the serial programming method. Forcing SEN_OUT (SEN

on the FIFO) HIGH inhibits serial loading. During Master Reset, SER_OUT S3 S10
FO RC E 0/0/SI
(FWFT/SI on the FIFO) selects the FIFO timing mode (HIGH for First Word PAE L SB PA E LSB
BIT 0 BIT 7
Fall Through mode, LOW for IDT Standard mode). The PAL program should
be adjusted so that SER_OUT is at the appropriate level during Master
FO RC E 0/0/SI
Reset.
For a Lattice GAL20V10 PAL (7 ns speed grade) operating at 100 MHz,
the reset pulse (going to both the PAL and the FIFO) must stay LOW for at
least two cycles of WCLK. In this case, the state machine will stay in S1 for S11 S17
FO RC E 0/0/SI
two cycles. This measure ensures meeting the reset setup time (tRSS) for PA E PAE
M SB M SB
LD, SEN, and FWFT/SI. (See Figure 9.) If the serial programming op- BIT 0 BIT 6
eration is carried out at a slower frequency with more relaxed timing, a one
FO RC E 0/0/SI
cycle reset pulse may be possible. (Modify the PAL program accordingly.)
Once in S1, when MRS_IN goes from LOW to HIGH, the state ma-
chine changes to S2, which provides a one cycle delay while continuing to
hold LD_OUT HIGH, SEN_OUT HIGH, and SI/FWFT at whichever level
S18 FO RC E 0/0/SI S25
corresponds to the desired timing mode. The purpose of S2 is to hold PAF LSB PAF LSB
BIT 0 BIT 7
these PAL output levels for an additional cycle, so that the reset recovery
time (tRSR) is satisfied.
One cycle later, S2 passes on to S3 and the serial load function com- FO RC E 0/0/SI

mences. The remaining states of the machine are used to clock out the
offsets–one bit per state. Since, on SuperSync FIFOs, both PAE and
PAF can be set anywhere in memory, the deeper FIFOs require more
S26 FO RC E 0/0/SI S32
offset bits to specify flag threshold locations. The deepest SuperSync is PAF M SB PAF M SB
the IDT72271 (32,768 words deep). The offsets for this device contain a BIT 0 BIT 6

combined total number of 30 bits. Therefore, the maximum number of

states required for holding offset bits is 30. If a smaller size FIFO is used, MRS = 0
then the number of states required to implement the machine will be corre-
spondingly less. MRS = 1
Upon entering S3, each WCLK rising edge advances the machine one 3 14 4 d rw 08

state. Each state transmits one bit starting with the PAE offset LSB and
ending with the PAF offset MSB. During this period, SEN_OUT and
LD_OUT are held LOW (the SEN and LD on the FIFO, respectively), and
offset bits are placed on SER_OUT (FWFT/SI on the FIFO).
After the last bit has been clocked out (S32 in the IDT72271 example),
the PAL first deasserts SEN_OUT, then deasserts LD_OUT one cycle later.
LD’s greater hold time requirement accounts for the different deassertion
time. Finally, the machine transitions to a wait state, S0 if MRS_IN is HIGH
or to S1 if MRS_IN is LOW.
NOTES:
1. FORCE LD_OUT/SEN_OUT/SER_OUT specifies the output levels forced in the next
state. X = Don't care.
2. At Master Reset: to select First Word Fall Through timing, set FWFT to 1, to
select IDT Standard timing, set FWFT to 0.
3. For S0 through S32, if, at any time, MRS = 0, the machine will proceed to
S1 and force 1/1/FWFT. For the sake of clarity, these branches are not
shown in the diagram.
4. The ABEL PAL program file provided in the appendix is based on this state
diagram.
Figure 8. State Diagram for Serially Loading the IDT72271

47
 IDT APPLICATION NOTE AN-130

48
NOTES:
1. tCO = Clock-to-output Delay, tSU = Setup Time. (tCO = 4.5 ns max. and tSU = 5 ns min. for the Lattice GAL22V10, 7 ns speed grade.)
2. Following power up, the state machine will begin operation in S0 if MRS_IN is HIGH, S1 if MRS_IN is LOW.
3. To ensure meeting the Reset Setup Time (tRSS ) for LD, SEN and FWFT/SI, MRS_IN must be held LOW for at least two WCLK cycles. As a result, the machine will stay in S1 for two consecutive WCLK cycles.
4. At Master Reset: to select First Word Fall Through timing, set FWFT to 1, to select IDT Standard timing, set FWFT to 0.
Figure 9. 20V10 PAL Timing

POWER UP CONSIDERATIONS
On power up, some PALs are initialized to a known state, others can
begin operation in any one of the available machine states. To ensure
proper initialization of the machine, a “go-to” command has been inserted
into every state listing of the ABEL program. For all functional states, this
command effectively says that any time a LOW is detected on MRS_IN, go
to S1 and wait for completion of the reset pulse.
Note that if the PAL powers up in any state from S1 through S32 and
MRS_IN is not LOW, the bit-loading function will proceed from that state.
In this case, switching on SEN_OUT, LD_OUT, and SER_OUT may par-
tially program the SuperSync FIFO before a Master Reset. This is of no
concern, since, once the system is properly reset (using the same pulse for
MRS on the FIFO and MRS_IN on the PAL), the bit-loading function will
start from the beginning.
Since only 33 of the 64 states specified by U, V, W, X, Y, and Z are used
in the design, 31 non-operational states remain. During power up, it may
be possible for the PAL to wake up in one of these “NO-OP” states. There-
fore, it is important to identify these states in the PAL program and assign
go-to commands, two for each NO-OP state. The first says that if MRS_IN
is LOW, go to S1 and wait for completion of the reset pulse. The second
says that if MRS_IN is HIGH, go to S0 and wait for the beginning of a reset
pulse.
PALS VERSUS SERIAL EEPROMS
Serial EEPROMs are often used for serial boot operations. However,
when constructing an interface to SuperSync FIFOs, a PAL solution has
certain advantages. For example, on many serial EEPROMs, the only way
to control data operations is to use a header byte, which must precede data
on the serial input. This header byte sets start/stop, read/write, and ad-
dress conditions. The serial boot application at hand would involve send-
ing one header byte to an EEPROM for every row of data accessed. Since
one important goal of the SuperSync serial boot circuit is keeping bus and
processor free to perform other activities, sending these header bytes would
require extra, dedicated logic, for instance, a PAL. However, since a single
20V10 PAL can accommodate the entire serial boot function including off-
set storage, the serial EEPROM becomes unnecessary. The single PAL
solution costs less and saves board space.
Another factor to consider is maximum frequency of the SuperSync
WCLK operation, since currently available Serial EEPROMS run at about
a 5 MHz clock frequency. If the frequency that a SuperSync application is
running at is higher, it will have to be divided down to the EEPROM operat-
ing range, necessitating additional external logic. Again, the single PAL
solution is preferable, since 20V10s capable of operating at 100MHz (4.5
ns clock to data) are available at a reasonable cost.
IDT APPLICATION NOTE AN-130
There are still other approaches: Note that the present design uses a
total of 33 states for loading 30 offset bits into the IDT72271. If the num-
ber of states can be reduced to 32 or less, the most significant state vari-
able and its corresponding registered output (U) can be eliminated, thus
permitting a 16V8 to be used. For example, if any of the three smaller
SuperSync FIFOs (IDT72255, IDT72265, or IDT72261) are used, the num-
ber of offset bits required to program the flags will be less than that re-
quired by the IDT72271. Fewer bits means fewer states.
Another way of achieving a 32-state machine is by eliminating the
wait state, S2. It is possible that the timing of a particular application may
not require S2, yet still satisfy Master Reset recovery requirements.
CONCLUSION
An important feature of IDT’s new SuperSync FIFO family is the abil-
ity to load programmable flag offsets in serial or parallel fashion. The
SuperSync FIFO family consists of four exceptionally deep FIFOs: the
IDT72255 (8,192 words x 18 bits), the IDT72265 (16,384 words x 18 bits),
the IDT72261 (16,384 x 9 bits), and the IDT72271 (32,768 words x 9 bits).
Serial programming can be especially useful since it does not need to
use the FIFO’s parallel data bus, which is left free to perform other tasks.
As has been shown, a single PAL can be used not only to serially load flag
offsets, but also to configure the FIFO during Master Reset (i.e. select
serial programming, and choose between IDT Standard mode and First
Word Fall Through timing). The advantages of using programmable logic
are manifold: low cost, high speed, low part count, small board area
usage, and ease of reprogramming.
The design example discussed in this paper serially loads a total of
30 offset bits (the maximum possible number) into the IDT72271 at a
frequency of 100MHz (the maximum possible frequency). The serial load-
ing function was implemented as a state machine, written in the ABEL
language, and programmed into a Lattice GAL20V10 (7 ns speed grade).
For many applications, timing requirements will be less stringent. For the
IDT72255, the IDT72265, and the IDT72261, the total number of offset
bits is less. In such cases, a 16V8 PAL will be suitable.

USING A 16V8 PAL

The solution offered meets the most stringent requirements of
SuperSync operation: programming the greatest number of offset bits (30
bits into the IDT72271) at the highest frequency (100 MHz). For many less
demanding applications, it is possible to use the smaller, cheaper 16V8
PAL. For example, the present design uses 9 registered outputs; requiring
a 22V10. If a particular application permits a design simplification that re-
duces the number of outputs to 8, then a 16V8 can be used. One way to
achieve this is to combine the LD_OUT and SEN_OUT functions by using
a single output that can drive both LD and SEN on the FIFO, while satis-
fying the hold time for each signal.
49
 IDT APPLICATION NOTE AN-130
APPENDIX: ABEL PROGRAM LISTING
MODULE SERLOAD
TITLE ‘IDT72271 100 MHZ SERIAL LOAD’
DECLARATIONS
SERLOAD DEVICE ‘P22V10’;
WCLK_IN PIN 1;
MRS_IN PIN 2;
LD_OUT PIN 23, ISTYPE ‘REG’;
SEN_OUT PIN 22, ISTYPE ‘REG’;
SER_OUT PIN 21, ISTYPE ‘REG’;
U PIN 20, ISTYPE ‘REG’;
V PIN 19, ISTYPE ‘REG’;
W PIN 18, ISTYPE ‘REG’;
X PIN 17, ISTYPE ‘REG’;
Y PIN 16, ISTYPE ‘REG’;
Z PIN 15, ISTYPE ‘REG’;
ST_VAL = [U,V,W,X,Y,Z];
S0 = [0,0,0,0,0,0];
S1 = [0,0,0,0,0,1]; “RESET, CONFIGURE FIFO
S2 = [0,0,0,0,1,0]; “RESET RECOVERY
S3 = [0,0,0,0,1,1]; “PAE LSB BIT0
S4 = [0,0,0,1,0,0]; “PAE LSB BIT1
S5 = [0,0,0,1,0,1]; “PAE LSB BIT2
S6 = [0,0,0,1,1,0]; “PAE LSB BIT3
S7 = [0,0,0,1,1,1]; “PAE LSB BIT4
S8 = [0,0,1,0,0,0]; “PAE LSB BIT5
S9 = [0,0,1,0,0,1]; “PAE LSB BIT6
S10 = [0,0,1,0,1,0]; “PAE LSB BIT7
S11 = [0,0,1,0,1,1]; “PAE MSB BIT0
S12 = [0,0,1,1,0,0]; “PAE MSB BIT1
S13 = [0,0,1,1,0,1]; “PAE MSB BIT2
S14 = [0,0,1,1,1,0]; “PAE MSB BIT3
S15 = [0,0,1,1,1,1]; “PAE MSB BIT4
S16 = [0,1,0,0,0,0]; “PAE MSB BIT5
S17 = [0,1,0,0,0,1]; “PAE MSB BIT6
S18 = [0,1,0,0,1,0]; “PAE LSB BIT0
S19 = [0,1,0,0,1,1]; “PAF LSB BIT1
S20 = [0,1,0,1,0,0]; “PAF LSB BIT2
S21 = [0,1,0,1,0,1]; “PAF LSB BIT3
S22 = [0,1,0,1,1,0]; “PAF LSB BIT4
S23 = [0,1,0,1,1,1]; “PAF LSB BIT5
S24 = [0,1,1,0,0,0]; “PAF LSB BIT6
S25 = [0,1,1,0,0,1]; “PAF LSB BIT7
S26 = [0,1,1,0,1,0]; “PAF MSB BIT0
S27 = [0,1,1,0,1,1]; “PAF MSB BIT1
S28 = [0,1,1,1,0,0]; “PAF MSB BIT2
S29 = [0,1,1,1,0,1]; “PAF MSB BIT3
S30 = [0,1,1,1,1,0]; “PAF MSB BIT4
S31 = [0,1,1,1,1,1]; “PAF MSB BIT5
S32 = [1,0,0,0,0,0]; “PAF MSB BIT6
50
S33 = [1,0,0,0,0,1]; “NO OP
S34 = [1,0,0,0,1,0]; “NO OP
S35 = [1,0,0,0,1,1]; “NO OP
S36 = [1,0,0,1,0,0]; “NO OP
S37 = [1,0,0,1,0,1]; “NO OP
S38 = [1,0,0,1,1,0]; “NO OP
S39 = [1,0,0,1,1,1]; “NO OP
S40 = [1,0,1,0,0,0]; “NO OP
S41 = [1,0,1,0,0,1]; “NO OP
S42 = [1,0,1,0,1,0]; “NO OP
S43 = [1,0,1,0,1,1]; “NO OP
S44 = [1,0,1,1,0,0]; “NO OP
S45 = [1,0,1,1,0,1]; “NO OP
S46 = [1,0,1,1,1,0]; “NO OP
S47 = [1,0,1,1,1,1]; “NO OP
S48 = [1,1,0,0,0,0]; “NO OP
S49 = [1,1,0,0,0,1]; “NO OP
S50 = [1,1,0,0,1,0]; “NO OP
S51 = [1,1,0,0,1,1]; “NO OP
S52 = [1,1,0,1,0,0]; “NO OP
S53 = [1,1,0,1,0,1]; “NO OP
S54 = [1,1,0,1,1,0]; “NO OP
S55 = [1,1,0,1,1,1]; “NO OP
S56 = [1,1,1,0,0,0]; “NO OP
S57 = [1,1,1,0,0,1]; “NO OP
S58 = [1,1,1,0,1,0]; “NO OP
S59 = [1,1,1,0,1,1]; “NO OP
S60 = [1,1,1,1,0,0]; “NO OP
S61 = [1,1,1,1,0,1]; “NO OP
S62 = [1,1,1,1,1,0]; “NO OP
S63 = [1,1,1,1,1,1]; “NO OP
EQUATIONS
LD_OUT.CLK = WCLK_IN;
SEN_OUT.CLK = WCLK_IN;
SER_OUT.CLK = WCLK_IN;
U.CLK = WCLK_IN;
V.CLK = WCLK_IN;
W.CLK = WCLK_IN;
X.CLK = WCLK_IN;
Y.CLK = WCLK_IN;
Z.CLK = WCLK_IN;
STATE_DIAGRAM ST_VAL
STATE S0: “WAITING FOR MASTER RESET
IF !MRS_IN THEN S1
WITH
LD_OUT := 1;
SEN_OUT := 1;
SER_OUT := 0;
ENDWITH;
ELSE S0
WITH
LD_OUT := 1;
 IDT APPLICATION NOTE AN-130
SEN_OUT := 1; SEN_OUT := 0;
SER_OUT := 0; SER_OUT := 1; “PAE LSB BIT2
ENDWITH; ENDWITH;

STATE S1: “MASTER RESET PULSE LOW STATE S5:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S2 ELSE S6
WITH WITH
LD_OUT := 1; LD_OUT := 0;
SEN_OUT := 1; SEN_OUT := 0;
SER_OUT := 0; SER_OUT := 0; “PAE LSB BIT3
ENDWITH; ENDWITH;

STATE S2: “MASTER RESET RECOVERY STATE S6:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S3 ELSE S7
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 1; “PAE LSB BIT0 SER_OUT := 1; “PAE LSB BIT4
ENDWITH; ENDWITH;

STATE S3: STATE S7:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S4 ELSE S8
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 1; “PAE LSB BIT1 SER_OUT := 0; “PAE LSB BIT5
ENDWITH; ENDWITH;

STATE S4: STATE S8:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S5 ELSE S9
WITH WITH
LD_OUT := 0; LD_OUT := 0;

51
 IDT APPLICATION NOTE AN-130
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 1; “PAE LSB BIT6 SER_OUT := 0; “PAE MSB BIT2
ENDWITH; ENDWITH;

STATE S9: STATE S13:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S10 ELSE S14
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 0; “PAE LSB BIT7 SER_OUT := 1; “PAE MSB BIT3
ENDWITH; ENDWITH;

STATE S10: STATE S14:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S11 ELSE S15
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 1; “PAE MSB BIT0 SER_OUT := 0; “PAE MSB BIT4
ENDWITH; ENDWITH;

STATE S11: STATE S15:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S12 ELSE S16
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 1; “PAE MSB BIT1 SER_OUT := 1; “PAE MSB BIT5
ENDWITH; ENDWITH;

STATE S12: STATE S16:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S13 ELSE S17
WITH WITH
LD_OUT := 0; LD_OUT := 0;

52
 IDT APPLICATION NOTE AN-130
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 0; “PAE MSB BIT6 SER_OUT := 0; “PAF LSB BIT3
ENDWITH; ENDWITH;

STATE S17: STATE S21:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S18 ELSE S22
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 1; “PAF LSB BIT0 SER_OUT := 1; “PAF LSB BIT4
ENDWITH; ENDWITH;

STATE S18: STATE S22:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S19 ELSE S23
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 1; “PAF LSB BIT1 SER_OUT := 0; “PAF LSB BIT5
ENDWITH; ENDWITH;

STATE S19: STATE S23:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S20 ELSE S24
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 1; “PAF LSB BIT2 SER_OUT := 1; “PAF LSB BIT6
ENDWITH; ENDWITH;

STATE S20: STATE S24:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S21 ELSE S25
WITH WITH
LD_OUT := 0; LD_OUT := 0;

53
 IDT APPLICATION NOTE AN-130
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 0; “PAF LSB BIT7 SER_OUT := 1; “PAF MSB BIT3
ENDWITH; ENDWITH;

STATE S25: STATE S29:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S26 ELSE S30
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 1; “PAF MSB BIT0 SER_OUT := 0; “PAF MSB BIT4
ENDWITH; ENDWITH;

STATE S26: STATE S30:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S27 ELSE S31
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 1; “PAF MSB BIT1 SER_OUT := 1; “PAF MSB BIT5
ENDWITH; ENDWITH;

STATE S27: STATE S31:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S28 ELSE S32
WITH WITH
LD_OUT := 0; LD_OUT := 0;
SEN_OUT := 0; SEN_OUT := 0;
SER_OUT := 0; “PAF MSB BIT2 SER_OUT := 0; “PAF MSB BIT6
ENDWITH; ENDWITH;

STATE S28: STATE S32:

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S29 ELSE S0
WITH WITH
LD_OUT := 0; LD_OUT := 0;

54
 IDT APPLICATION NOTE AN-130
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S33: “NO OP STATE S37: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S34: “NO OP STATE S38: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S35: “NO OP STATE S39: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S36: “NO OP STATE S40: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;

55
 IDT APPLICATION NOTE AN-130

SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S41: “NO OP STATE S45: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S42: “NO OP STATE S46: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S43: “NO OP STATE S47: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S44: “NO OP STATE S48: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;

56
 IDT APPLICATION NOTE AN-130

SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S49: “NO OP STATE S53: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S50: “NO OP STATE S54: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S51: “NO OP STATE S55: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;

STATE S52: “NO OP STATE S56: “NO OP

IF !MRS_IN THEN S1 IF !MRS_IN THEN S1
WITH WITH
LD_OUT := 1; LD_OUT := 1;
SEN_OUT := 1; SEN_OUT := 1;
SER_OUT := 0; SER_OUT := 0;
ENDWITH; ENDWITH;
ELSE S0 ELSE S0
WITH WITH
LD_OUT := 1; LD_OUT := 1;
57
 IDT APPLICATION NOTE AN-130
SEN_OUT := 1; SER_OUT := 0;
SER_OUT := 0; ENDWITH;
ENDWITH; ELSE S0
WITH
STATE S57: “NO OP LD_OUT := 1;
IF !MRS_IN THEN S1 SEN_OUT := 1;
WITH SER_OUT := 0;
LD_OUT := 1; ENDWITH;
SEN_OUT := 1;
SER_OUT := 0; STATE S61: “NO OP
ENDWITH; IF !MRS_IN THEN S1
ELSE S0 WITH
WITH LD_OUT := 1;
LD_OUT := 1; SEN_OUT := 1;
SEN_OUT := 1; SER_OUT := 0;
SER_OUT := 0; ENDWITH;
ENDWITH; ELSE S0
WITH
STATE S58: “NO OP LD_OUT := 1;
IF !MRS_IN THEN S1 SEN_OUT := 1;
WITH SER_OUT := 0;
LD_OUT := 1; ENDWITH;
SEN_OUT := 1;
SER_OUT := 0; STATE S62: “NO OP
ENDWITH; IF !MRS_IN THEN S1
ELSE S0 WITH
WITH LD_OUT := 1;
LD_OUT := 1; SEN_OUT := 1;
SEN_OUT := 1; SER_OUT := 0;
SER_OUT := 0; ENDWITH;
ENDWITH; ELSE S0
WITH
STATE S59: “NO OP LD_OUT := 1;
IF !MRS_IN THEN S1 SEN_OUT := 1;
WITH SER_OUT := 0;
LD_OUT := 1; ENDWITH;
SEN_OUT := 1;
SER_OUT := 0; STATE S63: “NO OP
ENDWITH; IF !MRS_IN THEN S1
ELSE S0 WITH
WITH LD_OUT := 1;
LD_OUT := 1; SEN_OUT := 1;
SEN_OUT := 1; SER_OUT := 0;
SER_OUT := 0; ENDWITH;
ENDWITH; ELSE S0
WITH
STATE S60: “NO OP LD_OUT := 1;
IF !MRS_IN THEN S1 SEN_OUT := 1;
WITH SER_OUT := 0;
LD_OUT := 1; ENDWITH;
SEN_OUT := 1; END SERLOAD
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or (408) 727-6116 e-mail: fifohelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 330-1753
58
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
58
 Application
Dual SyncFIFO Applications Using the
Note
728x1 and 728x5 Families
AN-134

By Kim Goldblatt
• Independent use of FIFOs 121-lead Ball Grid Array (BGA) which has an area of 225 mm2 .
• Two-level prioritization of data The two-FIFO-per-package arrangement lends itself to a wide variety of
• Network switching useful applications. Such as: Using FIFOs independently, two-level data
• Width expansion prioritization, network switching, width expansion, depth expansion, bidi-
• Depth expansion rectional configuration, and bus matching. While it is true that any of these
• Bidirectional application applications can be implemented using individual FIFOs (i.e. one FIFO per
• Bus matching package), the Dual FIFOs facilitate the process in designs where board
space is at a premium.
INTRODUCTION
IDT offers two families of dual FIFOs. Each device contains two INDEPENDENT FIFOS
independent FIFO functions in one package. The IDT728x1 family consists The only lines shared in common between the two FIFOs of a dual
of five members: the 72801, the 72811, the 72821, the 72831, and the device are VCC and GND. All control and data inputs, as well as status and
72841. The FIFOs contained in each of these dual products are 9 bits wide, data outputs operate independently for each FIFO. Therefore, no function
synchronous, as well as electrically and functionally compat-ible with the performed by one FIFO can adversely affect the operation of the other
widely-used 722x1 FIFO family, the 72201, the 72211, the 72221, the FIFO. The designer is free to use the two FIFOs for completely unrelated
72231, and the 72241, respectively. Table 1 lists the basic attributes of the functions.
7278x1 family.
The IDT728x5 family consists of three members: the 72805, the 72815, TWO-LEVEL PRIORITIZATION OF DATA
and the 72825. The FIFOs contained in each of these dual products are 18 The two-FIFO-per-package arrangement is useful for sort-ing two
bits wide, synchronous, as well as electrically and functionally compatible different kinds of data that share the same bus. This application is particu-
with the well-known 722x5 FIFO family, (the 72205, the 72215, and the larly useful for multi-media computing. Figure 1 shows how a 728x1 FIFO
72225, respectively). Table 2 lists the basic attributes of the 728x5 family. can be used to sort image and voice data. A processor places both kinds of
The most important advantage of Dual FIFOs is board space savings. data on a 9- bit bus. One FIFO (designated A) is assigned the function
A dual 728x1 (or 728x5) FIFO can perform any function two individual ofrelaying image data from the processor bus to an image processing card,
722x1 (or 722x5) FIFOs can, and, at the same time, occupies only half the the other FIFO (designated B) is assigned the function of sending voice data
board space. The 728x1 family is available in a 64-lead Thin Quad Flat Pack to a voice processing card. The processor’s address and data lines are
(TQFP) which has an area of 248 mm 2 . The 728x5 family is available in a decoded to enable writing to either FIFO A or FIFO B.

Table I: 728X1 Family Attributes

Functionally Max Clock
Part Number Organization Equivalent Frequency Package
To (MHz)
72801L Dual 256 x 9 Two 72201 67 64-pin TQFP
72811L Dual 512 x 9 Two 72211 67 64-pin TQFP
72821L Dual 1,024 x 9 Two 72221 50 64-pin TQFP
72831L Dual 2,048 x 9 Two 72231 50 64-pin TQFP
72841L Dual 4,096 x 9 Two 72241 50 64-pin TQFP

Table lI: 728X5 Family Attributes

Functionally Max Clock
Part Number Organization Equivalent Frequency Package
To (MHz)
72805LB Dual 256 x 18 Two 72205LB 50 121-pin BGA
72815LB Dual 512 x 18 Two 72215LB 50 121-pin BGA
72825LB Dual 1024 x 18 Two 72225LB 50 121-pin BGA

February 1995
59
 1999 Integrated Device Technology, Inc. DSC-3164
 IDT APPLICATION NOTE AN-134
Though, members of the 728x1 family all have redundant read enables
(RENA1 and RENA2 , RENB1 and RENB2), as well as redundant
write enables ( WENA1 and WENA2 , WENB1/ LDB and WENB2/LDB
), only one read enable and one write enable is required from each FIFO.
As shown in Figure 1, RENA1 and RENB1 are used to perform the read
enable function. The unused RENA2 and RENB2 lines are grounded.
WENA1 and WENB1 are used to perform the write enable function.
WENA2/LDA and WENB2/LDB act as write enables if HIGH during reset,
flag offset load enables if LOW during reset. Since these lines are
unecessary , they should be hard-wired to Vcc.
In the event partia l flag programming is desired, WENA2/ LDA and
WENB2/LDB may be configured for the flag offset load enable function
may be selected; however, following Master Reset, care should be taken
to disable loading until the time of programming.
This kind of application is effective not only for sorting different kinds of
data, but also, different priority levels of data; in this way, it can be described
as two-level data prioritization. By adding more Dual FIFOs, any number of
different priority levels or data types can be sorted.
Figure 2 shows how the 728x5 can be used for sorting two different kinds
of data on an18-bit bus. The connections are similar to the 728x1 example–
only the 728x5 does not have redundant read and write enables. Since, for
this application, the 728x5 operates in single device mode (as opposed to
depth expansion mode), the first load inputs (FLA , FLB ), as well as the
read and write expansion inputs ( RXAI and RXIB , WXIA and WXIB
) should be tied to GND.
NETWORK SWITCHING
Network switching products commonly employ large quantities of
FIFOs to switch data from one network destination to another. Dual FIFOs
prove invaluable for this type of application since they can cut the board
area used by a one-FIFO-per- package implementation in half.
The network switchbox design illustrated in Figure 3 shows how FIFOs
can be used to switch data between any combina-tion of available input and
output buses. Data flow is unidirectional. Dual FIFOs are used not only to
buffer the data, but also to manage address usage for a central data storage
memory. In the present example, four input paths and four output paths are
shown;however, the design architecture can be easily expanded to
accomodate as many buses as desired. Such a network switchbox using
the 728x1 is capable of switching 9-bit wide buses; a switchbox using the
728x5 is capable of switching 18-bit buses.
One bank of FIFOs is used to buffer incoming data–one FIFO for each
input bus. (In the diagram, these “Source FIFOs” are labeled A, B, C, and
D.) Another bank of FIFOs is used to buffer outgoing data–one FIFO for
each output bus. (In the diagram, these “Destination FIFOs” are labeled 1,
2, 3, and 4.)
An SRAM data storage block is used to hold cells of information already
received via the Source FIFOs and awaiting transfer to the Destination
FIFOs. For example, ATM cells, typically consist of a five byte header
(containing address information) and a 48-byte string of data. A network
switch box will handle these components differently. The SRAM may be
partitioned into a header section and a data section for more efficient
processing of cell components.
The “Free Address” FIFO keeps track of vacant address locations in the
SRAM storage block.
A final set of FIFOs, called “Available Cell” FIFOs, keep track of cells
stored in SRAM, waiting to be channeled to the Destination FIFOs. Each
“Available Cell” FIFO is associated with one of the output data buses and
holds the SRAM addresses of cells bound for that particular bus. (The
diagram shows four “Available Cell” FIFOs, designated 1, 2, 3, and 4.)
A microprocessor monitors the switch box status, assigns addresses,
and controls data movement.
The network switch box functions as follows: The Programmable
Almost Full ( PAF ) flags of the Source FIFOs are set to switch LOW after
receiving at least one cell of data. The processor periodically checks the
PAF flag of each Source FIFO. As soon as a cell gets written to one of
the Source FIFOs, the associated PAF flag goes LOW indicating data is
available. The processor responds by obtaining an available SRAM ad-
dress from the Free Address FIFO, then reading the cell from the Source

Im ag e
F IFO A P ro cessing
RC LK A Clock Card
W CL K A
Co ntro l

OEA
Lo gic

A ddress
WENA1 RENA1
Co ntro l
9 I/O D ata
DA 0 - DA 8 9
Q A 0-Q A 8 Da ta

V CC WENA2 RENA2
P ro cessor
Clock
Co ntro l

728x5
Lo gic

A ddress
9 -b it b u s

Co ntro l
V oice
F IFO B P ro cessing
Da ta RC LK B Clock Card
9 W CL K B
OEB
Co ntro l

WENB1
Lo gic

A ddress
RA M RENB1
9 Co ntro l
I/O D ata
DB 0 -
Q B 0 -Q B 8 Da ta
9 DB 8 9
WENB2 RENB2

3 1 6 4 drw 0 1

V CC

Figure 1: IDT728x1 Two-level Data Prioritization

60

FIFO and writing it into SRAM at the chosen free address. Once this has
been accomplished, the processor accesses the cell’s header from SRAM
and identifies which Destination FIFO the data is bound for by interpreting
and updating the eader. Then, the processor writes the cell’s SRAM address
to that Destination FIFO’s corresponding Available Cell FIFO.
The Programmable Almost Empty ( PAE ) flags of the Destination FIFOs
are set to switch LOW as soon as sufficient space is available to accomodate
one cell of data.The processor periodically checks the PAE flag of each
Destination FIFO. As soon as space is available in one of the
DestinationFIFOs, the associated PAE flag goes LOW. The processor
responds by obtaining an address from the Destination FIFO’s correspond-
ing Available Cell FIFO and using it to look up a cell stored in the SRAM
memory. Finally, the processor transfers the cell to the appropriate Destina-
tion FIFO and enters the newly-freed cell address into the Free Address
FIFO.
WIDTH EXPANSION
Expanding the data bus width beyond the capacity of a single FIFO is
simply a matter of connecting FIFOs in parallel. In this way, one 728x1
device can handle an 18-bit data bus (Figure 4), one 728x5 can handle a 36-
bit bus (Figure 5). One half of the data lines is directed through the first FIFO,
the other half is directed through the second FIFO. Data is written toboth
FIFOs simultaneously and in parallel. In similar fashion, data is read from
both FIFOs simultaneously and in parallel.
It is possible, due to normal variation of the tskew threshold between FIFOs,
that EFA and EFB will deassert one cycle apart. Consider the case where
a word is written to an empty FIFO. The empty flag, which is synchronized
to the read clock, is LOW. If the time from the rising WCLK edge that wrote
the word to the next rising read clock edge is less than tskew (min.), then
empty flag deassertion requires a second rising read clock edge.
Note that this tskew effect can only occur on flag deassertion, never on flag
assertion. To prevent the two FIFOs from getting out-of-step, EFA and
IDT APPLICATION NOTE AN-134
EFB should be AND-gated together to form a composite empty flag. Only
when both FIFOs have data available to be read, (both EFA and EFB are
HIGH) will the composite empty flag go HIGH.
For similar reasons, the FFA and FFB should be AND-gated together
to form a composite full flag. Consult the 728x1 and 728x5 datasheets for
more information on tskew behavior.
Since, on the 728x1 family devices, PAEA , PAEB , PAFA , and
PAFB are all synchronous, the skew issue applies. If a design calls for
their use, PAEA and PAEB should be AND-gated together to make a
composite programmable almost empty flag; also, PAFA and PAFB
should be AND-gated together to make a composite programmable almost
full flag.
Since, on the 728x5 family devices, PAEA , PAEB , PAFA , and
PAFB are all asynchronous, the skew issue does not apply. If a design
calls for their use, it is sufficient to monitor PAE and PAF on a single
FIFO. (Any FIFO in the width expansion may be chosen for this purpose.)
As shown in Figure 1, RENA1 and RENB1 are used to perform the
read enable function. The unused RENA2 and RENB2 lines are
grounded. Unless WENA2/LDA and WENB2/LDB will be used to load
programmable flag offsets, they should be hard-wired HIGH since WENA1
and WENB1 alone are sufficient to enable writes. If the flag offset load
enable function is selected, the lines should be LOW during reset, then
HIGH until the time of flag programming.
DEPTH EXPANSION
In the event the deepest member of a FIFO family lacks sufficient depth
for a particular application, multiple FIFOs can be connected together to
form a “depth expansion” whose total word capacity is the sum of the
individual FIFO depths. All Dual FIFO families can be depth-expanded
using at least one of the methods about to be described.
Since the goal of depth expansion is to increase the word storage
capacity beyond what is available for single FIFOs, it makes sense to talk

Image
FIF O A P rocessing
R C LK A C lock C ard
W C LKA
C ontrol

OEA
Logic

A ddress
WENA RENA
C ontrol
I/O Data
18 18
D A 0- QA 0 - D ata
D A 17 QA 1 7

P rocessor
C lock
C ontrol

72 8x 5
Logic

A ddress
18-bit bus

C ontrol
V oice
FIF O B P rocessing
D ata R C LK B C lock
18
C ard
W C LKB
OEB
C ontrol

WENB
Logic

A ddress
RAM REN B
18 C ontrol
I/O D ata
D B0- QB 0 -
D ata
18 D B17 QB 17 18

316 4 drw 02

Figure 2: IDT728x5 Two-level Data Prioritization

NOTE:
1. Tie FLA , FLB , WXIA , WXIB , RXIA , and RXIB to GND.

61
IDT APPLICATION NOTE AN-134

SOU R CE FIFO s D ESTIN ATIO N FIFOs

FIFO FIFO
D ATA A IN A D ATA 1 O U T
1
WR ITE
PAF A R EAD CON TRO L A C ON TR OL 1 PAE 1
728x1 or 728x5 728x1 or 728x5

FIFO FIFO
D ATA B IN D ATA 2 O U T
B 2
WR ITE
PAF B R EAD CON TROL B C ON TR OL 2 PAE 2

FIFO FIFO
D ATA C IN D ATA 3 OU T
C 3
R EAD CON TROL C WR ITE
PAF C C ON TR OL 3 PAE 3
728x1 or 728x5 728x1 or 728x5

FIFO FIFO
D ATA D IN 4 D ATA 4 OU T
D
R EAD
PAF D C ON TR OL D PAE 4
WR ITE
C ON TR OL 4
R EAD /WR ITE
AVA ILAB LE C ON TR OL
9-(or 18)BIT INTER N AL D ATA

CEL L
FIF O 1
R EAD /
728x1 or 728x5
W RITE
C ON TR OL
AVA ILAB LE AD D R ESS
CEL L D EC OD E R
FIF O 2

R EAD /WR ITE

AVA ILAB LE C ON TR OL
CEL L
FIF O 3

728x1 or 728x5
R EAD /WR ITE
AVA ILAB LE C ON TR OL
AD D R ESS BU S

CEL L
FIF O 4

R EAD /WR ITE

FRE E C ON TR OL
AD D R ESS
FIFO

M ICR O-
P RO CE S S O R
SRA M
C ELL STOR AGE

H EA D ER D ATA

R EAD /WR ITE

C ON TR OL

FIR M WA R E
POLL IN G O R
IN TER RU PT
C ON TR OL

3164 drw 03

Figure 3: Network Switch Box (9-bit version uses the 728x1, 18-bit version uses the 728x5).

62

about employing thedeepest Dual FIFOs in this way.
If an application requires a data path width of 9-bits and a word depth in
excess of 4,096, then the two FIFOs contained in a 72841 can be configured
as a depth expansion with an overall organization of 8,192 x 9. For about
the same foot-print, this application offers twice the maximum available
depth of the compatible 722x1 family. Figure 6 shows shows the connec-
tions.
Because the 728x1 devices are not equipped with a daisy-chain feature,
depth expansion is achieved by using a ping-pong-approach instead.
The basic idea is to alternate writes between FIFOs A and B. Data is read
out in the same order as was written, back and forth between FIFOs A and
B. The data inputs (DAn, DBn) are connected in parallel, as are the data
outputs (QAn, QBn). The system write clock drives both WCLKA and
WCLKB. The system read clock drives both RCLKA and RCLKB.
The 728x1 lends itself to the ping-pong implementation, since each of
its two FIFOs has dual write enables and dual read enables. WENA2/LDA
and WENB2/LDB are wired in parallel to start and stop the Dual FIFO write
sequence. A flip-flop divides the system write clock frequency by a factor of
two, creating two180° out-of-phase enable signals which synchronize the
interleaving of data writes. One of these lines drives WENA1 , the other
drives WENB1.
RENA2 and RENB2 are wired in parallel to startand stop the Dual
FIFO read sequence. A flip-flop divides the system read clock frequency by
a factor of two, creating two 180° out-of-phase enable signals which
synchronize the interleaving of data reads. One of these lines drives
RENA1 and is also gated with the system read clock to produce an output
enable pulse which drives the OEB line. The other drives RENB1 and is
also gated with the system read clock to produce an output enable pulse
which drives the OEA line. Using an OR gate to shape the output enable
pulses eliminates contention on the outputs.
EFA and EFB are OR -gated together to form a composite empty flag
which will go LOW only when both FIFOA andFIFO B are empty. FFA and
FFB are OR-gated together to form a composite full flag which will go LOW
9
RSA DB 0 - DB 8
D AT A IN 18 9 DA 0 - DA 8
FIFO
A RCL KA
W RITE CL OCK W CLKA
RENA1
256 X 9
W RITE ENABLE WENA 1 512 X 9
1024 X 9
2048 X 9 OEA
W RIT E ENABLE/LO A D W ENA2/ LDA 4096 X 9
W ENB2/ LDB
FFA
FULL FLA G
FFB
RENA 2
Figure 4: IDT728x1 18-bit Width Expansion
63
IDT APPLICATION NOTE AN-134
only when both FIFO A and FIFO B are full.
If an application demands a data path width of 18-bits and a word depth
in excess of 1,024 then the two FIFOs contained in a 72825 can be
configured as a depth expansion with an overall organization of 2,048 x 18.
Figure 7 demonstrates this application.
The 728x5 devices are capable of daisy chain depth expansion. For this
purpose, they are equipped with write expansion input and outputs ( WXIA
, WXIB and WXOA , WXOB , respectively) and read Expansion input
and outputs ( RXIA , RXIB and RXOA , RXOB , respectively). The
daisy chain approach employs less external logic than the ping-pong
approach. To implement the chain, the Write Expansion Out line of each
FIFO is connected to the Write Expansion In line of the next FIFO in
sequence; the Read Expanion Out line of each FIFO is connected to the
Read Expansion In line of the next FIFO.Thedatainputs (Dn)areconnectedin
parallel,as are the data outputs (Qn). The system write clock drives both
WCLKA and WCLKB . The system read clock drives both RCLKA and
RCLKB.
EFA and EFB are OR-gated together to form a composite empty flag
which will go LOW only when both FIFO A and FIFO B are empty. FFA and
FFB are OR-gated together to form a composite full flag which will go LOW
only when both FIFO A and FIFO B are full.
BIDIRECTIONAL CONFIGURATION
For applications that require two-way communication, say from a
processor to a peripheral and from the peripheral back, Dual FIFOs
conveniently permit bidirectional data flow all within a single package: one
of the FIFOs is used to transmit information in one direction, the other FIFO
is used to transmit in the reverse direction.
Figure 8 uses a member of the 728x1 family to transfer 9-bit-wide data
in two directions. The data bus on the processor side is connected to the
data inputs (DAn) of FIFO A and the data outputs (QBn) of FIFO B. The data
bus on the peripheral side is connected to the data inputs (DBn) of FIFO
B and the data outputs (QAn) of FIFO A. The processor’s address and
R ESET
RSB
EFA
EMP TY FLAG
EFB
FIFO
B RCLKB READ CLO CK
W CLKB
RENB1 READ ENAB LE
256 X 9
WENB 1 512 X 9
1024 X 9
2048 X 9 OEB OUTPUT ENABLE
4096 X 9
QB 0 - Q B 8 9 18 DATA OUT
RENB2
QA 0 - Q A 8
9 3164 d rw 04
 IDT APPLICATION NOTE AN-134
control lines are decoded to enable writes to FIFO A, as well as, enable
reads and activate data outputs on FIFO B. The peripheral’s address and
control lines are decoded to enable writes to FIFO B, as well as, enable
reads and activate data outputs on FIFO A. For each FIFO, only one of the
redundant write enables ( WENA1 and WENB1 ) are required. WENA2/
LDA and WENB2/LDB should be configured as secondary write enables
and tied to Vcc. Likewise, only one of theredundant read enables ( RENA1
and RENB1 ) are required. The unused read enables are grounded.
The processor monitors FFA of FIFO A and EFB of FIFO B. The
peripheral monitors FFB of FIFO B and EFA of FIFO A.
Figure 9 uses a member of the 728x5 family to transfer 18-bits of data
in two directions.
BUS-MATCHING
These days, microprocessor-based systems employ a wide variety of
bus widths: 9-bit, 16-bit, 32-bit, and even 64-bit. Communicating between
buses of different width is known as bus-matching. The Dual FIFO is an ideal
device for implementing the bus-matching function, since two FIFOs can be
configured to match various bus widths.
Figure 10 shows how a 728x1 device can be used to perform 18-to-9 bit
bus-matching. The data inputs (Dn) of both FIFOs are used side-by-side for
a full 18-bit-wide input data path. Data is written to both FIFOs simulta-
neously and in parallel.
Though the 728x1 comes with redundant write enables, only one write
enable is required from each FIFO. This example only requires the use of
WENA1 and WENB1. WENA2/LDA and WENB2/LDB should be configured
as secondary write enables and tied HIGH. The corresponding data outputs
(QAn, QBn) of both FIFOs are tied together to produce a 9-bit-wide output
data path. RENA2 and RENB2 are wired in parallel to start and stop the Dual
FIFO read sequence. A flip-flop divides the system read clock frequency by
a factor of two, creating two 180° out-of-phase enable signals which
18
RSA DB 0 - DB 8
DATA IN 36 18 DA0 - D A17
FIFO
A RCLKA
W RITE CLOCK W CLKA
RENA
W RITE ENA BLE WENA
25 6 X18
OEA
51 2 X18
1024 X18
FFA
FULL FLA G
FFB
NOTE:
1. Tie FLA , FLB , WXIA , WXIB , RXIA , and RXIB to ground.
Figure 5: IDT728x5 36-bit Width Expansion
synchronize the interleaving of data reads onto the 9-bit bus. One of these
lines drives RENA1 of FIFO A and OEB of FIFO B, the other drives RENB1
of FIFO B and OEA of FIFO A. Therefore, the same time data is being
accessed from FIFO A , FIFO B’s outputs are enabled with valid data–ready
to be captured. In the next cycle, FIFO A’s outputs are enabled with valid
data, and FIFO B's outputs are disabled in preparation for another data
access. Note that a brief period of contention between FIFO A’s and FIFO
B’s outputs will occur at the moment outputs are enabled on one FIFO and
disabled on the other. Such short contention is considered acceptable, and
will in no way compromise the reliable performance of the Dual FIFO.
As an optional measure, two OR gates can be added to completely
eliminate the output contention. An example of this practise is shown in the
ping-pong application, described in the section entitled “Depth Expansion”.
EFA and EFB are OR gated together to form a composite empty flag
which will go LOW only when both FIFO A and FIFO B are empty.
Whether or not the tskew specification is met could conceivably cause
one of the full flags to deassert a cycle ahead of the other. This is normal.
To prevent the FIFOs from getting out-of-step, FFA and FFB should be
AND-gated together to form a composite full flag. Then, only when both
FIFOs have space available for writing (i.e. both FFA and FFB are HIGH)
will the composite full flag go HIGH. See the “Width Expansion” section for
a more detailed description of how the tskew parameter effects flag
performance.
Figure 11 shows how a 728x5 device can be used to perform a 36-to-
18 bit bus-matching function. In this case, the data inputs (DAn, DBn) of
both FIFOs are used side-by-side for a full 36-bit-wide input data path. Data
is written to both FIFOs simultaneously and in parallel. The data outputs
(QAn, QBn) of both FIFOs are tied in parallel to produce an 18-bit-wide
output data path. Data is read, alternating between FIFOs.
The 728x5 comes with neither redundant write enables nor redundant
read enables. Only WENA and WENB are available to implement parallel
RESET
RSB
EFA
EM P TY FLAG
EFB
FIFO
B
RCLKB REA D CLOC K
W CLKB
RENB REA D ENAB LE
WENB
OEB OUTPUT ENABLE
256 X 18
512 X 18
1024 X18 QB 0 - QB 17 18 36 DATA O UT
QA 0 - QA 17
18 3164 d rw 05
64
 IDT APPLICATION NOTE AN-134

D AT A IN 9

9 9
W R IT E EN ABLE /LO A D

WRITE REF

TF F Q
T
. DA0 - DA8 D B 0 - D B8 728x1
. 2
Q

EM PT Y
W EN A 2 / LDA EFA
W EN B 2 / LDB EFB FL AG

WENA1 WEN B
W R IT E FIFO
C LO C K W C LKA A W C LKB
FIFO
RSA RSB
R ESE T B
R EAD
R CL KA R CL KB
C LO C K 4096 x 9 4096 x 9
RENB1
RENA1
TF F Q
T . RENB2
. 2 RENA2 FU L L
Q OEB FFB
OEA FFA F LA G
R EAD
EN ABLE READ R EF

QA 0 - QA8 QB 0 - QB8

9 9
D AT A OUT
9

3164 d rw 0 6

Figure 6: IDT728x1 8K x 9 Depth Expansion Using the Ping-Pong Approach

writes to FIFO A and FIFO B. However, accessing data for a 36-to-18 bit bus
matching application requires control of the reading process on two different
levels: alternating reads between FIFO A and FIFO B, and the ability to start
and stop the Dual FIFO read sequence. Interleaved reads are accom-
plished by creating two 180° out-of-phase “internal” read enable signals to
drive RENA and RENB , just as was done in the preceding 728x1 bus-
matching application. Initiating and terminating the read process is handled
by OR-gating each of the internal enables independently to the externally
driven read enable.
As in the 728x1 design, EFA and EFB are OR-gated together to form
a composite empty flag, FFA and FFB are AND-gated together to form a
composite full flag.
For matching larger bus widths, more than one Dual FIFO can be used
together. Figure 12 shows how two 728x1 devices can be used to
perform 36-to-9 bit bus-matching. The data inputs (DAn,DBn) of all four
FIFOs are used side-by-side for a full 36-bit-wide input data path. Data is
written to all four FIFOs simultaneously and in parallel.
In this example, two pairs of WENA1 and WENB1 are used to enable
writes to the four FIFOs. WENA2/LDA and WENB2/LDB , are not needed.
Unless the partial flags need program-ming, these lines should be config-
ured as redundant write enables and tied to VCC. The data outputs (QAn,
QBn) of all four FIFOs are tied in parallel to produce a 9-bit-wide output data
path. A PAL uses the system read clock signal to create four read enable
signals, each running at a quarter of the original frequency, each separated
from its neighbors by a 90° phase difference. These signals are used to
cycle through the four FIFOs, executing reads in sequence. Following a
data access from the last FIFO in line, reading continues with the first FIFO.
Each signal is connected to the output enable line ( OEA or OEB ) of one
FIFO and also to a read enable line ( RENA1 or RENB1 ) on the next
FIFO in the read sequence. In this way, each signal enables the outputs of
65
the first FIFO for data capture at the same time it enables a new data access
on the next FIFO in line. One PAL input serves as a system-level read
enable which initiates and terminates the read process. Internal to the PAL,
this signal exercises control over all four of the 90° out-of-phase PAL
outputs. The redundant read enable pins RENA2 and RENB2 are
unecessary and should be grounded.
EFA and EFB of both Dual FIFOs are all OR-gated together to form
a composite empty flag which will go LOW only when both FIFO A and FIFO
B are empty.
FFA and FFB of both DualFIFOs should be AND-gated together to
form a composite full flag. Then, only when all four FIFOs have space
available for writing (i.e. both pairs of FFA and FFB are HIGH) will the
composite empty flag go HIGH.
Figure 13 shows how two 728x5 devices can be used to perform 72-to-
18 bit bus-matching. The data inputs (DAn, DAn) of all four FIFOs are used
side-by-side for a full 72-bit-wide input data path. Data is written to all four
FIFOs simultaneously and in parallel. In this example, two pairs of WENA
and WENB are used to enable writes to the four FIFOs.
The data outputs (QAn, QBn) of all four FIFOs are tied in parallel to
produce an 18-bit-wide output data path. As in the preceding example, a
PAL uses the system read clock signal to create four read enable signals,
each running at a quarter of the original frequency, each separated from its
neighbors by 90° phase difference. These signals are used to cycle
through the four FIFOs, executing reads in sequence. Each signal is
connected to the output enable line ( OEA or OEB ) of one FIFO and also
to the read enable line ( RENA or RENB ) on the next FIFO in the read
sequence. In this way, one signal enables the outputs of the first FIFO for
data capture at the same time it enables a new data access on the next
FIFO in line. One PAL input serves as a system-level read enable which
initiates and terminates the read process.
IDT APPLICATION NOTE AN-134

WXOA RXOA

FIFO A

V CC 1024 x 18

FFB
FLB EFA

DATA IN (D)
WXIA RXIA DATA OU T (Q)

72825
WRITE CLOCK READ CLOCK
(WCLK) WXOB RXOB (RCLK)

WRITE ENABLE READ ENABLE

(WEN ) FIFO B (REN )

RESET (RS ) OUTPUT

ENABLE (OE)
LOAD (LD)
1024 x 18

FF EF
FLB EFB
FFB

WXIB RXIB

3 16 4 drw 07

Figure 7: IDT728x5 2K x 18 Depth Expansion Using the Daisy Chain Approach

FIFO A
V CC WENA2 RENA2

W CLKA RC LK A
OEA
WENA1
RENA1
Peripheral
DA 0 : QA 0: C ontroller
Processor 9 DA 8 QA 8 9
Clock D MAC lock
Control
Logic
Control
Logic

Address 728x1 Address

Control Control
9-bit bus

9-bit bus

I/O Data
Data FIFO B Data
9 9

RC LKB WENB1
RENB1
RA M W CLKB
9 OEB

QB 0: DB 0 :
9 QB 8 DB 8 9

RENB2 WENB2

316 4 drw 08

V CC

Figure 8: IDT728x1 Bidirectional Configuration

66
 IDT APPLICATION NOTE AN-134

FIFO A

RCLKA
WCLKA
OEA
WENA
RENA
Peripheral
DA 0 : QA 0: Controller
Processor 18 DA 17 QA 17 18
Clock DMAClock

Control
Logic
Control
Logic

Address IDT Address

728x5
Control Control
18-bit bus

18-bit bus
I/O Data
Data FIFO B Data
18 18
RCLKB WENB
RENB
RAM WCLKB
18 OEB
QB 0: DB 0 :
18 QB 17 DB 17 18

3164 drw 09

NOTE:
1. Tie FLA , FLB , WXIA , WXIB , and RXIA , RXIB to ground.
Figure 9: IDT728x5 Bidirectional Configuration

EFA and EFB of both Dual FIFOs are all OR-gated together to form
a composite empty flag which will go LOW only when both FIFO A and FIFO
B are empty.
FFA and FFB of both Dual FIFOs are all AND-gated together to form
a composite full flag, which will go HIGH only when all four FIFOs have
space available for writing.

CONCLUSION
The IDT728x1 family of nine-bit-wide Dual FIFOs offer two, indepen-
dent synchronous FIFOs in a 64-pin Thin Quad Flat Pack (TQFP) package.
Each FIFO is functionally equivalent to the 722x1 FIFO family.
The IDT728x5 family of 18-bit-wide Dual FIFOs offer two, independent
synchronous FIFOs in a 121-pin Ball Grid Array (BGA) package. Each FIFO
is functionally equivalent to the 722x5LB FIFO family.
The primary benefit of these new Dual FIFO families is to cut board area
occupied by FIFOs in half. Therefore, the new families lend themselves
particularly well to designs that require numerous FIFOs. Intensive data-
buffering applications such as data sorting and network switching gain the
most from using dual devices. However, other common ways of connecting
more than one FIFO, such as width expansion, depth expansion, bidirec-
tional data flow, and bus matching also benefit.

67
IDT APPLICATION NOTE AN-134
DATA IN 18

9 9
RESET

DA0 - DA8 DB 0 - DB 8

EFB
RSA EM PTY FLA G
RSB EFA
W RITE CLO CK W CLKA
W CLKB
W RITE ENA BLE WENA1 WENB1 FIFO
B REA D REF
W ENB2/ LD
W RIT E ENABLE/LOA D W ENA2/ LDA
OEA RENB1
Q _.
RENA1 OEB Q T
.2
FIFO
A
RCL KA
RCL KB REA D CLOCK
FFA RENA2
RENB2
FULL FLA G
FFB

728x1 QA0 - QA8 QB0 - QB8

9 9
9 DAT A OUT

READ ENABLE2

REA D ENABL E1

Figure 10: IDT728x1 18-to-9-Bit Bus-Matching 3164 drw 10

DAT A IN 36

18 18
RESET

DA0 - D A17 DB 0 - DB 17

EFA
RSA EM PTY FLAG
RSB FIFO EFB
W RITE CL OCK W CLKA B
W CLKB
W RITE ENABLE WENA WENB 256 X18 READ R EF
512 X18
1024 X18
FIFO OEA RENB Q
A +2
T
Q
256 X18 RENA OEB
512 X18 RE AD
1024 X18
RCLKA RCLKB CLO CK
FFA
FULL FLAG READ ENAB LE
FFB

QA 0 - Q A 17 QB 0 - Q B 17

18 18
NOTE: 18 DAT A O UT
1. Tie FLA , FLB , WXIA , WXIB , RXIA , and RXIB to GND.
3164 drw 11

Figure 11: IDT728x5 36-to-18 Bit Bus-Matching

68
 DATAIN 36
RESET 9 9 9 9

EMPTY
FLAG
DA0 - DA8 DB0 - DB8 728x1 DA0 - DA8 DB0 - DB8 728x1
RSA EFA RSB EFB RSA EFA RSB EFB
WRITE CLOCK WCLKA WCLKB WCLKA WCLKB
WRITE ENABLE WENA1 WENB1 WENA1 WENB1

WRITE ENABLE/LOAD WENA2/LDA WENB2/LDB WENA2/LDA WENB2/LDB

RCLKA RCLKB RCLKA RCLKB READ CLOCK
FIFO A FIFO B FIFO A FIFO B
256 X18 256 X18 256 X18 256 X18
RENA1 RENA2 RENA1 RENB2 RENB1
FFA 512 X18 RENB2 512 X18 512 X18 512 X18 READ
RENB1
1024 X18

69
RENA2 1024 X18 1024 FFA OEA FFB 1024 OEB ENABLE
OEA FFB X18 OEB X18

FULL
FLAG QA0-QA8 QB0-QB8 QA0-QA8 QB0-QB8
PAL
22V10

9 9 9 9
9 DATA OUT 3164 drw 12

Figure 12: IDT728x1 36-to-9-Bit Bus-Matching

IDT APPLICATION NOTE AN-134
IDT APPLICATION NOTE AN-134

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or (408) 727-6116 e-mail: fifohelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 330-1753
70
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
70
71
72
 THERMAL PERFORMANCE CALCULATIONS
FOR IDT'S PACKAGES

Since most of the electrical energy consumed by microelectronic θJA = [ TJ - TA ] / P

devices eventually appears as heat, poor thermal performance of the
device or lack of management of this thermal energy can cause a variety of TJ = TA + P[ θJA ] = TA + P[ θJC + θCA ]
deleterious effects. This device temperature increase can exhibit itself as
one of the key variables in establishing device performance and long term where
reliability; on the other hand, effective dissipation of internally generated
thermal energy can, if properly managed, reduce the deleterious effects and θJC = ( TJ - TC ) / P and θCA = ( TC - TA ) / P
improve component reliability.
A few key benefits of IDT's enhanced CMOS process are: low power θ = Thermal resistance
dissipation, high speed, increased levels of integration, wider operating J = Junction
temperature ranges and lower quiescent power dissipation. Because the P = Operational power of device (dissipated)
reliability of an integrated circuit is largely dependent on the maximum TA =Ambient temperature in degrees celsius
temperature the device attains during operation, and as the junction stability TJ =Temperature of the junction
declines with increases in junction temperature (TJ), it becomes increas- TC =Temperature of case/ package
ingly important to maintain a low (TJ). θCA = Case to Ambient, thermal resistance - usually a measure of
CMOS devices stabilize more quickly and at greatly lower temperature the heat dissipation due to natural or forced convection,
than bipolar devices under normal operation. The accelerated aging of an radiation and mounting techniques.
integrated circuit can be expressed as an exponential function of the θJC = Junction to Case, thermal resistance - usually measured
junction temperature as: with reference to the temperature at a specific point on the
package (case) surface. (Dependent on the package material
tA = tO exp [ Ea/ k ( 1/ TO - 1/ TJ ) ] properties and package geometry).
where θJA = Junction to Ambient, thermal resistance - usually measured
tA = lifetime at elevated junction (TJ) temperature. with respect to the temperature of a specified volume of still
tO = normal lifetime at normal junction (TO) temperature. air. (Dependent on θJC + θCA, which includes the influence
Ea = activation energy (eV) of areas and environmental condition).
k = Boltzmann's constant (8.617 x 10-5 ev/ k)
i.e. the lifetime of a device could be decreased by a factor of 2 for every
10°C. increase temperature.

To minimize the deleterious effects associated with this potential in-

crease, IDT has:
1. Optimized our proprietary low-power CMOS fabrication process to
ensure the active junction temperature rise is minimal.
2. Selected only packaging materials that optimize heat dissipation,
which encourages a cooler running device.
3. Physically designed all package components to enhance the
inherent material properties and to take full advantage of heat
transfer and radiation due to case geometries.
4. Tightly controlled the assembly procedures to meet or exceed the
stringent criteria of MIL-STD-883, to ensure maximum heat
transfer between die and packaging materials.

When calculating junction temperature (TJ), it is necessary to know the

thermal resistance of the package (θJA) as measured in "degrees celsius
per watt". With the accompanying data, the following equation can be used
to establish thermal performance, enhance device reliability and ultimately
provide you, the user, with a continuing series of high speed, low-power
CMOS solutions to your system design needs.

73
 1999 Integrated Device Technology, Inc.