Application Note

PowerPC® Embedded Controller JTAG Reset Requirements

Scope
Figure 1. Minimal TRST Wiring
The PowerPC 405 and 440 series of embedded
PowerPC
controllers feature an IEEE 1149.1 JTAG Test Embedded
Access Port (TAP) for both debug and board-level Controller
test use. For correct device operation, the JTAG JTAG-based TRST
TRST
TAP controller must be reset at system power-on. Debugger
This application note provides several options for 1k
resetting the TAP controller, while maintaining func-
tionality with JTAG-based debug tools such as the
IBM RISCWatch™ debugger. 3.3k

Power On POR
SysReset
Reset
JTAG TAP Reset Requirements
The IEEE Standard Test Access Port and
The circuit depicted in Figure 2 provides a solution
Boundary-Scan Architecture (IEEE® Std 1149.1-
that ensures the TAP controller resets in response
1990) specifies that the JTAG TAP controller must
to either a power-on reset or assertion of TRST from
be reset at power-up, either via a dedicated TRST
a JTAG-based debugger or a board-level boundary
input signal, or through circuitry built into the test
scan tool. Observe that SysReset, which may be
logic. It is further required that the TAP controller
actively driven by the PowerPC Embedded
must not be initialized by any other chip I/O, such as
Controller, does not affect the TRST input. This is
a system reset.
required as TRST must be not activated in response
Since IBM PowerPC embedded controllers do not to a system reset.
include internal circuitry to detect a power-up condi-
tion and reset the TAP controller, TRST must be Figure 2. Recommended TRST Wiring
asserted during power-on to reset the TAP
controller. Furthermore, TRST must not be directly
or logically connected to SysReset. Doing so PowerPC
10k Embedded
violates the requirement that the level on the Controller
SysReset input must not reset the JTAG TAP JTAG-based TRST
controller. Debugger TRST

Resetting the JTAG TAP Controller Power On POR

Reset
Designers can chose one of two methods to reset 3.3k
the JTAG controller. The simplest implementation,
shown in Figure 1, holds the TAP controller in reset SysReset

unless a JTAG-based debugger is connected. Since 1k

keeping the TAP controller in reset places all of the
chip I/Os in functional mode, this solution is the
simplest and easiest to implement. The only draw-
back is that if a JTAG-based debugger is attached
during a power-on sequence, the debugger may References
hold TRST high and prevent the TAP controller from 1. IEEE Standard Test Access Port and Boundary-
being reset. Scan Architecture. 1990. (IEEE Std 1149.1-
1990.)

JTAGReset.fm
May 2002 Page 1
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