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ADSP-218xN Series
PERFORMANCE FEATURES SYSTEM INTERFACE FEATURES
12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sus- Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation
tained performance All inputs tolerate up to 3.6 V regardless of mode
Single-cycle instruction execution 16-bit internal DMA port for high-speed access to on-chip
Single-cycle context switch memory (mode selectable)
3-bus architecture allows dual operand fetches in every 4M-byte memory interface for storage of data tables and pro-
instruction cycle gram overlays (mode selectable)
Multifunction instructions 8-bit DMA to byte memory for transparent program and data
Power-down mode featuring low CMOS standby power dissi- memory transfers (mode selectable)
pation with 200 CLKIN cycle recovery from power-down Programmable memory strobe and separate I/O memory
condition space permits “glueless” system design
Low power dissipation in idle mode Programmable wait state generation
Two double-buffered serial ports with companding hardware
INTEGRATION FEATURES
and automatic data buffering
ADSP-2100 family code compatible (easy to use algebraic Automatic booting of on-chip program memory from byte-
syntax), with instruction set extensions wide external memory, for example, EPROM, or through
Up to 256K byte of on-chip RAM, configured internal DMA Port
Up to 48K words program memory RAM Six external interrupts
Up to 56K words data memory RAM 13 programmable flag pins provide flexible system signaling
Dual-purpose program memory for both instruction and UART emulation through software SPORT reconfiguration
data storage ICE-Port™ emulator interface supports debugging in final
Independent ALU, multiplier/accumulator, and barrel shifter systems
computational units
Two independent data address generators
Powerful program sequencer provides zero overhead loop-
ing conditional instruction execution
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA
PO W E R-DO WN
C ONTR O L
FU L L M EM O R Y M O D E
M EM OR Y
PRO GRA M D A TA PROG RA MM ABL E EX TE RNAL
D A T A A D D RES S I/O
G ENERAT OR S ME M ORY ME M ORY AD D R ES S
PROG RAM UP TO UP TO AND BUS
D A G1 D AG2 SEQ U ENCER 48K ⴛ 24-B IT 56K ⴛ 16-B IT F LA GS
EX TE RNAL
D A TA
P R O GR A M M EM O R Y AD D R ES S BUS
BY TE DM A
D ATA M EM O RY A D D R ES S C ON T R OLL ER
ADSP-218xN series members integrate up to 256K bytes of on- The internal result (R) bus connects the computational units so
chip memory configured as up to 48K words (24-bit) of pro- that the output of any unit may be the input of any unit on the
gram RAM, and up to 56K words (16-bit) of data RAM. Power- next cycle.
down circuitry is also provided to meet the low power needs of A powerful program sequencer and two dedicated data address
battery-operated portable equipment. The ADSP-218xN is generators ensure efficient delivery of operands to these compu-
available in a 100-lead LQFP package and 144-ball BGA. tational units. The sequencer supports conditional jumps,
Fabricated in a high-speed, low-power, 0.18 μm CMOS process, subroutine calls, and returns in a single cycle. With internal
ADSP-218xN series members operate with a 12.5 ns instruction loop counters and loop stacks, ADSP-218xN series members
cycle time. Every instruction can execute in a single pro- execute looped code with zero overhead; no explicit jump
cessor cycle. instructions are required to maintain loops.
The ADSP-218xN’s flexible architecture and comprehensive Two data address generators (DAGs) provide addresses for
instruction set allow the processor to perform multiple opera- simultaneous dual operand fetches (from data memory and pro-
tions in parallel. In one processor cycle, ADSP-218xN series gram memory). Each DAG maintains and updates four address
members can: pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possi-
• Generate the next program address ble modify registers. A length value may be associated with each
• Fetch the next instruction pointer to implement automatic modulo addressing for
circular buffers.
• Perform one or two data moves
Five internal buses provide efficient data transfer:
• Update one or two data address pointers
• Program Memory Address (PMA) Bus
• Perform a computational operation
• Program Memory Data (PMD) Bus
This takes place while the processor continues to:
• Data Memory Address (DMA) Bus
• Receive and transmit data through the two serial ports
• Data Memory Data (DMD) Bus
• Receive and/or transmit data through the internal
DMA port • Result (R) Bus
Setting Memory Mode the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
Memory Mode selection for the ADSP-218xN series is made
level, and will not oscillate should the three-state driver’s level
during chip reset through the use of the Mode C pin. This pin is
hover around the logic switching point.
multiplexed with the DSP’s PF2 pin, so care must be taken in
how the mode selection is made. The two methods for selecting IDMA ACK Configuration
the value of Mode C are active and passive.
Mode D = 0 and in host mode: IACK is an active, driven signal
Passive Configuration and cannot be “wire-OR’ed.” Mode D = 1 and in host mode:
IACK is an open drain and requires an external pull-down, but
Passive Configuration involves the use of a pull-up or pull-
multiple IACK pins can be “wire-OR’ed” together.
down resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the INTERRUPTS
DSP application, a weak pull-up or pull-down resistance, on the
order of 10 kΩ, can be used. This value should be sufficient to The interrupt controller allows the processor to respond to the
pull the pin to the desired level and still allow the pin to operate eleven possible interrupts and reset with minimum overhead.
as a programmable flag output without undue strain on the pro- ADSP-218xN series members provide four dedicated external
cessor’s output driver. For minimum power consumption interrupt input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared
during power-down, reconfigure PF2 to be an input, as the pull- with the PF7–4 pins). In addition, SPORT1 may be reconfig-
up or pull-down resistance will hold the pin in a known state, ured for IRQ0, IRQ1, FI, and FO, for a total of six external
and will not switch. interrupts. The ADSP-218xN also supports internal interrupts
from the timer, the byte DMA port, the two serial ports, soft-
Active Configuration ware, and the power-down control circuit. The interrupt levels
are internally prioritized and individually maskable (except
Active Configuration involves the use of a three-statable exter-
power-down and reset). The IRQ2, IRQ0, and IRQ1 input pins
nal driver connected to the Mode C pin. A driver’s output
can be programmed to be either level- or edge-sensitive. IRQL0
enable should be connected to the DSP’s RESET signal such that
and IRQL1 are level-sensitive and IRQE is edge-sensitive. The
it only drives the PF2 pin when RESET is active (low). When
priorities and vector addresses of all interrupts are shown in
RESET is deasserted, the driver should be three-state, thus
Table 3.
allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
Disabling the interrupts does not affect serial port autobuffering Slow Idle
or DMA. When the processor is reset, interrupt servicing The IDLE instruction is enhanced on ADSP-218xN series mem-
is enabled. bers to let the processor’s internal clock signal be slowed, further
LOW-POWER OPERATION reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by a
ADSP-218xN series members have three low-power modes that selectable divisor given in the IDLE instruction.
significantly reduce the power dissipation when the device oper-
The format of the instruction is:
ates under standby conditions. These modes are:
IDLE (n);
• Power-Down
where n = 16, 32, 64, or 128. This instruction keeps the proces-
• Idle
sor fully functional, but operating at the slower clock rate. While
• Slow Idle it is in this state, the processor’s other internal clock signals,
1M ⍀
C L K IN X TAL CLKO UT
DSP
RESET
The RESET signal initiates a master reset of the ADSP-218xN.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
0x2000 0x2000
0x1FFF 0x1FFF 0x2000
0x1FFF
DM OVERLAY 1,2
EXTERNAL PM INTERNAL PM (EXTERNAL DM)
DM OVERLAY 0
(RESERVED)
0x0000 0x0000 0x0000
0x2000 0x2000
0x1FFF 0x1FFF 0x2000
0x1FFF
DM OVERLAY 1,2
EXTERNAL PM INTERNAL PM (EXTERNAL DM)
DM OVERLAY 0,4,5
(INTERNAL DM)
0x0000 0x0000 0x0000
0x2000 0x2000
0x1FFF 0x1FFF 0x2000
0x1FFF DM OVERLAY 1,2
(EXTERNAL DM)
EXTERNAL PM INTERNAL PM
DM OVERLAY
0,4,5,6,7
(INTERNAL DM)
0x0000 0x0000 0x0000
Program Memory DSPs of this series have up to 48K words of Program Memory
RAM on chip, and the capability of accessing up to two 8K
Program Memory (Full Memory Mode) is a 24-bit-wide space
external memory overlay spaces, using the external data bus.
for storing both instruction opcodes and data. The member
Data Memory All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
Data Memory (Full Memory Mode) is a 16-bit-wide space used
register and the wait state mode bit.
for the storage of data variables and for memory-mapped con-
trol registers. The ADSP-218xN series has up to 56K words of Data Memory (Host Mode) allows access to all internal mem-
Data Memory RAM on-chip. Part of this space is used by 32 ory. External overlay access is limited by a single external
memory-mapped registers. Support also exists for up to two 8K address line (A0).
external memory overlay spaces through the external data bus.
Memory-Mapped Registers (New to the ADSP-218xM and I/O Space (Full Memory Mode)
N series) ADSP-218xN series members support an additional external
ADSP-218xN series members have three memory-mapped reg- memory space called I/O space. This space is designed to sup-
isters that differ from other ADSP-21xx Family DSPs. The slight port simple connections to peripherals (such as data converters
modifications to these registers (Wait State Control, Program- and external registers) or to bus interface ASIC data registers.
mable Flag and Composite Select Control, and System Control) I/O space supports 2048 locations of 16-bit wide data. The lower
provide the ADSP-218xN’s wait state and BMS control features. eleven bits of the external address bus are used; the upper three
Default bit values at reset are shown; if no value is shown, the bit bits are undefined.
is undefined at reset. Reserved bits are shown on a grey field. Two instructions were added to the core ADSP-2100 Family
These bits should always be written with zeros. instruction set to read from and write to I/O memory space. The
I/O space also has four dedicated three-bit wait state registers,
Note: In Full Memory Mode, all 2048 locations of I/O space are B MW AIT CM S SEL PF TY P E
directly addressable. In Host Memory Mode, only address pin 0 = DIS ABLE CMS 0 = IN PUT
1 = E NABLE CMS 1 = O UTP UT
A0 is available; therefore, additional logic is required externally ( WH ERE BIT : 11- IOM , 10-B M, 9-DM , 8-PM )
to achieve complete addressability of the 2048 I/O
space locations. Figure 11. Programmable Flag and Composite Control Register
ateC N OTE: RESERVED BITS ARE SHO WN O N A G RAY FIELD . THESE B ITS
St
ait IOWAIT0–3 = N WAIT STATES,
WAIT STATE MODE SELECT SHOUL D ALW AYS BE WR ITTEN W ITH Z EROS.
rt W
0 = NORMAL MODE (PWAIT, DWAIT,
RANGING FROM 0 TOse7)
In DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES,
1 = 2N + 1 MODE (PWAIT,
Figure 12. System Control Register
RANGING FROM 0 TO 15)
select, and a flash memory could be connected to CMS. Because
Figure 10. Wait State Control Register at reset BMS is enabled, the EPROM would be used for booting.
After booting, software could disable BMS and set the CMS sig-
Composite Memory Select nal to respond to BMS, enabling the flash memory.
ADSP-218xN series members have a programmable memory
Byte Memory
select signal that is useful for generating memory select signals
for memories mapped to more than one space. The CMS signal The byte memory space is a bidirectional, 8-bit-wide,
is generated to have the same timing as each of the individual external memory space used to store programs and data. Byte
memory select signals (PMS, DMS, BMS, IOMS) but can com- memory is accessed using the BDMA feature. The byte memory
bine their functionality. Each bit in the CMSSEL register, when space consists of 256 pages, each of which is 16K ⴛ 8 bits.
set, causes the CMS signal to be asserted when the selected
The byte memory space on the ADSP-218xN series supports
memory select is asserted. For example, to use a 32K word
read and write operations as well as four different data formats.
memory to act as both program and data memory, set the PMS
The byte memory uses data bits 15–8 for data. The byte mem-
and DMS bits in the CMSSEL register and use the CMS pin to
ory uses data bits 23–16 and address bits 13–0 to create a 22-bit
drive the chip select of the memory, and use either DMS or PMS
address. This allows up to a 4 megabit ⴛ 8 (32 megabit) ROM
as the additional address bit.
or RAM to be used without glue logic. All byte memory accesses
The CMS pin functions like the other memory select signals are timed by the BMWAIT register and the wait state mode bit.
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the Byte Memory DMA (BDMA, Full Memory Mode)
selected memory select signal. All enable bits default to 1 at The byte memory DMA controller (Figure 13) allows loading
reset, except the BMS bit. and storing of program instructions and data using the byte
See Figure 11 and Figure 12 for illustration of the programma- memory space. The BDMA circuit is able to access the byte
ble flag and composite control register and the system memory space while the processor is operating normally and
control register. steals only one DSP cycle per 8-, 16-, or 24-bit word transferred.
Table 7. Data Formats Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
Internal Memory
The IDMA Port provides an efficient means of communication
BTYPE Space Word Size Alignment
between a host system and ADSP-218xN series members. The
00 Program Memory 24 Full Word port is used to access the on-chip program memory and data
01 Data Memory 16 Full Word memory of the DSP with only one DSP cycle per word over-
10 Data Memory 8 MSBs head. The IDMA port cannot, however, be used to write to the
11 Data Memory 8 LSBs DSP’s memory-mapped control registers. A typical IDMA
transfer process is shown as follows:
Unused bits in the 8-bit data memory formats are filled with 0s. 1. Host starts IDMA transfer.
The BIAD register field is used to specify the starting address for 2. Host checks IACK control line to see if the DSP is busy.
the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte 3. Host uses IS and IAL control lines to latch either the DMA
memory space. The 8-bit BMPAGE register specifies the start- starting address (IDMAA) or the PM/DM OVLAY selec-
ing page for the external byte memory space. The BDIR register tion into the DSP’s IDMA control registers. If Bit 15 = 1,
field selects the direction of the transfer. Finally, the 14-bit the values of Bits 7–0 represent the IDMA overlay; Bits
BWCOUNT register specifies the number of DSP words to 14–8 must be set to 0. If Bit 15 = 0, the value of Bits 13–0
transfer and initiates the BDMA circuit transfers. represent the starting address of internal memory to be
accessed and Bit 14 reflects PM or DM for access. Set
BDMA accesses can cross page boundaries during sequential IDDMOVLAY and IDPMOVLAY bits in the IDMA over-
addressing. A BDMA interrupt is generated on the completion lay register as indicted in Table 8.
of the number of transfers specified by the BWCOUNT register.
4. Host uses IS and IRD (or IWR) to read (or write) DSP
The BWCOUNT register is updated after each transfer so it can internal memory (PM or DM).
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener- 5. Host checks IACK line to see if the DSP has completed the
ated. The BMPAGE and BEAD registers must not be accessed previous IDMA operation.
by the DSP during BDMA operations. 6. Host ends IDMA transfer.
The source or destination of a BDMA transfer will always be on-
chip program or data memory. Table 8. IDMA/BDMA Overlay Bits
When the BWCOUNT register is written with a nonzero value IDMA/BDMA IDMA/BDMA
the BDMA circuit starts executing byte memory accesses with Processor PMOVLAY DMOVLAY
wait states set by BMWAIT. These accesses continue until the ADSP-2184N 0 0
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip ADSP-2185N 0 0
memory. The transfer takes one DSP cycle. DSP accesses to ADSP-2186N 0 0
external memory have priority over BDMA byte mem- ADSP-2187N 0, 4, 5 0, 4, 5
ory accesses. ADSP-2188N 0, 4, 5, 6, 7 0, 4, 5, 6, 7, 8
ADSP-2189N 0, 4, 5 0, 4, 5, 6, 7
IDMA port access occurs in two phases. The first is the IDMA IDMAA ADDRESS
Address Latch cycle. When the acknowledge is asserted, a 14-bit IDMAD DESTINATION MEMORY
TYPE
address and 1-bit destination type can be driven onto the bus by RESERVED SET TO 0 0 = PM
an external device. The address specifies an on-chip memory 1 = DM
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE
location, the destination type specifies whether it is a DM or PM BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS.
access. The falling edge of the IDMA address latch signal (IAL)
or the missing edge of the IDMA select signal (IS) latches this Figure 14. IDMA OVLAY/Control Registers
value into the IDMAA register.
The BDMA interface is set up during reset to the following
Once the address is stored, data can be read from, or written to,
defaults when BDMA booting is specified: the BDIR, BMPAGE,
the ADSP-218xN’s on-chip memory. Asserting the select line
BIAD, and BEAD registers are set to 0, the BTYPE register is set
(IS) and the appropriate read or write line (IRD and IWR
to 0 to specify program memory 24-bit words, and the
respectively) signals the ADSP-218xN that a particular transac-
BWCOUNT register is set to 32. This causes 32 words of on-
tion is required. In either case, there is a one-processor-cycle
chip program memory to be loaded from byte memory. These
delay for synchronization. The memory access consumes one
32 words are used to set up the BDMA to load in the remaining
additional processor cycle.
program code. The BCR bit is also set to 1, which causes pro-
Once an access has occurred, the latched address is automati- gram execution to be held off until all 32 words are loaded into
cally incremented, and another access can occur. on-chip program memory. Execution then begins at address 0.
Through the IDMAA register, the DSP can also specify the The ADSP-2100 Family development software (Revision 5.02
starting address and data format for DMA operation. and later) fully supports the BDMA booting feature and can
Asserting the IDMA port select (IS) and address latch enable generate byte memory space-compatible boot code.
(IAL) directs the ADSP-218xN to write the address onto the
The IDLE instruction can also be used to allow the processor to
IAD14–0 bus into the IDMA Control Register (Figure 14). If Bit
hold off execution while booting continues through the BDMA
15 is set to 0, IDMA latches the address. If Bit 15 is set to 1,
interface. For BDMA accesses while in Host Mode, the addres-
IDMA latches into the OVLAY register. This register, also
ses to boot memory must be constructed externally to the
shown in Figure 14, is memory-mapped at address DM
ADSP-218xN. The only memory address bit provided by the
(0x3FE0). Note that the latched address (IDMAA) cannot be
processor is A0.
read back by the host.
When Bit 14 in 0x3FE7 is set to zero, short reads use the timing IDMA Port Booting
shown in Figure 36 on Page 38. When Bit 14 in 0x3FE7 is set to ADSP-218xN series members can also boot programs through
1, timing in Figure 37 on Page 39 applies for short reads in short its internal DMA port. If Mode C = 1, Mode B = 0, and Mode A
read only mode. Set IDDMOVLAY and IDPMOVLAY bits in = 1, the ADSP-218xN boots from the IDMA port. IDMA feature
the IDMA overlay register as indicated in Table 8. Refer to the can load as much on-chip memory as desired. Program execu-
ADSP-218x DSP Hardware Reference for additional details. tion is held off until the host writes to on-chip program memory
Note: In full memory mode all locations of 4M-byte memory location 0.
space are directly addressable. In host memory mode, only
address pin A0 is available, requiring additional external logic to BUS REQUEST AND BUS GRANT
provide address information for the byte. ADSP-218xN series members can relinquish control of the data
and address buses to an external device. When the external
Bootstrap Loading (Booting) device requires access to memory, it asserts the Bus Request
ADSP-218xN series members have two mechanisms to allow
automatic loading of the internal program memory after reset.
The method for booting is controlled by the Mode A, B, and C
configuration bits.
When the mode pins specify BDMA booting, the ADSP-218xN
initiates a BDMA boot sequence when reset is released.
†
VisualDSP++ is a registered trademark of Analog Devices, Inc.
including:
Figure 15. Mode A Pin/EZ-ICE Circuit
• In-target operation
• Up to 20 breakpoints The ICE-Port interface consists of the following ADSP-218xN
pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and
• Single-step or full-speed operation ELOUT.
• Registers and memory values can be examined and altered These ADSP-218xN pins must be connected only to the EZ-ICE
• PC upload and download functions connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
• Instruction-level emulation of program booting down resistors. The traces for these signals between the
and execution ADSP-218xN and the connector must be kept as short as possi-
ble, no longer than 3 inches.
The following pins are also used by the EZ-ICE: BR, BG, RESET,
†
EZ-KIT Lite is a registered trademark of Analog Devices, Inc. and GND.
‡
EZ-ICE is a registered trademark of Analog Devices, Inc.
MEMORY INTERFACE PINS The operating mode is determined by the state of the Mode C
pin during RESET and cannot be changed while the processor is
ADSP-218xN series members can be used in one of two modes: running. Table 10 and Table 11 list the active signals at specific
Full Memory Mode, which allows BDMA operation with full pins of the DSP during either of the two operating modes (Full
external overlay memory and I/O capability, or Host Mode, Memory or Host). A signal in one table shares a pin with a sig-
which allows IDMA operation with limited external addressing nal from the other table, with the active signal determined by
capabilities. the mode that is set. For the shared pins and their alternate sig-
nals (e.g., A4/IAD3), refer to the package pinouts in Table 27 on
Page 41 and Table 28 on Page 43.
I/O
3-State Reset
Pin Name1 (Z)2 State Hi-Z3 Caused By Unused Configuration
XTAL O O Float
CLKOUT O O Float4
A13–1 or O (Z) Hi-Z BR, EBR Float
IAD12–0 I/O (Z) Hi-Z IS Float
A0 O (Z) Hi-Z BR, EBR Float
I/O
3-State Reset
Pin Name1 (Z)2 State Hi-Z3 Caused By Unused Configuration
D23–8 I/O (Z) Hi-Z BR, EBR Float
D7 or I/O (Z) Hi-Z BR, EBR Float
IWR I I High (Inactive)
D6 or I/O (Z) Hi-Z BR, EBR Float
IRD I I BR, EBR High (Inactive)
D5 or I/O (Z) Hi-Z Float
IAL I I Low (Inactive)
D4 or I/O (Z) Hi-Z BR, EBR Float
IS I I High (Inactive)
D3 or I/O (Z) Hi-Z BR, EBR Float
IACK Float
D2–0 or I/O (Z) Hi-Z BR, EBR Float
IAD15–13 I/O (Z) Hi-Z IS Float
PMS O (Z) O BR, EBR Float
DMS O (Z) O BR, EBR Float
BMS O (Z) O BR, EBR Float
IOMS O (Z) O BR, EBR Float
CMS O (Z) O BR, EBR Float
RD O (Z) O BR, EBR Float
WR O (Z) O BR, EBR Float
BR I I High (Inactive)
BG O (Z) O EE Float
BGH O O Float
IRQ2/PF7 I/O (Z) I Input = High (Inactive) or Program as Output, Set to
1, Let Float5
IRQL1/PF6 I/O (Z) I Input = High (Inactive) or Program as Output, Set to
1, Let Float5
IRQL0/PF5 I/O (Z) I Input = High (Inactive) or Program as Output, Set to
1, Let Float5
IRQE/PF4 I/O (Z) I Input = High (Inactive) or Program as Output, Set to
1, Let Float5
PWD I I High
SCLK0 I/O I Input = High or Low, Output = Float
RFS0 I/O I High or Low
DR0 I I High or Low
TFS0 I/O I High or Low
DT0 O O Float
SCLK1 I/O I Input = High or Low, Output = Float
RFS1/IRQ0 I/O I High or Low
DR1/FI I I High or Low
TFS1/IRQ1 I/O I High or Low
DT1/FO O O Float
EE I I Float
EBR I I Float
EBG O O Float
I/O
3-State Reset
Pin Name1 (Z)2 State Hi-Z3 Caused By Unused Configuration
ERESET I I Float
EMS O O Float
EINT I I Float
ECLK I I Float
ELIN I I Float
ELOUT O O Float
1
CLKIN, RESET, and PF3–0/Mode D–A are not included in this table because these pins must be used.
2
All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.
3
Hi-Z = High Impedance.
4
If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.
5
If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts
and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts, and let pins float.
ELECTRICAL CHARACTERISTICS
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-218xN features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
TO from which
OUTPUT 1.5V t DIS = t MEASURED – t DECAY
PIN
50pF
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
IOH Output Enable Time
Figure 19. Equivalent Loading for AC Measurements (Including All Fixtures) Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in Figure 20. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
SOURCE CURRENT – mA
General Notes VDDEXT = 2.5V @ +85ⴗC
20
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others. 0 VDDEXT = 1.8V @ +85ⴗC
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet –20 VDDEXT = 3.6V @ –40ⴗC
signals. Designers have no control over this timing—circuitry Figure 21. Typical Output Driver Characteristics
external to the processor must be designed for compatibility for VDDEXT at 3.6 V, 3.3 V, 2.5 V, and 1.8 V
with these signal characteristics. Switching characteristics tell
what the processor will do in a given circumstance. Switching
characteristics can also be used to ensure that any timing
requirement of a device connected to the processor (such as
memory) is satisfied.
Timing requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Capacitive Loading
Figure 24 and Figure 25 show the capacitive loading characteris-
tics of the ADSP-218xN.
VD D I N V 100
= 1 .9 45m W
45 VD D I N
T
4 2 mW = 1 .8 V
40 V DD INT 4 0 mW
38m W 1V
= 1 .7
VD D IN T
35 34 m W
10
30 30 m W
25
20
55 60 65 70 75 80 85 0
0 25 55 85
1 /tC K – MHz
TEMPERATURE – °C
NOTES
POW ER, IDLE1 , 2, 4 1. REFLECTS ADSP-218xN OPERATION IN LOWEST POWER
1 5. 0
MODE. (SEE THE "SYSTEM INTERFACE" CHAPTER OF THE
1 4. 0
13.5m W ADSP-218x DSP HARDWARE REFERENCE FOR DETAILS.)
1 3. 0 2. CURRENT REFLECTS DEVICE OPERATING WITH NO
0V
T
= 2.
1 2. 0 V D D IN 1 2 mW INPUT LOADS.
POWER (PID LE) – mW
9V
11 .0 = 1.
V D D I NT
10. 5 m W 10.5m W
10 .0 = 1.8V Figure 23. Typical Power-Down Current
9.5m W V DD IN T
9 .0
8 .5 mW V DD IN T
= 1.71 V 9m W
8 .0 30
7 .5 mW T = 85ⴗC
7 .0 VDD = 0V TO 2.0V
6 .0 25
RISE TIME (0.4V–2.4V) – ns
5 .0
55 60 65 70 75 80 85
20
1 /tC K – MHz
POWER, IDLE n MO DE S2 15
1 2.0
1 2. 0mW
10 .5mW
10
1 0.0
9 .5 mW
POWER (PID LEn ) – mW
8 .5m W
8.0 5
V D D C O RE = 1 . 9 V
V D D C OR E = 1 . 8 V
6.0 5.2 mW
0
4 .9 mW 0 50 100 150 200 250 300
4 .2 mW 4 .7 mW CL – pF
4.0 3 .8m W 4.3 mW
3 .4m W
Figure 24. Typical Output Rise Time vs. Load Capacitance (at Maximum
2.0
Ambient Operating Temperature)
0.0
55 60 65 70 75 80 85
18
1 /tC K – MHz
NOTES 16
VALID FOR ALL TEM PERATURE GRADES.
VALID OUTPUT DELAY OR HOLD – ns
1 14
POW ER REFLECTS DE VI CE OPE RATING WITH NO OUTPUT
LOADS. 12
2
TYP ICAL P OW ER DI SS IPATION AT 1. 8V OR 1. 9V VD D INT AND 10
25 °C, EX CEPT WHERE SPE CI FI ED.
3 8
ID D M EASUREM ENT TAKE N WITH ALL INS TRUCTIONS
EXE CUTING FRO M I NT ERNAL M EM ORY. 50 % OF THE 6
INSTRUCTIO NS ARE M ULT IFUNCTION (TYP ES 1 , 4 , 5 , 1 2, 13, 4
14 ), 30 % ARE TY PE 2 AND TY PE 6, AND 2 0% ARE IDLE
INSTRUCTIO NS. 2
4
IDLE RE FE RS TO S TATE OF OP ERATION DURI NG EX ECUTI ON NOMINAL
OF I DLE INSTRUCTION. DE ASSE RTE D PINS ARE DRI VEN TO
EI THE R VDD O R GND. –2
–4
Figure 22. Power vs. Frequency –6
0 50 100 150 200 250
CL – pF
Figure 25. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at
Maximum Ambient Operating Temperature)
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
MODE A D
tMS tMH
RESET
tRSP
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
CMS, WR, tSD tSEC
IOMS
BG
tSDB
tSE
BGH
tSDBH
tSEH
CLKOUT
ADDRESS LINES1
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP tRWR
tCRD
DATA LINES2
tRDD tRDH
tAA
WR
1ADDRESS LINES FOR ACCESSES ARE: 2DATA LINES FOR ACCESSES ARE:
BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs) BDMA: D15–8
I/O SPACE: A10–0 I/O SPACE: D23–8
EXTERNAL PM AND DM: A13–0 EXTERNAL DM: D23–8
EXTERNAL PM: D23–0
CLKOUT
ADDRESS LINES1
DMS, PMS,
BMS, CMS,
IOMS tWRA
WR
tDW
tWDE
RD
1ADDRESS LINES FOR ACCESSES ARE: 2DATA LINES FOR ACCESSES ARE:
BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs) BDMA: D15–8
I/O SPACE: A10–0 I/O SPACE: D23–8
EXTERNAL PM AND DM: A13–0 EXTERNAL DM: D23–8
EXTERNAL PM: D23–0
CLKOUT
t CC tCC tS C K
SCLK
tS CP
t SC S tSC H tSC P
DR
TFSIN
RFSIN
tRD
tR H
RFSO UT
TFSO UT
tS C DD
t SC D V
tS CD E tSC D H
DT
tTD E
t TD V
TFSO UT
A LTER N A TE
FRA M E
M OD E
tR DV
RFS OU T
MU LTIC H A NN E L
M ODE ,
FR A ME DE LA Y 0
tTD E
( MFD = 0 )
tTD V
TFSIN
ALTE R NA TE
FR A ME
MO DE
tR DV
RFSIN
MU LTIC H A NN E L
M ODE ,
FR A ME DE LA Y 0
( MFD = 0 )
IACK
tIKA tIALD
IAL
tIALP tIALP
IS
IAD15–0
tIASU tIASU
tIAH tIAH
tIALS
IRD OR IWR
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDH
tIDSU
IAD15–0 DATA
tIK W
IACK
tIKH W
tIK LW
IS
IWR
tIKSU
tIK H
IAD15–0 DATA
IACK
tIKHR
tIKR
IS
tIRK
IRD
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIRDE tIKDH
PREVIOUS
IAD15–0
DATA
tIRDV tIKDD
Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
IA CK
t IK R
t IK H R
IS
tIR P
IRD
t IR D E t IK D H
PR E V IO U S
IA D 15–0
D A TA
t IR D V tIK D D
L EG EN D :
IM PL IES TH A T IS A N D IR D C A N B E
HE LD IN D E FIN ITE LY B Y H O S T
Figure 37. IDMA Read, Short Read Cycle in Short Read Only Mode
94 PF0 [MODE A]
93 PF1 [MODE B]
88 PF3 [MODE D]
89 PF2 [MODE C]
96 PWDACK
98 A1/IAD0
100 A3/IAD2
99 A2/IAD1
90 VDDEXT
91 PWD
95 BGH
92 GND
80 GND
84 D23
83 D22
82 D21
79 D19
78 D18
77 D17
81 D20
76 D16
87 FL0
86 FL1
85 FL2
97 A0
A4/IAD3 1 75 D15
A5/IAD4 2 PIN 1 74 D14
IDENTIFIER
GND 3 73 D13
A6/IAD5 4 72 D12
A7/IAD6 5 71 GND
A8/IAD7 6 70 D11
A9/IAD8 7 69 D10
A10/IAD9 8 68 D9
A11/IAD10 9 67 VDDEXT
A12/IAD11 10 66 GND
A13/IAD12 11 65 D8
GND 12 ADSP-218xN 64 D7/IWR
CLKIN 13 63 D6/IRD
TOP VIEW
XTAL 14 (Not to Scale) 62 D5/IAL
VDDEXT 15 61 D4/IS
CLKOUT 16 60 GND
GND 17 59 VDD INT
VDDINT 18 58 D3/IACK
WR 19 57 D2/IAD15
RD 20 56 D1/IAD14
BMS 21 55 D0/IAD13
DMS 22 54 BG
PMS 23 53 EBG
IOMS 24 52 BR
CMS 25 51 EBR
IRQE+PF4 26
IRQL0+PF5 27
GND 28
IRQL1+PF6 29
IRQ2+PF7 30
DT0 31
TFS0 32
RFS0 33
DR0 34
SCLK0 35
VDDEXT 36
DT1/FO 37
TFS1/IRQ1 38
RFS1/IRQ0 39
DR1/FI 40
GND 41
SCLK1 42
ERESET 43
RESET 44
EMS 45
EE 46
ECLK 47
ELOUT 48
ELIN 49
EINT 50
12 11 10 9 8 7 6 5 4 3 2 1
D14 NC D15 D19 D21 VDDEXT PWD A7/IAD6 A5/IAD4 RD A 6/IAD5 PW DACK C
PF 2 PF 1
G ND NC D12 D13 NC A9/IAD8 BG H NC WR NC D
[MO DE C] [MO DE B]
V D D IN T V D D IN T D1/IAD14 BG RFS 1/IRQ 0 D 0/IAD13 SCL K0 VDDEXT VDDEXT NC VDDINT CLK OUT J
10.10 A1 CORNER
10.00 SQ INDEX AREA
9.90 11 9 7 5 3 1
12 10 8 6 4 2
A
BALL A1 B
INDICATOR C
D
8.80
BSC E
SQ F
G
0.80 H
BSC
J
(BALL
PITCH) K
L
M
DETAIL A
1.40
MAX DETAIL A 1.11
0.85
0.25
MIN
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY 0.50 SEATING
WITH JEDEC STANDARD MO-205-AC. 0.45 PLANE
2. ACTUAL POSTION OF THE BALL GRID IS WITHIN 0.40
0.15 OF ITS IDEAL POSTION RELATIVE TO THE (BALL DIAMETER, 0.12 MAX (BALL
PACKAGE EDGES. COPLANARITY)
SEE NOTE 4)
3. CENTER DIMENSIONS ARE NOMINAL.
4. DIMENSION IN DRAWING IS FOR PB-FREE BALL.
PB-BEARING BALL DIMENSION IS 0.45/0.50/0.55.
16.00 BSC SQ
1.60 MAX
14.00 BSC SQ
1.45
0.20
1.40
0.09
1.35
7° VIEW A
3.5°
0.15 25 51
0°
SEATING 26 50
0.05 0.08
PLANE MAX LEAD 0.27
0.50 BSC
COPLANARITY 0.22
VIEW A 0.17
ROTATED 90° CCW
Figure 41. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100-1)
Table 29. BGA Data for Use with Surface Mount Design