INTRODUCTION TO PIC MICROCONTROLLERS

The term PIC, or Peripheral Interface Controller, is the name given by

Microchip Technologies to its single – chip microcontrollers. These devices have

been phenomenally successful in the market for many reasons, the most significant

ones are mentioned below. PIC micros have grown in steadily in popularity over

the last decade, ever since their inception into the market in the early 1990s. PIC

micros have grown to become the most widely used microcontrollers in the 8- bit

microcontroller segment. The PIC16F877 is 40 pin IC. There are six ports in this

microcontroller. Namely PORT A, PORT B, PORT C, PORT D and PORT E.

Among these ports PORT B, PORT C and PORT D contains 8-pins, where PORTA

contains 6-pins and PORT E contains 3-pins.

Each pins in the ports can be used as either input or output pins. Before

using the port pins as input or output, directions should be given in TRIS register.

For example setting all the bits in TRIS D register indicates all the pins in PORT D

are used input pins.

Clearing all the bits in TRIS D register indicates all the pins in PORT D are

used as output pins. Likewise TRIS A, TRIS B, TRIS C, TRIS E registers

available for PORT A, PORT B, PORT C and PORT E.

The main factors that account for the popularity of PIC micros include the

following:
 Speed: When operated at its maximum clock rate, a PIC executes most

instructions in 0.2µs, or five instructions in a microsecond.

 Instruction set simplicity: The instruction set consists of just 35

instructions.

 Integration of operational features: PIC micros have features like Power

on Reset and Brown out protection which ensures that the chip operates only

when the supply voltage is within specification. A watchdog timer resets the

PIC if the chip ever malfunctions and deviates from its normal operations.

 Flexibility in clock sources: The PIC micros can be run with four different

types of clock sources which help in cost cutting and power saving.

 High current capabilities of ports: The ports pins on PIC micros can

source and sink up to 25mA, which make them all the more versatile and

economic.

 Serial programming via two pins: PIC micros can be programmed serially

with two pins, which bring down the complexity and the cost of PIC

programmers, drastically.

 On chip EEPROM: The on chip EEPROM helps retain critical data even if

the power is down. There by reducing the cost of and external EEPROM

from the overall system cost.

 Harvard Architecture
 Apart from these features are reasons of non technical nature like the

availability of free development software, low cost device programmers, and

availability of free datasheets and application notes.

GENERAL DESCRIPTION OF P16F877

The architecture of PIC16F877 contains 4-banks of register files such

as Bank 0, Bank 1, Bank 2 and Bank 3 from 00h-07h, 80h-FFh, 100h-17Fh and

180h-1FFh respectively. And it is also having program FLASH memory, Data

memory and Data EEPROM of 8K, 368 and 256 Bytes respectively.

REGISTER FILE

The term register file in PIC terminology used to denote the locations than an

instruction can access via an address. The register file consists of two components,

they are

1. General purpose register file

2. Special purpose register file

GENERAL PURPOSE REGISTER FILE

The general-purpose register file is another name for the microcontrollers

RAM. Data can be written to each 8-bit location, updated and retrieved any number

of times. All control registers are coming under the general purpose register file.
SPECIAL PURPOSE REGISTER FILE

The special purpose register file contains input and output ports as well as the

control registers used to establish each bit of port as either an input or output. It

contains registers that provide the data input and data output to the variety of

resources on the chip, such as the timers, the serial ports and the analog–to–digital

converter. It has registers that contain control bits for selecting the mode of

operation of a chip resource as well as enabling or disabling its operation.

Every instruction that can employ the direct addressing mode can, as an

alternative employ the indirect addressing mode. In this alternative mode, the full

8-bit register file address is first written into FSR, a special purpose register that

serves as an address pointer to any address throughout the entire register file. A

subsequent direct access of INDF will actually access the register file using the

content of FSR as a pointer to the desired location of the operand.

REGISTER FILE MAPS USED IN PIC16F877

NAME FUNCTION ADDRESS BIT

RAM ADDRESS ADDRESABLE

STATUS Status register 03H,83H,103H,183H Yes
FSR File select register 04H,84H,104H,184H Yes
PORTA I/O latch 05H Yes
PORTB I/O latch 06H Yes
PORTC I/O latch 07H Yes
PORTD I/O latch 08H Yes
PORTE I/O latch 09H Yes
INTCON Interrupt control 0BH,8BH,10BH,18BH Yes

register
PIR1 Peripheral interrupt 0CH Yes

control
RCSTA Receive status and 18H Yes

control register
TXREG Transmit register 19H Yes
RCREG Receive register 1AH Yes
OPTION_REG Optional register 81H Yes
TRISA I/O register 85H Yes
TRISB I/O register 86H Yes
TRISC I/O register 87H Yes
TRISD I/O register 88H Yes
TRISE I/O register 89H Yes
TXSTA Transmit status and 98H Yes

control register
SPBRG Baud rate generator 99H Yes

STATUS REGISTER

Flags are one bit registers provided to store results of certain program

instructions, other instructions can test the condition of the flags and make decisions

based on the flag states. In order to address the flags conveniently flags are

grouped inside the register named STATUS.

The PIC16F877 has three flags such as Zero(Z), Digit Carry(DC) and

Carry(C), that responds automatically to the outcomes of the mathematical

operations. These flags are set to logic-0 or logic-1 according to the Arithmetic and

Logical operations. The following figure shows the STATUS register,

STATUS REGISTER(ADDRESS 03H,83H,103H,183H)

IRP RP1 RP0 TO PD Z DC C

Bit 7 Bit 0

IRP: Register Bank Select Bit (used for indirect addressing)

1 = Bank 2,3 (100H – 1FFH)
0 = Bank 0,1 (00H – FFH)

RP1:RP0: Register Bank Select Bits (used for direct addressing)

11 = Bank3 (180H – 1FFH)
10 = Bank2 (100H – 17FH)
01 = Bank1 (80H – FFH)
00 = Bank0 (00H – 7FH)
Each bank is 128 bytes

To: Time-out bit

1 = After power-up, CLRWDT instructions, or SLEEP instruction
0 = A WDT time-out occurred

PD: Power-down bit

1 =After power-up or by the CLRWDT instructions
0 = By execution of the SLEEP instruction

Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most significant bit of the result occurred
OPTION_REG REGISTER (ADDRESS 81H,181H)

RPBU INTEDG TOCS TOSE PSA PS2 PS1 PSO

Bit 7 Bit 0

RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

TOCS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CK1 pin
0 = Internal instruction cycle clock (CLKOUT)

TOSE: TMR0 Source Edge Select not

1 = Increment on high-to-low transition on RA4/T0CK1 pin
0 = Increment on low-to-high transition on RA4/T0CK1 pin

PSA: Prescalar Assignment bit

1 = Prescalar is assigned to WDT
0 = Prescalar is assigned to the Timer0 module

PS2:PS0: Prescalar Rate Select bits

Bit value TMR0 Rate WDT Rate

000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1:16 1:8
100 1:32 1:16
101 1:64 1:32
110 1:128 1:64
111 1:256 1:128
INTERRUPTS

One of the methods to determine the condition that exists in internal and

external circuits is to respond to the hardware signals, called interrupts which force

the program to call a subroutine. Interrupts are generated by internal chip

operations and provided by external sources known as Internal interrupts and

External interrupts respectively. Any interrupts can cause or transfer the PIC16f877

microcontroller control to the address 0004h. By configuring the INTCON

register we enable the interrupts.

Types of External interrupts

1. Interrupt on Change

2. External interrupt

All the External interrupts are generated when the port pin is considered as

input pin.

INTERRUPT ON CHANGE

These external interrupts can be generated only on the PORT B, when it acts

as a input port. If any of the change in the port pins from PB4 – PB7 then the

interrupt will be generated. This type of external interrupt is known as Interrupt on

Change.

EXTERNAL INTERRUPT
 This external interrupt can be generated only at the PORT B-0 (PB0) , by

using the pull-ups resistors we can generate the interrupt during when the port pin

PB0 is in low or high.

TYPES OF INTERNAL INTERRUPTS

Timer-0 over flow interrupt, Timer-1 overflow interrupt, etc.

The following figure shows the INTCON register,

INTCON REGISTER (ADDRESS 0BN,8BH,10BH,18BH)

GIE PEIE TOIE I INTE RBIE T0IF INTF RBIF

Bit 7 Bit 0

GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts

PSIE: Peripheral Interrupt Enable bit

1 = Enables the unmasked peripheral interrupts
0 = Disables all peripheral interrupts

T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 Interrupt
0 = Disables the TMR0 Interrupt

INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT External Interrupt
0 = Disables the RB0/INT External Interrupt

RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)
 0 = TMR) register did not overflow

INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT External Interrupt occurred (must be cleared in software)
0 = The RB0/INT External Interrupt did not occur

RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state
0 = None of the RB7:RB4 pins have changed state

SERIAL DATA COMMUNICATION

Computers must be able to communicate with other computers in modern

multi processor distributed systems. One cost-effective way to communicate is to

send and receive data bytes serially. The P16F77 micro controller has serial data

communication circuits that transmits and receive the data. By configuring the

SPEN in RCSTA we can enable the serial communication in P16F877. Similarly

by configuring the TXSTA (Transmit Status and Control Register) and RCSTA

(Receive Status and Control Register) we can transmit and receive the data serially.

The any date in TXREG (Transmit Register) transmit the data and the data which is

in RCREG (Receive Register) is the receive data. The following figure shows the

TXSTA and RCSTA,

TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98H)

CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D

Bit 7
Bit 0

CSRC: Clock Source Select bit

Asynchronous mode : Don’t care
Synchronous mode:
1 = Master mode (Clock Generated internally from BRG)
0 = Slave mode (Clock from External source)

TX9: 9-bit Transmit Enable bit

1 = Transmit enabled
0 = Transmit disabled

TXEN: Transmit Enable bit

1 = Transmit enabled
0 = Transmit disabled

SYNC: USART Mode Select bit

1 = Synchronous mode
0 = Asynchronous mode

Unimplemented: Read as ‘0’

BRGH: High Baud Rate Select bit

Asynchronous mode:
1 = High Speed (for 20MHz crystal)
0 = Low Speed (for 4MHz crystal)
Synchronous mode: Unused in this mode

TRMT: Transmit Shift Register Status bit

1 = TSR empty
0 = TSR full

TX9D: 9th bit of Transmit Data,can be a parity bit

RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18H)

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

Bit 7 Bit 0

SPEN: Serial Port Enable bit

1 = Serial port enabled (configure RC7/Rx/DT and RC6/Tx/CK pins as serial port
pins)
0 = Serial port disabled

RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception
0 = Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode: Don’t care
Synchronous mode – master:
1 = Enables single receive
0 = Disables single receive
Synchronous mode – slave: Don’t care

CREN: Continuous Receive Enable bit

Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is Cleared
0 = Disable continuous receive

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 =1)
1 = Enables address detection, enables interrupt and load of the receive buffer when
RSR is set)
0 = Disables address detection, all bytes are received, and ninth bit can be used as
parity bit)

FERR: Framing Error bit

1 = Framing error(can be updated by reading RCREG register and receive next
valid byte)
0 = No framing error

OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error

RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user
Firmware)

MAX 232
 Many microcontrollers have asynchronous serial ports, but their inputs and

outputs use 5v logic rather than RS-232 port requires converting to and from RS-

232 level, with TTL logic, a logic low output must be no higher than 0.4v and a

logic low input must be no higher than 0.8V. A logic high output must be at least

2.4V while a logic-high input must be at least 2V using these levels, an interface

may have 0.4V of noise without causing errors.

The original MAX-232 includes two drivers that convert TTL inputs to RS-

232 outputs, and two receivers that accept RS-232 inputs and translate them to

CMOS – compatible outputs.

PCs and many microcontrollers have a component called a UART (universal

asynchronous receiver/ transmitter) that handles most of the details of sending and

receiving serial data.

In PCS the operating system and programming languages include support for

programming serial links without having to understand every detail of the UART’s

architecture. To open a link, the applications selects a data rate and other settings

and enables communications at the desired port.

INSTRUCTION SETS IN P16F877

Mnemonic Operands Description Cycles Status

Affected
ADDWF f, d Add W and f 1 C,DC,Z
ANDWF f, d AND W with f 1 Z
CLRF f Clear f 1 Z
CLRW - Clear W 1 Z
COMF f, d Complement f 1 Z
DECF f, d Decrement f 1 Z
DECFSZ f, d Decrement f, skip if 0 1(2)
INCF f, d Increment f 1 Z
INCFSZ f, d Increment f, skip if 0 1(2)
IORWF f, d Inclusive OR W with f 1 Z
MOVF f, d Move f 1 Z
MOVWF f Move W to f 1
NOP - No Operation 1
RLF f, d Rotate Left f through Carry 1 C
RRF f, d Rotate Right f through Carry 1 C
SUBWF f, d Subtract W from f 1 C,DC,Z
SWAPF f, d Swap nibbles in f 1 Z
XORWF f, d Exclusive OR W with f 1 Z
BCF Bit clear f 1
BSF Bit set f 1
BTFSC Bit Test f, Skip if Clear 1(2)
BTFSS Bit Test f, Skip if set 1(2)
ADDLW Add literal and W 1 C, DC, Z
ANDLW AND with literal and W 1 Z
CALL Call subroutine 2
CLRWDT Clear watchdog timer 1
GOTO Go to Address 2 ----
TO
IORLW Inclusive OR literal with W 1 Z
MOVLW Move literal to W 1
RETFIE Return from Interrupt 2
RETLW Return with literal in W 2
RETURN Return from Sub routine 2
SLEEP Go into stand by mode 1
SUBLW Subtract W from literal 1 Z
XORLW Exclusive OR with literal 1 C, DC, Z

ISOLATED LINKS

RS-232’s large noise margin help to make the interface reliable and immune

to data errors caused by external noise coupling into the wires. If a links

environment is electrically noisy, isolation can keep noise from coupling between

the link and the circuits it connects to.

 Isolation works by dividing a circuit into independent sections, the sections

use optical and magnetic coupling to transfer power and data, while filtering out the

much of the noise.

The isolation may isolate the ground, the datalink, or both. Ground isolation

makes a circuit immune to power surges and noise in the earth ground shared by

nearby circuit. In long links, ground isolation also makes the link immune to

differences in ground potential from end to end. Isolation the data link keeps noise

from coupling between the link and the circuits it connects to.

The isolated links consists of opto isolators, to transfer signals across an

isolation barrier. An optoisolator consists of a photodiode coupled to a photo

transistor. The current through the photodiode causes it to emit energy in the

visible or infrared band.