2 80 IEEE ELECTRON DEVICE LETTERS, VOL. 10, NO.

6, JUNE 1989

A Self-Aligned Retrograde Twin-Well Structure

with Buried p -Layer +

S. ODANAKA, T. YABU, N. SHIMIZU, H. UMIMOTO, AND T. OHZONE

Abstract-This paper reports a self-aligned retrograde twin-well struc- 4 4 4 4

ture with a buried p+-layer surrounding the n-well. The retrograde twin
wells and buried p+-layer are fabricated by a single lithographic step
using high-energy ion implantation. The retrograde n-well is self-aligned
to the retrograde p-well regions. This simple process allows a scalable
CMOS structure for the very tight n+-to-p+ spacing. It provides latch-up
immunity at the 1.5-pm n+-to-p+ spacing and good isolation characteris-
tics without additional n- and p-channel stops. BURIED p + - LAYER

I. INTRODUCTION

A WIDE variety of CMOS technologies has been proposed

to reduce CMOS latch-up susceptibility and to achieve
the high performance of n-channel and p-channel MOSFET’s
through advanced well processing. In epi-CMOS technology,
p - WELL
some authors [ 11 have focused on developing epi-n-well
CMOS processes using thin epitaxial layers on low-resistivity
BURIED p - LAYER
+

substrates with retrograde n-wells formed by high-energy ion p - SUBSTRATE

implantation. For non-epi-CMOS processes, another approach
has been proposed: that is, creating a buried p+-layer using
megaelectronvolt ion implantation [2] to produce a low- OXIDE I
resistivity substrate. As Terrill et al. pointed out, this n -WELL
p - WELL
approach has some advantages in quality and fabrication cost
of p-/p+ substrates, and process control of abrupt p+-layers
BURIED p + - LAYER
when compared with epi-CMOS processes. However, this
process can be considered as a variation of the epi-CMOS
(C)
technology.
The recent development of high-packing-density CMOS
circuits also requires the scaling down of CMOS structures
and the simplification of CMOS processing while maintaining
n - WELL
good isolation characteristics. As an effective approach to this p - WELL
problem, well processes with self-aligned channel stops have
been introduced in both the twin-well [3], [4] and retrograde n- BURIED p - LAYER
+

p - SUBSTRATE
well processes [5]. Moreover, it is reported that in a
retrograde twin-well process it is possible to eliminate an
(d)
additional channel stop process [6].
Fig. 1. Process sequence of the new CMOS structure: (a) after phosphorus
The purpose of this paper is to present a self-aligned implant, (b) after boron implant, (c) after forming the shallow trench
retrograde twin-well structure with a buried p +-layer, which isolation with 0.5 pm depth, and (d) after forming n-channel and p-channel
gives a scalable CMOS structure for the very tight n+-to-p+ MOSFET’s.
spacing of 1.5 pm. This is achieved by a non-epi-CMOS
process based on high-energy implantation technology. for both n- and p-channel stop doping, and a buried p+-layer
11. FABRICATION SEQUENCE surrounding the n-well for achieving high CMOS latch-up
immunity. The novel step in this process is a single litho-
The basic fabrication sequence is shown in Fig. 1. This graphic step to define the retrograde n-well and p-well regions
consists of forming retrograde twin wells, which are also used and to create the buried p -layer using two high-energy ion
+

implants. The photoresist with a stopping power of 0.82 is

Manuscript received November 28, 1988; revised February 26, 1989.
The authors are with the Semiconductor Research Center, Matsushita
Electric Industrial Company, Ltd., Moriguchi, Osaka 570, Japan.
IEEE Log Number 8928668.
deposited with the thickness of 1.9 pm. The value of 0.82 was
measured by using the SIMS data. The photoresist stops the
phosphorus implant, used for the retrograde n-well, in regions

0741-3106/89/06OO-0280$01.OO 0 1989 IEEE

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ODANAKA et ai: TWIN-WELL STRUCTURE WITH BURIED p+-LAYER 28 I

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Fig. 2. Simulated two-dimensional doping profiles. The 700-keV phos- 5 6 - I
phorus is implanted at a dose of 1.0 x l O I 3 cm-*. The 1.5-MeV boron is : I
implanted at a dose of 3.0 x lot3 They were subject to an anneal in . I
N2 at 1050’C for 2 h. 4 - I
I
I
which become p-wells. Its thickness is such as to allow the P + TO P-WELL I N + TO N-WELL
2-
boron implantation into the silicon region through the photore- I
sist for forming the retrograde p-well and buried p -layer +

under the n-well in the uncovered region. The 1.5-MeV boron
ions are implanted with moderate doses of 3.0 x 1013to 7.0
x lOI3 cm-2, which are known to avoid the generation of
secondary defects, especially dislocation loops [7]. Using the
same mask step, the retrograde n-well is formed by a second
700-keV phosphorus implant with a dose of 1.0 x l O I 3 cm-2.
The phosphorus implant is self-aligned to the p-well regions.
In the above range of boron doses, the reverse leakage current
of the n-well to the p-well was kept low, about 1.0 PA, in the
test device with a large area of 2.1 x cm2 when the n-
well voltage is applied to 10 V. In this work, the shallow
trench isolation [8] was used with an isolation oxide thickness
of 0.5 pm.
The simulation of Fig. 2 demonstrates doping profiles
achieved with the fabrication sequence shown in Fig. 1. A
process simulator (SMART-P [9]) was used to design the
doping profiles of the retrograde twin well and the buried p +-
layer. It represents a cross section of the twin-well structure
proposed in this work, which has a 2-pm n+-to-p+ spacing on
the mask. The 1.5-MeV boron implant determines the two
peak concentration regions. One is centered at a depth of 0.8
pm below the silicon surface under the photoresist and the
other at a depth of 2.3 pm below the silicon surface in the n-
well region. The simulation result also indicates that the high
concentration regions of the retrograde wells are effectively
placed as channel stops for active device isolation. The
channel stop processes are eliminated by using the tight spatial
profiles of the retrograde twin wells.
111. DEVICE
CHARACTERISTICS
The isolation characteristics of the present CMOS structure
were estimated by measuring the current characteristics of the
parasitic n- and p-channel field transistors formed between n-
channel and p-channel MOSFET’s. The gate was formed with
n+-polysilicon over field oxide. The experimental data and a
schematic of the configuration are shown in Fig. 3 as a
function of the distance from the active region to the well
0 1 1 I I I
4 3 2 1 0 1 2 3 4
ACTIVE AREA TO WELL EDGE, d ( pm )
Fig. 3. Isolation characteristics of the parasitic n-channel and p-channel field
transistors as a function of the distance from the active region to the well
edge. The maximum test voltage is limited at 12 V.
edge. Fig. 3 plots gate voltages defined by the subthreshold
leakage current of 1 pA/pm. The maximum test voltage is
limited at 12 V to prevent very thin gate oxide. The results
indicate that for the 1.5-pm n+-to-p+ spacing the leakage
currents are < 1 pA/pm where the n+ poly gate bias is
between - 10.0 and 12.0 V.
The CMOS latch-up immunity was characterized by mea-
suring the latch-up switching point at which switching from
the blocking state occurs [lo]. The switching points are
determined as functions of the n+-to-p+ spacing and different
boron dose conditions. To clarify the latch-up immunity of the
present CMOS structure, the switching points of this structure
are compared with those of a retrograde n-well CMOS and a
retrograde n-well CMOS with a blanket implanted p + buried
layer. The high-energy implantation conditions for these
CMOS structures are similar to those described in Section 11.
The test devices have a diffusion width of 40 pm and a topside
substrate contact. The experimental data and a schematic of
the configuration are shown in Fig. 4.
Fig. 4 shows latch-up switching currents for triggering due
to the forward-biased p + to n-well junctions. The present
CMOS structure provides the same latch-up immunity as the
retrograde n-well CMOS with the blanket implanted p + buried
layer. The latch-up immunity depends on the device parame-
ters of the buried p+-layer, which are the concentration,
thickness of transition region, and depth [ 111. In comparison
with the retrograde n-well CMOS having a n+-to-p+ spacing
of 1.5 pm, the latch-up switching current is increased by a
factor of 8.8 for a boron dose of 3.0 x l O I 3 cm-2, and a factor
of 16.7 for a boron dose of 7.0 x 1013cm-2. The results also
 ~

282 IEEE ELECTRON DEVICE LElTERS, VOL. 10, NO. 6, JUNE 1989

10-1L CMOS processing and allows a scalable CMOS structure for

NEW CMOS ....
the very tight n+-to-p+ spacing of 1.5 pm. It provides latch-up
0 BORON 7 . 0 1013
~ cm.* immunity at the 1.5-pm n+-to-p+ spacing and good isolation
i m BORON 3 . 0 1013
~ cm-’
characteristics without additional n- and p-channel stop proc-
BLANKET IMPLANTED
P’BURIED LAYER esses.
a BORON 3.0X 1013cm-’

A RETROGRADE n-WELL
”- ACKNOWLEDGMENT
....

The authors would like to thank Dr. H. Mizuno, T.

W processing.
zI
U REFERENCES
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due to the forward-biased p+ to n-well junctions.
indicate that the latch-up immunity order depends slightly on
the n+-to-p+ spacing down to 1.0 pm. The buried p+-layer is
shown to be effective in shunting the lateral n-p-n transistor in
the scaled CMOS structure.
IV. CONCLUSION
A self-aligned retrograde twin-well structure with a buried
p+-layer surrounding the n-well has been proposed. The
retrograde twin wells and buried p+-layer are formed by a
single lithographic step using high-energy ion implantation.
The phosphorus implant for the n-well is self-aligned to the p-
well regions. This process is compatible with-conventional
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