Akai LCT2715 Service Manual

SERVICE MANUAL
Model:
LCT2715
Safety Instructions
Production specification.
Block Diagram
Circuit Diagram
Disassembly
Pin Descriptions
LCD Panel specification
Exploded View Diagram
Spare parts list
V-chip password and software upgrade
This manual is the latest at the time of printing, and does not
include the modification which may be made after the printing,
by the constant improvement of product.
I. Safety Instructions
The l ig h tn i ng fla sh w i th arro wh e ad symb ol ,

within an equilatera l triangle, is intended to alert
CAUTION the user to the presence of uninsulated “ dangerous
voltage” within the prod uct’ s enclosure that may
RISK O F ELECT RIC SHO CK be of sufficie nt mag nitud e to consti tute a risk of
DO NO T O PEN electric shock to persons.
The excla mati on po i nt wi thi n a n e q ui l ate ra l

CAUTION: TO REDUCE THE RISK OF ELECTRIC tri a n gl e is i nte n de d to a le rt th e u se r to th e
SHOCK, DO NOT REMOVE COVER (OR BACK). NO presence of important operating and maintenance
USER-SERVICEABLE PARTSINSIDE. REFER (s e rv i ci n g ) i n str u ct i o n s i n th e l i te r a tu re
SERVICING TO QUALIFIED SERVICE PERSONNEL accompanying the appliance.
ONLY.
PRECAUTIONS DURING SERVICING WARNING:

1. In a ddition to safe ty, othe r parts and assemblies are
speci fied for conformance with such regulatio ns as Before servicing this TV receiver, read the X-RAY
those applyi ng to sp urious radiation . These must RADIATION PRECAUTION, SAFETY INSTRUCTION
also be replace d only with specifie d replacements. and PRODUCT SAFETY NOTICE.
Exampl es: RF converters, tun er units, a ntenna
selection switches, RF cables, noise-blo cking X-RAY RADIATION PRECAUTION
capacitors, noise-bl ocking filters, etc. 1. Excessively high can prod uce potentially hazardous
2. Use sp ecified inte rnal Wiring . Note especially: X-RAY RADIATION. To avoid such hazards, the high
1) Wires covered with PVC tubing volta ge must no t exceed the speci fied limit. The
2) Do uble insulated w ires normal va lue of the high voltage of this TV receiver
3) Hig h voltage leads is 2 7 KV at zero b ean current (mi nimum b rightne ss).
3. Use specified i nsulating material s for haza rdous The high voltage must no t exceed 30 KV u nder any
live pa rts. Note espe cially: circu mstances. Each time when a re ceiver req uires
1) In sulating Tape servici ng, the high voltage sho uld be checked. The
2) PVC tubing readi ng of the high voltage is re commended to be
3) Spa cers (insu lating barriers) reco rded as a part o f the service record, It is
4) Insula ting sheets for transistors important to u se an accurate and reliable high
5) Plastic screws for fixing micro switches voltage meter.
4. When replacing AC primary side compo nents 2. The only source of X-RAY RADIATION in this TV
(tran sformers, power cords, n oise blo cking receiver is the picture tube. For con tinued X-RAY
capacitors, e tc.), wra p ends o f wires securely about RADIATION protectio n, the repla cement tube must be
the te rminals be fore solde ring. exactly the sa me type as specified in th e parts list.
3. Some parts in this TV receiver have special safety
related characteristics fo r X-RADIATION protection.
For continued safety, the parts rep lacement should
be under taken only afte r referring the PRODUCT
5. Make sure that w ires do no t contact heat generating SAFETY NOTICE.
parts (he at sin ks, oxide me tal fi lm resistors, fusi ble
resistors, etc.) SAFETY INSTRUCTION
6. Check if replace d wires do not conta ct sharply edged The se rvice shoul d not be attempted by anyone
or po inted pa rts. unfamiliar with the ne cessary i nstructio ns on th is TV
7. Make sure that foreign objects (screws, solder receiver. The fo llowing are the necessary instru ctions
drop lets, etc.) do not remain insi de the set. to be ob served before se rvicing.
1. An isolation transformer shoul d be con nected i n the
MAKE YOUR CONTRIBUTION TO PROTECT THE power li ne between the receiver and the AC line
ENVIRONMENT when a service is performed o n the primary of the
Used batte ries wi th the ISO symbol conve rter tra nsformer of the set.
for recycling a s well as small 2. Comply wi th all caution an d safety related provided
accumu lators (re chargeable batteries), mini-batteries on th e back of the cabi net, inside the cabinet, o n the
(cell s) and starter b atteries should not be thrown chassis or p icture tube.
into the garbage can. 3. To avo id a shock hazard, alw ays discharge the
Please leave the m at an ap propriate depot. pictu re tube's anode to the chassis g round be fore
removi ng the anod e cap.
-2-
4. Completely discharge the high pote ntial voltage of the PRODUCT SAFETY NOTICE
picture tube before handli ng. The pi cture tube is a
Many e lectrical an d mechanica l parts in this TV
vacuum and if bro ken, the gl ass will explode.
5. When rep lacing a MAIN PC B in the cabinet, always receiver have special safety-related characteristics.
These characteri stics are offer passed unnoticed by
be certai n that all protective are installed properly
visual spection and the protecti on afforded by them
such as co ntrol knobs, adjustment co vers o r shie lds,
barri ers, iso lation resistor networks etc. cannot necessari ly be obta ined by using replacement
compon ents rates for a hig her voltag e, wattage , etc.
6. When se rvicing is re quired, observe the origin al lead
The replacemen t parts w hich have these sp ecial
dressing. Extra precau tion sho uld be gi ven to a ssure
correct lead dressing in the high voltage area. safety characteristics are identifie d by marks on
the schematic diag ram and on the parts l ist.
7. Keep wires away from high voltage or high te mpera
Before replacin g any of these compo nents, rea d the
ture compone nts.
8. Befo re returning the set to the customer, al ways parts list in thi s manua l care fully. The use of
substitute re placemen t parts which do not have the
perform an AC leaka ge current check on the exposed
same safety chara cteristics as speci fied in the p arts
meta llic parts of th e cabine t, such as anten nas,
termin als, screw heads, meta l overlay, control shafts, list may cre ate shock, fire, X-RAY RADIATION or
other h azards.
etc., to be sure the set i s safe to operate without
danger of electrica l shock. Plu g the AC lin e cord
directly to the AC outlet (do not use a line iso lation
transformer d uring th is check). Use an AC voltmeter
havin g 5K ohms volt sen sitivity or more i n the
following manner.
Conne ct a 1.5 K ohm 10 watt resistor pa ralleled by a
0.15µF AC type capacito r, between a go od earth
ground (water pipe, conductor etc.,) and the exposed
metallic parts, one a t a ti me.
Measure the AC vol tage across the combination of
the 1 .5K ohm resistor and 0.15 uF capacitor. Re verse
the AC p lug at the AC o utlet and repea t the AC
volta ge measurements fo r each exposed metallic
part.
The me asured voltage must not exceed 0.3 V RMS.
This correspo nds to 0.5mA AC. Any val ue exceeding
this limit co nstitute s a poten tial sho ck hazard and
must be corrected immedia tely.
The resista nce me asureme nt shou ld be done
betwe en accessi ble exposed metal parts and power
cord plug prong s with th e power switch "ON". The
resi stance should be mo re tha n 6M o hms.
AC VOLTMETER
Goo d ea rth grou nd Pl ace this pro be

su ch as th e wat er on eac h e x -
p ip e , c o n du c t or , p os ed me t al li c
etc. part
AC Leak age Curr ent Check
-3-
KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE
Product Specification
Reference No. : LC27HAB002
Revision :0
Date : 2005.08.1
Page : P.1 of 8
Model No. : LC27HAB

Customer Model No. : LCT2715
Design Code : LC27HABCUSXM1-A01
BOM No. : LC27HABCUSXM1-A01
Artwork Ass'y No. : 580-L26ABHM-TU02L
Description : AKAL LCD TV 26” NTSC AC100V-240 V AC USA
Checked By: Electronic Engineer
Mechanical Engineer
Approved By: Engineering Manager
Approved By: PM Department Head
DOC Rev The Latest Revision Details DATE

NO.
0 Initial Release
Reference No : LC27HAB001
Revision :0
Date : 2005.8.1
Page : P. 2 of 8
General Description
1. Main features
Production Description AKAL LCD TV 27” NTSC AC100V-240VAC USA
Panel Supplier and Model CHIMEI V270B1-L01
Chips Solution MK8205
Market USA
1.1 VIDEO SECTION
Display size 27”/16:9
Display Resolution 1366 X 768
Pixel Pitch 0.1460mm×0.4365mm
Peak Brightness 550(nits)
Contract Ratio 1000:1, Typical (1/100 White Window, Dark Room)
View Angle Hor. And Vert. ≥170 degree
Color Deeps 16.7M Color (R / G/ B each 256 Scales)
PC Resolution Supporting VGA, SVGA, XGA,WXGA
HDTV Compatible 480p / 720p / 1080i
Progressive Scanning Yes
Film Mode Pull Down Yes
“GAMMA” Correction Yes
Color Temperature Control Yes
Comb Filter Yes
Second De-interlace for Sub picture No
Wide Mode Full,Fill Aspect Ratio,Nonliner,LB to 16:9,
LB subtitles to 16:9 or Anamorphic
TV System NTSC M
Dual Tuner System No
AV Input Color System PAL /NTSC
PIP Basic mode (video on graphic mode,resolution≥1024×768)
1.2 AUDIO SECTION
Audio Output Power 6W×2 Max.(8 ohm)
Sound Effect NO
Tone Control Yes
1.3 Input Terminals D-Sub 15 Pin Type(Analog-RGB Input ) ×1
D-Sub 9 Pin (RS-233 Input ) ×1
Component Video-YPbPr/YCbCr ×2 RCA Terminals
S-Video Input (Mini Din 4Pin) ×1
Video Input RCA Terminals
Y / Pb / Pr, Y / Cb / Cr (RCA Type) ×2
Stereo Audio Input for YPbPr / YCbCr x 2
(3.5mm Phone Type) ×1
1.4 Output Terminals Audio Output (RCA ; L&R Type) ×1
1.5 Others
Closed Caption / V-Chip Yes
Teletext No
OSD Language English, FranÇais, Español
Revision :0
Date : 2005.8.1
Page : P. 3 of 8
Stereo Decode MTS with SAP

Power Rating AC 100-240V, 50/60Hz
Power Consumption 200W
1.6 Support the Signal Mode

This machine can support the different from VGA signal mode in 19 kinds
No Resolution Horizontal Vertical Dot Clock
Frequency(Hz) Frequency(KHz) Frequency(MHz)
1) 640×480 31.50 60.00 25.18
2) 640×480 35.00 67.00 30.24
3) 640×480 37.50 75.00 31.50
4) 640×480 37.86 72.81 31.50
5) 720×400 31.47 70.08 28.32
6) 800×600 35.16 56.25 36.00
7) 800×600 37.90 60.32 40.00
8) 800×600 46.90 75.00 49.50
9) 800×600 48.08 72.19 50.00
10) 832×624 49.00 75.00 57.27
11) 1024×768 48.40 60.00 65.00
12) 1024×768 56.50 70.00 75.00
13) 1024×768 60.00 75.00 78.75
14) 1152×864 63.86 70.02 94.51
15) 1152×864 67.52 75.02 108.03
16) 1280×960 60.02 60.02 108.04
17) 1280×1024 64.00 60.01 108.00
1.7 HDTV Mode (YPbPr)

No Resolution Horizontal Vertical Dot Clock
Frequency(KHz) Frequency(Hz) Frequency(MHz)
1) 480i 15.734 59.94 13.50

2) 480p(720×480) 31.468 59.94 27.00
3) 576p(720×576) 31.25 50.00 27.00
4) 720p(1280×720) 37.50 50.00 74.25
5) 720p(1280×720) 45.00 60.00 74.25
6) 1080i(1920×1080) 33.75 60.00 74.25
Revision :0
Date : 2005.8.1
Page : P. 4 of 8
2. LCD local control button Main power : push switch
Channel +/- volume up/down menu input. standby : soft touch
3. Led indicators : Power on: Green
Standby: Red
4. OSD language English, FranÇais, Español
5. OSD Full on screen display
6. Remote control unit
Customer Remote
Code: 609F(NEC)
1 POWER button
2 MUTE button
3 0-9 DIGITAL button
4 PIP button
5 SOURCE button
6 PIP SIZE button
7 PIP POS button
8 VOL +/- button
9 CH +/- button
10 MTS button
11 UP/DOWN,LEFT/RIGHT
ENTER buttons
12 SYSTEM button
13 MENU button
14 V-CHIP button
15 CCD button
16 FREEZE button
17 DISPLAY buttons
18 FAVORITE button
19 ADD/ERASE buttons
20 SOUND button
21 PIC SIZE button
22 P.MODE button
23 ZOOM button
24 RECALL button
25 SLEEP button
E7501-051001
7. Safety standard UL/FCC/cUL

8. EMC standard 15 Parts of the FCC rules,CLASS B
9. Performance standard LCD-TV Standard
10. Accessories Battery 2pcs
User Manual 1pcs
AC Cable 1pcs
Remote Control 1pcs
The Accessories box 1pcs
Revision :0
Date : 2005.8.1
Page : P. 5 of 8
Technical Data
1. Chassis MICO
2. Power supply TV AC 100-240 V, 50/60Hz
Remote controller Battery 3V (UM-4/R03/AAA×2)
3. TV system RF input NTSC M
Video input PAL/NTSC 3.58/NTSC 4.43
4. Receiving channels TV VHF-L : 2~6CH
VHF-H : 7~13CH
UHF : 14~69CH
CATV 1~125CH
5. Intermediate Picture 45.75MHz
frequencies
6 . Scanning Horizontal (Hz) 15625/15750
Vertical (Hz) 50/60
7 . AC plug UL Plug
8. Panel V270B1-L01
9. Speaker Internal 8 ohm 10W (max) ×2
10.Operating Fulfill all specifications 15°C ~ 30°C
temperature
Accept picture/sound 5°C ~ 33°C
reproduction
11. Operating relative Fulfill all specifications 45% ~ 75%
humidity
Accept picture/sound 20% ~ 80%
reproduction
12. Electrical & See the attachment 1.
optical
specification
13. Circuit diagram LC26HAB
drawing No.
15. Cabinet
16. Cabinet color
17. Packing 1 set per
18. Container stuffing RD/05/P/LC26HAB/CSI/02 REV: 01
method
19. Dimension (mm) LCD-TV 883(W) × 468(H) × 110(D)mm (w/o Stand)
(No packing) 883(W) × 523(H) × 250(D)mm (with Stand)
Remote control unit 183(L) × 53(W) ×28(T)mm
20. Net weight LCD-TV 14.1Kg (with Stand) approx.
Remote controller 70g (approx.)
21. Cell Defect Subject to Panel supplier specification
Revision :0
Date : 2005.8.1
Page : P. 6 of 8
Attachment 1：Electrical & Optical Specification
No. Items Instruction Typical Limit Unit
1 Video sensitivity For 30dB S/N 44 ≤51 dBuV
2 FM sound sensitivity For 30dB S/N 21 ≤35 dBuV
3 Color sensitivity For RF transmission 37 ≤40 dBuV
4 CCD sensitivity TV screen refreshes 40 times 43 ≤50 dBuV
number of mistakes≤8
5 Minimum NICAM threshold Without crackline noise N/A N/A dBuV
6 Stereo Channel Separation BTSC. 18 ≥15 dB
7 AGC static characteristic Accept. Picture/Sound repr. 90 ≥90 dBuV

8 Selectivity Adjacent sound carrier 30 ≥28
Below adjacent sound carrier 30 ≥30 dB
Adjacent picture carrier 45 ≥40
Up adjacent picture carrier 40 ≥30
9 IF rejection 55 ≥45 dB
10 Image rejection VHF 57 ≥45 dB
UHF 55 ≥40
11 AFT pull-in range ±1.0 ≥⏐±1.0⏐ MHz
12 Chroma sync pull-in range ±500 ≥⏐±200⏐ Hz
13 Color killer function -11 ≤-10 dB
14 Resolution RF Horizontal PAL 300 ≥300 Lines
NTSC 260 ≥240 Lines
Vertical PAL 410 ≥400 Lines
NTSC 320 ≥300 Lines
Video Horizontal 450 ≥450 Lines
Vertical 400 ≥400 Lines
15 Color White XW Full Pattern 0.295 0.295±0.02

Coordination YW 0.300 0.300±0.02
16 View Horizontal 170 ≥170 Degree
Angle(Lo/3) Vertical
17 Overscan Cross hatch signal 96 94~98 %
18 Picture position In all direction ±2 ≤⏐±3⏐ mm
19 H sync pull-in range ±400 ≥⏐±200⏐ Hz
20 V sync pull-in range 6 ≥6 Hz
21 Audio frequency response ±3dB ref. to 1KHz 0.15~12 0.2~12 KHz
Revision :0
Date : 2005.8.1
Page : P. 7 of 8
22 Max Audio Output Power 7×2 ≥5.0×2 W
23 Audio output power 1KHz 10% THD 6×2 ≥4.0×2 W

10% THD
24 THD Po=0.5W 0.5 ≤3 %
25 Signal to buzz ratio coeighting 50 ≥30 dB
26 Minimum volume hum coeighting 6 ≤10 mVrms
27 Maximum woofer output power N/A N/A W
28 Woofer audio frequency ±3dB ref. to 15Hz AV N/A N/A Hz
response mode
29 Tone low frequency 100Hz ref. to 1KHz ±8 ≥⏐±3⏐ dB
AV mode
30 Tone high frequency 10KHz ref. to 1KHz ±8 ≥⏐±3⏐ dB
AV mode
31 Balance Center 0 ≤⏐±2⏐
Max. 3 >2 dB
Min. -35 ≤-30
32 Video input level 1.0 1±0.3 Vpp

33 Audio input level*（1） 1.0 * 0.5±0.3 Vrms
34 Video output level N/A N/A Vrms
35 Audio output level*（2） 0.3 * 0.5±0.3 Vrms
36 AV Audio input max. level 2 ≤2 Vrms
37 AV Audio output L/R 35 ≥30 dB
Separation
38 Power consumpution Operating 200 ≤200 W
Stand by 3 ≤5 W
39 IR receiving distance 0 Degree 7 ≥6 m
40 IR receiving left/right 5m 60 ≥45 Degree
angle Up/down 20 ≥15 Degree
41 Dielectric strength DC 3KV 1min. 5 ≤10 mArms
42 The vibration noise from The distance between No obvious vibration noise can be
electromagnetic devices in LCD- the tester and the heard
TV set LCD-TV set is four
times as many as the
screen height
Revision :0
Date : 2005.8.1
Page : P. 8of 8
Test Condition
All tests shall be performed under the following conditions unless otherwise specified
1 Picture Modulation 87.5%
2 Sound Modulation 27KHz Dev. For DK/I/BG
15KHz Dev. For M/N
3 Picture to Sound Ratio 10dB
4 Sound Artificial Load 8 ohm
Resistor
5 Video signal Stair and Special
6 Audio signal 1KHz sine wave 0.5Vrms
7 Other conditions:
A. Switch LCD-TV on and let it warm up for more than 30 minutes.
Viewing distance: 3H (H: Panel High) in front of LCD, about 2M.
Ambient light: ≤0.1 cd/ m2
B. Brightness, Contrast, Saturation, Tint, sharpness set at normal.
C. Connect RMS volt meter to speaker terminals and adjust the LCD volume to get 500mW RMS
power at each terminals.
D. With image sticking protection of LCD module. The luminance will descend by time on a same
still screen and rapidly go down in 5 minutes, when measuring the color tracking and luminance
of a same still screen, be sure to accomplish the measurement in one minute to ensure its
accuracy.
E. Due to the structure of LCD module. The extra-high-bright same screen should not hold over 5
minutes for fear of branding on the panel.
F. RF test point: Video output.
8 Note:
*(1) Now this project cannot fit the limited spec. the typical audio input level is 1.0 Vrms,
*(2) The audio out level is controlled by the volume level, the range is from 0 to 0.5Vrms.
A B C D E
4 4
Flash
LVDS SIGNAL
IR
Keypad LVDS SIGNAL LVDS PANEL
TV
Tuner
3 3
AV1
S_Video
GPIO
Backlight
GPIO
Y1PbPr
YPbPr
MT8205 AOSDATA1 COD_VOUTR
Y2PbPr MUX
DACBCLK
DACMCLK Audio Board Speaker
DACLRC
WM8776 COD_VOUTL
VGA
DOUT
VGA_L/R
S1_AV1_L/R
2 2
Y1PbPr_L/R
Y2PbPr_L/R
DDR1 DDR2
1 1
A B C D E
A B C D E
MT8205P1V3.2 Rev History P# Date
V0.1 1.FIRST VERSION 2004/11/29

MT8205E (PBGA388) LCDTV BOARD 4 LAYERS V0.2 1. 2.5V use 5VSB conversion. All 0402 change to 0603
2005/03/09
2. LED_RED/GRN CIRCUIT CHANGE

3. Change Power on/off circuit(ORO7 CTRL PIN)
1. INDEX 4. WM8776 DVDD Needed
5. Del the Si9936 LVDS Parts
4 2. LDO 6. Del DVI&AD9883 PARTS
4
3. MT8205E PBGA388
4. MT8205 ANALOG DECOUPLING
5. MT8205 DIGITAL DECOUPLING
6. ICE I/F
7. DDR MEMORY & FLASH
8. DVI INPUT
9. AD9883
10. VGA IN & PC AUDIO IN
11. VIDEO IN & TUNER I/O J24
VCC 5VSB
12. AUDIO / VIDEO IN CIRCUIT 1

2 R359
3 +12V 10k
13. WM8776 AUDIO CODEC 4
5
J6
ORO7 High :POWER OFF
6 5 SYS_PWR ORO7 LOW :POWER ON
14. LVDS / CRT / TTL OUT 7
8
4
3
5VSB Q14
TXD
TXD 3
2
R364 RXD
3 2 3
15 BACK LIGHT / KEYPAD DIP8/P2.0
1 1 ORO7
RXD 3
SOT23/SMD 4.7k SCL

16. READER CARD I/F 5x1 W/HOUSING 2N3904 SDA
SCL 6,9,11,13
3
DIP5/W/H/P2.0 SDA 6,9,11,13
TO Power BD
5VSB
+12V
24V +12V 2
J108
INVERTER_PWR
UP3_0 BLACKLIGHT ON/OFF 1
2 + CE16 TUNER_12V
MUTE<-->UP1_5 220uF/16v TUNER_12V 11
3
4 C220UF16V/D6H11
5 ORO7
ORO7 3
6
PWR_GND
8x1 W/HOUSING MUTE
UP1_5 6
DIP8/W/H/P2.54
HOLE/GND
H1
9 9 2 2
8 8 3 3
7 7 4 4
6 6 5 5
1
1
DV33A
+12V For Tuner

2 2
HOLE/GND
H2 L14
9 2 R51 R52 TUNER_12V
8
7
9
8
2
3 3
4
10k 10k J2
FB
FOR Tuner
7 4 + CE93 BEAD/SMD/0805 + CE17
6 6 5 5 1
RxD 2 220uF/16v 47uF/16v CB11
1
TxD 3 C220UF16V/D6H11 0.1uF

4
1
RS-232 4x1 W/HOUSING

DIP4/W/H/P2.0
HOLE/GND HOLE/GND
H3 H5
9 9 2 2 9 9 2 2
8 3 8 3 5VSB
8 3 8 3 P5
7 7 4 4 7 7 4 4
6 5 6 5 CONNECTOR DB9 5VSB
6 5 6 5 RSRXD SYSTEM EEPROM
1
1
6 U6
RSTXD R53 R54
1
2 13 R1IN R1OUT 12
7 8 9 10k 10k
R2IN R2OUT CB75 U13
3 11 T1IN T1OUT 14
8 10 T2IN T2OUT 7 1 NC VCC 8
4 5VSB 0.1uF 2 7
C1 0.1uF TXD NC WP SCL
9 1 C+ TXD 3 NC SCL 6
5 3 4 5 SDA
HOLE/GND HOLE/GND C3 0.1uF C1- RXD GND SDA
H4 H6 4 C2+ VCC 16 RXD
5 C2- EEPROM 24C16
9 2 9 2 C6 0.1uF 2 C8
9 2 9 2 V+ 0.1uF SOP8/SMD
8 8 3 3 8 8 3 3 6 V- GND 15
7 4 7 4 C7 0.1uF
7 4 7 4
1 6 5 6 5 MAX232A 1
6 5 6 5
1
1
1
Title
LCD TV - MediaTek MT8205 Solution
AUIO IN/OUT GND ANALOG INPUT GND DIGITAL GND
Size Doc Number Rev
C INDEX V0.1
Date: Tuesday, May 10, 2005 Sheet 1 of 16
A B C D E
A B C D E
Power ON alive source
Vout
ADJ/GND
ADJ/GND
4
VCC U1 CM1117-3.3V U35 M1117-3.3V
4
DV33 5VSB
1
L8 L7
3 2 DV33 3 2
IN OUT IN OUT
FB CE6 FB
BEAD/SMD/0805 + BEAD/SMD/0805
+ CE4 + CE5 CB200 + CE118
220uF/16v CB4 220uF/16v CB5 220uF/16v 0.1uF 220uF/16v CB201
0.1uF SOT223/SMD 0.1uF SOT223/SMD 0.1uF
DV33A
Vout
DV33A
ADJ/GND
ADJ/GND
U5 CM1117-1.8V
DV18A
1
L6
U3 CM1117-3.3V
AV33
1
3 2 DV18A
L11 IN OUT
3 2 AV33 FB
IN OUT BEAD/SMD/0805
FB + CE11 + CE12
BEAD/SMD/0805 + CE10 100uF/16v CB7 220uF/16v CB8
220uF/16v C5 CB6 0.1uF SOT223/SMD 0.1uF
10uF/10v 0.1uF
SOT223/SMD
1.25x(1+300/680)=1.8V
3 1.25x(1+180/110)=3.3V 3
5VSB
+ CE128 + CE129
220uF/16v 220uF/16v CB212 CB213 CB214 CB215 CB216 CB217
0.1uF 0.1uF 0.1uF 3300pF 3300pF 3300pF
2
5V ==> +12v 2
VCC L9 +12V
L107 D2 L10 R325

R3 0 +12V
1 2
FB R0805/SMD DIODE SMD FB 0
1N4148/SMD
+ CE8 + CE107
100uF/16v CHOKE-100uH L18W10H18
C100UF16V/D6H11 R5 L/CHOKE/DIP/1810 R6 100uF/25v/NC
13k C2
10 270pF
R0805/SMD
U2 + CE7
8 SOIC8 1 100uF/16v
DRC SWC
7 Ipk SWE 2
6 VCC TC 3
5 CII GND 4
R8
1.5k
AZ34063A-PWM
C4
100pF
1 1
Title
Size Doc Number Rev
C LDO V0.1
A B C D E
A B C D E
VI[0..23]
VI[0..23] 9
XTALI DVIODCK
XTALI 4 DVIODCK 8,9
XTALO DV33A DVIDE
XTALO 4 DVIDE 8,9
DVIHSYNC
DVIHSYNC 8,9
DVIVSYNC
ANALOGVDD
ANALOGVDD
DVIVSYNC 8,9
GND
GND
DVISCL
ADCPLLVDD1
ANALOGVDD
APLL_CAP
VGAVSYNC#
VGAHSYNC#
ADCPLLVDD
DVISCL 8
ADCVDD0
ADCVDD0
ADCVDD0
ADCVDD0
ADCVDD0
APLLVDD
GND
DVIODCK
DV18A
D5 R18 DVISDA
VGASOG
DV18A
GREEN+
GREEN-
CVBS2+
CVBS1+
CVBS0+
DVISDA 8
CVBS2-
CVBS1-
CVBS0-
XTALO
1N4148/SMD 10k
BLUE+
VOCM
BLUE-
XTALI
AVCM
RED+
VICM
RED-
GND
GND
GND
GND
GND
GND
GND
SOY
GND
SC+
CB+
VI10
VI11
VI12
VI13
VI14
VI15
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
CR+
SY+
SC-
CB-
CR-
SY-
VI0
VI1
VI2
VI3
VI4
VI5
VI6
VI7
VI8
VI9
Y+
GND
GND
GND
GND
URST# URST# 6,15
Y-
URST# A_DQS[0..3] A_DQS[0..3] 7
U7 A_RA[0..11] A_RA[0..11] 7
M13
M14
M15
M16
N13
D10
D11
C11
D13
C10
D12
C12
C13
C14
N14
D14
D15
C15
D16
C16
D18
D17
C17
C18
C19
D19
C20
D20
C21
D21
C22
D22
C23
D23
B10
A10
B11
A11
B12
A12
B13
A13
B14
A14
B15
A15
A16
B16
A17
B17
A18
B18
E23
A19
B19
A20
B20
A21
B21
A22
B22
A23
B23
L12
L13
L14
L15
L16
D5
C4
C5
D6
C6
D7
C7
C8
D9
C9
D8
A_BA[0..1] A_BA[0..1] 7
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
B8
A8
B9
A9
ANALOGVDD A_DQM[0..1] A_DQM[0..1] 7
ANALOGVDD 4 SW1
A_DQ[0..31] A_DQ[0..31] 7
AVCM
VOCM
VICM
SOG
CVBS2N
CVBS2P
CVBS1N
CVBS1P
CVBS0N
CVBS0P
SCN
SCP
SYN
SYP
CRN
CRP
CBN
CBP
YN
YP
SOY
RN
RP
GN
GP
BN
BP
VSYNC
XTALO
HSYNC
DVSS
DVDD
DMPLLVDD
ADCPLLVDD
ADCPLLVSS
SYSPLLVSS
SYSPLLVDD
TESTP
TESTN
XTALVDD
XTALI
XTALVSS
APLL_CAP
APLLVDD
VFEVSS1
ADCVDD0
ADCVSS0
REFP0
REFN0
ADCVDD1
ADCVSS1
REFP1
REFN1
VFEVDD0
VFEVSS0
ADCVDD2
ADCVSS2
REFP2
REFN2
MON0
MON1
ADCVDD3
ADCVSS3
APLLVSS
REFP3
VI18
VI19
VI20
VI21
VI22
VI23
VCLK_DVI
REFN3
ADCPLLVSS1
DMPLLVSS
VI0
VI1
VI2
VI3
VI4
VI5
VI6
ADCPLLVDD1
DVDD18
VI7
VI8
VI9
VI10
VI11
DVSS3
VI12
VI13
VI14
VI15
VI16
VI17
DVSS18
4 4
A_CLK A_CLK 7
2=4
2 4
ADCVDD 1 3 + CE21 A_CLK# A_CLK# 7
ADCVDD 4 10uF/25v
1=3
A_CKE A_CKE 7
ADCVDD0 C3 C24 DVIDE SW4P/DIP/FLAT A_CS# A_CS# 7
ADCVDD0 VFEVDD1 DE_DVI DVIVSYNC A_RAS# A_RAS# 7
D3 ADCVDD4 VSYNC_DVI D24
APLLVDD MPX1 C1 A24 DVIHSYNC A_CAS# A_CAS# 7
APLLVDD 4 SIF HSYNC_DVI
MPX2 C2 Y24 DV18A A_WE# A_WE# 7
GND AF DVDD18 AOSDATA0 SDV25 SDV25 7
L11 ADCVSS4 AOSDATA0 A25
VREFP4 D1 A26 AOSDATA1 VREF VREF 7
VPLLVDD VREFN4 REFP4 AOSDATA1 AOSDATA2
VPLLVDD 4 D2 REFN4 AOSDATA2 B26
GND F2 F23 DV33A IOWR#
ADCVSS DVDD3I IOWR# 6
D4 B25 AOSDATA3 IOCE#
ADIN4 AOSDATA3 IOCE# 6
E1 B24 DOUT GND
ADCPLLVDD1 ADIN3 LIN DACBCLK FCLK FCLK 16
ADCPLLVDD1 4 E2 ADIN2 AOBCK C26
E3 C25 DACLRC FCMD FCMD 16
ADIN1 AOLRCK DACMCLK FDAT FDAT 16
E4 ADIN0 AOMCLK E24
ADCVDD F1 N15 GND
ADCPLLVDD PWM2VREF ADCVDD DVSS3 A_DQ24 8205UP1_[2..7]
ADCPLLVDD 4 F4 PWM2VREF DQ24 G26 8205UP1_[2..7] 6
AUXTOP F3 G25 A_DQ25
AUXBOTTOM AUXVTOP DQ25 A_DQ26
G3 AUXVBOTTOM DQ26 F26 DV33A
GND J3 F24 SDV25 F_A[8..21] F_A[8..21] 6,7
AUXTOP VPLLVDD VPLLVSS DVDD2 A_DQ27 F_D[0..7] F_D[0..7] 6,7
AUXTOP 4 G4 VPLLVDD DQ27 F25
AUXBOTTOM VPLLVDD H3 E26 A_DQ28
AUXBOTTOM 4 DLLVDD DQ28
GND K3 N16 GND F_OE# F_OE# 7
REXTA GND DLLVSS DVSS2 A_DQ29
REXTA 4 K4 BGVSS DQ29 E25
REXTA J4 G24 SDV25 R365
APLL_CAP VPLLVDD REXTA DVDD2 A_DQ30 47k 8205UP3_0
APLL_CAP 4 H4 BGVDD DQ30 D26 8205UP3_0 6
LVDDA L3 D25 A_DQ31 8205UP3_1
LVDDA DQ31 8205UP3_1 6
AP7 G2 H25 A_DQS3 ICE
A7P DQS3 ICE 6
AN7 G1 H26 A_DQM1
CLK2+ A7N DQM1 GND DACBCLK
H2 CLK2P DVSS18 P14
PWM2VREF CLK2- H1 J25 A_DQS2
PWM2VREF 4 CLK2N DQS2
GND M12 J26 A_DQ23
AP6 LVSSA DQ23 A_DQ22 MPX1
J2 A6P DQ22 K25 MPX1 12
AN6 J1 P16 GND MPX2
A6N DVSS2 MPX2 12
AP5 K2 K26 A_DQ21
AN5 A5P DQ21 A_DQ20 ORO[0..7] ORO[0..7] 11,13,16
K1 A5N DQ20 L25
3 ADCVDD0 LVDDA L4 AA24 DV18A OGO[0..7] OGO[0..7] 8,11 3
ADCVDD0 4 LVDDB DVDD18
AP4 L2 L26 A_DQ19
AN4 A4P DQ19 SDV25 OBO[0..7] OBO[0..7] 15
L1 A4N DVDD2 H24
AP3 M2 M25 A_DQ18
AN3 A3P DQ18 A_DQ17
M1 A3N DQ17 M26
GND M11 N25 A_DQ16
AVCM CLK1+ LVSSB DQ16 A_RA4 VSYNC VSYNC 14
AVCM 4 N2 CLK1P RA4 J23
CLK1- N1 R16 GND HSYNC HSYNC 14
VOCM AP2 CLK1N DVSS2 A_RA5
VOCM 4 P2 A2P RA5 J24
VICM AN2 P1 K23 A_RA6
VICM 4 A2N RA6
LVDDA M3 K24 A_RA7
LVDDC RA7
MT8205
AP1 R2 L23 A_RA8 VGASDA VGASDA 10
AN1 A1P RA8 GND VGASCL VGASCL 10
R1 A1N DVSS18 R14
AP0 T2 L24 A_RA9
AN0 A0P RA9 A_RA11 RED+ RED+ 12
T1 A0N RA11 M23
GND N12 N26 A_CKE RED- RED- 12
DACVDD LVSSC CKE SDV25 GREEN+ GREEN+ 12
N3 DACVDDC DVDD2 H23
DACVREF M4 P26 A_CLK GREEN- GREEN- 12
DACFS VREF RCLK A_CLK# BLUE+ BLUE+ 12
N4 FS RCLKB P25
GND N11 P15 GND BLUE- BLUE- 12
SVM DACVSSC DVSS2 A_RA3
T4 SVM RA3 M24
DACVDD P3 N23 A_RA2 VGASOG VGASOG 12
GND DACVDDB RA2 A_RA1
R3 DACVSSB RA1 N24
DACVDD P4 R26 A_RA0
VREFP4 G DACVDDA RA0 A_RA10 VGAHSYNC# VGAHSYNC# 10
VREFP4 4 U4 G RA10 P24
VREFN4 GND R4 P23 A_BA1 VGAVSYNC# VGAVSYNC# 10
VREFN4 4 DACVSSA BA1
B U3 U23 SDV25
R B DVDD2I DV18A CVBS0+ CVBS0+ 12
V4 R DVDD18 AA23
DACFS T3 R24 A_BA0 CVBS0- CVBS0- 12
DACFS 4 DE BA0
VSYNC U1 R23 A_CS# SY+ SY+ 12
DACVREF HSYNC VSYNCO RCS# A_RAS# SY- SY- 12
DACVREF 4 U2 HSYNCO RAS# T24
V1 R15 GND SC+ SC+ 12
VCLK DVSS2 A_CAS# SC- SC- 12
V2 EBO7 CAS# T23
DACVDD V3 U24 A_WE# Y+ Y+ 12
DACVDD 4 EBO6 RWE#
W1 W26 A_DQ8 Y- Y- 12
EBO5 DQ8 A_DQ9 CB+ CB+ 12
W2 EBO4 DQ9 V25
DV33A AC9 V26 A_DQ10 CB- CB- 12
LVDDA DVDD3I DQ10 SDV25 CR+ CR+ 12
2 LVDDA 4 W3 EBO3 DVDD2 V23 2
W4 U25 A_DQ11 CR- CR- 12
EBO2 DQ11 GND
Y1 EBO1 DVSS18 T13
Y2 U26 A_DQ12 AP[0..7] AP[0..7] 14
EBO0 DQ12 A_DQ13 AN[0..7] AN[0..7] 14
Y3 EGO7 DQ13 T25
GND P11 T15 GND
DVSS18 DVSS2 A_DQ14 CLK1+ CLK1+ 14
Y4 EGO6 DQ14 T26
AA1 R25 A_DQ15 CLK1- CLK1- 14
EGO5 DQ15 A_DQS1 CLK2+ CLK2+ 14
AA2 EGO4 DQS1 W25
AA3 W23 GND CLK2- CLK2- 14
EGO3 AVSS18 DV18A
AA4 EGO2 AVDD18 Y23
AB1 G23 VREF
EGO1 RVREF GND SCL SCL 1,6,9,11,13
AB2 EGO0 DVSS18 T16
IR AB3 Y26 A_DQM0 SDA SDA 1,6,9,11,13
IR 15 ERO7 DQM0
AB4 Y25 A_DQS0
ERO6 DQS0 A_DQ7
AC1 ERO5 DQ7 AA26
DV18A AC18 V24 SDV25 DACBCLK DACBCLK 6,13
DVDD18 DVDD2 A_DQ6 DACMCLK DACMCLK 13
AC2 ERO4 DQ6 AA25
AC3 AB26 A_DQ5 DACLRC DACLRC 13
ERO3 DQ5 GND AOSDATA3 AOSDATA3 6,13
AC4 ERO2 DVSS2 T14
GND R11 AB25 A_DQ4 HWSCL DOUT DOUT 13
DVSS3 DQ4 HWSCL 6
AD1 AC26 A_DQ3
ERO1 DQ3 SDV25 AOSDATA0 AOSDATA0 6,13
AD2 ERO0 DVDD2 W24
OBO7 AD3 AC25 A_DQ2 HWSDA AOSDATA1 AOSDATA1 6,13
OBO7 DQ2 HWSDA 6
OBO6 AD4 AD26 A_DQ1 AOSDATA2 AOSDATA2 6,13
OBO5 OBO6 DQ1 A_DQ0 SOY SOY 11
AE1 OBO5 DQ0 AD25
TXD
TXD 1
AD18DVDD18
AC19DVDD18
AD19DVDD18
AE22 FCICMD
T11 DVSS18
P12 DVSS18
T12 DVSS18
P13 DVSS18
AF8 HIGHA7
AE9 HIGHA6
AF9 HIGHA5
AE10 HIGHA4
AF10 HIGHA3
AC11HIGHA2
AD11HIGHA1
AF12 HIGHA0
RXD CVBS1+ CVBS1+ 12

AC10DVDD3I
AF23 FCIDAT
AF22 FCICLK
AD9 DVDD3
AD10DVDD3
R12 DVSS3
R13 DVSS3
AC12IOWR#
AC21PRST#
RXD 1
AF15 IOOE#
AE23 GPIO0
AC14IOCS#
AD23PWM0
AC23PWM1
AE17 IOALE
AE4 OGO7
AF4 OGO6
AC5 OGO5
AD5 OGO4
AE5 OGO3
AF5 OGO2
AC6 OGO1
AD6 OGO0
AE12 IOA18
AD12IOA19
AE11 IOA20
AF11 IOA21
AE6 ORO7
AF6 ORO6
AC7 ORO5
AD7 ORO4
AE7 ORO3
AF7 ORO2
AC8 ORO1
AD8 ORO0
AE2 OBO4
AF1 OBO3
AF2 OBO2
AE3 OBO1
AF3 OBO0
AF19 INT0#
AE26 SDA0
AB24 SDA1
CVBS1- CVBS1- 12
AF26 SCL0
AB23 SCL1
AE19 UP12
AF20 UP13
AE20 UP14
AD20UP15
AC20UP16
AF21 UP17
AE21 UP30
AD21UP31
AD22UP34
AC22UP35
AD17IOA0
AD14IOA1
AE14 IOA2
AF14 IOA3
AF13 IOA4
AE13 IOA5
AD13IOA6
AC13IOA7
AF18 WR#
AE24 RXD
AE25 SDA
AD24TXD
AE18 RD#
AE15 AD0
AD15AD1
AC15AD2
AF16 AD3
AE16 AD4
AD16AD5
AC16AD6
AF17 AD7
AF25 SCL
AE8 A16
AC17A17
AC24ICE
CVBS2+ CVBS2+ 12
AF24 IR
IOA[0..7] CVBS2- CVBS2- 12
IOA[0..7] 6
SVM
SVM 14
8205UP3_4
8205UP3_4 6
R
8205UP1_2
8205UP1_3
8205UP1_4
8205UP1_5
8205UP1_6
8205UP1_7
8205UP3_0
8205UP3_1
8205UP3_4
8205UP3_5
R 14
BGA388/SOCKET 8205UP3_5 G
VGASDA
VGASCL
DVISDA
8205UP3_5 6 G 14
DVISCL
HWSCL
HWSDA
MT8205 B
URST#
IOWR#
F_OE#
IOCE#
PWM0
PWM1
FCMD
OGO7
OGO6
OGO5
OGO4
OGO3
OGO2
OGO1
OGO0
F_A15
F_A14
F_A13
F_A12
F_A11
F_A10
F_A16
F_A17
F_A18
F_A19
F_A20
F_A21
ORO7
ORO6
ORO5
ORO4
ORO3
ORO2
ORO1
ORO0
OBO4
OBO3
OBO2
OBO1
OBO0
B 14
FCLK
FDAT
F_A9
F_A8
GPIO
F_D0
F_D1
F_D2
F_D3
F_D4
F_D5
F_D6
F_D7
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
DV33A
DV18A
DV18A
DV33A
DV33A
DV18A
TxD
RxD
ICE
IR
GND
GND
GND
GND
GND
GND
1 GPIO 1
GPIO 14
PWM0
PWM0 13
PWM1
PWM1 13
DV33A DV18A
Title
DV33A DV18A
Size Doc Number Rev
C MT5205BGA388 V0.1
A B C D E
A B C D E
MT8205 ANALOG DECOUPLING

R20
DACVREF
DACVREF 3
DACFS 100k
DV18A
DACFS 3 L17
DACVREF DACFS DV18A ADCPLLVDD1
Y1
FB C9 CB14
4 ADCPLLVDD1 C10 R21 XTALI XTALO BEAD/SMD/0603 4.7uF 0.1uF 4
ADCPLLVDD1 3
0.1uF/NC 560 C0603/SMD C0603/SMD
GND
FOR DACVDD C0603/SMD 27MHz
ADCPLLVDD GND GND C11 C12

ADCPLLVDD 3 33pF 33pF DEL
AV33
APLLVDD DV33A
APLLVDD 3 L18 L19
AV33 DACVDD GND ANALOGVDD
CE23 FB C13 CB15 FB C14 CB16

+ CB17 BEAD/SMD/0603 CE24 4.7uF 0.1uF BEAD/SMD/0603 4.7uF 0.1uF
ANALOGVDD + C0603/SMD C0603/SMD C15 C0603/SMD C0603/SMD
ANALOGVDD 3
10uF/25v 0.1uF GND 0.1uF GND
10uF/25v R22
DACVDD ADCPLLVDD
VPLLVDD
VPLLVDD 3
C16 CB18 33 C17 CB19
LVDDA 4.7uF 0.1uF + CE25 4.7uF 0.1uF
LVDDA 3 22uF/25v
C0603/SMD C0603/SMD C0603/SMD C0603/SMD
GND
GND
DACVDD
ADCVDD C18 CB20 APLL_CAP ANALOGVDD

ADCVDD 3
4.7uF 0.1uF
DACVDD C0603/SMD C0603/SMD C19 CB21
DACVDD 3
GND + CE78 4.7uF 0.1uF
C20 47uF/16v C0603/SMD C0603/SMD
1500pF
C0603/SMD GND
AVCM
FOR ADCVDD GND
AVCM 3
VOCM R23
3
VICM
VOCM
VICM
3
3
Note for Fix or Adj Regulator APLLVDD
3
33 C21 CB22
+ CE26 4.7uF 0.1uF
22uF/25v C0603/SMD C0603/SMD
ADJ/GND
GND
Vout
ANALOGVDD
VCC
U8 CM1117-3.3V
1
ADC_VDD AV33 C22 CB23

L28 L29 4.7uF 0.1uF
3 2 ADC_VDD AV33 LVDDA C0603/SMD C0603/SMD
VREFP4 IN OUT GND
VREFP4 3
VREFN4 FB FB CB24
VREFN4 3
BEAD/SMD/0805 CB25 CB26 BEAD/SMD/0603 0.1uF
+ CE27 + CE28 + CE29 CE30 C0603/SMD
ADCVDD0
ADCVDD0 3
100uF/16v CB27 220uF/16v 10uF/25v 0.1uF 0.1uF + GND
0.1uF SOT223/SMD C23
0.1uF 47uF/16v AV33
L30
PWM2VREF AZ1117 Rdown Rup GND LVDDA
AV33 VPLLVDD
PWM2VREF 3
CB28
Fix regulator 0 ohm OFF 0.1uF FB C24 CB29
1.25x(1+Rdown/Rup) C0603/SMD BEAD/SMD/0603 4.7uF 0.1uF
GND C0603/SMD C0603/SMD
AUXTOP
AUXTOP 3 Adj regulator 180 1% 110 1% 1.25x(1+180/110)=3.3V GND
AUXBOTTOM C25 + CE31
AUXBOTTOM 3 0.1uF 47uF/16v
LVDDA
VPLLVDD
REXTA CB30
REXTA 3
0.1uF C26 CB31
APLL_CAP C0603/SMD 4.7uF 0.1uF
APLL_CAP 3
GND C0603/SMD C0603/SMD
GND
XTALI
XTALI 3
XTALO
XTALO 3
2 VPLLVDD 2
ADC_VDD
C27 CB32
L32 4.7uF 0.1uF
ADC_VDD ADCVDD0 C0603/SMD C0603/SMD
AVCM GND
FB CB34
BEAD/SMD/0805 0.1uF
C0603/SMD
GND R27
CB36 REXTA GND
ADCVDD0 4.7uF
C0603/SMD 3.3k
CB38
0.1uF GND
C0603/SMD
GND
ADCVDD0
L37
CB39 VOCM ADCVDD0 ADCVDD
0.1uF
C0603/SMD FB TP3
GND C28 CB42
CB44 CB41 4.7uF 0.1uF R31
ADCVDD0 0.1uF 0.1uF C0603/SMD C0603/SMD LVDDA L38 FB AUXTOP
C0603/SMD
CB45 GND GND 50 TP4
0.1uF
C0603/SMD GND PWM2VREF R34
GND AUXBOTTOM
CB47
ADCVDD0 + CE32 0.1uF 50
47uF/16v C0603/SMD
CB48 VICM
0.1uF GND
C0603/SMD
GND
1 CB50 1
ADCVDD0 0.1uF
C0603/SMD
CB52
0.1uF
C0603/SMD GND
GND
ADCVDD0
CB54 VREFP4
0.1uF Title
C0603/SMD LCD TV - MediaTek MT8205 Solution
GND CB56
4.7uF Size Doc Number Rev
C0603/SMD C MT8205 DECOUPOMG--ANALOG V0.1
GND
CB58 Date: Tuesday, May 10, 2005 Sheet 4 of 16
4.7uF
A B C C0603/SMD D E
CB60
4.7uF
VREFN4 C0603/SMD
A B C D E
MT8205 DIGITAL POWER & DECOUPLING
4 4
DV33A
0603 PUT ON NEARLY BGA
DV18A
DV18A
0603 PUT ON NEARLY BGA

CB61
0603 CB62
PUT ON NEARLY BGA CB69 CB70 CB71 CB72
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C0603/SMD C0603/SMD C0603/SMD C0603/SMD
3 3
CB68 C29 C30 C31 C32 C33 C34

0.1uF 0.01uF 3300pF 3300pF 3300pF 3300pF 3300pF
C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD
2 2
1 1
Title
Size Doc Number Rev
B MT8205 DECOUPOMG--DIGITAL V0.1
A B C D E
A B C D E
ICE
4 4
SCL R311
SCL 1,9,11,13
SDA 1k
SDA 1,9,11,13
RN38
IOA0 7 8 A0
IOA[0..7] IOA1 5 6 A1
IOA[0..7] 3
IOA2 3 4 A2
IOA3 1 2 A3
ICE
ICE 3
0x4
RN39
IOA4 7 8 A4
IOA5 5 6 A5
IOA6 3 4 A6
IOWR# IOA7 1 2 A7
IOWR# 3
3 3
IOCE# 0x4
IOCE# 3
PWR#
PWR# 7
R314
IOWR# PWR#
PCE#
PCE# 7
0
R315
IOCE# PCE#
A[0..7]
A[0..7] 7
0
F_A[8..21] F_A[8..21] 3,7

RN40
8205UP3_0 7 8 UP3_0
UP1_2 8205UP3_1 5 6 UP3_1
UP1_2 15
UP1_6 8205UP3_4 3 4 UP3_4
UP1_6 11
UP1_3 8205UP3_5 1 2 UP3_5
UP1_3 11
UP3_1 0x4
UP3_1 15
2 UP1_4 RN41 2
UP1_4 1
8205UP1_2 7 8 UP1_2
UP1_5 8205UP1_3 5 6 UP1_3
UP1_5 1
8205UP1_4 3 4 UP1_4
UP3_0 8205UP1_5 1 2 UP1_5 MUTE
UP3_0 1
HWSCL 0x4
HWSCL 3
R313
HWSDA 8205UP1_6 UP1_6
HWSDA 3
0
8205UP3_0
REMOVE WHENR312
USE ICE MODE TP28
8205UP3_0 3
8205UP1_7 UP1_7
8205UP3_1
8205UP3_1 3
0
DEL TEST POINT DIP1.0
8205UP1_[2..7] TP/DIP/D1.0
8205UP1_[2..7] 3
8205UP3_4
8205UP3_4 3
UP3_4 FOR S/W SCL
8205UP3_5
8205UP3_5 3
1 UP3_5 FOR S/W SDA 1
HWSDA R300 R SDA
HWSCL R301 R SCL
Title
UP3_5 R302 0
Size Doc Number Rev
UP3_4 R303 0
B MT8205 DECOUPOMG--DIGITAL V0.1
A B C D E
A B C D E
SDV25 SDV25 U14

A1 25 29 F_D0
RN2 U15 D1V25 A2 A0 D0 F_D1
24 A1 D1 31
A_RA3 7 8 D_RA3 1 66 A3 23 33 F_D2
A_RA2 D_RA2 D_DQ0 VDD VSS D_DQ15 RN3 A4 A2 D2 F_D3
5 6 2 DQ0 DQ15 65 22 A3 D3 35
A_RA1 3 4 D_RA1 3 64 D_RA0 7 8 A5 21 38 F_D4
A_RA0 D_RA0 D_DQ1 VDDQ VSSQ D_DQ14 D_RA1 A6 A4 D4 F_D5
1 2 4 DQ1 DQ14 63 5 6 20 A5 D5 40
D_DQ2 5 62 D_DQ13 D_RA2 3 4 A7 19 42 F_D6
RN4 22x4 DQ2 DQ13 D_RA3 F_A8 A6 D6 F_D7
6 VSSQ VDDQ 61 1 2 18 A7 D7 44
4 A_RA4 7 8 D_RA4 D_DQ3 7 60 D_DQ12 F_A9 8 30 4
A_RA5 D_RA5 D_DQ4 DQ3 DQ12 D_DQ11 75x4 F_A10 A8 D8
5 6 8 DQ4 DQ11 59 7 A9 D9 32
A_RA6 3 4 D_RA6 9 58 RN5 F_A11 6 34 DV33A
A_RA7 D_RA7 D_DQ5 VDDQ VSSQ D_DQ10 D_RA4 F_A12 A10 D10
1 2 10 DQ5 DQ10 57 8 7 5 A11 D11 36
D_DQ6 11 56 D_DQ9 D_RA5 6 5 F_A13 4 39
RN6 22x4 DQ6 DQ9 D_RA6 F_A14 A12 D12 DV33A 5VSB
12 VSSQ VDDQ 55 4 3 3 A13 D13 41
A_RA8 7 8 D_RA8 D_DQ7 13 54 D_DQ8 D_RA7 2 1 DV33A F_A15 2 43 R55
A_RA9 D_RA9 DQ7 DQ8 F_A16 A14 D14 A0
5 6 14 NC NC 53 1 A15 D15 45
A_RA11 3 4 D_RA11 15 52 75x4 F_A17 48 16 F_A19
A_DQS[0..3] A_DQS[0..3] 3 D_DQS0 VDDQ VSSQ D_DQS1 RN7 F_A18 A16 A18 10k R56 R57
1 2 16 LDQS UDQS 51 17 A17 NC 13
A_RA[0..11] A_RA[0..11] 3 17 50 2 1 15 14 0 R
A_BA[0..1] A_BA[0..1] 3 22x4 NC NC VREF D_RA11 R58 F_A20 RY/BY WP/ACC
18 VDD VREF 49 4 3 9 A19 BYTE 47
A_DQM[0..1] A_DQM[0..1] 3 A_RA10 R59 22 D_RA10 19 48 D_RA9 6 5 F_A21 10
A_DQ[0..31] A_DQ[0..31] 3 D_DQM0 DNU VSS D_DQM0 CB76 D_RA8 PCE# A20 FLASHVCC
20 LDM UDM 47 8 7 26 CE VCC 37
D_WE# 21 46 D_CLK# 10k F_OE# 28 TSOP 48 pin
A_CLK A_CLK 3 RN8 D_CAS# WE CK D_CLK 75x4 PWR# OE
22 CAS CK 45 11 WE GND1 27
A_CLK# A_CLK# 3 A_DQ0 7 8 D_DQ0 D_RAS# 23 44 D_CKE 0.1uF 46 CB77
A_CKE A_CKE 3 A_DQ1 D_DQ1 D_CS# RAS CKE D_RA10 R60 75 GND2 0.1uF
5 6 24 CS NC 43 DV33A 12 RESET
A_CS# A_CS# 3 A_DQ2 3 4 D_DQ2 25 42
A_RAS# A_RAS# 3 A_DQ3 D_DQ3 D_BA0 NC A12 D_RA11
1 2 26 BA0 A11 41
A_CAS# A_CAS# 3 D_BA1 27 40 D_RA9 RN9 MX29LV160BT
A_WE# A_WE# 3 RN10 47x4 D_RA10 BA1 A9 D_RA8 D_DQ0
28 A10/AP A8 39 7 8
A_DQ4 7 8 D_DQ4 D_RA0 29 38 D_RA7 D_DQ1 5 6
A_DQ5 D_DQ5 D_RA1 A0 A7 D_RA6 D_DQ2 D1V25
5 6 30 A1 A6 37 3 4
SDV25 SDV25 3 A_DQ6 D_DQ6 D_RA2 D_RA5 D_DQ3
VREF VREF 3 A_DQ7
3 4
D_DQ7 D_RA3
31 A2 8M x 16 A5 36
D_RA4
1 2
D1V25
1 2 32 A3 DDR A4 35
33 34 75x4
RN11 47x4 VDD VSS RN12
A_DQ8 7 8 D_DQ8 M13L128168 8Mx16-6 D_DQ4 7 8
A_DQ9 5 6 D_DQ9 D_DQ5 5 6 CB78 CB79 CB80 CB81 CB82 CB83 CB84 CB85
A_DQ10 3 4 D_DQ10 D_DQ6 3 4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A_DQ11 1 2 D_DQ11 D_DQ7 1 2
RN13 47x4 75x4

A_DQ12 7 8 D_DQ12 RN14
A_DQ13 5 6 D_DQ13 D_DQ8 7 8
A_DQ14 3 4 D_DQ14 D_DQ9 5 6 D1V25
A_DQ15 1 2 D_DQ15 D_DQ10 3 4
3 D_DQ11 3
1 2
47x4
SDV25 SDV25 75x4 CB86 CB87 CB88 CB89 CB90 CB91 CB92 CB93
RN15 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RN16 U16 D_DQ12 7 8
A_DQ16 7 8 D_DQ16 1 66 D_DQ13 5 6
A_DQ17 D_DQ17 D_DQ16 VDD VSS D_DQ31 D_DQ14 3
5 6 2 DQ0 DQ15 65 4
A_DQ18 3 4 D_DQ18 3 VDDQ VSSQ 64 D_DQ15 1 2 NEW ADD
RWR# PWR# 6 A_DQ19 1 2 D_DQ19 D_DQ17 4 63 D_DQ30
D_DQ18 DQ1 DQ14 D_DQ29 75x4 D1V25
5 DQ2 DQ13 62
PCE# PCE# 6 RN17 47x4 6 61 RN18
A_DQ20 D_DQ20 D_DQ19 VSSQ VDDQ D_DQ28 D_DQ16 2
7 8 7 DQ3 DQ12 60 1
A_DQ21 5 6 D_DQ21 D_DQ20 8 59 D_DQ27 D_DQ17 4 3
A[0..7] A[0..7] 6 A_DQ22 D_DQ22 DQ4 DQ11 D_DQ18 6 CB94 CB95 CB96 CB97 CB98 CB99 CB100 CB101 CB102 CB103 CB104
3 4 9 VDDQ VSSQ 58 5
F_D[0..7] F_D[0..7] 3,6 A_DQ23 1 2 D_DQ23 D_DQ21 10 57 D_DQ26 D_DQ19 8 7 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
D_DQ22 DQ5 DQ10 D_DQ25
11 DQ6 DQ9 56
RN19 47x4 12 55 75x4
F_OE# F_OE# 3 A_DQ24 D_DQ24 D_DQ23 VSSQ VDDQ D_DQ24 RN20
7 8 13 DQ7 DQ8 54
A_DQ25 5 6 D_DQ25 14 53 D_DQ20 2 1
A_DQ26 D_DQ26 NC NC D_DQ21 4 D1V25
3 4 15 VDDQ VSSQ 52 3
A_DQ27 1 2 D_DQ27 D_DQS2 16 51 D_DQS3 D_DQ22 6 5
F_A[8..21] F_A[8..21] 3,6 LDQS UDQS D_DQ23 8
17 NC NC 50 7
RN21 47x4 18 49 VREF
A_DQ28 D_DQ28 VDD VREF 75x4 C40 C41 C42 C43 C44 C45 C46 C47
7 8 19 DNU VSS 48
A_DQ29 5 6 D_DQ29 D_DQM1 20 47 D_DQM1 CB105 RN22 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF
A_DQ30 D_DQ30 D_WE# LDM UDM D_CLK# D_DQ27 1
3 4 21 WE CK 46 2
A_DQ31 D_DQ31 D_CAS# D_CLK D_DQ26 3
Change to 47 ohm
1
47x4
2
D_RAS#
D_CS#
22
23
24
CAS
RAS
CK
CKE
45
44
43
D_CKE 0.1uF D_DQ25 5
D_DQ24 7
4
6
8 D1V25
CS NC
25 NC A12 42
D_BA0 26 41 D_RA11 75x4
A_DQS0 R61 47 D_DQS0 D_BA1 BA0 A11 D_RA9 RN23 + CE33 + CE34
27 BA1 A9 40
D_RA10 28 39 D_RA8 D_DQ31 1 2
A_DQS1 R62 47 D_DQS1 D_RA0 A10/AP A8 D_RA7 D_DQ30 3 270uF/16v OS-CON/NC 220uF/16v
29 A0 A7 38 4
D_RA1 30 37 D_RA6 D_DQ29 5 6 C270UF16V/D10H12
A_DQS2 R63 47 D_DQS2 D_RA2 A1 A6 D_RA5 D_DQ28 7
31 A2 8M x 16 A5 36 8
D_RA3 32 35 D_RA4
A_DQS3 R64 47 D_DQS3 A3 DDR A4 75x4
2 33 VDD VSS 34 2
RN24 SDV25
M13L128168 8Mx16-6/NC FOR ENTRY
D_RAS# 7 8
D_CS# 5 6 SDV25 SDV25
RN25 D_BA0 3 4
A_CS# 7 8 D_CS# D_BA1 1 2
A_RAS# 5 6 D_RAS#
A_CAS# 3 4 D_CAS# 75x4 CB106 CB107 CB108 CB109 CB110 CB111 CB112 CB113
A_WE# 1 2 D_WE# 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
22x4 D_DQS2 R65 75 DEL

A_BA1 R66 22 D_BA1
D_DQS3 R67 75
A_BA0 R68 22 D_BA0 R69 4.7k
D_CAS# R70 75 SDV25
A_DQM0 R71 22 D_DQM0 D1V25 U17 SDV25
A_DQM1 R73 22 D_DQM1

1
2
GND VTT 8
7
D_WE# R72 75 0402 PUT ON NEARLY
CB118
BGACB120
CB119 CB121
D1V25 SD PVIN D_DQM1 R74 75 CB114 CB115 CB116 CB117
3 VSENSE AVIN 6
A_CKE R75 22 D_CKE VREF 4 5 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
TP10 VREF VDDQ D_DQS1 R76 75 C0603/SMD C0603/SMD C0603/SMD C0603/SMD
A_CLK R77 22 D_CLK IC LP2996 DDR Termination SOP8 + CE35
47uF/16v D_DQS0 R78 75
A_CLK# R79 22 D_CLK#
CB122 CB123 + CE36 D_DQM0 R80 75 SDV25
220uF/16v
0.1uF 0.1uF
C48 C49 C50 C51 C52 C53 C54 C55

3300pF 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF
C0603/SMD C0603/SMD
SDV25
SDV25
ADJ/GND
1 CB125 CB126 CB127 CB128 CB129 CB130 CB131 CB124 1

CB132 CB133 CB134 CB135 CB136 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
VREF VREF DECOUPLING
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 5VSB U4 CM1117-2.5V
SDV25
1
VREF
3 2 SDV25
IN OUT
VREF
+ CE38 + CE39 + CE40
+ CE37
VREF 220uF/16v 220uF/16v 220uF/16v Title
+ CE41 SOT223/SMD 220uF/16v LCD TV - MediaTek MT8205 Solution
CB137 CB138 CB139 CB140 CB141 220uF/16v Size Doc Number Rev
C DDR MEMORY&FLASH V0.1
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A B C D E
A B C D E
VCC
4 D6 4
VGA_PLUGPWR
DIODE SMD
D19 1N4148/SMD
VGA_PLUGPWR VGA_PWR VGA_PLUGPWR
VGA_PLUGPWR
DIODE SMD
1N4148/SMD
CB157 R115 R116

U22 10k 10k
1 NC VCC 8
0.1uF 2 7
NC WP VGASCL VGA_IN_L
3 NC SCL 6 VGA_IN_L 13
4 5 VGASDA
GND SDA VGA_IN_R
VGA_IN_R 13
EEPROM 24C02 GND
P4
3 3
+
R 1 VGA_R CE100 10uF/25v R323 10k VGA_IN_R VGASDA
VGASDA 3
2
3 VGASCL
VGASCL 3
+
L 4 VGA_L CE101 10uF/25v R324 10k VGA_IN_L
PHONEJACK STEREO G
PHONEJACK/DIP HSYNC_VGA
VGAHSYNC# 3
K1
K2
K3
K4
K5
VSYNC_VGA
VGAVSYNC# 3
VGASDA R110 100 VGA_SDA

RED_GND
RED_GND 12
VGASCL R111 100 VGA_SCL GRN_GND
GRN_GND 12
2 BLU_GND 2
BLU_GND 12
RED
RED 12
GREEN
GREEN 12
P6 BLUE
BLUE 12
16
L98
D-SUB15 FEMALE
DSUB15/DIP/F VSYNC# VSYNC_VGA
11 1 RED FB
6 RED_GND BEAD/SMD/0603 R298
VGA_SDA 12 2 GREEN 2.2k C157
7 GRN_GND 5pF
HSYNC# 13 3 BLUE
8 BLU_GND
VSYNC# 14 4
VGA_PWR L99
9
VGA_SCL 15 5 HSYNC# HSYNC_VGA
10
FB
BEAD/SMD/0603 R299
1 2.2k C158 1
17
5pF
Title
Size Doc Number Rev
B VGA IN&PC AUDIO IN V0.1
A B C D E
A B C D E
CVBS0---TUNER1
CVBS1---FRONT BD AV_IN
CVBS2---AV BD (AV/S-V) IN
R40
Y SY_IN R41 0 SY
Y 12
Y_GND
Y_GND 12
TUNER_12V
AV , TUNER I/O 0 R42
75
TUNER_12V 1
CB
4
CB 12 4
CB_GND JP1
CB_GND 12 CON\SVHS
6
TU_VCC R43 0 SY_GND
CR J4 SC_IN 2 3 SY_IN
CR 12
TU_12V 1 4
CR_GND 1 FB6
CR_GND 12 2
3 7 5 0
SOY
SOY 3 4
SDA 5
SY SCL 6 R44
SY 12 7
SIF1_OUT SC_IN R45 0 SC
SY_GND AF1_OUT 8
SY_GND 12 9 0
TV_GND 10
SC TV 11 R46
SC 12 12
SC_GND
TU VCC FOR TUNER POWER USE CON12
75
SC_GND 12
OGO3
DIP12/P2.0 FOR AV SWITCH IO-1 R47 0 SC_GND
TV
CVBS0 12 ORO7 FOR TUNER SIF SELECT SWITCH IO-1
FB5
TV_GND
CVBS0_GND 12 OGO0 FOR TUNER SIF SELECT SWITCH IO-2 0
UP1_2 FOR POWER ON/OFF
OGO1 FOR TUNER BOARD PAL/NTSC SWITCH
CVBS1
CVBS1 12
VCC
L102
ORO7 FOR SYS_PWR
ORO6 FOR AUDIO 1st SWITCH IO-1
CVBS1_GND TU_VCC
CVBS1_GND 12
3
OGO5 FOR AUDIO 1st SWITCH IO-2 3
FB CE97
+ OGO6 FOR AUDIO 2nd SWITCH IO-1
CB197
RESERVER
1000uF/16v 0.1uF OGO2 FOR AUDIO 2nd SWITCH IO-2
OGO4 FOR AUDIO 2nd SWITCH IO-2
SIF1_OUT
SIF1_OUT 12
AF1_OUT
AF1_OUT 12
R17
SCL SOY1
SCL 1,6,9,13
TP20
TP21
TP24
TP25
TP27
TP6
TP7
TP8
TP9
SDA 0
SDA 1,6,9,13
R29
ORO6
OGO0
OGO1
OGO2
OGO4
OGO5
OGO6
R30 0 Y
OGO3
ORO7
TUNER_12V YPBPR 0 R32
75
L103
TU_12V
R33 0 Y_GND
HP_SENSE
FB + CE98
OGO0 1000uF/16v CB198
OGO0 3 0.1uF FB2
+
OGO1 R11
OGO1 3 0
2
0 2
OGO2 P2
OGO2 3
+
2 1
OGO3 3
OGO3 3
CE14 R35
OGO4 YPBPR1_L 10uF/25v 5 6 R36 0 CB
OGO4 3 TP5
4
OGO5 0
OGO5 3
YPBPR1_R CE15 8 9 R37
+
OGO6 10uF/25v 7 75
OGO6 3
ORO6 RCA1X3
ORO6 3 P1
+
R1 RCA5/9P/Y R19 0 CB_GND

ORO7 1 AV1_IN R7 0 CVBS1
ORO7 3
2
18 FB3
S1_AV1_L 3 CE9 S1_AV1_L R15
S1_AV1_L 11 0
4 10uF/25v 56
S1_AV1_R
S1_AV1_R 11
5 CE13 S1_AV1_R
YPBPR1_L 6 R16 0 CVBS1_GND R24
YPBPR1_L 11
YPBPR1_R 10uF/25v R25 0 CR
YPBPR1_R 11
RCA1X3
RCA3/6P/DIP FB1 0
R26
0 75
R28 0 CR_GND
1 1
S1_AV1_R
S1_AV1_L FB4
YPBPR1_R
YPBPR1_L 0
Title
R39 R38 R48 R49 LCD TV - MediaTek MT8205 Solution
100K 100K 100K 100K
Size Doc Number Rev
A3 VIDEO IN & TUNER IO V0.1
A B C D E
A B C D E
VGASOG
VGASOG 3
RED+ R338 C88
RED+ 3 R348 C94 Y R160 0 Y+
RED- CVBS0 R166 0 CVBS0+
RED- 3
100
4 22 47nF 4
GREEN+ 47nF R161 C162
GREEN+ 3 30pF
R168
GREEN- C168 NC
GREEN- 3 330pF
NC R339 C90
R349 C96 Y_GND Y-
BLUE+ CVBS0_GND CVBS0-
BLUE+ 3
100
BLUE- 0 47nF
BLUE- 3
47nF
R340 C91
CB+ CB R164 0 CB+
CB+ 3 R350 C98
CB- CVBS1 R170 0 CVBS1+ 100
CB- 3
47nF
CR+ 22 R165 C163
CR+ 3 10pF
47nF
CR- R172 NC
CR- 3
C169 R341 C93
Y+ NC 330pF CB_GND CB-
Y+ 3 R351 C100
Y- CVBS1_GND CVBS1- 100
Y- 3
47nF
0
SY+ 47nF
SY+ 3
R342 C95
SY- CR R167 0 CR+
SY- 3
R352 C89 100
SC+ CVBS2 R162 0 CVBS2+ 47nF
SC+ 3
R169 C164
SC- 22 10pF
SC- 3
47nF NC
R163 R343 C97
CVBS0+ C170 CR_GND CR-
CVBS0+ 3 330pF
NC
CVBS0- R353 C92 100
3 CVBS0- 3 3
CVBS2_GND CVBS2- 47nF
CVBS1+ 0
CVBS1+ 3 R354
47nF C99
CVBS1- SY R171 0 SY+
CVBS1- 3
22
CVBS2+ 47nF
CVBS2+ 3
FROM Tuner
+
R173
CVBS2- C171
CVBS2- 3 330pF
NC
R355 C101
SY_GND SY-
OUTPUT
MPX1 CE116 0
MPX1 3
47nF
MPX2
MPX2 3
47uF/16v /NC R356 C102
SC R174 0 SC+
C104
SIF1_OUT R176 0 R344 0 MPX1 22
47nF
R175
47nF C172
Y C106 C165 NC 330pF
Y 11 15pF/NC 15pF/NC R357 C103
Y_GND
Y_GND 11 AF Path SC_GND SC-
+
CB C166 0
CB 11
47nF
CB_GND
CB_GND 11
CR 47nF/NC
CR 11
CR_GND CE62
CR_GND 11 L55
AF1_OUT R333 39k R332 39k MPX2 C105
2 SOY RED RED_IN R178 100 RED+ 2
SOY 3,11
47uF/16v FB R179
SY C160 C161 BEAD/SMD/0603 47nF
SY 11 15pF 15pF 75 C107
SY_GND 5pF
SY_GND 11
C108
SC RED_GND R180 100 RED-
SC 11
SC_GND
SC_GND 11
L104 47nF
FB C109
R183 0 VGASOG
4.7nF
CVBS0
CVBS0 11 L57 C111
CVBS0_GND GREEN GREEN_IN R185 100 GREEN+
CVBS0_GND 11
FB
CVBS1 BEAD/SMD/0603 47nF
CVBS1 11
R186 C112
CVBS1_GND 5pF
CVBS1_GND 11
75
C113
CVBS2 GRN_GND GRN_GND R187 100 GREEN-
CVBS2 11
CVBS2_GND
CVBS2_GND 11
L106 47nF
SIF1_OUT FB
SIF1_OUT 11
AF1_OUT
AF1_OUT 11
L59 C114
RED BLUE BLUE_IN R191 100 BLUE+
1 RED 10 1
GREEN FB
GREEN 10
BEAD/SMD/0603 47nF
BLUE R195 C115
BLUE 10 5pF
75
INPUT
RED_GND
RED_GND 10
C116
BLU_GND R199 100 BLUE-
GRN_GND
GRN_GND 10
BLU_GND L105 47nF
BLU_GND 10 Title
FB LCD TV - MediaTek MT8205 Solution
Size Doc Number Rev
C AUDIO/VIDEO IN CIRCUIT V0.1
A B C D E
A B C D E
Del Parts
VCC
L61
HPVDD
VGA_IN_L FB
VGA_IN_L 10
TP17 C117
VGA_IN_R DVI_R R212 0 + CB161
VGA_IN_R 10 0.1uF SCL R213 100 SCL14
5k
5k
TP18 DVI_L R214 0 10uF/25v
+
4 SDA R215 100 SDA14 4
S1_AV1_L
S1_AV1_L 10
+
VGA_IN_R R216 0
S1_AV1_R
S1_AV1_R 10
VGA_IN_L R217 0
R219
R220
+
S1_AV1_R CE108 10uF/25v R218 10k
+
S1_AV1_L CE109 10uF/25v R221 10k HPVDD
48
47
46
45
44
43
42
41
40
39
38
37
AIN2R
AIN3R
AIN4R
AIN5R
AINOPR
AINVGR
AGND
AIN3L
AIN4L
AIN5L
AINOPL
AINVGL
Del Parts
TP16 YPBPR1_R CE110 10uF/25v R222 10k
+
SCL SCL 1,6,9,11 TP15 YPBPR1_L CE111 10uF/25v R223 10k
+
SDA SDA 1,6,9,11 + CE63
10uF/25v CB163
ORO3 ORO3 TP30 U28 0.1uF
ORO3 3
ORO4 ORO4 TP31
ORO4 3
+
ORO5 TP13 S2_AV2_R CE112 10uF/25v R224 10k
ORO5 3
ORO5
+
TP32 S2_AV2_L CE113 10uF/25v R225 10k 1 36 HPVDD
MUTE TP2 AIN2L AVDD ADCREFP ADCREFP
UP1_5 1,6 2 AIN1R ADCREFP 35
3 AIN1L ADCREFGND 34
DACBCLK 4 33 VMIDADC VMIDADC
DACBCLK DACBCLK 3,6 DACMCLK DACBCLK VMIDADC AUXL CE64 10uF/25v + CE65
5 DACMCLK AUXL 32 TP22
DACMCLK DACMCLK 3 AOSDATA1 6 31 AUXR 10uF/25v CB165
HPOUTR
ADCLRC
HPOUTL
DIN AUXR
HPGND
0.1uF
HPVDD
DACLRC DACLRC 3 DACLRC 7 30 HPVDD CE66 10uF/25v + CE67
MODE
DGND
DVDD
DACLRC DACREFP TP23 10uF/25v CB166
8 ZFLAGR DACREFN 29
NC
CE
0.1uF
CL
DOUT DOUT 3 9 VMIDDAC
DI
ZFLAGL VMIDDAC 28
DACBCLK 10 27 COD_VOUTR
DACMCLK ADCBCLK VOUTR COD_VOUTL
11 26
13
14
15
16
17
18
19
20
21
22
23
24
AOSDATA0 AOSDATA0 3,6 GND DOUT ADCMCLK VOUTL + CE68
12 DOUT NC 25
AOSDATA1 AOSDATA1 3,6 10uF/25v CB167
+
AOSDATA2 AOSDATA2 3,6 0.1uF
HPVDD
SDA14
SCL14
AOSDATA3 AOSDATA3 3,6
DACLRC
DVDD
3 3
PWM1 DACLRC WM8776

PWM1 3
CE69
R226 COD_VOUTR AUSPR
DV33 1k
L63 DVDD 10uF/25V R227
DV33 DVDD
10k
+
CODHPOUTR
FB
PWM0 + CE74 TWO WIRE SERIAL CONTROL DEVICE ADDRESS 0x34h
CODHPOUTL
PWM0 3 47uF/16v CB170
0.1uF
TP29
PWM1 CE71
COD_VOUTL AUSPL
10uF/25v R229
10k
VCC WMVDD
L62
+
VCC WMVDD
FB
+ CE70
J3 47uF/16v CB168 R228
0.1uF WMVDD WMVREFP
AUSPR CE73
1
AUSPL 2 560 CODHPOUTR HPOUTR
3 + CE115
MUST USE SHIELD CABLE
MUTE 220uF/16v CB169
4
0.1uF 220uF/16v R230
2 47k 2
+
TO AUDIO BD
4x1 W/HOUSING
DIP4/W/H/P2.0
GND
CE75
CODHPOUTL HPOUTL
28
5
DVDD WMVDD 220uF/16v R233
DVDD
AVDD
47k
U29
17 WMVREFP
DACMCLK R231 33 SACLK VREFP
2 MCLK
DACBCLK R232 33 SBCLK 3
DACLRC R234 33 SLRCK BCLK
4 LRCLK
VREFN 16
AOSDATA0 R362 33 7
AOSDATA3 R363 33 DATA0
8 DATA1
AOSDATA2 R361 33 9 21 AUAVL TP14
DATA2 VOUT1L AUAVR TP12
VOUT1R 22
23 AULS TP11
VOUT2L AULR
VOUT2R 24
DVDD TP19
ORO3 10 25 AUCEN TP26
DNC VOUT3L AUSUB TP42
VOUT3R 26
ML 11
MC ML/I2S
12
DGND
AGND
R238 MD MC/IWL
13 MD/DM
1 0 VMID 1
VMID 18
14
27
MUTE
6
+ CE77
MODE 1 20 10uF/25v CB171
MODE NC 0.1uF
NC 19
15 PCM/DSD
R240
R R241 R242 R243 Wolfson-WM8766/8796 ADAC
C173 SSOP28/SMD
0.1uF 0 0 0 Title
Hardware Mode -> 24-bit Right Justified. LCD TV - MediaTek MT8205 Solution
Size Doc Number Rev
C WM8776/WM8766/AUDIO CODEC V0.1
A B C D E
A B C D E
LVDS OUT
J8
4 4
AN0 1
AP0 2
AN1 3
AP1 4
AN2 5
AP2 6
7
CLK1- 8
CLK1+ 9
AN3 10
AP3 11
AN4 12
AP4 13
14
AN5 15
AP5 16
17
AN6 18
AP6 19
CLK2- 20
CLK2+ 21
+12V VCC AN7 22
3 AP7 23 3
24
25
26
JP2 F1 27
L3
28
1 2 LVDS LVDSVDD LVDSVDD 29
3 4 30
FB
2x2 BEAD/SMD/0805 4A/?v
JP2X2/DIP/P2.54 FUSE/DIP/P10.0 + CE86 FI-SE30P-HF
330uF/25v LVDS/30P/P1.25/S
C330UF25V/D8H14 + CE87 + CE88
220uF/16v 220uF/16v CB185 CB186
0.1uF 0.1uF
R277
GPIO
CRT OUT
2k L75
R RED_OUT
R278 0.082uH
L/IND/SMD/0603
CLK1+ 75 1% C149 C150
CLK1+ 3
2 CLK1- J9 2
CLK1- 3
33pF 33pF
CLK2+ GND 1
CLK2+ 3
CLK2- RED_OUT 2
CLK2- 3
GRN_OUT 3
BLU_OUT 4
AP[0..7] AP[0..7] 3 SVM 5
AN[0..7] AN[0..7] 3 HSYNC 6
VSYNC 7
L76 R366 8
R G GRN_OUT
R 3
G 75
G 3
B R279 0.082uH GND
B 3
SVM L/IND/SMD/0603
SVM 3
VSYNC 75 1% C151 C152
VSYNC 3
HSYNC 8x1 W/HOUSING
HSYNC 3 33pF 33pF DIP8/W/H/P2.54
GND
GPIO
GPIO 3
1 1
L78
B BLU_OUT
R281 0.082uH
Title
L/IND/SMD/0603
75 1% C154 C155 LCD TV - MediaTek MT8205 Solution
Size Doc Number Rev
33pF 33pF
GND B LVDS/CRT OUT V0.1
A B C D E
A B C D E
PANEL INVERTER POWER

UP1_2
UP1_2 6
UP3_1
UP3_1 6,8
4 4
OBO0
OBO0 3
Inverter_PWR Inverter_PWR
OBO1
OBO1 3
OBO2
OBO2 3 FOR CHI-MEI INVERTER
+ CE1 + CE2 + CE3 CB1 CB2
OBO3 470uF/50v 470uF/50v 470uF/50v 0.1uF 0.1uF CONNECTOR
OBO3 3
URST# URST# 3,6 OBO4 PWR_GND
OBO4 3
OBO5
OBO5 3
IR
IR 3
OBO6
OBO6 3 VCC
R. ANGLE
OBO7 J10
OBO7 3
Inverter_PWR 1
R336 0 2
UP3_0 3
UP3_0 6
4
R285 5
2
PWM0 10k 6
PWM0 3
TP1 7
8
9
VCC SELECT Hi For External
3
R286 10
Dimming 11
12 SELECT Low For Internal
R288 100k
PWM0 1
Back
2N3904Light circuit
Q12 CB190
0.1uF VCC 12x1 W/HOUSING R.A
R289
R
SOT23/SMD R50 DIP12/WH/P2.0/R
2
4.7k 0
R291 SELECT
10k
3
R290
3 KEYPAD - MAX 8-KEYS 0 3
BL_ON/OFF
R293
UP3_0 1 Q13
2N3904
4.7k SOT23/SMD
J12
R. ANGLE
1 J11
OBO0 L81 FB TV/AV 2
OBO1 L82 FB MENU 3 Inverter_PWR 1
5VSB OBO2 L83 FB VOL- 4 2
POWER OBO3
ON/OFF L84 FB VOL+ 5 3
OBO4 L85 FB CH- 6 4
2
OBO5 L86 FB CH+ 7 5

R2 510 IR 8 6
LED_RED 9 7
2
R14 R13 R4 510 LED_GRN 10 8

3
10K 10K UP1_2 11 9

R0603/SMD R0603/SMD 12 10
R81 0
DV33A
3
R9 4.7K PWR_GND
OBO6 1 Q1 12x1 W/HOUSING 10x1 W/HOUSING R.A.
2N3906 DIP12/W/H/P2.0 DIP10/WH/P2.0/R
R10
OBO7 4.7K 1 Q2
2N3906
5VSB IR & POWER
R57 0 ON LED L89
FB
L90
FB
DV33A BEAD/SMD/1206 BEAD/SMD/1206
2 2
1 1
Title
Size Doc Number Rev
C BACK_LIGHT/KEYPAD V0.1
A B C D E
1 2 3 4 5 6
TUNER1 IN P# Date
ADDRESS
TUNER1
TUNER IF
C2 86
FQ1236 / : NTSC TV AV , TUNER I/O
TU1
D FQ1236-MK3 D
TU_VCC
1J1
TU_12V
1
2nd SIF OUT

2
VS_TUNER
3
AF /MPX
4
GND1
GND2
GND3
GND4
VS_IF
CVBS
AF-R
AF-L
SDA
5
SCL
NC
NC
NC
NC
AS
SDA
6
SCL
1R1 7
SIF1_OUT
8
1
TU_CVBS 1 2 1R21 20 TV AF1_OUT
10
11
12
13
14
TH1
TH2
TH3
TH4
1
2
3
4
5
6
7
8
9
9
18 1R3 10
TV_GND
56 11
TV
12
1
CON12
M1 M2
1R41 20 TV_GND
12
GNDS GNDS FB1 9 2 9 2
9 2 9 2
GNDS 8 3 8 3
FB2
0 8 3 8 3
VCC 7 4 7 4
7 4 7 4
6 5 6 5
2
0 6 5 6 5
NC
NC
TU_SCL
2
TU_SDA GNDS GND HOLE GND HOLE
1
SIF1_IN TU_CVBS
GNDS
AF1_IN
GNDS GNDS
C C
SIF_12V
1R5 100 TUNER1 SIF1 BPF
TU_SCL 1 2
SCL NTSC 4.5MHz　PAL 6MHz
1R6
1
100
TU_SDA 1 2
SDA 1R7 1R8
1.8K 1k
1C1 10nF
2
1 2 SIF1
22
1C2 1C3 1C4 10nF 1R9 0 1C5 22pF/27pF 1L2 47uH/22uH 1C6 10nF
47pF 47pF SIF1_IN 1 2 1 2 1 2 1 2 1 2 1 1Q1
2N3904
1
1
2
31
1C7 1L3 1C8 1L4 TU_VCC VCC
1R10 1R11 1L5 FB
820pF/560pF 1.5uH/1.2uH 820pF/560pF 1.5uH/1.2uH 220 10 1 2
1
1
1
CE4 CE5
+ CE3 CB3 + + CB4 CB5
2
12
100uF/16V 0.1uF 0.1uF 0.1uF
1
2
GND V GND V 100uF/16V 100uF/16V
2
GND V GND V 1R12 1C9 + CE6
2
71.5 NC 10uF/25v
GNDS
2
GNDS
2
GND V GND V GND V GND V
B B
TU_12V SIF_12V
1L6 FB
CE7
1 2 1 2
+
AF1_IN AF1 TU_12V SIF_12V
1
33uF/16V
+ CE8 CB6 + CE9 CB7

100uF/16V 0.1uF 220uF/16V 0.1uF
2
2
2
AF1 1R14
1 02 AF1_OUT
AF1_OUT
GNDS GND V
SIF1 1R15
1 02 SIF1_OUT TU_12V
SIF1_OUT TU_12V
SIF1_IN 1R16
1 0/NC
2 SIF1_OUT
TU_VCC
TU_VCC
GNDV GNDS
GND V GNDS
AUDIO GROUND VIDEO GROUND
A A
1 2 3 4 5 6
1 2 3 4 5 6
C1
2 1
22pF NPO
2 5% 1
D R1 D
82K +24V
R2
+24V
1
1 2
1
1
5%
1
R11 + 100K
5%
C10
2
R10 10K C12 R5 C5 +
10K 100NF 100UF/25V 100K 4.7uF C7 C4
5%
5%
C14 NPO X5R C6 1UF 100UF/25V
2
22UF/16V 4.7nF 100NF
2
2
X7R
U2A C8 U1 FILM
1
X7R
3 1 2 1 8 C38
+ C3 R3 PIN PGND L5 10uH
1 1 2 2 5% 1 2 7 1 2 1 2
OUT NIN SW
+
R12
AUSPL C20 2 R47 21 R66 21 R67 11 22 1UF 10K 3 6
- AGND VPP 1000UF/25V
2
1
RC4558 X5R C9
10UF 1K8 4K7 4K7 10K 5%
5% 5% 5% 4 5 1 2
C54 C55 EN BS
1
R6
1n 1n R7
1
R4 AGND 1UF 10
5% ATA-120
100K 2 1 X5R R8 R9 D1 C11
5%
MUTEC 5%
22
C24 10 10K MBRS130LTR 470NF
1
5%
5%
10K C15
21
C16
2
22pF
C 2.2UF D2 C17 C
100NF
1 R15 47K 2 6.2V 390PF
1
X7R
NPO
5%
2
C21
2 1
22pF NPO
2 5% 1
R14
82K +24V
+24V R16
1 2
1
1
5%
5%
1
R36 R17 100K
2
R37 10K 100K C27 +
10K 4.7uF C29 C25
5%
C19 NPO X5R C28 100UF/25V

5%
1UF
2
22UF/16V 4.7nF 100NF
2
2
B X7R B
U2B C30 U3
1
X7R
5 1 2 1 8 C39
+ C31 R18 PIN PGND L6 10uH
5%
7 1 22 1 2 7 1 2 1 2
OUT NIN SW
+
R39
AUSPR C40 2 R33 21 R45 21 R46 1 1 26 1UF 10K 3 6
- AGND VPP 1000UF/25V
2
1
RC4558 X5R C32
10UF 1K8 4K7 4K7 10K 5%
5% 5% 5% 4 5 1 2
EN BS
1
R19 R20
R21
C52 C53 1UF C33 10
100K
1n 1n
AGND ATA-120
2 1 X5R R22 R23 D3 470NF
5%
5% MUTEC 5%
22
C41 10 10K MBRS130LTR FILM
1
C34
5%
5%
2
10K
21
NS C35
2
22pF
D4 C36 100NF
1 47K 2 6.2V 390PF
1
X7R
R38 NPO
5%
2
A
A A
Title
Size Number Revision

B
Date: 2-Sep-2005 Sheet of
File: D:\正在进行的项目\LCD TV\LCD TV.DdbDrawn By:
1 2 3 4 5 6
1 2 3 4 5 6
R24
2 3K 1 MUTEC
1
5%
2
R25
5%
10K C37
1UF
+24V
1
X5R
D Q1 Q3 D
D6 2N3906 R40 Q2
2 10K 1 2N3904 2 R29 1 MUTE
1
1K
1N4148 5%
+ R41
5% 2N3904
C42 5%
10K
100UF/25V
2
R42
AGND 1k
AGND AGND AGND
D10
D8 NC LOUT
1N4148 D7 Q5
4.7V 2 R34 1 2N3904
1K 5%
R43
0R
C Q4 AGND C
D5 2N3906
1
MUTEB
NC +
C18
ROUT
NC
2
R28 Q6
1k R35
AGND 1 2 2N3904
1K 5%
R30
1
22k
D9 +
C51
AGND
220UF/25V
R54 10K R55 10K 1N4148
2
1
1 2 1 2
+24V
5% 5%
AGND
C22 C2 C13 Q7
100U/35V 100N NC
U5A MUTE
2
22U/16V 3
+
B B
1 C26 2 R13 1
OUT
2
R48 1k8 R49 4K7 R50 4K7 R51 10K 5%
C60 1K
AUSPL 2 1 1 2 1 2 1 2 1 2 2 10U/16V R65
- R27
2
47K
5% 5% 5% 5% NC
5%
10UF RC4558
X5R 5%
R53 C45 C46
100K 1n 1n 1 C49 2 AGND
1
R52 22K 22P AGND

2
J10
1 2 AGND LOUT
1
5%
ROUT
1 R62 10K 2 1 R63 10K 2 rca2

+24V
5% 5%
C44
U5B
22U/16V 5
+ C43
7 2 R26 1
OUT
2
R56 1k8 R57 4K7 R58 4K7 R59 10K 5%

C59 1K
AUSPR 2 1 1 2 1 2 1 2 1 2 6 10U/16V R61
-
2
47K
5% 5% 5% 5%
5%
10UF RC4558
A X5R 5% A
R60 C47 C48
100K 1n 1n Title
1
1 C50 2 AGND
2
R64 22K 22P AGND

1
1 2 Size Number Revision

5% B
Date: 2-Sep-2005 Sheet of
File: D:\正在进行的项目\LCD TV\LCD TV.DdbDrawn By:
1 2 3 4 5 6
1 2 3 4 5 6
D1 C11
1KV 470P
STTH3L06
D3 R21
NTC1 V_BUKE
1 L3 2 V_BUKE 100R 2W L4 10UH
400UH 12 +24V
3
PQ32-20
4 STTH8R06 2.5R R15
D5
R20 4A
R4 R13 +24V4A ?? 100R 2W
1KV 4700P
1.8M 1
F1 L1 L2 750K 2 10
10mH 10mH 1.6M
1
R8 11
D L R6 C6 C14 C15 C16 C17 C18 C19 D
250VAC 5A R14
R2
1.6M C1 68K 25V 1U
36K R16 +12V C12
R5 750K C10 1KV 470P 0.1U
CX2 4 2 C5 1.8M 8 R23
35V 470U
35V 1000U
35V 1000U
R1
35V 470U
CX1
35V 470U
1.6M 680NF C8 5 9
470R/1W
0.33 D2 68K 6
1.6M
1
$0.28
1UF 630V
0.33U Q1 R19 TR1 +24V1A
1 2 BD1 STBR608
N 8 R11 C9
450V 100UF
1N4148 ??
450V 100UF
ZCD
INV
GND COMP
VCC 7
STP20NM50
PQ3220
3
C2 7 R17 12
CY1 CY2 L6562 U1 GD 8.2K
C3 10R 100K
R3 R7 +24V4A
35V 22U
250V1000P 250V1000P 3
CS
MULT
1 C13
20K C4 2 10
100NF R12 11 1KV 470P
4
10NF R18 D4
R9 R10 C7
1.6K 20K +12V R22
0.33R 0.33R STTH310 100R 2W 10UH
10N
8 L5
5 9 D7 +12V
6 R37 2A
TR2 +24V1A ?? 100R 2W
Q2 ?? 7
BC337 R25 PQ3220 C30 C31 C32 C33 R42 C35 C36
20R R30 GND C29
R36
25V 1000U
25V 470U
25V 470U
470R/1W
25V 470U
25V 1000U
22R Q4 1KV 470P 0.1U
OPEN
STP12NK80
R24 D6 1N4148
R27 $0.45
1
10K 5.6K
15
SYNC
DC
VC
VCC
DCL R32
C20 OUT
10 C27
11 R46
50V 22UF PGND
L5991 M1 10R R40 R44
OPEN
12 R33 33.2K
SGND 30K
COMP
1.2K
VREF
STBY
13
VFB
RCT
ISEN
C 14 C
SS
1
DIS 1K
Q3 R26
BC327 R39 U3B
C34
16
6
6.8K 1K
R29 R41 0.1UF
R35
LCD-TV 200W SMPS SPEC: C25 R34
2
5.6K 22K
0.47R 3W
C24
0.47R 3W
C26
3.3N
U2
1. +5V 4A 8.2N
R28 220PF C28 TL431 R43 R45
2. +5VS 1A (Standby 5V) 1KV 470P 75K 2.7K
15K
3. +12V 2A
4
R31 R38
4.+24V 4A C22
100R 2W L6 10UH
C23
5. +24VA 1A C21
0.1UF 50V 2.2U
4.7K D8 +24VA
U3A
??
R60 1A
3.3NF
PC817 100R 2W
3
C46
C47 C48 C49 C50 C51

Q6
R52 1K R62 0.1U
25V 470U
BC327 1KV 470P
25V 1000U
25V 1000U
25V 470U
SHORT CIRCUIT PROTECTION 470R/1W
L8
D11 1N4148
L
R54 43K CY3
C38 C40
R51 250V 2200P
R53
120K 50V 4.7U AGND
10NF 130K
AGND
B B
J1
+5V
1
+5V
2
+5V
3 R59 R61
GND
4
GND V_BUKE
GND
5 2.0K 4.7K
1
6
+12V
+12V
7 R50 +12V ZD2 BZX79C12RL
8 R47 C37 TR3 R55 R58 U4B
C39 1 1KV 472P R64
1000V 10nF 47K/1W PC817
PH-2.0 30K 10nF 14
10R 2W C42 56K
13 L7 10UH R63 Q8 4.7K
D10 2 12 R56 0.01R +5VS +24V
1K
2
FER107 1A
J2 R48 D12 ?? 25V 2200U ZD1 27V
R57 0.01R
MMBT3906
+5VS 3 C41 C43 C44
1 Q5 30K
+5VS FER104 10 C45
GND
2 BC327 R49 10R D9 4 9 16V 2200U 16V 2200U Q7 D13
3 25V 470U
GND 8
ON/OFF
4
5
BC337
5 R66 1N4148
FER104 R78
PH2.0 C53 U5 R67 10R D14
10K C52 35V 47U Q13
6
Vstr
1
6 EC28卧式 Q9
STP22NF0 +5V 4.7K
MMBT3904
J3 Drain ?? Q12
+24V
5
NC 4A
1 22NF C58 R76 R77 BC337 R79
+24V
2 R65 4 $0.60 C57 4.7K 10K C59
+24V
3
Vfb
2 16V 470U 100N 4.7K
GND 10K GND
4 3 100N
GND
5
Vcc R80 47K
GND R68 R69 R73 +12V
6 FSDM0565 1K 1.2K 470R/1W 4.7K
4
PH2.5 R74
ZD3 U6
C54 C55
U4A 22V 0.1U Q10
35V 47U R70 1.2K R71
PC817
J4 5.6K BC337 ON
A +24VA PC817B C56 A
1
+24VA 47nF
3
2
GND STBY
3 U7
GND
4 Q11 R75 4.7K ON/OFF
TL431
PH2.0 R72 BC337
5.6K
Title
LCD-TV 200W SMPS Sch
Size Number Revision
Orcad C Ver1.0
Date: 3-Jun-2005 Sheet of 1/1
File:
1 2 3 4 5 6
Basic Operations & Circuit Description
Main Electric Components

(1). MODULE:
There are 1 pc. panel and 2 pcs. PCB including 1 pc. INVERTER
board(L), 1 pc. T-CONTROL board,
(2).SIGNAL PROCESS
There are 4 pcs. PCBs including
1 pc. Audio&Tuner board,

1 pc. Main digital board,
1 pc. Keypad board,
1 pc. Remote Control Receiver board,
(3).POWER
There are 1 pc. PCB for power.
PCB function
1. Power:
(1). Input voltage: AC 100V~240V, 47Hz~63Hz.
Input range: AC 90V(Min)~264V(Max) auto regulation.
(2). To provide power for PCBs.
a). +24V for Inverter.
b). +5Vsb for standby,
c). +5V for signal power,
d). +24V for Audio Amp power and converter to
e). +12V for Tuner power.
2. Main (Video InterFace) board:

(1).Decoder the video signal (TV,CVBS,S-VIDEO) from analog to digital
signal.
(2).Converter the Video signals( TV,CVBS,S-VIDEO ) and graphics signal
(VGA,YPbPr) from internace to progressive,
(3). Converter the Digital to fit the panel display mode and output the LVDS
signal to Panel.
3. Tuner & Audio Board:

(1)Convert TV RF signal to video and audio signal to Main board.
(2 ). Decoder the TV SIF signal to audio signal,
(3 ). Converter the audio to audio Ampifile and out put to the speaker.
4. KEYBOARD
To get the main button control on LCD_TV as SOURCE,MENU,
CHANEL +,CHANEL -, VOL +,VOL-, STANDBY functions.
5. Remote control board

Receive the remote signal and active for the control.
6. T-CONTROL board
Converter the LVDS signal to the digital signal for fitting the PANEL.
7. INVERTER board
Converter the low DC voltage +24V to high AC voltage to drive the backlight.
PCB failure analysis
1. CONTROL:
a. Abnormal noise on screen.
b. No picture.
2. MAIN (VIDEO):
a. Lacking color, Bad color scale.
b. No voice.
c. No picture but with signals output, OSD and back light.
d. Abnormal noise on screen.
3. POWER:
No picture, no power output.
Basic operation of LCD-TV

1. After turning on power switch, power board sends 5Vst-by Volt to Micro
Processor IC waiting for ON signals from Key Switch or Remote Receiver.
2. When the ON signal from Key Switch or Remote Receiver is detected, Micro
Processor will send ON Control signals to Power. Then Power sends (5Vsc,
12Vsc, 24V and RLY ON, Vs ON) to PCBs working. This time VIF will send
signals to display back light, OSD on the panel and start to search available
signal sources. If the audio signals input, them will be amplified by Audio AMP
and transmitted to Speakers.
3. If some abnormal signals are detected (for example: over volts, over current,
over temperature and under volts), the system will be shut down by Power off.
LCD basic display theory.
When an electrical field is applied to the LC planes, the LC molecules re-align
themselves so that they are parallel to the electrical field. This electrical process
is known as twisted nematic field effect or TNFE. In this alignment, polarized
light is not twisted as it passes through the LC material (see Diagram 3A and
3B). If the front polarizer is oriented perpendicular to the rear polarizer, light will
pass through the energized display but will be blocked by the rear polarizer. An
LCD in this form is acting as a light shutter.
Displays with variable characters are created by selectively etching away the
conductive surface that was originally deposited on the glass. Etched areas
become the display’s background; unetched areas become the display’s
characters.
Diagram 3A. The “off” state of a TN LCD-the LC molecules form a twist and therefore
cause polarized light to twist as it passes through.
Diagram 3B. The “on” state-the electrical field re-aligns the LC molecules so they do
not twist the polarized light.
Disassembly
In case of trouble, etc., Necessitating disassemble, please disassemble in the order shown in the
illustrations.
Reassemble in the reverse order.
1. Removal of the Back Cover
2. Removal of the MAIN PCB

a. Remove the screws.
b . Slide out the LCD chassis slightly; pull up the connector of AC cord from PCB; pull up the
LCD PCB from LCD.
c . Remove the Anode cap from Thepicture tube. To avaid a shock hazard, be sure to discharge
d . Take out the LCD chassis.
IC DESCRIPTION
-MT8205G
-AT24C02
-MX29LV160BBTC
-LP2996
-AZ1117/H
-WM8776
-MX232A
-ISAV330
AE1
AD4
AD3
AD2
AD1
R11
AC4
AC3
AC2
AC18
AC1
AB4
AB3
AB2
AB1
AA4
AA3
AA2
AA1
Y4
P11
Y3
Y2
Y1
W4
W3
AC9
W2
W1
V3
V2
V1
U2
U1
T3
V4
U3
R4
U4
P4
R3
P3
T4
N11
N4
M4
N3
N12
T1
T2
R1
R2
M3
P1
P2
N1
N2
M11
M1
M2
L1
L2
L4
K1
K2
J1
J2
M12
H1
H2
G1
G2
L3
H4
J4
K4
K3
H3
G4
J3
G3
F3
F4
F1
E4
E3
E2
E1
D4
F2
D2
D1
L11
C2
C1
D3
C3
B
R
G
AF
FS
DE
SIF
A0P
A1P
A2P
A3P
A4P
A5P
A6P
A7P
A0N
A1N
A2N
A3N
A4N
A5N
A6N
A7N
SVM
VCLK
EBO0
EBO1
EBO2
EBO3
EBO4
EBO5
EBO6
EBO7
VREF
OBO5
OBO6
OBO7
ERO0
ERO1
ERO2
ERO3
ERO4
ERO5
ERO6
ERO7
EGO0
EGO1
EGO2
EGO3
EGO4
EGO5
EGO6
EGO7
ADIN0
ADIN1
ADIN2
ADIN3
ADIN4
CLK1P
LVSSB
LVSSA
CLK2P
REXTA
LVSSC
CLK1N
CLK2N
DVSS3
U?
REFP4
REFN4
LVDDB
LVDDA
BGVSS
LVDDC
BGVDD
DVDD3I
DLLVSS
DVSS18
DLLVDD
DVDD18
ADCVSS
ADCVDD
VSY NCO
VPLLVSS
HSYNCO
VPLLVDD
AUXVTOP
ADCVSS4
VFEVDD1
DACVSSA
DACVSSB
DACVSSC
ADCVDD4
AE2 L12
DACVDDA
DACVDDB
DACVDDC
VFEVSS1
PWM2VREF
AF1 OBO4 D5
AVCM
AUXVBOTTOM
AF2 OBO3 C4
AE3 OBO2 ADCVDD0 B1
AF3 OBO1 CVBS2N A1
AE4 OBO0 CVBS2P B2
AF4 OGO7 CVBS1N A2
AC5 OGO6 CVBS1P B3
T11 OGO5 CVBS0N A3
AD5 DVSS18 CVBS0P L13
AE5 OGO4 ADCVSS0 B4
AF5 OGO3 REFP0 A4
AC6 OGO2 REFN0 C5
AD9 OGO1 ADCVDD1 B5
AD6 DVDD3 SCN A5
AE6 OGO0 SCP B6
Pinout information
AF6 ORO7 SYN A6

AC7 ORO6 SYP M13
AD7 ORO5 ADCVSS1 D6
AD18 ORO4 REFP1 C6
AE7 DVDD18 REFN1 D7
AF7 ORO3 VFEVDD0 B7
AC8 ORO2 VOCM N13
AD8 ORO1 VFEVSS0 A7
AF8 ORO0 VICM C7
P12 HIGHA7 ADCVDD2 B8
AE9 DVSS18 CRN A8
AF9 HIGHA6 CRP B9
AE10 HIGHA5 CBN A9
AF10 HIGHA4 CBP B10
AC11 HIGHA3 YN A10
AD11 HIGHA2 YP C8
AF12 HIGHA1 SOY D10
AE15 HIGHA0 ADCVSS2 D9
AD15 AD0 REFP2 C9
AC19 AD1 REFN2 D11
AC15 DVDD18 MON0 C11
AF16 AD2 MON1 D8
AE16 AD3 ADCVDD3 B11
R12 AD4 RN A11
AD16 DVSS3 RP B12
AC16 AD5 GN A12
AF17 AD6 GP D13
AD17 AD7 SOG B13
AD14 IOA0 BN A13
AE14 IOA1 BP C10
AF14 IOA2 ADCVSS3 D12
AF13 IOA3 REFP3 C12
AE13 IOA4 REFN3 C13
AD13 IOA5 VSYNC C14
AC13 IOA6 HSYNC N14
AE8 IOA7 DVSS D14
AC10 A16 DVDD L14
AC17 DVDD3I ADCPLLVSS1 D15
AE12 A17 ADCPLLVDD1 C15
AD12 IOA18 ADCPLLVDD M14
AE11 IOA19 ADCPLLVSS L15
T12 IOA20 SYSPLLVSS D16
AF11 DVSS18 SYSPLLVDD B14
AE17 IOA21 TESTP A14
AF15 IOALE TESTN C16
AC12 IOOE# XTALVDD B15
AC14 IOWR# XTALO A15
AF18 IOCS# XTALI M15
AE18 WR# XTALVSS A16
AD10 RD# APLL_CAP D18
DVDD3 APLLVSS
MT8205
AF19 D17
AE19 INT0# APLLVDD C17
AF20 UP12 DMPLLVDD C18
AE20 UP13 DMPLLVSS B16
AD19 UP14 VI0 A17
AD20 DVDD18 VI1 B17
AC20 UP15 VI2 A18
AF21 UP16 VI3 B18
AE21 UP17 VI4 C19
AD21 UP30 VI5 D19
P13 UP31 VI6 E23
AC21 DVSS18 DVDD18 A19
AD22 PRST# VI7 B19
AC22 UP34 VI8 C20
AF22 UP35 VI9 D20
AE22 FCICLK VI10 A20
AF23 FCICMD VI11 L16
AE23 FCIDAT DVSS3 B20
AD23 GPIO0 VI12 C21
AC23 PWM0 VI13 D21
AF24 PWM1 VI14 A21
AE24 IR VI15 M16
AD24 RXD DVSS18 B21
R13 TXD VI16 C22
AC24 DVSS3 VI17 D22
AF25 ICE VI18 A22
AE25 SCL VI19 B22
AF26 SDA VI20 C23
AE26 SCL0 VI21 D23
AB23 SDA0 VI22 A23
AB24 SCL1 VI23 B23
SDA1 VCLK_DVI
RVREF
VSYNC_DVI
DE_DVI
DQM0
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
CAS#
RAS#
RA0
RA1
RA2
RA3
RA9
RA8
RA7
RA6
RA5
RA4
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM1
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
AOSDATA3
AOSDATA2
AOSDATA1
AOSDATA0
AOMCLK
AOLRCK
AOBCK
DVDD2
DVSS2
DVDD2
AVDD18
AVSS18
DVSS2
DVDD2
DVSS2
DVSS2
DVDD2
DVSS2
DVDD2
DVSS2
DVDD2
DVSS2
DVDD2
DVSS3
DVDD2I
DVDD3I
HSYNC_DVI
LIN
RCLKB
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS0
DVSS18
DQS1
DVSS18
DQ9
DQ8
RWE#
RCS#
BA0
DVDD18
BA1
RA10
RA11
DVSS18
DVDD18
DQS2
DVSS18
DQS3
DVDD18
RCLK
CKE
T14
T16
T26
T15
T25
T13
T23
T24
L24
L23
J24
J23
L26
L25
J26
J25
V24
V23
V26
V25
P23
P24
P15
P25
P26
K24
K23
K26
P16
K25
P14
E25
E26
F25
F24
F26
E24
B24
B25
F23
B26
A26
A25
A24
Y25
Y26
G23
Y23
R25
U26
U25
U24
R15
R23
R24
U23
R26
N24
N23
M24
H23
N26
M23
R14
R16
N25
M26
M25
H24
H26
H25
D25
D26
G24
N16
G25
G26
N15
C25
C26
Y24
D24
C24
W24
W23
W25
W26
AB25
AB26
AA25
AA26
AA23
AA24
AD25
AD26
AC25
AC26
MT8205
BGA388/SOCKET
12
Pin Descriptions
2.3 Pin Descriptions

Table 2-1 provides detail video/audio port pin descriptions.
Table 2-1 video/audio port pin descriptions.
Pin Symbol Type Description
E24 O Audio out master clock

AOMCLK
C25 O Audio out left-right clock

AOLRCK
C26 O Audio out bit clock

AOBCK
A25 O Audio out data line 0

AOSDATA0
A26 O Audio out data line 1

AOSDATA1
B26 O Audio out data line 2

AOSDATA2
B25 O Audio out data line 3

AOSDATA3
B24 I Audio line in

LIN
A3 I Composite Video input 0

CVBS0P

CVBS1P

CVBS2P
C1 I Tuner Sound SIF

SIF
C2 I Tuner Sound AF
AF
13
AT24C01A/02/04/08/16
Features
• Low Voltage and Standard Voltage Operation
5.0 (VCC = 4.5V to 5.5V)
2.7 (VCC = 2.7V to 5.5V)
2.5 (VCC = 2.5V to 5.5V)
1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
• 2-Wire Serial Interface
• Bidirectional Data Transfer Protocol 2-Wire
• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
• Write Protect Pin for Hardware Data Protection
Serial CMOS
• 8-Byte Page (1K, 2K), 16-Byte Page (4K, 8K, 16K) Write Modes
• Partial Page Writes Are Allowed
E2PROM
• Self-Timed Write Cycle (10 ms max)
• High Reliability
Endurance: 1 Million Cycles 1K (128 x 8)
Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available 2K (256 x 8)
• 8-Pin and 14-Pin JEDEC SOIC and 8-Pin PDIP Packages
4K (512 x 8)
Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec- 8K (1024 x 8)
trically erasable and programmable read only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many 16K (2048 x 8)
industrial and commercial applications where low power and low voltage operation are
essential. The AT24C01A/02/04/08/16 is available in space saving 8-pin PDIP, 8-pin
and 14-pin SOIC packages and is accessed via a 2-wire serial interface. In addition,
the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to
5.5V) and 1.8V (1.8V to 5.5V) versions.
AT24C01A/2/4/8/16
Pin Configurations
8-Pin PDIP
Pin Name Function
A0 to A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
14-Pin SOIC
8-Pin SOIC
0180C
2-25
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
Operating Temperature................... -55°C to +125°C mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
Storage Temperature...................... -65°C to +150°C device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
Voltage on Any Pin
implied. Exposure to absolute maximum rating conditions
with Respect to Ground ..................... -0.1V to +7.0V for extended periods may affect device reliability.
Maximum Operating Voltage ........................... 6.25V
DC Output Current ......................................... 5.0 mA
Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive The AT24C04 uses the A2 and A1 inputs for hard wire
edge clock data into each E2PROM device and negative addressing and a total of four 4K devices may be ad-
edge clock data out of each device. dressed on a single bus system. The A0 pin is a no con-
SERIAL DATA (SDA): The SDA pin is bidirectional for se- nect.
rial data transfer. This pin is open-drain driven and may be The AT24C08 only uses the A2 input for hardwire ad-
wire-ORed with any number of other open-drain or open dressing and a total of two 8K devices may be addressed
collector devices. on a single bus system. The A0 and A1 pins are no con-
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 nects.
and A0 pins are device address inputs that are hard wired The AT24C16 does not use the device address pins which
for the AT24C01A and the AT24C02. As many as eight limits the number of devices on a single bus to one. The
1K/2K devices may be addressed on a single bus system A0, A1 and A2 pins are no connects.
(device addressing is discussed in detail under the Device (continued)
Addressing section).
2-26 AT24C01A/02/04/08/16
R MX29LV160BT/BB
16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V erase operation completion.
• 2,097,152 x 8/1,048,576 x 16 switchable • Ready/Busy pin (RY/BY)
• Single power supply operation - Provides a hardware method of detecting program or
- 3.0V only operation for read, erase and program erase operation completion.
operation • Sector protection
• Fully compatible with MX29LV160A device - Hardware method to disable any combination of
• Fast access time: 70/90ns sectors from program or erase operations
• Low power consumption - Temporary sector unprotect allows code changes in
- 30mA maximum active current previously locked sectors.
- 0.2uA typical standby current • CFI (Common Flash Interface) compliant
• Command register architecture - Flash device parameters stored on the device and
- Byte/word Programming (9us/11us typical) provide the host system to access
- Sector Erase (Sector structure 16K-Bytex1, • 100,000 minimum erase/program cycles
8K-Bytex2, 32K-Bytex1, and 64K-Byte x31) • Latch-up protected to 100mA from -1V to VCC+1V
• Auto Erase (chip & sector) and Auto Program • Boot Sector Architecture
- Automatically erase any combination of sectors with - T = Top Boot Sector
Erase Suspend capability. - B = Bottom Boot Sector
- Automatically program and verify data at specified • Low VCC write inhibit is equal to or less than 1.4V
address • Package type:
• Erase Suspend/Erase Resume - 44-pin SOP
- Suspends sector erase operation to read data from, - 48-pin TSOP
or program data to, any sector that is not being erased, - 48-ball CSP
then resumes the erase. • Compatibility with JEDEC standard
• Status Reply - Pinout and software compatible with single-power
- Data polling & Toggle bit for detection of program and supply Flash
• 10 years data retention
GENERAL DESCRIPTION
The MX29LV160BT/BB is a 16-mega bit Flash memory 100% TTL level control inputs and fixed power supply
organized as 2M bytes of 8 bits or 1M words of 16 bits. levels during erase and programming, while maintaining
MXIC's Flash memories offer the most cost-effective maximum EPROM compatibility.
and reliable read/write non-volatile random access
memory. The MX29LV160BT/BB is packaged in 44-pin MXIC Flash technology reliably stores memory contents
SOP, 48-pin TSOP and 48-ball CSP. It is designed to be even after 100,000 erase and program cycles. The MXIC
reprogrammed and erased in system or in standard cell is designed to optimize the erase and programming
EPROM programmers. mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
The standard MX29LV160BT/BB offers access time as for erase and program operations produces reliable cy-
fast as 70ns, allowing operation of high-speed micropro- cling. The MX29LV160BT/BB uses a 2.7V~3.6V VCC
cessors without wait states. To eliminate bus conten- supply to perform the High Reliability Erase and auto
tion, the MX29LV160BT/BB has separate chip enable Program/Erase algorithms.
(CE) and output enable (OE) controls.
The highest degree of latch-up protection is achieved
MXIC's Flash memories augment EPROM functionality with MXIC's proprietary non-epi process. Latch-up pro-
with in-circuit electrical erasure and programming. The tection is proved for stresses up to 100 milliamps on
MX29LV160BT/BB uses a command register to man- address and data pin from -1V to VCC + 1V.
age this functionality. The command register allows for
P/N:PM1041 REV. 1.2, JUL. 01, 2004

1
LP2996 DDR Termination Regulator
November 2003
LP2996
DDR Termination Regulator
General Description Features
The LP2996 linear regulator is designed to meet the JEDEC n Source and sink current
SSTL-2 specifications for termination of DDR-SDRAM. The n Low output voltage offset
device contains a high-speed operational amplifier to provide n No external resistors required
excellent response to load transients. The output stage pre- n Linear topology
vents shoot through while delivering 1.5A continuous current n Suspend to Ram (STR) functionality
and transient peaks up to 3A in the application as required
n Low external component count
for DDR-SDRAM termination. The LP2996 also incorporates
n Thermal Shutdown
a VSENSE pin to provide superior load regulation and a VREF
output as a reference for the chipset and DIMMs. n Available in SO-8, PSOP-8 or LLP-16 packages
An additional feature found on the LP2996 is an active low
shutdown (SD) pin that provides Suspend To RAM (STR) Applications
functionality. When SD is pulled low the VTT output will n DDR-I and DDR-II Termination Voltage
tri-state providing a high impedance output, but, VREF will n SSTL-2 and SSTL-3 Termination
remain active. A power savings advantage can be obtained n HSTL Termination
in this mode through lower quiescent current.
Typical Application Circuit
20057518
© 2003 National Semiconductor Corporation DS200575 www.national.com

SCDS164A – MAY 2004 − REVISED MAY 2004
D Low Differential Gain and Phase D, DBQ, OR PW PACKAGE

(DG = 0.64%, DP = 0.1 Degrees Typ) (TOP VIEW)
D Wide Bandwidth (BW = 300 MHz Min)

IN 1 16 VCC
D Low Crosstalk (XTALK = −63 dB Typ) S1A 2 15 EN
D Low Power Consumption S2A 3 14 S1D
(ICC = 3 µA Max) DA 4 13 S2D
D Bidirectional Data Flow, With Near-Zero S1B 5 12 DD
Propagation Delay S2B 6 11 S1C
D Low ON-State Resistance (ron = 3 Ω Typ) DB 7 10 S2C
GND 8 9 DC
D VCC Operating Range From 4.5 V to 5.5 V
D Ioff Supports Partial-Power-Down Mode
Operation RGY PACKAGE
D Data and Control Inputs Provide (TOP VIEW)
VCC
Undershoot Clamp Diode
IN
D Control Inputs Can Be Driven by TTL or
1 16
5-V/3.3-V CMOS Outputs
S1A 15 EN
D Latch-Up Performance Exceeds 100 mA Per
2
S2A 3 14 S2D
JESD 78, Class II
DA 4 13 S2D
D ESD Performance Tested Per JESD 22 S1B 5 12 DD
− 2000-V Human-Body Model S2B 6 11 S1C
(A114-B, Class II) DB 7 10 S2C
− 1000-V Charged-Device Model (C101) 8 9
D
DC
Suitable for Both RGB and
GND
Composite-Video Switching
description/ordering information
The TI TS5V330 video switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (EN) input.
When EN is low, the switch is enabled and the D port is connected to the S port. When EN is high, the switch
is disabled and the high-impedance state exists between the D and S ports. The select (IN) input controls the
data path of the multiplexer/demultiplexer.
ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
QFN − RGY Tape and reel TS5V330RGYR TE330
Tube TS5V330D
SOIC − D TS5V330
Tape and reel TS5V330DR
−40°C to 85°C
SSOP (QSOP) − DBQ Tape and reel TS5V330DBQR TE330
Tube TS5V330PW
TSSOP − PW TE330
Tape and reel TS5V330PWR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

!"# $"%&! '#( Copyright  2004, Texas Instruments Incorporated
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

19-0175; Rev 3; 5/96
±15kV ESD-Protected, +5V RS-232 Transceivers
_______________General Description ____________________________Features
MAX202E–MAX213E, MAX232E/MAX241E
The MAX202E–MAX213E, MAX232E/MAX241E line ♦ ESD Protection for RS-232 I/O Pins:
drivers/receivers are designed for RS-232 and V.28 ±15kV—Human Body Model
communications in harsh environments. Each
transmitter output and receiver input is protected ±8kV—IEC1000-4-2, Contact Discharge
against ±15kV electrostatic discharge (ESD) shocks, ±15kV—IEC1000-4-2, Air-Gap Discharge
without latchup. The various combinations of features ♦ Latchup Free (unlike bipolar equivalents)
are outlined in the Selection Guide. The drivers and
receivers for all ten devices meet all EIA/TIA-232E and ♦ Guaranteed 120kbps Data Rate—LapLink™
CCITT V.28 specifications at data rates up to 120kbps, Compatible
when loaded in accordance with the EIA/TIA-232E ♦ Guaranteed 3V/µs Min Slew Rate
specification.
♦ Operate from a Single +5V Power Supply
The MAX211E/MAX213E/MAX241E are available in 28-
pin SO packages, as well as a 28-pin SSOP that uses
60% less board space. The MAX202E/MAX232E come
_________________Pin Configurations
in 16-pin narrow SO, wide SO, and DIP packages. The
MAX203E comes in a 20-pin DIP/SO package, and TOP VIEW
needs no external charge-pump capacitors. The
MAX205E comes in a 24-pin wide DIP package, and C1+ 1 16 VCC
also eliminates external charge-pump capacitors. The V+ 2 15 GND
MAX206E/MAX207E/MAX208E come in 24-pin SO,
C1- 3 14 T1OUT
SSOP, and narrow DIP packages. The MAX232E/
MAX241E operate with four 1µF capacitors, while the C2+ 4 MAX202E 13 R1IN
MAX202E/MAX206E/MAX207E/MAX208E/MAX211E/ MAX232E
C2- 5 12 R1OUT
MAX213E operate with four 0.1µF capacitors, further
V- 6 11 T1IN
reducing cost and board space.
T2OUT 7 10 T2IN
________________________Applications
R2IN 8 9 R2OUT
Notebook, Subnotebook, and Palmtop Computers
Battery-Powered Equipment DIP/SO
Hand-Held Equipment Pin Configurations and Typical Operating Circuits continued at
end of data sheet.
Ordering Information appears at end of data sheet.
_____________________________________________________________Selection Guide
RECEIVERS No. of
No. of RS-232 No. of RS-232 LOW-POWER TTL THREE-
PART ACTIVE IN EXTERNAL
DRIVERS RECEIVERS SHUTDOWN STATE
SHUTDOWN CAPACITORS
MAX202E 2 2 0 4 (0.1µF) No No
MAX203E 2 2 0 None No No
MAX205E 5 5 0 None Yes Yes
MAX206E 4 3 0 4 (0.1µF) Yes Yes
MAX207E 5 3 0 4 (0.1µF) No No
MAX208E 4 4 0 4 (0.1µF) No No
MAX211E 4 5 0 4 (0.1µF) Yes Yes
MAX213E 4 5 2 4 (0.1µF) Yes Yes
MAX232E 2 2 0 4 (1µF) No No
MAX241E 4 5 0 4 (1µF) Yes Yes
LapLink is a registered trademark of Traveling Software, Inc.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
±15kV ESD-Protected, +5V RS-232 Transceivers
MAX202E–MAX213E, MAX232E/MAX241E
Table 3. DB9 Cable Connections

Commonly Used for EIA/TIAE-232E and
V.24 Asynchronous Interfaces
PIN CONNECTION
Received Line Signal
Detector (sometimes
1 Handshake from DCE
called Carrier Detect,
DCD)
2 Receive Data (RD) Data from DCE
3 Transmit Data (TD) Data from DTE
4 Data Terminal Ready Handshake from DTE
Reference point for

5 Signal Ground
signals
6 Data Set Ready (DSR) Handshake from DCE
7 Request to Send (RTS) Handshake from DTE
8 Clear to Send (CTS) Handshake from DCE

9 Ring Indicator Handshake from DCE
____________Pin Configurations and Typical Operating Circuits (continued)
+5V INPUT
TOP VIEW 0.1µF*
0.1µF
6.3V
16
1 VCC 2
C1+ V+ +10V
0.1µF* +5V TO +10V
6.3V 3
C1- VOLTAGE DOUBLER
4 6 -10V
C2+ V-
C1+ 1 16 VCC 0.1µF* +10V TO -10V 0.1µF*
5 C2- VOLTAGE INVERTER
16V 16V
V+ 2 15 GND
C1- 3 14 T1OUT
11 T1IN T1OUT 14
C2+ 4 MAX202E 13 R1IN T1
MAX232E TTL/CMOS RS-232
C2- 5 12 R1OUT INPUTS OUTPUTS
V- 6 11 T1IN 10 T2IN T2OUT 7
T2
T2OUT 7 10 T2IN
12 R1OUT R1IN 13
R2IN 8 9 R2OUT R1
TTL/CMOS 5k RS-232
DIP/SO OUTPUTS INPUTS
9 R2OUT R2IN 8
R2
5k
PIN NUMBERS ON TYPICAL OPERATING CIRCUIT REFER TO DIP/SO PACKAGE, NOT LCC. GND
* 1.0µF CAPACITORS, MAX232E ONLY. 15
14 ______________________________________________________________________________________
TFT LCD Preliminary Specification
MODEL NO.: V270B1 - L01
LCD TV Head Division

AVP 郭振隆
TVHD / PDD
QRA Dept.
DDIII DDII DDI
Approval Approval Approval Approval
陳永一李汪洋藍文錦林文聰
LCD TV Marketing and Product Management Division

Product Manager 陳立宜謝芳宜
1
- CONTENTS -
REVISION HISTORY ------------------------------------------------------- 3
1. GENERAL DESCRIPTION ------------------------------------------------------- 4

1.1 OVERVIEW
1.2 FEATURES
1.3 APPLICATION
1.4 GENERAL SPECIFICATIONS
1.5 MECHANICAL SPECIFICATIONS
2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 5

2.1 ABSOLUTE RATINGS OF ENVIRONMENT
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
2.2.2 BACKLIGHT UNIT
3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 7

3.1 TFT LCD MODULE
3.2 BACKLIGHT INVERTER UNIT
3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS
3.2.2 INVERTER CHARACTERISTICS
3.2.3 INVERTER INTERTFACE CHARACTERISTICS
4. BLOCK DIAGRAM ------------------------------------------------------- 12

4.1 TFT LCD MODULE
5. INTERFACE PIN CONNECTION ------------------------------------------------------- 13

5.1 TFT LCD MODULE
5.2 BACKLIGHT UNIT
5.3 INVERTER UNIT
5.4 BLOCK DIAGRAM OF INTERFACE
5.5 LVDS INTERFACE
5.6 COLOR DATA INPUT ASSIGNMENT
6. INTERFACE TIMING ------------------------------------------------------- 19

6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
7. OPTICAL CHARACTERISTICS ------------------------------------------------------- 22

7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS
8. DEFINITION OF LABELS ------------------------------------------------------- 26

8.1 CMO MODULE LABEL
9. PACKAGING ------------------------------------------------------- 27
9.1 PACKING SPECIFICATIONS
9.2 PACKING METHOD
10. PRECAUTIONS ------------------------------------------------------- 29

10.1 ASSEMBLY AND HANDLING PRECAUTIONS
10.2 SAFETY PRECAUTIONS
11. MECHANICAL CHARACTERISTICS ------------------------------------------------------- 30
2
REVISION HISTORY
Page
Version Date Section Description
(New)
Ver 1.0 Jun. 15,’05 All All Preliminary Specification was first issued.
3
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V270B1- L01 is a TFT Liquid Crystal Display module with 14-CCFL Backlight unit and 1ch-LVDS
interface. The display diagonal is 27”. This module supports 1366 x 768 WXGA format and can display true
16.7M colors(8-bits colors). The inverter module for backlight is built-in.
1.2 FEATURES
- Excellent brightness (550 nits)
- Ultra high contrast ratio (1000:1)
- Fast response time (8ms)
- High color saturation NTSC 75%
- WXGA (1366 x 768 pixels) resolution
- DE (Data Enable) only mode
- LVDS (Low Voltage Differential Signaling) interface
- Optimized response time for both 50/60 Hz frame rate
- Ultra wide viewing angle: 176(H)/176(V) (CR>20) Super MVA technology
- 180 degree rotation display option
- Low color shift function option
- Color reproduction (Nature color)
1.3 APPLICATION
- TFT LCD TVs
- High brightness, multi-media displays
-
1.4 GENERAL SPECIFICATI0NS
Item Specification Unit Note
Active Area 596.259 (H) x 335.232 (V) (27” diagonal) mm
(1)
Bezel Opening Area 603.22 (H) x 341.98 (V) mm
Driver Element a-si TFT active matrix -
Pixel Number 1366 x R.G.B. x 768 pixel
Pixel Pitch (Sub Pixel) 0.1460 (H) x 0.4365 (V) mm
Pixel Arrangement RGB vertical stripe -
Display Colors 16.7M color
Display Operation Mode Transmissive mode / Normally black -
Hardness : 3H, Haze : 40%
Surface Treatment -
Anti-reflective coating < 2% reflection
1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note
Horizontal(H) 636.85 637.55 638.25 mm
Vertical(V) 379.1 379.8 380.5 mm
Module Size
Depth(D) 33.9 35.4 36.9 mm To PCB cover
Depth(D) 39.2 40.7 42.2 mm To inverter cover
Weight 3700 4000 4300 g
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
4
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Value
Item Symbol Unit Note
Min. Max.
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 +50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta ≦ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 60 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 60 ºC. The range of operating temperature may degrade in case of improper
thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 500 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough
so that the module would not be twisted or bent by the fixture.
Relative Humidity (%RH)
100
90
80
60
Operating Range
40
20
10 Storage Range
-40 -20 0 20 40 60 80
Temperature (ºC)
5
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
Value
Item Symbol Unit Note
Min. Max.
Power Supply Voltage Vcc -0.3 6.0 V
(1)
Input Signal Voltage VIN -0.3 3.6 V
2.2.2 BACKLIGHT UNIT

Test
Item Symbol Min. Type Max. Unit Note
Condition
Lamp Voltage VW Ta = 25 ℃ －－ 3000 VRMS
Power Supply Voltage VBL － 0 － 30 V (1)
Control Signal Level －－ -0.3 － 7 V (1), (3)
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Functional
operation should be restricted to the conditions described under normal operating conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals includes Backlight On/Off Control, Internal PWM Control, External PWM
Control and Internal/External PWM Selection.
6
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE Ta = 25 ± 2 ºC
Value
Parameter Symbol Unit Note
Min. Typ. Max.
Power Supply Voltage VCC 4.5 5.0 5.5 V (1)
Power Supply Ripple Voltage VRP - - 150 mV
Rush Current IRUSH - - 3.0 A (2)
White - 1.8 - A
Power Supply Current Black ICC - 1.2 - A (3)
Vertical Stripe - 1.65 - A
Differential Input High
VLVTH - - +100 mV
Threshold Voltage
LVDS
Differential Input Low
Interface VLVTL -100 - - mV
Threshold Voltage
Common Input Voltage VLVC 1.125 1.25 1.375 V
Terminating Resistor RT 100 ohm
CMOS Input High Threshold Voltage VIH 2.7 - 3.3 V
interface Input Low Threshold Voltage VIL 0 - 0.7 V
Note (1) The module should be always operated within above ranges.
Note (2) Measurement Conditions:
+5.0V
Q1 2SK1475
Vcc
C3
FUSE (LCD Module Input)
R1 1uF
47K
(High to Low)
(Control Signal)
Q2
R2
SW 2SK1470
1K
+12V
VR1 47K C2
C1
0.01uF
1uF
Vcc rising time is 470us

+5V
0.9Vcc
0.1Vcc
GND
470us
7
Note (3) The specified power supply current is under the conditions at Vcc = 5 V, Ta = 25 ± 2 ºC, fv = 60 Hz,
whereas a power dissipation check pattern below is displayed.
a. White Pattern b. Black Pattern
Active Area Active Area
c. Vertical Stripe Pattern
R G B R G B
B R G B R G B R
B R G B R G B R
R G B R G B
Active Area
3.2 BACKLIGHT INVERTER UNIT

3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 ± 2 ºC)
Value
Min. Typ. Max.
Lamp Voltage VW - 1120 - VRMS IL = 4.7mA
Lamp Current IL 4.2 4.7 5.2 mARMS (1)
- - 1650 VRMS (2), Ta = 0 ºC
Lamp Starting Voltage VS
- - 1500 VRMS (2), Ta = 25 ºC
Operating Frequency FO 50 - 70 KHz (3)
Lamp Life Time LBL 50,000 60,000 - Hrs (4)
8
3.2.2 INVERTER CHARACTERISTICS (Ta = 25 ± 2 ºC)
Value
Min. Typ. Max.
Power Consumption PBL - 92 - W (5), IL = 4.7mA
Power Supply Voltage VBL 22.8 24 25.2 VDC
Power Supply Current IBL - 3.8 - A Non Dimming
Input Ripple Noise - - - 500 mVP-P VBL =22.8V
Backlight Turn on 1790 - - VRMS Ta = 0 ºC
VBS
Voltage 1200 - - VRMS Ta = 25 ºC
Oscillating Frequency FW 53 56 59 kHz
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio DMIN - 10 - %
Note (1) Lamp current is measured by utilizing high frequency current meters as shown below:
HV (Pink) 1
A
HV (White)
2
A
HV (Pink) 1
A
HV (White)
A 2
HV (Pink) 1
A
HV (White)
A LCD 2 Inverter
Module HV (Pink) 1
A
HV (White)
A 2
HV (Pink) 1
A
HV (White)
A 2
A HV (Pink) 1
HV (White)
A 2
A HV (Pink) 1
HV (White)
A 2 LV (Gray)
Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second under starting
up duration. Otherwise the lamp could not be lighted on completed.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency from the
display, and this may cause line flow on the display. In order to avoid interference, the lamp
frequency should be detached from the horizontal synchronous frequency and its harmonics as far
as possible.
9
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value
and the effective discharge length is longer than 80% of its original length (Effective discharge
length is defined as an area that has equal to or more than 70% brightness compared to the
brightness at the center point.) as the time in which it continues to operate under the condition Ta
= 25 ±2℃ and IL = 4.2 ~ 5.2 mARMS.
Note (5) The power supply capacity should be higher than the total inverter power consumption PBL. Since
the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current
changed as PWM duty on and off. The transient response of power supply should be considered
for the changing loading when inverter dimming.
3.2.3 INVERTER INTERTFACE CHARACTERISTICS

Test
Item Symbol Min. Typ. Max. Unit Note
Condition
On/Off Control ON － 2.0 － 5.0 V

VBLON
Voltage OFF － 0 － 0.8 V
Internal/External HI － 2.0 － 5.0 V

VSEL
PWM Select Voltage LO － 0 － 0.8 V
Internal PWM MAX －－ 3.0 V minimum duty ratio

VIPWM VSEL = L
Control Voltage MIN － 0 － V maximum duty ratio
External PWM HI 2.0 － 5.0 V duty on

VEPWM VSEL = H
Control Voltage LO 0 － 0.8 V duty off
Control Signal Rising Time Tr －－－ 100 ms
Control Signal Falling Time Tf －－－ 100 ms
PWM Signal Rising Time TPWMR －－－ 50 us
PWM Signal Falling Time TPWMF －－－ 50 us
Input impedance RIN － 1 －－ MΩ
BLON Delay Time Ton － 1 －－ ms
BLON Off Time Toff － 1 －－ ms
Note (1) The SEL signal should be valid before backlight turns on by BLON signal. It is inhibited to change
the internal/external PWM selection (SEL) during backlight turn on period.
10
Note (2) The power sequence and control signal timing are shown as the following figure.
VBL
0 Ton Toff
VBLON 2.0V
0.8V
0
Backlight on duration
Tr Tf
VSEL 2.0V
0.8V Int. Dimming Function
0 Ext. Dimming Function
TPWMR TPWMF
VEPWM 2.0V
0.8V
0
3.0V
VIPWM
0
VW
External External
PWM PWM Duty
Period
Minimun 100%
Duty
11
4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
SCAN DRIVER IC
FRAME BUFFER TFT LCD PANEL
RX0(+/-)
(1366x3x768)
INPUT CONNECTOR
(JAE,FI-X30SSL-HF)
RX1(+/-)
RX2(+/-)
TIMING
RX3(+/-)
RXCLK(+/-)
CONTROLLER
Vcc
DATA DRIVER IC
GND
DC/DC CONVERTER &
REFERENCE VOLTAGE
CN1
VBL
GND
BACKLIGHT
CN3-CN9:SM02 (8.0)B-BHS-1-TB(LF)(JST)
CN2 INVERTER CONNECTOR UNIT
VBL CN1:S10B-PH-SM3-TB(D)(LF)(JST)
GND CN2: S12B-PH-SM3-TB(D)(LF)(JST)
SEL
E_PWM
I_PWM
BLON
CN10: S2B-ZR-SM3A-TF (D)(LF)(JST)
12
5. INTERFACE PIN CONNECTION
5.1 TFT LCD MODULE
CNF1 Connector Pin Assignment
Pin No. Symbol Description Note
1 GND Ground
2 RPF Display Rotation (3)
3 SELLVDS Select LVDS data format (5)
4 NC No Connection (2)
5 NC No Connection
6 ODSEL Overdrive Lookup Table Selection (4)
7 EN LCS Low Color Shift (6)
8 GND Ground
9 RX0- Negative transmission data of pixel 0
10 RX0+ Positive transmission data of pixel 0
15 RXCLK- Negative of clock
16 RXCLK+ Positive of clock
19 GND Ground
20 GND Ground
21 GND Ground
22 GND Ground
23 GND Ground
24 GND Ground
25 GND Ground
26 VCC Power supply: +5V
Note (1) Connector Part No.: FI-X30SSL-HF(JAE) or compatible
Note (2) Reserved for internal use. Left it open.
Note (3) Low : normal display (default), High : display with 180 degree rotation
Note (4) Overdrive lookup table selection. The Overdrive lookup table should be selected in accordance to the
frame rate to optimize image quality.
ODSEL Note
L Lookup table was optimized for 60 Hz frame rate.
H Lookup table was optimized for 50 Hz frame rate.
Note (5) Please refer to 5.5 LVDS INTERFACE (Page 17)
Note (6) Enable Low color shift function.
EN LCS Note
L Low color shift off
H Low color shift on
13
5.2 BACKLIGHT UNIT
The pin configuration for the housing and leader wire is shown in the table below.
CN3-CN9 (Housing): BHR-03VS-1 (JST)
Pin No. Symbol Description Wire Color
1 HV High Voltage Pink
2 HV High Voltage White
Note (1) The backlight interface housing for high voltage side is a model BHR-03VS-1, manufactured by JST.
The mating header on inverter part number is SM02(8.0)B-BHS-1-TB(LF) or equivalent.
CN10 (Housing): ZHR-2 (JST) or equivalent

Pin No. Symbol Description Wire Color
1 LV Low Voltage (+) Gray
2 NC No Connection -
Note (2) The backlight interface housing and return cable for low voltage side is a model ZHR-2 , manufactured
by JST or equivalent. The mating header on inverter part number is S2B-ZR-SM3A-TF(D)(LF) or
equivalent.
14
5.3 INVERTER UNIT
CN1(Header):S10B-PH-SM3-TB(D)(LF)(JST) or equivalent.
Pin Name Description
1
2
3 VBL +24V Power input
4
5
6
7
8 GND Ground
9
10
CN2(Header): S12B-PH-SM3-TB(D)(LF)(JST) or equivalent.

1
2
3 VBL +24V Power input
4
5
6
7 GND Ground
8
Internal/external PWM selection
9 SEL High : external dimming
Low : internal dimming
External PWM control signal
10 E_PWM E_PWM should be connected to low when internal
PWM was selected (SEL = low).
Internal PWM control signal
11 I_PWM I_PWM should be connected to ground when
external PWM was selected (SEL = high).
12 BLON Backlight on/off control
CN3-CN9(Header): SM02(8.0)B-BHS-1-TB(LF)(JST) or equivalent

1 CCFL HOT CCFL high voltage
2 CCFL HOT CCFL high voltage
CN10(Header): S2B-ZR-SM3A-TF(D)(LF)(JST) or equivalent

1 CCFL COLD CCFL low voltage
2 NC -
Note (1) Floating of any control signal is not allowed.
15
5.4 BLOCK DIAGRAM OF INTERFACE
CNF1
Rx0+ 51Ω
100pF RxOUT
TxIN Rx0- R0-R7
R0-R7 51Ω
Rx1+ 51Ω G0-G7
G0-G7
Rx1-
100pF
51Ω B0-B7
B0-B7
Rx2+ 51Ω
DE Rx2-
100pF
DE
51Ω
Rx3+ 51Ω
Rx3-
100pF
51Ω
Host
CLK+ 51Ω
Graphics PLL DCLK
PLL
100pF
CLK-
Controller 51Ω Timing
Controller
LVDS Transmitter LVDS Receiver
THC63LVDM83A THC63LVDF84A
(LVDF83A)
R0~R7 : Pixel R Data ,

G0~G7 : Pixel G Data ,
B0~B7 : Pixel B Data ,
DE : Data enable signal
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
16
5.5 LVDS INTERFACE
TRANSMITTER INTERFACE RECEIVER TFT CONTROL

SIGNAL
THC63LVDM83A CONNECTOR THC63LVDF84A INPUT
SELLVDS SELLVDS SELLVDS SELLVDS

PIN INPUT Host TFT-LCD PIN OUTPUT
=L =H =L =H
R0 R2 51 TxIN0 27 Rx OUT0 R0 R2
R2 R4 54 TxIN2 TA OUT0+ Rx 0+ 30 Rx OUT2 R2 R4
R5 R7 3 TxIN6 TA OUT0- Rx 0- 35 Rx OUT6 R5 R7
G0 G2 4 TxIN7 37 Rx OUT7 G0 G2
G3 G5 11 TxIN12 TA OUT1+ Rx 1+ 43 Rx OUT12 G3 G5
G4 G6 12 TxIN13 45 Rx OUT13 G4 G6
G5 G7 14 TxIN14 46 Rx OUT14 G5 G7
B0 B2 15 TxIN15 TA OUT1- Rx 1- 47 Rx OUT15 B0 B2
B1 B3 19 TxIN18 51 Rx OUT18 B1 B3
24 B2 B4 20 TxIN19 53 Rx OUT19 B2 B4
bit B3 B5 22 TxIN20 54 Rx OUT20 B3 B5
B4 B6 23 TxIN21 TA OUT2+ Rx 2+ 55 Rx OUT21 B4 B6
B5 B7 24 TxIN22 1 Rx OUT22 B5 B7
DE DE 30 TxIN26 6 Rx OUT26 DE DE
R6 R0 50 TxIN27 TA OUT2- Rx 2- 7 Rx OUT27 R6 R0
G7 G1 10 TxIN11 42 Rx OUT11 G7 G1
B6 B0 16 TxIN16 TA OUT3+ Rx 3+ 49 Rx OUT16 B6 B0
B7 B1 18 TxIN17 50 Rx OUT17 B7 B1
RSVD 1 RSVD 1 25 TxIN23 2 Rx OUT23 NC NC
RSVD 2 RSVD 2 27 TxIN24 TA OUT3- Rx 3- 3 Rx OUT24 NC NC
RSVD 3 RSVD 3 28 TxIN25 5 Rx OUT25 NC NC
DCLK 31 TxCLK IN TxCLK OUT+ RxCLK IN+ 26 RxCLK OUT DCLK
TxCLK OUT- RxCLK IN-
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE: Data enable signal
Notes(1) RSVD(reserved)pins on the transmitter shall be “H” or “L”.
17
5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for
the color. The higher the binary input, the brighter the color. The table below provides the assignment of
color versus data input.
Data Signal
Color Red Green Blue
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Basic Blue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Colors Cyan 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Magenta 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Red(0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(1) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(2) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Red(253) 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red
Red(254) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(255) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green(0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Green(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Green(253) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0
Green
Green(254) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
Green(255) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Blue(0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Blue(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Blue(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Blue(253) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1
Blue
Blue(254) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0
Blue(255) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Note (1) 0: Low Level Voltage, 1: High Level Voltage
18
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency 1/Tc 60 86 88 MHZ
LVDS Receiver Clock Input cycle to
Trcl - - 200 ps
cycle jitter
Setup Time Tlvsu 600 - - ps
LVDS Receiver Data
Hold Time Tlvhd 600 - - ps
Fr5 47 50 53 Hz (2)
Frame Rate
Fr6 57 60 63 Hz
Vertical Active Display Term Total Tv 770 795 888 Th Tv=Tvd+Tvb
Display Tvd 768 768 768 Th -
Blank Tvb 2 27 120 Th -
Total Th 1436 1798 1936 Tc Th=Thd+Thb
Horizontal Active Display Term Display Thd 1366 1366 1366 Tc -
Blank Thb 70 432 570 Tc -
Note (1) Since this module is operated in DE only mode, Hsync and Vsync input signals should be set to
low logic level. Otherwise, this module would operate abnormally.
(2) Please refer to 5.1 for detail information.
INPUT SIGNAL TIMING DIAGRAM
Tv
Tvd
Tvb
DE
Th
DCLK
Tc
Thd
Thb
DE
DATA Valid display data (1366 clocks)
19
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T 3T 5T 7T 9T 11T 13T
14 14 14 14 14 14 14
20
6.2 POWER ON/OFF SEQUENCE
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the
diagram below.
Power Supply 0.9 VCC 0.9 VCC
VCC
0.1VCC 0.1Vcc
0V
0≦T1≦10ms T1 T3
0≦T2≦50ms
0≦T3≦50ms
500ms ≦T4 T2
T4
VALID
Signals
0V
Power On Power Off
Backlight (Recommended) 50% 50%

500ms≦T5
100ms≦T6
T5 T6
Power ON/OFF Sequence
Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.
21
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
o
Ambient Temperature Ta 25±2 C
Ambient Humidity Ha 50±10 %RH
Supply Voltage VCC 5.0 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL 4.7 ± 0.5 mA
Oscillating Frequency (Inverter) FW 56 ± 3 KHz
7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should
be measured under the test conditions described in 7.1 and stable environment shown in Note (6).
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR (1000) - (2)
Gray to gray
Response Time (8) ms (3)
average
Center Luminance of White LC (550) cd/m2 (4)
White Variation δW (1.3) - (7)
Cross Talk CT θx=0°, θY =0° (4) % (5)
Rx Viewing Normal (0.652) -
Red
Ry (0.331) -
Gx Angle (0.275) -
Green
Gy (0.597) -
Color (6)
Bx (0.143) -
Chromaticity Blue
By (0.063) -
Wx (0.285)
White Target
Wy (0.293)
Color Gamut CG (75) % NTSC
θx+ (88)
Horizontal
Viewing θx- (88)
CR≥20 Deg. (1)
Angle θY+ (88)
Vertical
θY- (88)
22
Note (1) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by EZ-Contrast 160R (Eldim)
Normal
θx = θy = 0º
θy- θy+
θX- = 90º x- 12 o’clock direction

y+
θx− θy+ = 90º
θx+
6 o’clock
y- x+ θX+ = 90º
θy- = 90º
Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L255 / L0
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (5)
CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (7).
Note (3) Definition of Gray to Gray Switching Time :
100%
90%
Optical
Response
10%
0%
Time
Gray to gray Gray to gray
switching time switching time
The driving signal means the signal of gray level 0, 63, 127, 191, 255.
Gray to gray average time means the average switching time of gray level 0 ,63,127,191,255 to each
other .
23
Note (4) Definition of Luminance of White (LC, LAVE):
Measure the luminance of gray level 255 at center point and 5 points
LC = L (5)
LAVE = [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5
L (x) is corresponding to the luminance of the point X at the figure in Note (7).
Note (5) Definition of Cross Talk (CT):

CT = | YB – YA | / YA × 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
(0, 0) Active Area (0, 0)

Active Area
YA, U (D/2,W/8) YB, U (D/2,W/8)
(D/4,W/4)
YA, L (D/8,W/2) YB, L (D/8,W/2) YB, R (7D/8,W/2)

Gray 128 Gray
Gray0 0
YA, R (7D/8,W/2)
(3D/4,3W/4)
YA, D (D/2,7W/8)
YB, D (D/2,7W/8) Gray 128
(D,W) (D,W)
Note (6) Measurement Setup:

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature
change during measuring. In order to stabilize the luminance, the measurement should be
executed after lighting Backlight for 1 hour in a windless room.
LCD Module
LCD Panel
Center of the Screen Display Color Analyzer

(Minolta CA210)
Light Shield Room

(Ambient Luminance < 2 lux)
24
Note (7) Definition of White Variation (δW):
Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
Horizontal Line
D
D/4 D/2 3D/4
Vertical Line
W/4 1 2
W W/2 5 X : Test Point

X=1 to 5
3W/4 3 4
Active Area
25
8. DEFINITION OF LABELS
8.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
CHI MEI E207943

OPTOELECTRONICS V270B1 -L01 Rev. XX MADE IN TAIWAN
XXXXXXXYMDLNNNN
(a) Model Name: V270B1-L01

(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
(c) Serial ID: X X X X X X X Y M D L N N N N
Serial No.
Product Line
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
CMO Internal Use

Serial ID includes the information as below:
(a) Manufactured Date: Year: 1~9, for 2001~2009
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
(b) Revision Code: Cover all the change
(c) Serial No.: Manufacturing sequence of product
(d) Product Line: 1 -> Line1, 2 -> Line 2, …etc.
26
9. PACKAGING
9.1 PACKING SPECIFICATIONS
(1) 4 LCD TV modules / 1 Box
(2) Box dimensions : 742(L) X 327 (W) X 510 (H)
(3) Weight : approximately 19Kg ( 4 modules per box)
9.2 PACKING METHOD

Figures 9-1 and 9-2 are the packing method
LCD TV Module
Anti-Static Bag
Carton dimensions: 742(L)x327(W)x510(H)mm
Weight : Approx 19Kg(4modules per carton)
PE Foam(Bottom)
Drier
Carton Carton Label
Figure.9-1 packing method
27
Corner Protector:L1020*50mm*50mm
Pallet:L1100*W1100*H135mm
Corrugated Fiberboard:L1100*W1100mm
Pallet Stack:L1100*W1100*H1160mm
Gross:168kg
PE Sheet
Carton Label
Film
PP Belt
Figure. 9-2 packing method
28
10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly.
(2) It is recommended to assemble or to install a module into the user’s system in clean working areas.
The dust and oil may cause electrical short or worsen the polarizer.
(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight.
(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
(5) Do not plug in or pull out the I/F connector while the module is in operation.
(6) Do not disassemble the module.
(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.
(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD
modules in the specified storage conditions.
(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
10.2 SAFETY PRECAUTIONS

(1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while assembling
with the inverter. Do not disassemble the module or insert anything into the backlight unit.
(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In
case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
(3) After the module’s end of life, it is not harmful in case of normal operation and storage.
29
11. MECHANICAL CHARACTERISTICS
奇美電子股份有限公司
CHI MEI
30
31
CHI MEI 奇美電子股份有限公司
SPARE PART LIST
LC27HAB CUSXM1-A01 AKAI MICO USA LCT2715(FULL PIP)
Item Component Description/Country Origin Unit Quantity

一, ELECT PART
1 E1301-041090 CAPACITOR EC V A SAII 100M 16DC T05 PCS 1
2 E1501-001001 RESISTOR CBF H 1/6W 100J T52 PCS 1
3 E1501-001004 RESISTOR CBF H 1/6W 103J T52 PCS 7
4 E2509-094001 DIODE LED A D3.0 GR/RD (LT036 PCS 1
5 E2701-023002 DETECTOR IR AT138A PCS 1
6 E3101-171001 PLUG V HX2007(PH)-12A P2.0 12P WHT PCS 1
7 E3204-023001 SOCKET AC HF-301 FOR 26LA PCS 1
8 E3403-001001 TUBE SHRINKABLE D30.0 BLK 600V M 0.04
9 E3403-004001 TUBE SUMITUBE D5.0 BLK 600V M 0.105
10 E3403-005001 TUBE SHRINKABLE D20.0 BLK M 0.03
11 E3421-229007 WIRE ASSY 1H3.96-2KN3 0N2 L400 CJ PCS 1
12 E3421-925029 WIRE ASSY PH2.0-12Y/12Y L=550MM KEY PCS 1
13 E3421-925030 WIRE ASSY PH2.0-8Y/8Y 5V/12V L=220 PCS 1
14 E3421-925031 WIRE ASSY PH2.0-5Y/5Y L=250MM 5VSB PCS 1
15 E3421-925032 WIRE ASSY PH2.0-4Y/4Y L=450MM AMP2 PCS 1
16 E3421-925033 WIRE ASSY PH2.0-12Y/12Y L=250MM IN PCS 1
17 E3421-925034 WIRE ASSY PH2.0-10Y/10Y L=250MM INV PCS 1
18 E3421-925035 WIRE ASSY PH2.0-4Y/4Y L=100MM AUDI PCS 1
19 E3421-925036 WIRE ASSY PH2.0-12Y/12Y L=280MM TU PCS 1
20 E3421-925037 WIRE ASSY TTJC3-2Y L=450MM SPK-R PCS 1
21 E3421-925038 WIRE ASSY TJC3-2Y L=850MM SPK-L PCS 1
22 E3421-925039 WIRE ASSY LVDS L=300MM 30P/30P PCS 1
23 E3421-925040 WIRE ASSY TJC3-6Y/6Y L=350MM POWER PCS 1
24 E3421-941001 WIRE ASSY 1KN5-2TKN0 45 L110 BJ PCS 1
25 E3451-000406 WIRE WD 1672#20 RED L=250MM PCS 1
26 E3451-000407 WIRE WD 1672#20 BLACK L=250MM PCS 1
27 E3731-052020 PCB KEY V0 124.5X20.5MM W 1.6MM 2 LA PCS 1
28 E4101-027001 SWITCH POW MR-22-N2BB-F2 ROCKET PCS 1
29 E4102-044001 SWITCH TACT H 6*6*5W PCS 7
30 E4801-123001 SPEAKER 8 OHM 10W D2.5X4" YDT711 (SG PCS 2
31 E6203-024001 DISPLAY LCD 27" V270W1-L03 PCS 1
32 E7802-004001 PCB ASSY MAIN BOARD FOR 27" LCD MICO SET 1
33 E7802-004002 PCB ASSY POWER200 BOARD FOR 27" LCD SET 1
34 E7802-004003 PCB ASSY TUNER AMP BOARD FOR 27" LCD SET 1
二, MECH PART
1 200-26LA21-04AV CABINET FRONT AKAI BLK LCT2715 (MICO PCS 1
2 202-26LA11-01AV BACK CABINET 26LA A (470+70%) PCS 1
3 206-26LA01-01PV THE BACK COVER SPEAKER 26LA P (470 PCS 2
4 230-26LA11-02RV STAND COVER 26LA BLK LCT2715 R PCS 1
5 269-290803-01S POWER LENS (D) 2908 PCS 1
6 269-290804-01L SENSOR LENS (D) 2908 PCS 1
7 277-26LA01-01S FUNCTION KNOB 26LA PCS 1
8 361-101261-01 CABLE TIE PCS 5
9 370-42D101-01 RUBBER FOOT 20X20X7.0MM 42D1 PCS 4
10 379-972501-01Y SPECIAL RUBBER PARTS SPK 9725 PCS 8
11 379-972502-01Y SPECIAL RUBBER PARTS 9725 PCS 8
12 388-L27AB01-01H POWER PLATE AKAI LC26HAB H PCS 1
13 389-26LA01-07H PVC PLATE AKAI FOR TERMINAL SHEET LC PCS 1
14 389-26LA02-01H OTHER PVC PLATE 26LA PCS 2
15 389-27LA01-01H PVC SHEET FOR BACK CABINET GATE PCS 1
16 423-27LA07-01 STAND SUPPORT PLATE SPCC 27LA PCS 1
17 423-27LA08-01 METAL PLATE FOR STAND SUPPORT PLATE PCS 1
18 423-27LA09-01 METAL PLATE FOR WALL BRACKET 27LA PCS 2
19 426-27LA11-01 SUPPORT BRACKET FOR POWER JACK 27LA PCS 1
20 428-27LA11-01 MAIN METAL PLATE FOR PANEL 27LA PCS 1
21 436-27LA01-01 BACK TERMINAL SHEET 27LA PCS 1
22 449-27LA01-01 METAL PLATE FOR STAND BASE PCS 1
23 481-27LA01-01 SHIELD COVER FOR MAIN PCB 27LA TINPL PCS 1
24 481-27LA02-01 SHIELD COVER FOR POWER PCB 27LA TINP PCS 1
25 486-M32111-01 NAME PLATE M AKAI PCS 1
26 521-100105-01 FELT PAPER 100X10X0.5 PCS 10
27 521-150105-01 FELT PAPER 150X10X0.5 PCS 25
28 563-119- SERIAL NO. LABEL PCS 1
29 579-LC2701-03 UPC LABEL (50X23)MM OF UNIT LCT2715( PCS 1
30 579-LC2702-03 UPC LABEL OF G/B LCT2715 MICO) PCS 2
31 580-L26ABHM-TU01 L IB E FOR AKAI LC26HAB CMO MICO USA PCS 1
32 590-LC2701-03 INSERTION CARD AKAI LC26HAB PCS 1
33 590-LC2701-04 WARRANTY CARD AKAI LCT2715 216X279MM PCS 1
34 601-305008-00 MACH.SCREW CTS 3X8 BZN + PCS 3
35 601-305010-00 MACH.SCREW CTS 3X10 BZN + PCS 5
36 602-305004-10 MACH. SCREW PAN-WASHER M3X4 NIP +H PCS 30
37 602-305008-10 MACH.SCREW WHR 3X8 NIP + PCS 12
38 604-305022-00 MACH. SCREW BINDING M3X22MM B ZNP +H PCS 2
39 604-508022-00 MACH. SCREW BINDING M5X22MM B ZNP +H PCS 8
1 610-300210-10 TS RBD3X10 A NIP +H PCS 11
2 614-300108-10 S-TAP SCREW BID 3.0X8 PCS 4
3 614-400412-10 S-TAP.SCREW BID 4X12 D NIP + PCS 40
4 614-400420-10 S-TAP.SCREW BID 4X20 T NIP + PCS 8
5 615-400414-10 S-TAP.SCREW BWH 4X14 T NIP + PCS 8
6 802-005005-20 TAPE 2S T4000 5X50M RLS 0.0198
三, PACKING
1 300-27AB01-02C POLYFOAM TOP 27AB PCS 1
2 300-27AB02-02C POLYFOAM BOTTOM 27AB PCS 1
3 310-111404-07V POLYBAG 11"X14"X0.04 PCS 1
4 310-453510-07V BAG LAMIFILM PCS 1
5 510-27LA02-03K GIFT BOX AKAI LCT2715 (MICO) K PCS 1
7 E3404-157001 AC CORD UL 1.88M MET-4D7+SJT 16AWG/ PCS 1
8 E7301-010002 BATTERY AAA R03P1.5V <2> PCS 2
9 E7501-051004 REMOTE CRTL FOR 27" USA LCT2716 SET 1
If you forget your V-Chip Password
- Omnipotence V-Chip Password: 8205.
- Press MENU button.
- Press LEFT RIGHT buttons to highlight "MISC" Menu.
- Press Up, Down buttons to highlight "Parentald".
- Press ENTER button to pop up "Input your Password Please".
- Use the Number buttons (0~9) to enter an omnipotence Password.
- Press ENTER button to confirm and your can select "CHANGE PASSWORD".
- Suggest: Change to your familiar Password again.
Software upgrade
- Connect the RS-232C input jack to an external control device (such as a computer) and software upgrade.
Type of connector; D-Sub 9-pin male 1

No. Pin name
5
1 No connection
2 RXD (Receive data)
3 TXD (Transmit data)
4 DTR (DTE side ready)
5 GND
6 DSR (DCE side ready) 9
7 RTS (Ready to send)
8 CTS (Clear to send) 6
9 No Connection
RS-232C configurations
7-wire configuration 3-wire configuration

(Standard RS-232C cable) (Not standard)
PC PDP PC PDP
RXD 2 2 TXD RXD 2 2 TXD

TXD 3 3 RXD TXD 3 3 RXD
GND 5 5 GND GND 5 5 GND
DTR 4 6 DSR DTR 4 4 DTR
DSR 6 4 DTR DSR 6 6 DSR
RTS 7 8 CTS RTS 7 7 RTS
CTS 8 7 RTS CTS 8 8 CTS
D-Sub 9 D-Sub 9 D-Sub 9 D-Sub 9

Software upgrade Process
- Power Switch OFF.

- Connect the serial port of the control device to the RS-232 jack on the LCD-TV back panel.
RS-232C connection cables are not supplied with the LCD-TV.
- Power Switch ON. The power indicator on the front of the panel should now display red, means
that the LCD-TV is in standby mode.
- Copy the software (MTKTOOL) to the computer.
- Open the software (MTKTOOL.EXE)
- Select MTK 8205 and Point "browse" on the interface of the MTKTOOL.exe.
- Select the file which will be update.
- Point "update" on the interface of the MTKTOOL.exe.
- Waiting for the upgrader programing, when it is finished, the bar will display 100%.
- After the upgrader is finished, shut down the power switch, take out the RS-232C connection
after the power indicator is extinguished.
Note: After upgrading, the first time of power on will be some long.

Akai LCT2715 Service Manual

Enviado por

Dados do documento

Descrição original:

Título original

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

Akai LCT2715 Service Manual

Enviado por

Direitos autorais:

Formatos disponíveis

SERVICE MANUAL

The l ig h tn i ng fla sh w i th arro wh e ad symb ol ,

The excla mati on po i nt wi thi n a n e q ui l ate ra l

PRECAUTIONS DURING SERVICING WARNING:

Goo d ea rth grou nd Pl ace this pro be

Model No. : LC27HAB

BOM No. : LC27HABCUSXM1-A01

Artwork Ass'y No. : 580-L26ABHM-TU02L

Description : AKAL LCD TV 26” NTSC AC100V-240 V AC USA

Checked By: Electronic Engineer

Approved By: Engineering Manager

Approved By: PM Department Head

DOC Rev The Latest Revision Details DATE

Stereo Decode MTS with SAP

1.6 Support the Signal Mode

1.7 HDTV Mode (YPbPr)

1) 480i 15.734 59.94 13.50

7. Safety standard UL/FCC/cUL

7 AGC static characteristic Accept. Picture/Sound repr. 90 ≥90 dBuV

15 Color White XW Full Pattern 0.295 0.295±0.02

22 Max Audio Output Power 7×2 ≥5.0×2 W

23 Audio output power 1KHz 10% THD 6×2 ≥4.0×2 W

32 Video input level 1.0 1±0.3 Vpp

Keypad LVDS SIGNAL LVDS PANEL

MT8205P1V3.2 Rev History P# Date

V0.1 1.FIRST VERSION 2004/11/29

2. LED_RED/GRN CIRCUIT CHANGE

12. AUDIO / VIDEO IN CIRCUIT 1

SOT23/SMD 4.7k SCL

+12V For Tuner

TxD 3 C220UF16V/D6H11 0.1uF

RS-232 4x1 W/HOUSING

Power ON alive source

L107 D2 L10 R325

RXD CVBS1+ CVBS1+ 12

MT8205 ANALOG DECOUPLING

ADCPLLVDD GND GND C11 C12

CE23 FB C13 CB15 FB C14 CB16

ADCVDD C18 CB20 APLL_CAP ANALOGVDD

ADC_VDD AV33 C22 CB23

MT8205 DIGITAL POWER & DECOUPLING

0603 PUT ON NEARLY BGA

CB68 C29 C30 C31 C32 C33 C34

F_A[8..21] F_A[8..21] 3,7

SDV25 SDV25 U14

RN13 47x4 75x4

22x4 D_DQS2 R65 75 DEL

A_DQM1 R73 22 D_DQM1

C48 C49 C50 C51 C52 C53 C54 C55

1 CB125 CB126 CB127 CB128 CB129 CB130 CB131 CB124 1

CB157 R115 R116

VGASDA R110 100 VGA_SDA

R1 RCA5/9P/Y R19 0 CB_GND

PWM1 DACLRC WM8776

PANEL INVERTER POWER

OBO5 L86 FB CH+ 7 5

R14 R13 R4 510 LED_GRN 10 8

10K 10K UP1_2 11 9

DV33A BEAD/SMD/1206 BEAD/SMD/1206

2nd SIF OUT

AF1_IN AF1 TU_12V SIF_12V

+ CE8 CB6 + CE9 CB7

_General Description ______________Features