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Data Sheet
Description Features
The ADNS-9500 LaserStream gaming sensor comprises x Small form factor chip-on-board package
of sensor and VCSEL in a single chip-on-board (COB) x Dual power supply selections, 3V or 5V
package. ADNS-9500 provides enhanced features like pro-
grammable frame rate, programmable resolution, config- x VDDIO range: 1.65 – 3.3V
urable sleep and wake up time to suit various PC gamers’ x 16-bits motion data registers
preferences. x High speed motion detection at 150ips and acceleration
The advanced class of VCSEL was engineered by Avago up to 30g
Technologies to provide a laser diode with a single longi- x Advanced technology 832-865nm wavelength VCSEL
tudinal and a single transverse mode.
x Single mode lasing
This LaserStream gaming sensor is in 16-pin integrated x No laser power calibration needed
chip-on-board (COB) package. It is designed to be used
with ADNS-6190-002 small form factor (SFF) gaming laser x Compliance to IEC/EN 60825-1 Eye Safety
lens to achieve the optimum performance featured in this – Class 1 laser power output level
document. These parts provide a complete and compact – On-chip laser fault detect circuitry
navigation system without moving part and laser calibra- x Self-adjusting frame rate for optimum performance
tion process is NOT required in the complete mouse form, x Motion detect pin output
thus facilitating high volume assembly.
x Internal oscillator – no external clock input needed
Theory of Operation x Enhanced Programmability
The sensor is based on LaserStream technology, which – Frame rate up to 11,750 fps
measures changes in position by optically acquiring – 1 to 5 mm lift detection
sequential surface images (frames) and mathematically – Resolution up to 5000cpi with ~90cpi step
determining the direction and magnitude of movement. – X and Y axes independent resolution setting
It contains an Image Acquisition System (IAS), a Digital – Register enabled Rest Modes
Signal Processor (DSP), and a four wire serial port. The – Sleep and wake up times
IAS acquires microscopic surface images via the lens and
illumination system. These images are processed by the
Applications
DSP to determine the direction and distance of motion. x Corded and cordless gaming laser mice
The DSP calculates the 'x and 'y relative displacement x Optical trackballs
values. An external microcontroller reads the 'x and 'y
information from the sensor serial port. The microcon- x Motion input devices
troller then translates the data into PS2, USB, or RF signals
before sending them to the host PC or game console.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Pinout of ADNS-9500 Optical Mouse Sensor
Pin No Pin Name for 5V mode Pin Name for 3V mode Description
1 +VCSEL +VCSEL Positive Terminal Of VCSEL
2 LASER_NEN LASER_NEN LASER Enable (Active Low Output)
3 NCS NCS Chip Select (Active Low Input)
4 MISO MISO Serial Data Output (Master In/Slave Out)
5 SCLK SCLK Serial Clock Input
6 MOSI MOSI Serial Data Input (Master Out/Slave In)
7 MOTION MOTION Motion Detect (Active Low Output)
8 XYLASER XYLASER Laser Current Output Control
9 VDD5 VDD3 5V input for 5V mode
3V Input for 3V mode
10 PWR_OPT (GND) PWR_OPT (VDD3) Power Option:
Connect to GND for 5V Mode
Connect to VDD3 for 3V Mode
11 GND GND Analog Ground
12 REFB VDD3 3V Regulator Output for 5V Mode
3V Input for 3V Mode
13 REFA REFA 1.8V Regulator Output
14 DGND DGND Digital Ground
15 VDDIO VDDIO IO Voltage Input (1.65 - 3.3V)
16 -VCSEL -VCSEL Negative Terminal Of VCSEL
1 16
2 15
3 14
4 13
5 12
6 11
7 10
8 9
W = Subcon Code
XXYY = Date Code
Z = Sensor Die Source
V = VCSEL Die Source
2
15.60 ± 0.20 Pin 1
Notes:
1. Dimensions in millimeter
2. Dimension tolerance ±0.1mm unless specified otherwise
3. Coplanarity of leads: 0.15mm
14.40 ± 0.20 6.55 4. Lead pitch tolerance: ±0.15mm
5. Non-cumulative lead pitch tolerance ±0.15mm
6. Maximum flash +0.2mm
7. Lead width: 0.5mm
8. Bracket ( ) indicates reference dimensions
10.29
TOP VIEW
15.60
0.80
5.15 3.70
16 X 0.50
(7.20)
1.78
8.00
(6.30)
2.95 2.55
3.68
(1.57)
0.70
1.23 SECTION A - A
13.45
BOTTOM VIEW
Figure 2. Package outline drawing
3
Overview of Laser Mouse Sensor Assembly
A A
TOP
FRONT RIGHT
SECTION A-A
Note: Dimensions in millimeter and for reference only
Figure 3. 2D Assembly drawing of ADNS-9500 sensor and ADNS-6190-002 lens coupled with PCB and base plate
4
Figure 4. Isometric drawing of ADNS-9500 sensor and ADNS-6190-002 lens
5.02 Pin #1
12.96 0.50
6.30
10.90 12.60
14 X 1.78 16 X n0.80
Optical Center
Figure 5. Recommended PCB mechanical cutouts and spacing
Assembly Recommendation
1. Insert the COB sensor and all other electrical compo- 5. Insert the PCB assembly over the lens onto the base
nents into the application PCB. plate. The sensor package should self-align to the lens.
2. Wave-solder the entire assembly in a no-wash soldering The optical position reference for the PCB is set by the
process utilizing a solder fixture. The solder fixture is base plate and lens. The alignment guide post of the
needed to protect the sensor during the solder process. lens locks the lens and integrated molded lead-frame
The fixture should be designed to expose the sensor DIP sensor together. Note that the PCB motion due to
leads to solder while shielding the optical aperture button presses must be minimized to maintain optical
from direct solder contact. alignment.
3. Place the lens onto the base plate. Care must be taken 6. Optional: The lens can be permanently locked to the
to avoid contamination on the optical surfaces. sensor package by melting the lens’ guide posts over
the sensor with heat staking process.
4. Remove the protective kapton tapes from the optical
aperture of the sensor and VCSEL respectively. Care 7. Install the mouse top case. There must be a feature in
must be taken to keep contaminants from entering the the top case (or other area) to press down onto the
aperture. sensor to ensure the sensor and lenses are interlocked
to the correct vertical height.
5
6
VDD VDD2
J2
1 2
R11 VDD VDD1
2
100k
Q2 10nF 1uF/10V
0R
U2
1
1 8
J1 CS VCC
1 2 6 3
SCK WP
5 7 C12
VCC VCC1 SI HOLD 100nF
R2 2 4
VDD SO VSS NTA4151P
3
0R
C2
25LC040P
10nF C9 C10 C7 C8 VDD1 VDD2
100nF 1uF/10V 4.7uF/10V 100nF
Application Circuits
H1 U3 C15
VDD1 VDD2
R VBUS 1 20R J3
D- R3 EEPROM 1 470pF
6
W 2 20R VCSEL+VE 3 1
R4 16
G D+ 3 VCSEL-VE
U1 2 8
GND
2
B 4 LASER_NEN XYLASER
SHIELD 7 1 SCLK SCLK 5 15
5 VREGIN P0.1/SCLK SCLK VDDIO
8 32 MISO MISO 4 9 VCC1 VDD1
VDD
HEADER 5 VBUS P0.2/MISO MISO VDD3 / VDD5 C20
5 31 MOSI MOSI 6 VCC1 VDD1 C21
R5 R6 D- P0.3/MOSI MOSI
4 30 NCS NCS 3 ADNS-9500 13 J4
0R 0R D+ P0.4/NCS NCS REF A 3.3uF/16V
29 MOTION MOTION 7 12 3 1 100nF
P0.5 MOTION VDD3 / REF B
28
P0.6
2
C3 C11 26 ZB 10
20pF 20pF P1.0 PWR_OPT
11 25 ZA
DGND
GND
P2.7 P1.1 C22
12 24 LEFT C16
P2.6 P1.2
23 RIGHT VCC
P1.3 4.7uF/10V
22 MIDDLE D1 100nF
14
11
P1.4 R12
21 +CPI LED1
P1.5
20 -CPI 470R
P1.6
C8051F347
19
P1.7 YELLOW
9 VDD2
C2CK/RST
10 18 LED1 D2
P3.0/C2D P2.0 R13
17 LED2 LED2
P2.1 C17 C23
16 LED3 470R C18 C19
VDD P2.2
R10 15
P2.3 YELLOW 10uF/10V 10uF/10V
14 100nF 100nF
1 CON1 1k P2.4
13 D3
1 2 VCC P2.5 R14
LED3
3 4
2 470R
5 6 P0.0
27
GND
7 8 P0.7 YELLOW
9 10
3
PIN HEADER 2.54MM10P/D
MCU CPI Indication LED Sensor Block
VDD
JTAG
R1 R7
1k 1k 1 P1
CON2 VDD +CPI 1
+CPI
LEFT 1 2 RIGHT
MIDDLE 3 4 ZA -CPI 1 P2
-CPI
ZB 5 6
7 8 1 P3
VSS
8
C4 C5
1uF/10V 100nF
1
CON3 VDD
LEFT 1 2 RIGHT
MIDDLE 3 4 ZA
ZB 5 6
7 8
8
+CPI
PIN HEADER 2MM8P/D
SW4 VDD VDD VDD
3
1
2 R8 R9 R16
+CPI 10k 10k 10k
P4 1
+CPI
P5 LEFT R IG H T M ID D L E
1 -CPI
-CPI
SW2 SW3 Q1
P6 1 SW5 SW1 3 3
Z-Encoder 3
VSS 3 3 COM
C1 C6 1 C24 1 ZB 2
1 1 B
100nF 100nF 2 100nF 2 ZA 1
2 2 A
-CPI
Left Click Right Click Middle Click
6
7
NO T E : L E D I n d i c a ti o n T a b l e :
R 2 = 8 20kohm V dd = 2. 8V I n di c a ti o n L E D1 ( Pl _0) L E D 2 (P 1_1)
R 2 = 910kohm Vdd = 3. 0V
R 2 = 1 Mohm = 3. 3V O N 3 s ec
1 0 0 0 c pi OFF
1 6 0 0 c pi( d efa ult) OFF OFF
L1
4.7uH
3 2 0 0 c pi O N 3 s ec OFF
VDD3
6 0 0 0 c pi O N 3 s ec O N 3 s ec
1
J4 L o w batter y ( 2 . 2 5 – 2. 3 5 V ) B li nkin g O n 1 s e c , Off 4 s e c OFF
U1
VB AT T P S 6 1070 L o w batter y ( <2 . 2 0 V ) B li nkin g O n 1 s e c , O F F 1 s e c OFF
S W1
1 2 6 1
VBAT SW
3 EN
2
S W S LI DE-S P S T
VOUT 5
4
1
GND
FB
VDD3 VB AT
+ R2
Note: 820K
2 A A B attery 1.5v B TI
R4 R5
C onnec ted in s eries - B AT TE R Y
2
C6 C7 0R Open
4.7uF/16V 4.7uF/16V
2
R3 C 12 C 13 C 14 VDD3
180K 4.7uF/16V 4.7uF/16V 10uF/16V
2
R6
60R4
J7
1
1
J10
2
3
Q2 1 R9 VDD3 VDD3
C 17
MMB T 2222A
C 15 C 16 100nF C 18 C 19 C 20 C 21
2
499R 100nF 22nF 100nF 100nF 22onF
100nF
EI
L E FT C LIC K R IG HT C L IC K C E NTE R C LIC K J 13 R 10 R 11
2 1 U4 ANT E NNA
1K 1K
S W4 T I C C 2510
S W2 S W3
1 2 1 2 1 2
D2 D3 2
AVDD 19
DVV D
1
2
1
J1 Q3 6 P 0_0/AT E S T P 2_3/XOS 32_Q2 17
7 P 0_1 19
NTA4151P P 0_2 P 2_3/XOS C32_Q1 J8
A 1 8
2 Q1 P 0_3 21 2 1
C8 C9 B 2 9 XOS C _Q1
1 3 11 P 0_4 20
1uF/10V C OM VDD3 P 0_5 XOS C _Q2 J9
12
2
100nF VDD3 VDD3 P 0_6 2 1
X1
2
C 10 3 R7 R8 26MHz
C1 C2 1 3
470pF 27K 27K VDD3 1 3
100nF R 12 R 13 13 27
10uF/16V J 12 R BI AS
OR 47K P INR OW_2X5 P 0_7 C28
J UMP E R _3 31 37 C 27
J 11 G ND E xpos ed 22pF 22pF
C4 C3 1 2 R E S E T _N R 16
100nF 1 6 8 3 4 56K
10uF/16V -V C S E L X Y _L AS E R 5 6 Hor izontal S croll (S witc h)
9 VDD5/VDD3 +VC S E L 1 7 8
10 2 9 10
P WR _OP T LAS E R _NE N V AB T
VDD3 12 NCS 3
V DD3/R E FB 4
13 MIS O
R E FA 5
15 S CLK
C 11 VDDIO MOSI 6 R 14
C5 14 7 S OC Debug/flas h
DG ND MOTION 0R
11
100nF G ND
3.3uF/16V
U3 ADNS -9500
1 J5 2 B atter y Low Level Detec tion
VDD3 R 14 on, R 15 off = = E nabl e
J6 R 14 off, R 15 on = = Dis able
1 2
S E NS OR P A R T R 15
Notes: 0R
Us e jumper wir e
7
ADNS-9500
Eye Safety
The ADNS-9500 sensor and the associated components
VDD5/VDD3 NCS in the schematic of Figure 6 are intended to comply with
8
LASER Output Power (LOP) Single Fault Detection
The LOP can be measured for testing purpose as per steps ADNS-9500 sensor is able to detect a short circuit or fault
below. condition at –VCSEL pin, which could lead to excessive
laser output power. A leakage path to ground on this
1. Power up reset the mouse system.
node will trigger the fault detection circuit, which will turn
2. Enable the laser by setting Forced_Disabled bit of off the laser drive current source and set the LASER_NEN
LASER_CTRL0 register (address 0x20) to 0. output high. When used in combination with external
3. Enable the Calibration mode by writing 010b to bits component as shown in the block diagram below, the
[3,2,1] of LASER_CTRL0 register (address 0x20) to set system will prevent excessive laser power for a resistive
the laser to continuous (CW) mode. path at XY_LASER by shutting off the laser. In addition
to the ground path fault detection described above, the
4. Measure the LOP at the navigation surface plane.
fault detection circuit is periodically checking for proper
The pre-calibrated LOP value at typical operating supply operation by internally generating a path to ground with
voltage and temperature of 25 ± 5°C should not exceeding the laser turned off via LASER_NEN. If the –VCSEL pin is
506μW, otherwise the LOPmax limit in the Absolute shorted to VDD5, VDD3, REFA or REFB pin, this test will fail
Maximum Rating is applicable. The following conditions and will be reported as a fault.
apply:
x The system is operated within the recommended
operating supply voltage and temperature range.
x In 3V mode, the VDD3 value is no greater than 300mV
above the pre-calibration voltage of 3.0V. In 5V mode,
REFB should be used to drive the PMOSFET connecting
to VCSEL.
x No allowance for optical power meter accuracy is
assumed.
VDD3/REFB
(Pin 12)
Microcontroller ADNS-9500
S
LASER DRIVER LASER_NEN G P_MOSFET
VDD3
D
fault control
block
470 pF
current set –VCSEL
GND
9
Absolute Maximum Ratings
Parameter Symbol Minimum Maximum Units Notes
Storage Temperature TS -40 85 °C
Lead-Free Solder Temp 260 °C For 7 seconds, 1.8mm below seating plane. Re-
fer to soldering reflow profile in PCB Assembly
& Soldering Considerations Application Note
AN 5023.
Supply Voltage VDD5 -0.5 5.5 V
VDD3 -0.5 3.4 V
VDDIO -0.5 3.4 V
ESD (Human body model) 2 kV All Pins
Input Voltage VIN -0.5 3.4 V All I/O Pins
Laser Output Power LOPmax 716 PW Class 1 Eye Safety Limit
Comments:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are the stress ratings only and functional operation of the device at these or any other condition beyond those indicated for
extended period of time may affect device reliability.
2. The inherent design of this component causes it to be sensitive to electrostatic discharge. The ESD threshold is listed above.
To prevent ESD-induced damage, take adequate ESD precautions when handling this product.
10
Recommended Operating Conditions
Parameter Symbol Minimum Typical Maximum Units Notes
Operating Temperature TA 0 40 °C
Supply voltage VDD5 4.0 5.0 5.25 Volts Including Supply Noise for 5V
mode
VDD3 2.7 2.8 3.3 Volts Including Supply Noise for 3V
mode
VDDIO 1.65 3.3 Volts Including noise.
Power supply rise time VRT5 1 100 ms 0 to 5.0V for 5V mode
VRT3 1 100 ms 0 to 2.8V for 3V mode
Supply noise (Sinusoidal) VNA 100 mVp-p 50kHz - 50MHz
Serial Port Clock Frequency fSCLK 2 MHz Active drive, 50% duty cycle
Distance from lens reference Z 2.18 2.40 2.62 mm Results in +/- 0.22mm minimum
plane to surface DOF. Refer to Figure 9.
Speed S 150 200 ips inch/sec
Maximum speed performance on
select gaming surfaces.
Acceleration A 30 g In Run mode only
Load Capacitance Cout 100 pF MOTION, MISO
Frame Rate FR 11,750 fps Frame per second
VCSEL Peak Wavelength O 832 865 nm
11
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. (Typical values at 25 °C, VDD3 = 2.8V, VDDIO = 1.8V)
Parameter Symbol Minimum Typical Maximum Units Notes
Motion delay after reset tMOT-RST 30 ms From SW_RESET register write to
valid motion, assuming motion is
present
Shutdown tSTDWN 500 ms From Shutdown mode active to low
current
Wake from shutdown tWAKEUP 30 ms From Shutdown mode inactive to
valid motion. Notes: A RESET must
be asserted after a shutdown. Refer
to Shutdown
section, also note tMOT-RST
Forced Rest enable tREST-EN 1 s From RESTEN bits set to low current
Wake from Forced Rest tREST-DIS 1 s From RESTEN bits cleared to valid
motion
MISO rise time tr-MISO 50 200 ns CL = 100pF
MISO fall time tf-MISO 50 200 ns CL = 100pF
MISO delay after SCLK tDLY-MISO 120 ns From SCLK falling edge to MISO data
valid, no load conditions
MISO hold time thold-MISO 200 ns Data held until next falling SCLK
edge
MOSI hold time thold-MOSI 200 ns Amount of time data is valid after
SCLK rising edge
MOSI setup time tsetup-MOSI 120 ns From data valid to SCLK rising edge
SPI time between tSWW 120 Ps From rising SCLK for last bit of the
write commands first data byte, to rising SCLK for last
bit of the second data byte.
SPI time between write and tSWR 120 Ps From rising SCLK for last bit of the
read commands first data byte, to rising SCLK for last
bit of the second address byte.
SPI time between read and tSRW 20 Ps From rising SCLK for last bit of the
subsequent commands tSRR first data byte, to falling SCLK for the
first bit of the address byte of the
next command.
SPI read address-data delay tSRAD 100 Ps From rising SCLK for last bit of the
address byte, to falling SCLK for first
bit of data being read.
NCS inactive after motion tBEXIT 500 ns Minimum NCS inactive time after
burst motion burst before next SPI usage
NCS to SCLK active tNCS-SCLK 120 ns From last NCS falling edge to first
SCLK rising edge
SCLK to NCS inactive tSCLK-NCS 120 ns From last SCLK rising edge to NCS ris-
(for read operation) ing edge, for valid MISO data transfer
SCLK to NCS inactive tSCLK-NCS 20 us From last SCLK rising edge to NCS ris-
(for write operation) ing edge, for valid MOSI data transfer
NCS to MISO high-Z tNCS-MISO 500 ns From NCS rising edge to MISO high-Z
state
MOTION rise time tr-MOTION 50 200 ns CL = 100pF
MOTION fall time tf-MOTION 50 200 ns CL = 100pF
Transient Supply Current IDDT5 90 mA Max supply current during a VDD5
ramps from 0 to 5.0V
IDDT3 65 mA Max supply current during a VDD3
ramps from 0 to 2.8V
12
DC Electrical Specifications
Electrical Characteristics over recommended operating conditions.
For 3V mode, Typical values at 25°C, VDD = 2.8 V, VDDIO = 2.8V. For 5V mode, Typical values at 25°C, VDD = 5.0 V, VDDIO = REFB
13
Sensor’s Typical Performance Characteristics
Resolution Vs. Z
Straight Line At 45 Degrees, Path Length = 4 inches; Speed = 6 ips ; Resolution = 1600cpi
1800
White Paper
1600
1400 Photo Paper
Resolution (cpi)
1200 Manila
1000
Spruce Wood
800
600 Black Formica
400 White Formica
200
White Delrin
0
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
Distance from Lens Reference Plane to Navigation Surface, Z (mm)
Figure 10. Mean Resolution vs. Z at default resolution at 1600cpi
25 Photo Paper
20 Manila
15 Spruce Wood
10 Black Formica
White Formica
5
White Delrin
0
1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4
Distance from Lens Reference Plane to Navigation Surface, Z (mm)
Figure 11. Average Error vs. Distance at default resolution at 1600cpi (mm)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
400 450 500 550 600 650 700 750 800 850 900 950 1000
Wavelength (nm)
Figure 12. Wavelength Responsivity
14
Synchronous Serial Port Chip Select Operation
The synchronous serial port is used to set and read param- The serial port is activated after NCS goes low. If NCS is
eters in the ADNS-9500 Sensor, and to read out the motion raised during a transaction, the entire transaction is
information. The serial port is also used to load PROM data aborted and the serial port will be reset. This is true for all
into the ADNS-9500 Sensor. transactions including PROM download. After a transac-
tion is aborted, the normal address-to-data or transaction-
The port is a four wire port. The host micro-controller
to-transaction delay is still required before beginning the
always initiates communication; the ADNS-9500 Sensor
next transaction. To improve communication reliability,
never initiates data transfers. SCLK, MOSI, and NCS may be
all serial transactions should be framed by NCS. In other
driven directly by a micro-controller. The port pins may be
words, the port should not remain enabled during periods
shared with other SPI slave devices. When the NCS pin is
of non-use because ESD and EFT/B events could be inter-
high, the inputs are ignored and the output is tri-stated.
preted as serial communication and put the chip into an
The lines that comprise the SPI port are: unknown state. In addition, NCS must be raised after each
burst-mode transaction is complete to terminate burst-
SCLK: Clock input. It is always generated by the master
mode. The port is not available for further use until burst-
(the micro-controller).
mode is terminated.
MOSI: Input data. (Master Out/Slave In)
Write Operation
MISO: Output data. (Master In/Slave Out)
Write operation, defined as data going from the micro-
NCS: Chip select input (active low). NCS needs to be low controller to the ADNS-9500 Sensor, is always initiated by
to activate the serial port; otherwise, MISO will be high the micro-controller and consists of two bytes. The first
Z, and MOSI & SCLK will be ignored. NCS can also be used byte contains the address (seven bits) and has a “1” as its
to reset the serial port in case of an error. MSB to indicate data direction. The second byte contains
the data. The ADNS-9500 Sensor reads MOSI on rising
Motion Pin edges of SCLK.
The motion pin is an active low output that signals the
micro-controller when motion has occurred. The motion
pin is lowered whenever the motion bit is set; in other
words, whenever there is data in the Delta_X_L, Delta_XH,
Delta_Y_L or Delta_Y_H registers. Clearing the motion
bit (by reading Delta_X_L, Delta_XH, Delta_Y_L and
Delta_Y_H, or writing to the Motion register) will put the
motion pin high.
NCS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2
SCLK
MOSI 1 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 A6
MISO
SCLK
MOSI
tHold,MOSI
tsetup , MOSI
15
Read Operation
A read operation, defined as data going from the ADNS-9500 Sensor to the micro-controller, is always initiated by the
micro-controller and consists of two bytes. The first byte contains the address, is sent by the micro-controller over MOSI,
and has a “0” as its MSB to indicate data direction. The second byte contains the data and is driven by the ADNS-9500
Sensor over MISO. The sensor outputs MISO bits on falling edges of SCLK and samples MOSI bits on every rising edge of
SCLK.
NCS
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Cycle #
SCLK
MOSI 0 A6 A5 A4 A3 A2 A1 A0
MISO D7 D6 D5 D4 D3 D2 D1 D0
tSRAD delay
Figure 15. Read Operation
SCLK
NOTE:
tHOLD-MISO
tDLY-MISO The minimum high state of SCLK is also the minimum MISO data hold
time of the ADNS-9500 Sensor. Since the falling edge of SCLK is actually
MISO the start of the next read or write command, the ADNS-9500 Sensor will
D0
hold the state of data on MISO until the falling edge of SCLK.
SCLK
Address Data Address Data
If the rising edge of the SCLK for the last data bit of the second write command occurs before the tsww delay, then the
first write command may not complete correctly.
tSWR
SCLK
Address Data Address
If the rising edge of SCLK for the last address bit of the read command occurs before the tswr required delay, the write
command may not complete correctly.
16
tSRW & tSRR
tSRAD for read
SCLK
Address Data Address
During a read operation SCLK should be delayed at least Motion Burst Read
tSRAD after the last address data bit to ensure that the
Sensor has time to prepare the requested data. Reading the Motion_Burst register activates this mode.
The ADNS-9500 sensor will respond with the contents
The falling edge of SCLK for the first address bit of either of the Motion, Observation, Delta_X_L, Delta_X_H,
the read or write command must be at least TSRR or Delta_Y_L, Delta_Y_H, Pixel Statistic, Shutter and Frame
TSRW after the last SCLK rising edge of the last data bit period registers in that order. After sending the register
of the previous read operation. In addition, during a read address, the micro-controller must wait one frame, and
operation SCLK should be delayed after the last address then begin reading data. All data bits can be read with
data bit to ensure that the ADNS-9500 Sensor has time to no delay between bytes by driving SCLK at the normal
prepare the requested data. rate. The data are latched into the output buffer after the
last address bit is received. After the burst transmission is
Burst Mode Operation complete, the micro-controller must raise the NCS line for
Burst mode is a special serial port operation mode which at least tBEXIT to terminate burst mode. The serial port is
may be used to reduce the serial transaction time for three not available for use until it is reset with NCS, even for a
predefined operations: motion read, PROM download second burst transmission.
and frame capture. The speed improvement is achieved
by continuous data clocking to or from multiple registers
without the need to specify the register address, and
by not requiring the normal delay period between data
bytes.
tSRAD
SCLK
Motion_Burst Register Address Read First Byte
17
Procedure to start motion burst: SROM Download
1. Lower NCS This function is used to load the Avago supplied firmware
2. Send 0x50 to Motion_Burst register. file contents into the ADNS-9500 after sensor power up
sequence. The firmware file is an ASCII text file. There are
3. Wait for one frame. (This only applicable in Run mode
2 methods of SROM downloading in ADNS-9500:1.5K and
for wakeup but not require for rest mode)
3K bytes. 1.5K SROM download will only download 1.5K
4. Start reading SPI Data continuously up to 14bytes. bytes data into the first half of SROM and leave the rest
Motion burst may be terminated by pulling NCS high empty, while 3K SROM download will download the full
for at least tBEXIT. 3K bytes data into SROM. They can be selected through
5. To read new motion burst data, repeating from step 1. Configuration_IV register, where default setting is 1.5K
SROM download. In the current version of ADNS-9500
6. Write any value to Motion register (address 0x02) to
sensor, 3K bytes of SROM will be used.
clear any residual motion.
SROM download procedure:
Motion burst reporting:
BYTE [00] = Motion 1. Select the 3K bytes SROM size at Configuration_IV
BYTE [01] = Observation register, address 0x39
BYTE [02] = Delta_X_L 2. Write 0x1d to SROM_Enable register for initializing
BYTE [03] = Delta_X_H 3. Wait for one frame
BYTE [04] = Delta_Y_L
BYTE [05] = Delta_Y_H 4. Write 0x18 to SROM_Enable register again to start
BYTE [06] = SQUAL SROM downloading
BYTE [07] = Pixel_Sum 5. Write SROM file into SROM_Load_Burst register, 1st data
BYTE [08] = Maximum_Pixel must start with SROM_Load_Burst register address. All
BYTE [09] = Minimum_Pixel the SROM data must be downloaded before SROM
BYTE [10] = Shutter_Upper start running.
BYTE [11] = Shutter_Lower
BYTE [12] = Frame_Period_Upper
BYTE [13] = Frame_Period_Lower
Note: In rest mode, motion burst data is always available or in other
words, motion burst data can be read from Motion_Burst register even
in rest modes.
2 reg writes, see text SROM_Enable reg write SROM_Load reg write
MOSI address key data address byte 1 byte 2 byte 3070 address
≥ 1 frame enter burst
period mode
SCLK
tNCS-SCLK
>120ns ≥10 Ps
≥120 Ps ≥15 Ps ≥15 Ps ≥160 Ps
Soonest to read SROM_ID
Figure 21. SROM Download Burst Mode
18
Frame Capture
This is a fast way to download a full array of pixel values Procedure of Frame Capture:
from a single frame. This mode disables navigation and 1. Reset the chip by writing 0x5a to Power_Up_Reset
overwrites any downloaded firmware. A hardware reset register (address 0x3a).
is required to restore navigation, and the SROM firmware
must be reloaded. 2. Enable laser by setting Forced_Disable bit (bit-0) of
LASER_CTRL0 register to 0.
To trigger the capture, write to the Frame_Capture register.
3. Write 0x93 to Frame_Capture register.
The next available complete 1 frame image will be stored
to memory. The data are retrieved by reading the Pixel_ 4. Write 0xc5 to Frame_Capture register.
Burst register once using the normal read method, after 5. Wait for two frames.
which the remaining bytes are clocked out by driving
6. Check for first pixel by reading bit zero of Motion
SCLK at the normal rate. If the Pixel_Burst register is read
register. If =1, first pixel is available.
before the data is ready, it will return all zeros.
7. Continue read from Pixel_Burst register until all 900
pixels are transferred.
8. Continue step 3-7 to capture another frame.
Note: Manual reset and SROM download are needed after frame capture
to restore navigation for motion reading.
19
Cable
Top Xray View of Mouse
Positive Y
LB RB
Positive X
1 16
A9500
8 9
last output
29 59 89 119 149 179 209 239 269 299 329 359 389 419 449 479 509 539 569 599 629 659 689 719 749 779 809 839 869 899
28 58 88 118 148 178 208 238 268 298 328 358 388 418 448 478 508 538 568 598 628 658 688 718 748 778 808 838 868 898
27 57 t t t
first output
20
Power Up
The ADNS-9500 Sensor does not perform an internal 5. Read from registers 0x02, 0x03, 0x04, 0x05 and 0x06
power up self-reset; the Power_Up_Reset register must (or read these same 5 bytes from burst motion register)
be written every time power is applied. The appropriate one time regardless of the motion pin state.
sequence is as follows: 6. SROM download.
1. Apply power to VDD5/VDD3 and VDDIO in any order 7. Enable laser by setting Forced_Disable bit (bit-0) of
2. Drive NCS high, and then low to reset the SPI port. LASER_CTRL0 register (address 0x20) to 0.
3. Write 0x5a to Power_Up_Reset register (address 0x3a). During power-up there will be a period of time after the
power supply is high but before any clocks are available.
4. Wait for at least 50ms time.
The table below shows the state of the various pins during
power-up and reset.
Shutdown
The ADNS-9500 can be set in Shutdown mode by writing Pin Status when Shutdown Mode
0xb6 to register 0x3b. The SPI port should not be accessed NCS Functional *1
when Shutdown mode is asserted, except the power-up
MISO Undefined *2
command (writing 0x5a to register 0x3a). (Other ICs on
the same SPI bus can be accessed, as long as the sensor’s SCLK Ignore if NCS = 1 *3
NCS pin is not asserted.) The table below shows the state MOSI Ignore if NCS = 1 *4
of various pins during shutdown. To deassert Shutdown
LASER_NEN High (off )
mode:
MOTION Undefined *2
1. Drive NCS high, then low to reset the SPI port.
*1 NCS pin must be held to 1 (high) if SPI bus is shared with other
2. Write 0x5a to Power_Up_Reset register (address 0x3a). devices. It is recommended to hold to 1 (high) during Power Down
unless powering up the Sensor. It must be held to 0 (low) if the sensor
3. Wait for at least 50ms time. is to be re-powered up from shutdown (writing 0x5a to register
4. Clear observation register. 0x3a).
*2 Depends on last state. MISO should be configured to drive LOW
5. Wait at least one frame and check observation register, during shutdown to meet the low current consumption as specified
Bit[5:0] must be set. in the datasheet. This can be achieved by reading Inverse_Product_
ID register (address 0x3f ) since the return value (0xcc) on MISO line
6. Read from registers 0x02, 0x03, 0x04, 0x05 and 0x06 ends in a 0 (low state).
(or read these same 5 bytes from burst motion register) *3 SCLK is ignored, if NCS is 1 (high). It is functional if NCS is 0 (low).
one time regardless of the motion pin state. *4 MOSI is ignored, if NCS is 1 (high). If NCS is 0 (low), any command
present on the MOSI pin will be ignored except power-up command
7. SROM download. (writing 0x5a to register 0x3a).
21
Registers
The ADNS-9500 registers are accessible via the serial port. The registers are used to read motion data and status as well
as to set the device configuration.
Address Register Read/Write Default Value
0x00 Product_ID R 0x33
0x01 Revision_ID R 0x03
0x02 Motion R 0x00
0x03 Delta_X_L R 0x00
0x04 Delta_X_H R 0x00
0x05 Delta_Y_L R 0x00
0x06 Delta_Y_H R 0x00
0x07 SQUAL R 0x00
0x08 Pixel_Sum R 0x00
0x09 Maximum_Pixel R 0x00
0x0a Minimum_Pixel R 0x00
0x0b Shutter_Lower R 0x20
0x0c Shutter_Upper R 0x4e
0x0d Frame_Period_Lower R 0xc0
0x0e Frame_Period_Upper R 0x5d
0x0f Configuration_I R/W 0x12
0x10 Configuration_II R/W 0x00
0x12 Frame_Capture R/W 0x00
0x13 SROM_Enable W 0x00
0x14 Run_Downshift R/W 0x32
0x15 Rest1_Rate R/W 0x01
0x16 Rest1_Downshift R/W 0x1f
0x17 Rest2_Rate R/W 0x09
0x18 Rest2_Downshift R/W 0xbc
0x19 Rest3_Rate R/W 0x31
0x1a Frame_Period_Max_Bound_Lower R/W 0xc0
0x1b Frame_Period_Max_Bound_Upper R/W 0x5d
0x1c Frame_Period_Min_Bound_Lower R/W 0xa0
0x1d Frame_Period_Min_Bound_Upper R/W 0x0f
0x1e Shutter_Max_Bound_Lower R/W 0x20
0x1f Shutter_Max_Bound_Upper R/W 0x4e
0x20 LASER_CTRL0 R/W 0x01
0x21- 0x23 Reserved
0x24 Observation R/W 0x00
0x25 Data_Out_Lower R Undefined
0x26 Data_Out_Upper R Undefined
0x27 - 0x29 Reserved
0x2a SROM_ID R 0x00
0x2e Lift_Detection_Thr R/W 0x10
0x2f Configuration_V R/W 0x12
0x30 - 0x38 Reserved
0x39 Configuration_IV R/W 0x00
0x3a Power_Up_Reset W NA
0x3b Shutdown W Undefined
0x3c - 0x3e Reserved
0x3f Inverse_Product_ID R 0xcc
0x40 – 0x4f Reserved
0x50 Motion_Burst R 0x00
0x62 SROM_Load_Burst W Undefined
0x64 Pixel_Burst R 0x00
22
Product_ID Address: 0x00
Access: Read Only Reset Value: 0x33
Bit 7 6 5 4 3 2 1 0
Field PID7 PID6 PID5 PID4 PID3 PID2 PID1 PID0
Bit 7 6 5 4 3 2 1 0
Field RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0
23
Motion Address: 0x02
Access: Read Only Reset Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field MOT FAULT LP_Valid Reserved Reserved OP_Mode1 OP_Mode2 FRAME_
Pix_First
24
Delta_X_L Address: 0x03
Access: Read Only Reset Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field X7 X6 X5 X4 X3 X2 X1 X0
Bit 7 6 5 4 3 2 1 0
Field X15 X14 X13 X12 X11 X10 X9 X8
Bit 7 6 5 4 3 2 1 0
Field Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Bit 7 6 5 4 3 2 1 0
Field Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8
NOTES: Avago RECOMMENDS that registers 0x02, 0x03, 0x04, 0x05 and 0x06 to be read sequentially.
25
SQUAL Address: 0x07
Access: Read Only Reset Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field SQ7 SQ6 SQ5 SQ4 SQ3 SQ2 SQ1 SQ0
150
SQUAL (Count)
100
50
0
1 51 101 151 201 251 301 351 401 451 501 551 601 651 701 751
Count
Figure 24. SQUAL Values at 1600cpi (White Paper)
80
60
40
20
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
Distance from Lens Reference Plane to Navigation Surface (mm)
Figure 25. Mean SQUAL vs. Z (White Paper)
26
Pixel_Sum Address: 0x08
Access: Read Only Reset Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Bit 7 6 5 4 3 2 1 0
Field MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0
Bit 7 6 5 4 3 2 1 0
Field MinP7 MinP6 MinP5 MinP4 MinP3 MinP2 MinP1 MinP0
Bit 7 6 5 4 3 2 1 0
Field S7 S6 S5 S4 S3 S2 S1 S0
27
Shutter_Upper Address: 0x0C
Access: Read Only Reset Value: 0x4e
Bit 7 6 5 4 3 2 1 0
Field S15 S14 S13 S12 S11 S10 S9 S8
100
80
Shutter Value
60
40
20
0
1 51 101 151 201 251 301 351 401 451 501 551 601 651 701 751
Count
Figure 26. Shutter Values at 5000cpi (White Paper)
150
100
50
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
Distance from Lens Reference Plane to Navigation Surface, Z (mm)
Figure 27. Mean Shutter vs. Z (White Paper)
28
Frame_Period_Lower Address: 0x0D
Access: Read Only Reset Value: 0xc0
Bit 7 6 5 4 3 2 1 0
Field FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0
Bit 7 6 5 4 3 2 1 0
Field FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8
Bit 7 6 5 4 3 2 1 0
Field Reserved Reserved RES5 RES4 RES3 RES2 RES1 RES0
Configuration_I Approximate
Register Value Resolution (cpi) Description
0x01 90 Minimum
0x12 1620 Default
0x24 3240
0x38 5040 Maximum
Note: Rpt_Mod bit in Configuration_II register is used to select CPI reporting mode either XY axes resolution setting in sync or independent setting
for X-axis and Y-axis respectively. Refer to Configuration_V register for Y-axis resolution setting.
29
Configuration_II Address: 0x10
Access: R/W Reset Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field F_Rest1 F_Rest0 Rest_En NAGC Fixed_FR Rpt_Mod 0 0
30
Frame_Capture Address: 0x12
Access: R/W Reset Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0
Bit 7 6 5 4 3 2 1 0
Field SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0
Bit 7 6 5 4 3 2 1 0
Field RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
31
Rest1_Rate Address: 0x15
Access: R/W Reset Value: 0x01
Bit 7 6 5 4 3 2 1 0
Field R1R7 R1R6 R1R5 R1R4 R1R3 R1R2 R1R1 R1R0
Bit 7 6 5 4 3 2 1 0
Field R1D7 R1D6 R1D5 R1D4 R1D3 R1D2 R1D1 R1D0
Bit 7 6 5 4 3 2 1 0
Field R2R7 R2R6 R2R5 R2R4 R2R3 R2R2 R2R1 R2R0
32
Rest2_Downshift Address: 0x18
Access: R/W Reset Value: 0xbc
Bit 7 6 5 4 3 2 1 0
Field R2D7 R2D6 R2D5 R2D4 R2D3 R2D2 R2D1 R2D0
Bit 7 6 5 4 3 2 1 0
Field R3R7 R3R6 R3R5 R3R4 R3R3 R3R2 R3R1 R3R0
33
Frame_Period_Max_Bound_Lower Address: 0x1A
Access: R/W Reset Value: 0xc0
Bit 7 6 5 4 3 2 1 0
Field FBM7 FBM6 FBM5 FBM4 FBM3 FBM2 FBM1 FBM0
Bit 7 6 5 4 3 2 1 0
Field FBM15 FBM14 FBM13 FBM12 FBM11 FBM10 FBM9 FBM8
34
Frame_Period_Min_Bound_Lower Address: 0x1C
Access: R/W Reset Value: 0xa0
Bit 7 6 5 4 3 2 1 0
Field FBm7 FBm6 FBm5 FBm4 FBm3 FBm2 FBm1 FBm0
Bit 7 6 5 4 3 2 1 0
Field FBm15 FBm14 FBm13 FBm12 FBm11 FBm10 FBm9 FBm8
35
Shutter_Max_Bound_Lower Address: 0x1E
Access: R/W Reset Value: 0x20
Bit 7 6 5 4 3 2 1 0
Field SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
Bit 7 6 5 4 3 2 1 0
Field SB15 SB14 SB13 SB12 SB11 SB10 SB9 SB8
36
LASER_CTRL0 Address: 0x20
Access: R/W Reset Value: 0x01
Bit 7 6 5 4 3 2 1 0
Field Reserved Reserved Reserved Reserved CW2 CW1 CW0 Force_
Disabled
Bit 7 6 5 4 3 2 1 0
Field OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0
37
Data_Out_Lower Address: 0x25
Access: Read Only Reset Value: Undefined
Bit 7 6 5 4 3 2 1 0
Field DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Bit 7 6 5 4 3 2 1 0
Field DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8
Bit 7 6 5 4 3 2 1 0
Field SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
Bit 7 6 5 4 3 2 1 0
Field Reserve Reserve Reserve LD_Thr4 LD_Thr3 LD_Thr2 LD_Thr1 LD_Thr0
38
Configuration_V Address: 0x2F
Access: R/W Reset Value: 0x12
Bit 7 6 5 4 3 2 1 0
Field ResY7 ResY6 ResY5 ResY4 ResY3 ResY2 ResY1 ResY0
Bit 7 6 5 4 3 2 1 0
Field Reserved Reserved Reserved Reserved Reserved Reserved SROM_Size Reserved
Bit 7 6 5 4 3 2 1 0
Field PUR7 PUR6 PUR5 PUR4 PUR3 PUR2 PUR1 PUR0
Bit 7 6 5 4 3 2 1 0
Field OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0
39
Inverse_Product_ID Address: 0x3F
Access: Read Only Reset Value: 0xcc
Bit 7 6 5 4 3 2 1 0
Field PID7 PID6 PID5 PID4 PID3 PID2 PID1 PID0
Bit 7 6 5 4 3 2 1 0
Field MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0
Bit 7 6 5 4 3 2 1 0
Field SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0
USAGE: The SROM_Load_Burst register is used for high-speed programming SROM from an external PROM or micro-
controller. See SROM Download section for use details.
Bit 7 6 5 4 3 2 1 0
Field PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
AV02-1726EN - December 16, 2009