`~ivjvcbx t Telephone :

wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING
KwgDwb‡Kkb BwÄwbqvwis wefvM
UNIVERSITY OF DHAKA
XvKv wek¦we`¨vjq DHAKA-1000, BANGLADESH
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
E-MAIL: APECE@univdhaka.edu

Ref. No............................ May 16, 2010

Dated, the………………………….

Data Routing Using MUX:

Counter 1 Counter 2
Tens Units Tens Units
BCD BCD BCD BCD
counter counter Clock #1 counter counter Clock #2

COUNTER
SELECT
I1 74ALS157 I0
S
MUX
E (tens)

Za Zb Zc Zd
I1 74ALS157 I0
S
MUX
E (units)

Za Zb Zc Zd

BCD-to-7-segment BCD-to-7-segment
decoder/driver (7447) decoder/driver (7447)

TENS UNITS

LED display LED display

Fig.: System for displaying two multidigit BCD counters one at a time.
Multiplexers can route data from one of several sources to one destination. For example, 74157 multiplexers are
used to select and display the contents of either of two BCD counters using a single set of decoder/drivers and LED
displays.
Each counter consists of two cascaded BCD stages, and each one is driven by its own clock signal. When the
COUTER SELECT line is HIGH, the outputs of counter 1 will be allowed to pass through the multiplexers to the
decoder/drivers to be displayed on the LED readouts. When COUNTER SELECT line is LOW, the outputs of counter
2 will pass through the multiplexers to the displays.
Here the purpose of multiplexing is to time-share the decoder/drivers and display circuits between the two counters
rather than have a separate set of decoder/drivers and displays for each counter. This results –
(I) in a significant saving in the number of wiring connections and
(II) it represents a significant decrease in power consumption.
This technique has the limitation that only one counter’s contents can be displayed at a time.

Lec-02, Pg-01 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
 `~ivjvcbx t Telephone :
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING
KwgDwb‡Kkb BwÄwbqvwis wefvM
UNIVERSITY OF DHAKA
XvKv wek¦we`¨vjq DHAKA-1000, BANGLADESH
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
E-MAIL: APECE@univdhaka.edu

Ref. No............................ May 16, 2010

Dated, the………………………….

Parallel-to-Serial Conversion Using MUX:

I0
X0
I1
X1
I2
X2
I3
X3 74HC151
I4
X4 8-input Z
I5 MUX
X5
I6
X6
I7
X7
Storage E
register
S2 S1 S0

1 1 1
C J J J
B A CLOCK
CLK CLK CLK
1 1 1
K K K

1
CLOCK 0
S0
S1
S2
Z
X0 X1 X2 X3 X4 X5 X6 X7 X0 X1 X2 X3 X4 X5
Fig.: Parallel-to-serial converter and waveforms for X7X6X5X4X3X2X1X0=10110101.
One method for performing parallel-to-serial conversion using a multiplexer is illustrated in the figure.
The data are present in parallel form at the outputs of X register and are fed to the eight-input multiplexer. A three-bit
MOD-8 counter is used to provide the select code bits S2S1S0 so that they cycle through from 000 to 111 as clock
pulses are applied.
The output of the multiplexer will be X0 during the first clock period, X1 during the second clock period, and so on. The
output Z is a waveform that is a serial representation of the parallel input data.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

Lec-02, Pg-02 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)