IP Block Authoring: Clock Issues: - Core Area

IP Block Authoring: Clock Issues
T.Arslan
All rights reserved 2008
Block Area Components
• Core Area
• Power Rails Width
• I/O Pins around the Block
T.Arslan
1
Physical Block Attributes
Block
abstract
Power
rings
Block’s core
(cells 65%
routing 35%) Hierarchical
pin
H
P
L W
Area=(L+2W+2P) * (H+2W+2*P)
T.Arslan
Speed, Power ?
Clocking Strategy
• Clock planning should be employed
early during the design process.
• Based on the analysis of constituent
blocks a global clock frequency need to
be chosen. +
• Selection of appropriate clocking
structure , and whether to
• Use PLLs, and how.
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2
Clock Parameters
• Jitter: uncertainty in clock

• Slew Rate: time from ~10% to ~70% of
clock. CAD tools indicate this as
transition time value. (V/ns)
• Period
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Issues
• INSERTION DELAY (ID): Time

difference between clock edge at the
clock pin (origin) and the destination pin
at the end of the clock structure tree.
• SKEW (S): The difference between the

min and maximum IDs on a clock
structure/tree.
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3
Clocking Structures
•
• …
•
•
•
…
H-tree
Balanced Grid
tree
T.Arslan
Choice of Clocking Structure

Delay
HTree
Grid
BTree
Load
BT Best for Large Load

T.Arslan
HT Best for
4
Clock Tree and Block Hardening
Skew Insertion_delay
•
•
Clock Tree Generation •

Clock Tree:
Buffers/Cells
•
Add cells to Core Cells Need Placement •
+
Optimisation
Block’s core
(cells 65%
routing 35%)
Full Layout
OR
{Accurate Model}
T.Arslan
Producing a Final GDSII
Hierarchical Verilog
DP
Routed DEF
Partitioning
Block 1 Block 2
Top level DEF Lib LEF
Size block + Place Pins SE

Output (DEF)
LEF
Lib LEF SE Place and Route

LEF
Routed DEF Abstracted Creation
DP
T.Arslan
5
Parasitic Extraction
T.Arslan
(1) Extraction Models
PP
uses the Parallel Plate mode for
extraction. This mode gives you the most
control over the extraction, by using the
capacitance and edge capacitance values
from your LEF file in the following
formula:
Capacitance (wire) =
(L*W) + Capacitance + 2 * (L+W) *
EdgeCapacitance (where L=Length and
W=Width)
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6
Extraction Models cont.
VDMF
uses the Van Der Meijs Fokkema (VDMF)
formula mode for extraction. This mode
gives you less control over the extraction
because Report RC will just use the
following formula:
c=e*[(w/h) + 0.77 + 1.06*(w/h)**0.25 +

1.06 * (w/h)**0.5]
In this formula, "e" is the dielectric

constant, "w" is the width of the wire,
"t" is the thickness of the wire, and "h"
is the height of the wire.
T.Arslan
Extraction formats
RSPF
reports in the Reduced Standard Parasitic
Format. This is simply a reduced format, much
more simplified than the more detailed DSPF
report format.
DSPF
reports in the Detailed Standard Parasitic
Format. This format reports every resistor and
capacitor in your design, producing a very
large, detailed report.
GE/SE
reports in the old GE/SE format. This format
used to be called "Standard" and contains the
same information as the new RSPF format, but
presented in a different format.
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7
Hierarchical Parasitic Extraction:
RSPF
-Useful for accurate cross coupling parasitics for crosstalk analysis
-Performed for all routed full chip
For each load, a net is mapped →
For each driver, a net is mapped →
T.Arslan
Hierarchical Paracitic Extraction:

DSPF
•A net Model is
⇒More detailed resistance and capacitance values per wire

⇒Larger File, specifically for long nets
⇒Simulate using Spice
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8
Sample File
*|RSPF 1.5
*|DESIGN "chip"
*|DATE "27 February 2000, 16:40:27"
*|VENDOR "Cadence Design Systems,
Inc."
*|PROGRAM "Silicon Ensemble"
*|VERSION "5.2.9"
*|DIVIDER /
*|DELIMITER :
*|BUSBIT []
*
* Resistance Units : 1 ohms
* Capacitance Units : 1 pico farads
*
*
.SUBCKT chip OUT IN
*
*|GROUND_NET VSS
*
* TIMING.CAPACITANCE.MODEL = PP
*
* rst_s2 is a one-pin net.
*
*|NET CRF/Mem\[10\]\[7\] .012641PF
*
*|DRIVER CRF/Mem\[10\]_reg_7:Q CRF/Mem
\[10\]_reg_7 Q
*|S (CRF/Mem\[10\]_reg_7:Q:OUTP1 0.0
0.0)
*
R2 CRF/Mem\[10\]_reg_7:Q CRF/Mem\[10\]
_reg_7:Q:OUTP1 2.473233
C1 CRF/Mem\[10\]_reg_7:Q:OUTP1 VSS
.012088PF
C2 CRF/Mem\[10\]_reg_7:Q VSS .000553PF
*|LOAD CRF/i_873:A CRF/i_873 A
*|S (CRF/i_873:A:INP1 0.0 0.0)
E1 CRF/i_873:A:INP1 VSS CRF/Mem\[10\]
_reg_7:Q VSS 1.0
R3 CRF/i_873:A:INP1 CRF/i_873:A .032478
C3 CRF/i_873:A VSS 1.0PF
*
*|NET CRF/Mem\[10\]\[6\] .015852PF
T.Arslan
IP Block Authoring: Analogue

and Mixed Block Issues
T.Arslan
9
Floor plan considerations
• Critical analogue components must be placed

far from digital elements.
• Connections to critical nodes should be as
short as possible.
• Crossing between analogue bias lines and
digital buses should be avoided.
• Separate analogue and digital power
• Use guard rings to separate main groups of
certain type
T.Arslan
Shielding and Separation Methods
Analog
Vss metal shielding Digital hndb lndb AB Power
Power rails
Analog hndb lndb lndb

block
hndb hndb hndb

Metal shielding
an
analog block
Separate power for
analog and digital
blocks
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10
Guard Rings & Noise filtering
Analog Noisy signal input

from digital block
Clean signal
block C output after
RC filter
Low pass noise filter
Internal Peripheral
guard ring
T.Arslan
Overall AMS Floorplan
Digital
guard Digital
resistor
capacitor
Resistor guard
Cap guard ring
ring
analog
Analog
guard
ring
T.Arslan
11
AMS Virtual Component Packaging
Package an AMS Block as a VC includes the

generation of the proper views. This involves
generating :
• Layout Abstract view
• Netlist view
• Functional Model of digital interface.
• Static timing model
• Physical block description (GDSII).
⇓
AMS VC
T.Arslan
Layout View Generation
• Involves the generation of an analogue abstract (LEF) block

from the actual layout block.
• This is important in order to do P&R at SYSTEM level.
• This procedure is tool-independent. E.g, AutoAbgen is an
example tool.
• Make sure info such as the following are generated, otherwise
P&R will not complete.
-prBoundry
Block Layout Technology file
-Pin/Connector + Metal type
-routing Track Tool
-.
LEF Block
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12
Netlist View Generation
• This is mainly used for back-end verification when the AMS is

• integrated within the SoC.
• An LVS (Layout Vs. Schematic) verification is usually
performed. This needs both netlist (Spice) and layout data.
• An Extractor Tool , such s Diva, can be used to extract a netlist
from a layout or a schematic.
• Make sure netlist format is correct. Check Transistor, resistor,
Capacitor parameters are consistent with layout.
Schematic /Layout Extractor Technology file
Tool
T.Arslan
Transistor netlist
Functional Model of Digital Interface

Generation
• This is required when a test vector simulation

is carried out at the SoC level of the complete
digital interface circuitry.
• For this a functional model of the digital
interface circuitry is required.
• No tool exists to convert analogue layout to
HDL. So this needs to be done manually.
T.Arslan
13
Static Timing Model Generation
• Generate Spice netlist from layout using

extractor (see earlier).
• Use netlist to generate static timing arcs,
k-factors etc. (Use Pspice,Hspice, or
Spectre).
• Build your Model in the required file
format (Manual Process).
T.Arslan
Generating GDSII Layout View
• GDSII is a layout format that is

universally understood by majority of
tools.
• Use a Layout Format Converter to
convert block layout to GDSII format
(e.g. CIF2GDS2).
T.Arslan
14
IP Block Authoring: Signal
Integrity Issues in
Block Authoring
T.Arslan
Signal and design Integrity in DSM

Block Design
• Timing and Reliability problems at .25 and

.18 micro technologies.
• These effect chip functionality and need to
tackled as early as possible during the design
flow.
⇒
• Main Strategy: detection and prevention early
at the design stage.
• Must be built in to design tools.
T.Arslan
15
Signal and design Integrity in DSM
Block Design
• Signal
-Crosstalk: errors+ Timing
-IR drop: power supplies
• Design
• Electromigration on power wires
• Hot Electron effects on devices
• Wire Self Heat on clocks and signals
T.Arslan
Crosstalk Effects - Errors
If VW (Victim Wire) is 0, a 0 to 1 transition on AW

(Aggressor Wire) will cause A GLITCH ON VW if voltage
change is beyond Threshold Voltage.
Effects:
Failure of dynamic logic AW
static logic will have timing problems
Wire R
Driver R
Grounded C
VW
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16
Crosstalk Effects - Timing Delays
Condition: VW and AW switching at the same time.

Timing on VW depends on: gate + interconnect delay,
behavior of adjacent wires.
Symptom: Inaccurate timing: 3-1diference VW
Result: Design constraints not satisfied.

Wire R
Driver
R Grounded Coupling C
C
AW
T.Arslan
Crosstalk and Delay
• Helpful Glitch: AW and VW switching

at the same time in same direction.
• Unhelpful Glitch: AW and VW
switching at the same time in opposite
direction.
Sketch the profile of the waveforms!
T.Arslan
17
Cross talk Modeling
in TLF and LEF Files
• Crosstalk effect on timing is modeled by

plots of relative delay vs. relative rise
time for different coupling percentages.
• Valid model files:

TLF 4.1
LEF 5.3
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Supply Voltage Drop
Timing depends
on power pin
Voltage Drop
Pad limits
Components with high activity have poor supply hence act slower.
T.Arslan
18
Supply Electromigration
Current limit
related to
Wire width
Pad
High current causes degradation of the wire. This causes failure during the
lifetime of the product.
T.Arslan
Hot Electron Effect on devices
• Electron mobility in the channel will

damage the oxide above.
⇒effects device parameters/size
⇒ device operates out-of

spec,timing changes
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19
Wire Self Heat
•Typically occurs at clock nets and other with high switching frequency.
•A wire (metal) expands and contracts due to switching activity, but oxide
does not.
⇒Wire will break or pass signal with reduced efficiency.
Oxide Metal
T.Arslan
Dealing with Crosstalk within Block
Analysis: Compare slew with that of adjacent cells if not close, then
either:
-insert buffer (with better s-characteristics)
-upsize Rsource
Rwire
Rsource
Cwire
T.Arslan
20
Dealing with Wire Self Heat within Block
Analysis performed during placement:

Average, Peak , and RMS current calculations are compared to AC
current density limits for layers and vias in LEF.
Buffer insertion.
Wide wire routing.
Rwire
Rsource
Cwire
T.Arslan
Post Routing Crosstalk Fix

Wide Space Routing
Shielded
Buffer
Routing
Insertion
Rsource
T.Arslan
21
Hot Electron: Slow input + Large Load
Fixes:
•Downsize effected driver, or
•Upsize driver on upstream logic to speed up input transition time
•insert driver on driver et to reduce output
Sketch the waveform profile !
T.Arslan
Hot Electron: Fast input, Small Load
delete
Fixes:
•Upsize effected driver to reduce input transition rate,
•Remove intermediate buffer on driver net to increase load
capacitance
Sketch the waveform profile !

T.Arslan
22
Conclusions
• There are number of clocking schemes

which could be employed in the SoC
and an individual IP. Balanced Clock
Tree is the most commonly used.
Parameters such as skew are crucial in
designing a clock tree.
T.Arslan
Conclusions
• AMS IP Blocks require special design

features/guidelines.
• IP Blocks targeting smaller DSM
technologies may require special design
features in order to overcome problems
due to SI. Some of these could be solved
with IPO or post-layout modifications.
T.Arslan
23

IP Block Authoring: Clock Issues: - Core Area

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IP Block Authoring: Clock Issues

Block Area Components

• Power Rails Width

• I/O Pins around the Block

• Jitter: uncertainty in clock

• INSERTION DELAY (ID): Time

• SKEW (S): The difference between the

Choice of Clocking Structure

BT Best for Large Load

Clock Tree Generation •

Producing a Final GDSII

Size block + Place Pins SE

Lib LEF SE Place and Route

(1) Extraction Models

c=e*[(w/h) + 0.77 + 1.06*(w/h)**0.25 +

In this formula, "e" is the dielectric

For each load, a net is mapped →

For each driver, a net is mapped →

Hierarchical Paracitic Extraction:

⇒More detailed resistance and capacitance values per wire

⇒Simulate using Spice

IP Block Authoring: Analogue

• Critical analogue components must be placed

Shielding and Separation Methods

Analog hndb lndb lndb

hndb hndb hndb

Analog Noisy signal input

Low pass noise filter

Overall AMS Floorplan

Package an AMS Block as a VC includes the

Layout View Generation

• Involves the generation of an analogue abstract (LEF) block

• This is mainly used for back-end verification when the AMS is

Functional Model of Digital Interface

• This is required when a test vector simulation

• Generate Spice netlist from layout using

Generating GDSII Layout View

• GDSII is a layout format that is

Signal and design Integrity in DSM

• Timing and Reliability problems at .25 and

Crosstalk Effects - Errors

If VW (Victim Wire) is 0, a 0 to 1 transition on AW

static logic will have timing problems

Condition: VW and AW switching at the same time.

Result: Design constraints not satisfied.

Crosstalk and Delay

• Helpful Glitch: AW and VW switching

Sketch the profile of the waveforms!

• Crosstalk effect on timing is modeled by

• Valid model files:

Supply Voltage Drop

Hot Electron Effect on devices

• Electron mobility in the channel will

⇒ device operates out-of

Dealing with Crosstalk within Block

Analysis performed during placement:

Post Routing Crosstalk Fix

Hot Electron: Fast input, Small Load

Sketch the waveform profile !

• There are number of clocking schemes

• AMS IP Blocks require special design

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c=e[(w/h) + 0.77 + 1.06(w/h)**0.25 +