Digital Design, EE240,

Spring 2011

Şenol Mutlu

Department of Electrical and Electronic Engineering

Boğaziçi University
34342 Bebek/Istanbul
Tel: (212) 359-7442, FAX: (212) 287-2465
e-mail: senol.mutlu@boun.edu.tr
Website: http://www.bumems.ee.boun.edu.tr

Şenol Mutlu, EE240, Digital Design 1

 HARDWARE DESCRIPTION
LANGUAGES (HDL)
• HDL are used to describe the hardware for the purpose of
modeling, simulation, testing, design, and documentation.
– Modeling: structure, flow of data, behavior.
– Simulation: verification and test
– Design: synthesis
History of VHDL
• Two widely-used HDLs today
– VHDL
– Verilog HDL (from Cadence, now IEEE standard)
• VHDL - Very High Speed Integrated Circuit (VHSIC)
Hardware Description Language
• VHDL history
– Created by Department of Defense (DOD) to document
military designs for portability
– IEEE standard 1076 (VHDL) in 1987
– Revised IEEE standard 1076 (VHDL) in 1993
– IEEE standard 1164 (object types standard) in 1993
– IEEE standard 1076.3 (synthesis standard) in 1996

Şenol Mutlu, EE240, Digital Design 2

 Basic VHDL Terms: ENTITY
Entity: All designs are expressed in terms of entities. It is the most
basic building block in a design. The entity describes the interface
of the design to the outside world. It specifies the number of ports,
the direction of ports and the type of ports.

a x
b
c ENTITY
d mux
s0
s1

The keyword ENTITY starts the entity statement. The name of the
entity is mux. Six ports are of mode of IN and one port is of mode
OUT. The four data input ports (a,b,c,d) are of type BIT. The two
multiplexer select inputs, s0 and s1 are also of type BIT. The output
port is of type BIT. END keyword ends the entity. A lot more
information can be put into an entity
Adapted from (D.L. Perry, VHDL Programming by Example). Copyright 2002 McGraw-Hill
Şenol Mutlu, EE240, Digital Design 3
 Ports
PORT (in1,in2: IN BIT; out1,out2:OUT BIT);
Port Declaration constitutes the primary content of the Entity Declaration. Each port
represents either external pins of the device, or wires connecting two or more entities
within a complete device. Each port has Port names, Mode (direction), and Type
(kind of values possible).
IN: data flows only INTO this entity, driven by another entity used on right side of assignments.
(z <= a NAND inport_name)
OUT: data flows only OUT of this entity into other entities. It can not be read by its entity (no
internal feedback). It is used on left side of assignments. (outport_name <= x OR y)
BUFFER: data flows only OUT of the entity, into other entities. It can be read by its entity. It
can only have one driver. It can be used on both sides of assignments. (bufport <= z;
IF bufport=„1‟ THEN…)
INOUT: data can flow bidirectionally, either in or out or both. It can be read by its entity. It can
also be driven by external driver. It can be used on both sides of assignments.

Ports are always signals

(object class - others are variables, constants, files)

Types useful for synthesis and simulation : bit, bit_vector, std_logic, std_logic_vector,
std_ulogic, std_ulogic_vector, boolean, integer

Types only useful for simulation: real, time

Şenol Mutlu, EE240, Digital Design 4

 Basic VHDL Terms: ARCHITECTURE
Architecture: It describes the functionality of the entity and
contains statements that describes the behavior of the entity.

The keyword ARCHITECTURE signifies that it describes an architecture of an entity. The

architecture name is dataflow. Note that dataflow is a user defined name of the architecture. It
is not a VHDL term. The architecture is describing the entity called mux.
The area between the keywords ARCHITECTURE and BEGIN is where local signals and
components are declared for later use. Here, signal select is declared as a local integer.
The statement area begins with the keyword BEGIN. All statements between BEGIN and END
are called concurrent statements because they are executed concurrently.
An architecture is always related to an entity. An entity can have
many architectures.
Şenol Mutlu, EE240, Digital Design 5
 ARCHITECTURAL STYLES in VHDL
• Levels of Abstraction (Architectural Styles):
• Structural
– Low level, netlist, component instantiations and wiring
– Essentially the text version of a schematic
– Uses a package of pre-defined lower-level components
– No VHDL Process or concurrent signal assignment statements
– Trivial to synthesize
– Hardest to write and understand (very detailed and low level)
• Dataflow
– Medium level, register-to-register transfers, concurrent execution
– Also called RTL (Register Transfer Level) style
– Clock level timing details are given: Executes in non-zero simulation time
– No VHDL Process
– Multiple concurrent signal assignment statements
– Easy to synthesize well
– Harder to write and understand (like assembly code)
• Behavioral
– High level, algorithmic, sequential execution (order is important)
– Hard to synthesize well
– Easy to write and understand (like high-level language code)
– Executes in zero simulation time

An architecture may be written entirely in one style, or in a mixture of

styles (more common)
Şenol Mutlu, EE240, Digital Design 6
 Structural Architecture Style Example
a[3:0]
4-bit y[3:0]
USE work.gates_pkg.all;
b[3:0] 2-to-1
ARCHITECTURE structural OF entity_mux IS
SIGNAL ta, tb: bit_vector (3 downto 0); mux
SIGNAL seln: bit;
sel
BEGIN seln
u0: and2 PORT MAP (a(3),seln, ta(3)); a(3) ta(3)
u1: and2 PORT MAP (a(2),seln, ta(2)); u0 y(3)
u2: and2 PORT MAP (a(1),seln, ta(1)); a(2) tb(3) u8
u3: and2 PORT MAP (a(0),seln, ta(0)); u1
u4: and2 PORT MAP (b(3),sel, tb(3)); a(1)
u2 ta(2) y(2)
u5: and2 PORT MAP (b(2),sel, tb(2)); tb(2) u9
a(0)
u6: and2 PORT MAP (b(1),sel, tb(1)); u3
u7: and2 PORT MAP (b(0),sel, tb(0)); b(3)
u8: or2 PORT MAP (ta(3), tb(3), y(3)); u4 y(1)
u9: or2 PORT MAP (ta(2), tb(2), y(2)); b(2) ta(1) u10
u10: or2 PORT MAP (ta(1), tb(1), y(1)); u5 tb(1)
u11: or2 PORT MAP (ta(0), tb(0), y(0)); b(1)
u12: not PORT MAP (sel, seln); u6 y(0)
b(0) ta(0) u11
END structural; u7 tb(0)
u12
sel
Şenol Mutlu, EE240, Digital Design 7
 Dataflow Architecture Style Example
ARCHITECTURE boolean_dataflow OF entity_mux IS
BEGIN
y(3) <= (a(3) AND NOT sel) OR (b(3) AND sel);
y(2) <= (a(2) AND NOT sel) OR (b(2) AND sel);
y(1) <= (a(1) AND NOT sel) OR (b(1) AND sel);
y(0) <= (a(0) AND NOT sel) OR (b(0) AND sel);
END boolean_ dataflow ;
Behavioral Architecture Style Example
ARCHITECTURE behavior OF entity_mux IS
BEGIN
mux: PROCESS (a,b,sel)
BEGIN
IF sel = ‘0’ THEN y <= a;
ELSE y <= b;
END IF;
END PROCESS mux;
END behavior;
Şenol Mutlu, EE240, Digital Design 8
 Object Classes
A variable in a software language has a value and it can accept new value through
assignments. Constants have fixed values throughout the program. Since VHDL
has to model timing of a hardware, it also supports signals in addition to variables
and constants. A VHDL object consists of one of the following:
Signals, which represent interconnection wires that connect component instantiation ports
together. Signals have hardware significance and have a time component associated with
them. They can be used inside concurrent and sequential bodies of the VHDL but they can
be only declared in concurrent bodies.
Variables, which are used for intermediate values in the software sense in behavioral
descriptions. They are used for local storage of temporary data, visible only inside a process.
They do not have a time component associated with them. := assignment is used to assign
values. They can only be declared and used in sequential bodies of VHDL like processes,
functions and procedures. They are local to the body which they are declared. Variable
assignments can happen immediately, which makes them inherently more efficient, whereas
signals must be scheduled to occur. Variables take less memory, whereas signals need more
information to allow for scheduling and signal attributes.
Constant, which names specific values.
SIGNAL signal_name : signal_type [:= initial_value];
VARIABLE variable_name {,variable_name} : variable_type[:=value];
CONSTANT constant_name {,constant_name} : type_name[:=value];
Many object names can be declared within the same definition by separating them
with a comma. VARIABLE delay1, delay2, delay3, delay4 : time;
Şenol Mutlu, EE240, Digital Design 9
 Objects in VHDL

BODY

Concurrent Sequential

Object Declare Assign Use Declare Assign Use

Signal YES YES YES NO YES YES

Variable NO NO YES YES YES YES

Constant YES ___ YES YES ___ YES

File YES ___ YES YES ___ YES

Şenol Mutlu, EE240, Digital Design 10

 Data Types
VHDL contains many types
that can be used to create
simple or complex objects.
Also you can define your own
type. To define a new type,
you must create a type
declaration. A type declaration
defines the name of the type
and the range of the type.

Identifiers
Identifiers are the names of things you
create:
signals, variables, constants
architecture names, entity names,
process names, component names

Rules:
Cannot be reserved words First character is letter
Uppercase and lowercase equivalent First and last character NOT underscore
Only letters, numbers, and underscore _ Two underscores in succession illegal

Adapted from (D.L. Perry, VHDL Programming by Example). Copyright 2002 McGraw-Hill
Şenol Mutlu, EE240, Digital Design 11
 VHDL Predefined Types
Predefined integer type: Predefined physical type:
TYPE integer IS RANGE –2147483648 TO 2147483647; TYPE time IS RANGE -2**31-1 TO 2**31-1
UNITS
Predefined floating point type: fs; --femtosecond =10-15 sec
TYPE real IS RANGE -1.0E38 TO 1.0E38; ps = 1000 fs; --picosecond =10-12 sec
ns = 1000 ps; --nanosecond =10-9 sec
Predefined enumeration types: us = 1000 ns; --microsecond =10-6 sec
TYPE bit IS (`0','1'); ms = 1000 us; --millisecond =10-3 sec
TYPE boolean IS (false,true); sec =1000 ms; --second
TYPE severity_level IS (note,warning,error,failure); min =60 sec; --minute
TYPE character IS (`a','b','c',...); hr =60 min; --hour
END UNITS;
Predefined array types:
TYPE string IS ARRAY (positive RANGE <>) OF character;
TYPE bit_vector IS ARRAY (natural RANGE <>) OF bit;

Predefined scalar subtypes:

SUBTYPE natural IS integer RANGE 0 TO 2147483647;
SUBTYPE positive IS integer RANGE 1 TO 2147483647;

STD and IEEE libraries have more defined operators and types.
STD_LOGIC ('U','X','0','1','Z','W','L','H','-') where:
'U' means uninitialized, 'X' means unknown , '0' means low , '1' means high, 'Z' means high impedance,
'W' means weak unknown, 'L' means weak low, 'H' means weak high, '-' means don't care
For XST synthesis, the '0' and 'L' values are treated identically, as are '1' and 'H'. The 'X', and '-' values are
treated as don't care. The 'U' and 'W' values are not accepted by XST. The 'Z' value is treated as high
impedance.
Şenol Mutlu, EE240, Digital Design 12
 VHDL Operators
VHDL can use most of the
operators used in software
languages.

Logical operators can operate

on predefined BIT and
BOOLEAN types. The result is
returned in the same type.

Relational operators return the

result only in BOOLEAN type.
/= means not equal to.

** is used for exponentiation.

ab, a to the power of b.

The concatenation operator, &,

is used to unite two arrays. For
example, if x_byte and y_byte
are 8-bit arrays of BITS . Then:
z_byte <= x_byte & y_byte
results in 16-bit array of BITS.
Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill
Şenol Mutlu, EE240, Digital Design 13
 VHDL Predefined Operators
Binary logical operators: not and or nand nor xor xnor
Operand Type: Bit, Boolean Result Type: Bit, Boolean
Relational operators: = /= < <= > >=
Operand Type: any type Result Type: Boolean
Arithmetic operators: + - * / ** mod rem abs
Operand Type: Integer, real, physical Result Type: Integer, real, physical
Concatenation operator: &
Operand Type: array of any type Result Type: array of any type
Shifts operators: sll srl sla sra rol ror
Operand Type: Any one-dimensional array type with elements of type bit or
boolean Result Type: Same Shift Amount: integer
B=“10010101”
B sll 2 = “01010100” --shift left logical, filled with „0‟
B srl 3 = “00010010” --shift right logical, filled with „0‟
B sla 3 = “10101111” --shift left arithmetic, filled with right bit
B sra 2 = “11100101” --shift right arithmetic, filled with left bit
B rol 3 = “10101100” --rotate left by 3
B ror 5 = “10101100” --rotate right by
VHDL Predefined Function & Procedures
Function now RETURN time;
Function endfile (variable f: IN text) RETURN Boolean;
Procedure read (I: INOUT line; value: OUT bit; good: OUT boolean);
Procedure write (I: INOUT line; value: IN bit; justified: IN side := right; field: IN width :=0);
Şenol Mutlu, EE240, Digital Design 14
 Component Definition Inside Architecture
ARCHITECTURE structural OF sequence_detector IS
COMPONENT
clock_component PORT(en: IN BIT; ck: OUT BIT);
END COMPONENT
COMPONENT
fsm_component PORT(x,y,clk: IN BIT; z: OUT BIT);
END COMPONENT
FOR ALL : clock_component USE ENTITY WORK.clock_comp (structural);
FOR C2 : fsm_component USE ENTITY WORK.fsm_comp (structural);
SIGNAL internal_line: BIT;
BEGIN
c1: clock_component PORT MAP (enable, internal line);
c2: fsm_component PORT MAP (x_in,y_in, internal line, z_out);
END structural;

c1 c2
internal_line z_out
enable en clock_ ck clk z
component fsm_
x_in x component
y_in y
Şenol Mutlu, EE240, Digital Design 15
 Packages
Used for grouping elements like components, subprograms, types so that they can be
shared globally by the design units that specify the usage of that package. It consists
of package declaration and package body. Items declared in the package declaration
section are visible to any design unit that uses the package with a USE clause.
Package declaration: The package declaration can
PACKAGE std_logic_1164 IS contain the following declarations:
TYPE std_ulogic IS ......;  Subprogram declaration
FUNCTION resolved (....) RETURN std_logic Type, subtype declaration
... Constant, deferred constant
END std_logic_1164; declaration
Signal declaration creates a global
Package body: signal
PACKAGE BODY std_logic_1164 IS File declaration
TYPE stdlogic_1d IS ARRAY (std_logic) OF std_ulogic; Alias declaration
CONSTANT .....; Component declaration
FUNCTION resolved (...) RETURN std_logic IS Attribute declaration, a user-
function description defined attribute
END resolved; Attribute specification
... Disconnection specification
END std_logic_1164; Use clause

Şenol Mutlu, EE240, Digital Design 16

 Libraries
Library: set of components (entities and architectures) and packages. It is used for
design organization. It allows sharing of components between designers. It can be
used to group components of standard logic families and categorize special
purpose subprograms and types.
Predefined libraries in VHDL are STD and WORK libraries. STD library contains all
the standard types and utilities like BIT, BIT_VECTOR, TIME …,etc. It also
includes utility functions and procedures to read and write ASCII files. WORK
refers to the root library of the user.
The following first statement makes IEEE library visible to a design. The second
statement makes all declarations of std_logic_1164 package available.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
The following first statement makes all entities and architectures of mylib available to
the design.
LIBRARY mylib;
USE mylib.ALL;
Then configuration statements can be used in the architecture of the design to
specify which architectures the component instances will use.

Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill

Şenol Mutlu, EE240, Digital Design 17
 Things needed for Structural VHDL Design
structural description
Selection of a
component from a
certain library or ENTITY inv IS
PORT (i1 : IN BIT; o1 : OUT BIT)
package.
END inv;
Binding or associating
a component to a ARCHITECTURE single_delay OF inv IS
BEGIN
certain package or
o1 <= NOT i1 AFTER 4 NS;
library.
END single_delay;
Wiring methods
Constructs for
repetitive hardware.

VHDL has the following ENTITY nand2 IS

operators that act on type
bit : not and or nand nor
xor xnor
‟not‟ has the highest
precedence.
‟and‟, ‟or‟, ‟nand‟, ‟nor‟,
‟xor‟, ‟xnor‟ have equal
precedence.
Use () to give precedence.
Şenol Mutlu, EE240, Digital Design
PORT (i1,i2 : IN BIT; o1 : OUT BIT)
END nand2;
ARCHITECTURE single_delay OF nand2 IS
BEGIN
o1 <= i1 NAND i2 AFTER 5 NS;
END single_delay;
Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill
18
 Set-Reset Latch
Because q is defined as
OUT port, it can not be
read. It cannot be used as
an input to any component
and cannot be on the right
hand side of an
ENTITY sr_latch IS PORT (s, r, c : IN BIT; q : OUT BIT); assignment. That is why
END sr_latch; im3 is used as an
intermediate q value.
ARCHITECTURE gate_level OF sr_latch IS
COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); If somehow q and q_bar
END COMPONENT; become same when the
FOR ALL : n2 USE ENTITY WORK.nand2 (fast_single_delay);clock is zero, then this
SIGNAL im1, im2, im3, im4 : BIT; circuit goes into an
BEGIN
oscillation. This can be
g1 : n2 PORT MAP (s, c, im1);
g2 : n2 PORT MAP (r, c, im2); remedied by making the
g3 : n2 PORT MAP (im1, im4, im3); delay of g3 different.
g4 : n2 PORT MAP (im3, im2, im4);
q <= im3;
END gate_level;

Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill

Şenol Mutlu, EE240, Digital Design 19
 Set-Reset Latch With Different Delays
ARCHITECTURE
fast_single_delay OF nand2 IS
BEGIN
o1 <= i1 NAND i2 AFTER 3 NS;
END fast_single_delay;

ARCHITECTURE gate_level OF sr_flipflop IS

COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT);
END COMPONENT;
FOR g1, g3 : n2 USE ENTITY WORK.nand2 (fast_single_delay);
FOR g2, g4 : n2 USE ENTITY WORK.nand2 (single_delay);
SIGNAL im1, im2, im3, im4 : BIT;
BEGIN
g1 : n2 PORT MAP (s, c, im1);
g3 : n2 PORT MAP (im1, im4, im3);
g2 : n2 PORT MAP (r, c, im2);
g4 : n2 PORT MAP (im3, im2, im4);
q <= im3;
END gate_level; Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill
Şenol Mutlu, EE240, Digital Design 20
 Dataflow Description in VHDL
Dataflow or register transfer level (RTL) description of a hardware in VHDL is in-
between structural and behavioral descriptions. Descriptions in this level specify
the flow of data through registers and buses. The flow is controlled by external
signals, which can be generated by other hardware.

Data in
Register Register
Data out
Register
Combinational Transfer Level
logic
CLK CLK
(RTL)
Clock description

Signal assignments are the primary constructs of VHDL in dataflow descriptions.

These assignments allow controlled movement of data through registers and
buses. These assignments used for explicit clock control and handshaking can
be divided into three:
Conditional Selected Guarded

Şenol Mutlu, EE240, Digital Design Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill 21
 Conditional Signal Assignment

out <= data1 AFTER tp WHEN select1 ELSE

data2 AFTER tp WHEN select2 ELSE
‘X’ AFTER tp;

Multiplexing and Data Selection

There are various ways to select and
place data on registers and buses.
The simplest form is a multiplexer,
shown on the right.
Other form is to use wired
connections of tri-state gate
outputs and parallel connection of
MOS transmission gates.

Şenol Mutlu, EE240, Digital Design 22

 General Multiplexing Example: Selected Signal
Assignment
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux_8_to_1 IS
PORT (i7, i6, i5, i4, i3, i2, i1, i0 : IN std_logic;
s7, s6, s5, s4, s3, s2, s1, s0 : IN std_logic;
z : OUT std_logic );
END mux_8_to_1;
--
ARCHITECTURE dataflow OF mux_8_to_1 IS
SIGNAL sel_lines : std_logic_vector ( 7 DOWNTO 0);
BEGIN
sel_lines <= s7&s6&s5&s4&s3&s2&s1&s0;
WITH sel_lines SELECT
z <= '0' AFTER 3 NS WHEN "00000000",
This is an example of a i7 AFTER 3 NS WHEN "10000000" | "Z0000000",
selected signal i6 AFTER 3 NS WHEN "01000000" | "0Z000000",
i5 AFTER 3 NS WHEN "00100000" | "00Z00000",
assignment. It is a 1-bit i4 AFTER 3 NS WHEN "00010000" | "000Z0000",
8-to-1 multiplexer with 8 i3 AFTER 3 NS WHEN "00001000" | "0000Z000",
select lines. i2 AFTER 3 NS WHEN "00000100" | "00000Z00",
i1 AFTER 3 NS WHEN "00000010" | "000000Z0",
i0 AFTER 3 NS WHEN "00000001" | "0000000Z",
'X' WHEN OTHERS;
END dataflow;

Şenol Mutlu, EE240, Digital Design Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill 23
 Syntax of Selected Signal Assignment
The WITH keyword
starts the construct. All
possibilities must be
included. OTHERS
eliminates the need to
individually write all
possibilities.

Şenol Mutlu, EE240, Digital Design Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill 24
3-to8 Decoder Example: Select Signal Assignment

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dcd_3_to_8 IS
PORT (adr : IN std_logic_vector (2 DOWNTO 0);
so : OUT std_logic_vector (7 DOWNTO 0));
END dcd_3_to_8;
--
ARCHITECTURE dataflow OF dcd_3_to_8 IS
BEGIN
WITH adr SELECT
so <= "00000001" AFTER 2 NS WHEN "000",
"00000010" AFTER 2 NS WHEN "00Z" | "001",
"00000100" AFTER 2 NS WHEN "0Z0" | "010",
"00001000" AFTER 2 NS WHEN "0ZZ" | "0Z1" | "01Z" | "011",
"00010000" AFTER 2 NS WHEN "100" | "Z00",
"00100000" AFTER 2 NS WHEN "Z0Z" | "Z01" | "10Z" | "101",
"01000000" AFTER 2 NS WHEN "ZZ0" | "Z10" | "1Z0" | "110",
"10000000" AFTER 2 NS WHEN "ZZZ" | "ZZ1" | "Z1Z" | "Z11" |
"1ZZ" | "1Z1" | "11Z" | "111",
"XXXXXXXX" WHEN OTHERS;
END dataflow;

Şenol Mutlu, EE240, Digital Design Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill 25
 Vector Operations
If signals are defined as follows:

signal A, B, Z: std_logic_vector(7 downto 0);

Then the following logical operation and assignment is equivalent to:

Z <= A and B; for i  0 to 7 Zi  A i and Bi ;

– Operands must be the same size

– Assignment target must also have the same number of bits as the result
– Operations are applied bitwise to operands to produce the vector result

Vector Arithmetic Operations

Vector arithmetic operations are basically the same as vector logical operations
– Operands must be the same size
– Assignment target must also have the same number of bits as the result
– Operations are applied bitwise to operands to produce the vector result
– Multiplication is an exception.
– Carry or borrow in addition must be handled separately
– Carry in/out must be specially handled
– Result of addition can be 1 bit larger than operands

Şenol Mutlu, EE240, Digital Design 26

 16 bit Adder Example (Data Flow VHDL)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
USE ieee.std_logic_arith.all ;

ENTITY myadder16 IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;
Cout, Overflow : OUT STD_LOGIC ) ;
END myadder16 ;

ARCHITECTURE dataflow OF myadder16 IS

SIGNAL tmpsum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;
BEGIN
tmpsum <= ('0' & X) + („0‟&Y) + (“0000000000000000” & Cin) ;
S <= tmpsum(15 DOWNTO 0) ;
Cout <= tmpsum(16) ;
Overflow <= tmpsum(16) XOR X(15) XOR Y(15) XOR tmpsum(15) ;
END dataflow;
– The “&” symbol is the concatenation operator, joins operands together so that result length is
sum of lengths of operands.
– In order to access the MSB carry out we have to add 17-bit values (used & operator to add
leading zeros to operands)
– To assign result to S, we had to access only the least significant 16 bits of S. This is a slice of S.
– The carry out is a single bit assignment of the result
Şenol Mutlu, EE240, Digital Design 27
 Slice Reference and Assignment
A slice is a part of a vector.
It is accessed by a range clause :
(hi downto lo) or (lo to hi)
Indexes must be inside original range declaration. Range direction match the original
range declaration.
e.g. tmpsum(15 downto 0);
A single index is use to access a single bit
e.g. tmpsum(16);
Assignee must be the same size as the slice
Cout <= tmpsum(16);

Multiplication (Dataflow VHDL)

For multiplication (*), the result of the operation is twice the size of the operands.
– For F <= A * B;
– If A and B are 4-bit vectors, result is 8 bits
– F must be declared as an 8-bit vector

Şenol Mutlu, EE240, Digital Design 28

 Multiplication Example
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
USE ieee.std_logic_arith.all ;

entity mymultiply is
port(
a : in STD_LOGIC_VECTOR(15 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
mult : out STD_LOGIC_VECTOR(23 downto 0);
);
end mymultiply;

architecture dataflow of mymultiply is

begin

mult <= a * b;

end dataflow;

Şenol Mutlu, EE240, Digital Design 29