c

c PROJECT REPORT ON
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Arithmetic Logic Unit
c DESIGN AND IMPLEMENTATION OF 32-BIT ALU ON XILINX FPGA
c
USING VHDL
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PROJECT MENTOR:
c
c RAJ MOHAN DEY SARKAR
c
c 6


c c
c ARITRA RANJAN PAL
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SHREYASI KOLEY
c
c ANINDITA PAUL
c
c INDRANI DEY
c
c
TANAYA DAS
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c ›
›
›




 






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c SEACOM ENGINEERING COLLEGE
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It gives me great pleasure to find an opportunity to express my deep gratitude and sincerest thanks to my project
mentor, {
{
  at 
 
of  for giving most valuable
suggestion, helpful guidance and encouragement in the execution of this project. His guidance and
encouragement has led to the successful completion of my project titled:-    {{ 
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We are highly indebted to him for the way he modeled
and structured our work with his valuable tips and suggestions that he accorded to us in every respect of our
work.
Last but not the least I humbly extend my sense of gratitude to other faculty member and staffs of the institute
for providing me their valuable help and time with a congenial working environment.c
c

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m 

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?he aim of the project was to make a 32-bit Arithmetic and Logical Unit, using VHDL module in Xilinx I.S.E.
8.2i. here we have tried to design and implement the 32-bit A.L.U. by behavioral programming method in
VHDL module. We have used various techniques as per our knowledge, we have used various logic gates,
arithmetic circuits using logic gates and usi ng them we have prepared the arithmetic unit and the logical
unit of the A.L.U... ?hen using multiplexers we have combined them and organized the A.L.U. structure. In
this report we have shown various diagrams to show the structures of the A.L.U. and also the basic
structures which constitutes the A.L.U. as a proof that the output is as per expected one can check the
output waveforms of the different blocks with their respective theoretical values and truth tables.
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V.L.S.I. chip design us ing A.S.I.C. and F.P.G.A. procedure .

A.S.I.C. (Application Specific Integrated Circuit) is an integrated circuit designing method for integrated
chip and circuit boards. But in this method designing can be done for one purpose only, it can·t be
modified. Circuit diagrams were previously used to specify the configuration, as they were for ASICs, but
this is increasingly rare.

F.P.G.A. (Field-Programmable Gate Array) is an integrated circuit designed to be configured by the

customer or designer after manufacturing³hence "field-programmable". ?he FPGA configuration is
generally specified using a hardware description language (HDL), similar to that used for an application-
specific integrated circuit (ASIC). FPGAs can be used to implement any logical function that an ASIC could
perform. ?he ability to update the functionality after shipping, partial re-configuration of the portion of
the design and the low non-recurring engineering costs relative to an ASIC design offer advantages for
many applications.


›


?he objective of the project was to make a 32-bit Arithmetic and Logic Unit using V.H.D.L. module in Xilinx
I.S.E. 8.2i. this report shows explicit details of Xilinx, Spartan 3E starter kit board, F.P.G.A., V.H.D.L., the
program coding of the A.L.U. blocks and its basic blocks are also given in this report. Diagrammatic
representation of the block diagrams and the gates and the circuits as well as the waveforms of each and
every design is also supplied so that one can easily understand and check whether the output is correct or
not.
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M  › 








 



Xilinx is the world·s largest supplier (Electronics Company) of programmable logic devices and the inventor of the
field programmable gate array (FPGA). ?oday Xilinx is the number one FPGA vendor in the world. Xilinx is the
worldwide leader of complete programmable logic solutions.

Xilinx has two main FPGA families: - the high-performance Virtex series and the high-volume Spartan series. Each
model series has been released in multiple generations since its launch. ?he latest Virtex-6 and Spartan-6 FPGA
families are said to consume 50 percent less power, cost 20 percent less, and have up to twice the logic capacity of
previous generations of FPGAs. ?he Spartan series targets applications with a low-power footprint, extreme cost
sensitivity and high-volume; e.g. displays, set-top boxes, wireless routers and other applications.

 

 



 
 

Xilinx ISE 8.2i (Integrated Software Environment) tool is the latest release of the Xilinx·s widely-used design solutions.
Xilinx delivers ISE 8.2i ² A complete logic design solution for the next Virtex-5 FPGA family. ?he ISE 8.2i design
environment enables 30 percent faster performance than previous generation FPGAs. ?he ISE 8.2i design suite is
accompanied by the release of the Chip Scope Pro 8.2 debug and verification software. Available as an add-on
option, the Chip Scope Pro 8.2 solution reduces verification cycles by up to 50 percent. ISE software delivers
programmable logic design solutions to over 300,000 users worldwide with an intuitive, front-to-back design
environment for all Xilinx product families, including Spartan-3 Generation FPGAs. All versions of ISE 8.2i software
packages support Windows 2000 and Windows XP and Linux Red Hat Enterprise 3.0.
c

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or
designer after manufacturing³hence "field-programmable". ?he FPGA configuration is generally specified using a
hardware description language (HDL). FPGAs can be used to implement any logical function.
FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable
interconnections that allow the blocks to be "wired together". Logic blocks can be configured to perform complex
combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include
memory elements, which may be simple flip-flops or more complete blocks of memory.
At the highest level, FPGAs are reconfigurable silicon chips. Using prebuilt logic blocks and programmable routing
resources, we can configure these chips to implement custom hardware functionality.

?here are two basic types of FPGAs: SRAM-based reprogrammable and O?P (One ?ime Programmable). ?hese two
types of FPGAs differ in the implementation of the logic cell and the mechanism used to make connections in the
device.
c

VHDL is an acronym for Very High Scale Integrated Circuits Hardware Description Language. ?his language can be
used to model a digital system at the levels of abstraction, algorithmic level to the gate level.

A hardware description language is inherently parallel, i.e., commands, which correspond to logic gates, are executed
(computed) in parallel, as soon as a new input arrives. It also allows incorporation of timing specification (gate
delays) as well as to describe a system as an interconnection of different components.

?he complexity of ASIC and designs has meant an increase in the number of specialist design consultants with specific
tools and with their own libraries of macro and mega cells written in either VHDL or Verilog.

Verilog HDL is another Hardware Description Language.

VHDL offers several advantages to the designers.
šc Standard language and readily available tool.
šc Powerful and versatile description language.
šc Multiple mechanisms to support design hierarchy.
šc Versatile design reconfiguration support.
šc Support of multiple levels of abstraction.



 
î
 
?he latest Spartan-6 FPGA families are said to consume 50 percent less power, cost 20 percent less, and have up to
twice the logic capacity of previous generations of FPGAs. ?he Spartan series targets applications with a low-power
footprint, extreme cost sensitivity and high-volume; e.g. displays, set-top boxes, wireless routers and other
applications.

ISE software delivers programmable logic design solutions to over 300,000 users worldwide with an intuitive, front-
to-back design environment for all Xilinx product families, including Spartan-3 Generation FPGAs.

?he Spartan series targets applications with a low-power footprint, extreme cost sensitivity and high-volume.
? ›




  
c
Computer :c IBM or compatible.c

Hard Disk : 20 GB or higher.c

PROCESSOR : PEN?IUM-IV 2 GHz and abovec

ccccc
RAM : ccc 512 MB and abovec
c
VDU : ccccc VGAc
c


 ccccccccccccccccccccccccc 

OPERATING SYSTEMc c c :cc Windows XP, Windows 7, Windows vista, Linux, Solaris

DEVELOPMENT SOFTWAREc c :ccc Xilinx ISE 8.2i, ModelSim Simulator

c


  



c
During installation, you must enter a 16-digit Registration ID, which allows you to finish the software installation.
Registration of Xilinx software on a "per end-user" basis ensures that you receive the full complement of support and
services to which you are entitled.
c

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?he first step in the system development life cycle is the identification of the need. ?his is a user·s request to change,
improve or enhance an existing system. Because there is likely to be a stream of such requests, standard procedures
must be established to deal with them. ?he success of a system depends largely on how accurately a problem is
defined, thoroughly investigated and properly carried out through the choice of solution. User need identification
and analysis are concerned with what the user needs rather that what he/she wants. Not until the problem has been
identified, defined and evaluated should the analyst think about solutions and whether the problem is worth solving.
?his step is intended to help the user and the analyst understand the real problem rather than its symptoms. ?he user
or the analyst may identify the need for a candidate system or for enhancements in the existing system. If objectives
are misunderstood, it is easy to solve the wrong problem. ?he successful design of a system requires a clear knowledge
of what the system is intended to do. In the present scenario of Information ?echnology it is needed that most of the
manual operational systems in an organization are needed to be converted into information management system. In
a huge organization like correction house there is a need of co-relation between the different independent operations
related to the organization. ?he primary need is to design a reconfigurable CPU that is extendible.
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Once a project is found to be feasible, project planning is undertaken and completed before any development activity
starts. Project planning consists of the following essential activities:-

Estimating some basic attributes of the project:-

šc Cost: How much will it cost to develop the project?
šc Duration: How long will it take to complete the development?
šc Effort: How much effort would be required?

?he effectiveness of the subsequent planning activities is based on the accuracy of these estimations.

Scheduling manpower and other resources

Staff organization and staffing plans

Risk identification and analysis

Miscellaneous plans such as quality assurance plan, configuration management plan, etc.

Developing a system requires planning and coordinating resources with a given time. More important, effective
project management is needed to organize the available resources, schedule the events, and establish standards.





A GAN?? chart is a bar chart, which is perhaps the simplest form of formal project management. ?he bar chart is used
almost exclusively for scheduling purposes and therefore controls only the time dimension of projects.

GAN?? Charts (developed by Henry L Gantt) are a project control technique that can be used for several purposes,
including scheduling, budgeting and resource planning. A GAN?? chart is bar chart with each bar representing an
activity. ?he bars are drawn against a time line. ?he length of each bar is proportional to the length of time planned
for the activity.
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?he requirement specification is the starting point for the next phase: design. Consequently, a very precise, even
mathematical description is preferable. On the other hand, the specification must also be understandable to the user.
?his often means a readable document, using natural language and pictures. In practice, one has to look for a
compromise. Alternatively, the requirements specification may be presented in different, but consistent, forms to the
different audiences involved.

  
 




     



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Ë
Introduction
.c Purpose: ?his document states the requirements of a 32-bit ALU design and implementation. ?he
requirements stated serve as a basis for the acceptance procedure of this system. ?he document is also
intended as a starting point for the design phase.
2.c Scope: ?he intended product creates 32-bit ALU. Its purpose is to fetch instruction from memory and execute
them.
Ë2
cOverall Description c
?he top-level design of 32-bit ALU consists of the 4-bit ALU blocks whose inputs are in the form of bus. ?he ALU
fetches inputs from the input bus and executes its logic to run a program. ?hese outputs are shown in the form of
waveforms.
Ë3
User Characteristics
Anyone can be the user of this system and must have some familiarization with computer to operate this type system.
?he users should have access to the instruction manual of the ALU.
Ë
Constraints
.c Design Constraints: ?his is only a 16-bit CPU. In future, I hope to extend it.
2.c Software Constraints: ?he system can run under the Windows XP professional operating systems.
3.c Hardware Constraints: ?he system will run with minimum 512 MB RAM and 4.3 GB HARD -DISK spaces.

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?he AND gate performs logical multiplication, more commonly known as AND function. In this gate two or more
inputs are used. When all inputs are high then only output is high, otherwise the output is low.

CODING:

entity ANDBI? is ?RU?H ?ABLE:³

Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC; INPU?S OU?PU?
C : out S?D_LOGIC);
end ANDBI?; A B C

0 0 0
architecture Behavioral of ANDBI? is
0 1 0
begin
C <= A AND B; 1 0 0
end Behavioral;
1 1 1

DESIGN:

WAVEFORM:

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?he OR gate performs logical addition, more commonly known as OR function. In this gate two or more inputs are
used. When all inputs are low then only output is low, otherwise the output is high.

CODING:

entity ORBI? is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
C : out S?D_LOGIC); ?RU?H ?ABLE:³
end ORBI?;
INPU?S OU?PU?
architecture Behavioral of ORBI? is
A B C

begin 0 0 0

C <= A OR B; 0 1 1

1 0 1
end Behavioral;
c 1 1 1
DESIGN:

WAVEFORM:





?his circuit is also called inequality comparator or detector because it produces output only when the two inputs are
different. In this gate two or more inputs are used. When number of high inputs is even then the output is low,
otherwise the output is high.

CODING:

entity XORBI? is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC; ?RU?H ?ABLE:³
C : out S?D_LOGIC);
end XORBI?; INPU?S OU?PU?

A B C
architecture Behavioral of XORBI? is
0 0 0
begin
0 1 1
C <= A XOR B;
1 0 1
end Behavioral; 1 1 0

DESIGN:

WAVEFORM:

 
V V


?his is a universal gate. In this gate two or more inputs are used. When all inputs are high then only output is low,
otherwise the output is high.

CODING:

entity NANDBI? is
Port ( A : in S?D_LOGIC;
?RU?H ?ABLE:³
B : in S?D_LOGIC;
C : out S?D_LOGIC); INPU?S OU?PU?
end NANDBI?;
A B C
architecture Behavioral of NANDBI? is
0 0 1
begin 0 1 1

C <= A NAND B; 1 0 1

end Behavioral; 1 1 0

DESIGN:

WAVEFORM:

 

V

?his is also a universal gate. In this gate two or more inputs are used. When all inputs are low then only output is high,
otherwise the output is low.

CODING:

entity NORBI? is
Port ( A : in S?D_LOGIC; ?RU?H ?ABLE:³
B : in S?D_LOGIC;
C : out S?D_LOGIC); INPU?S OU?PU?
end NORBI?;
A B C
architecture Behavioral of NORBI? is 0 0 1

begin 0 1 0

1 0 0
C <= A NOR B;
1 1 0
end Behavioral;

DESIGN:

WAVEFORM:

V


?he EX-NOR gate is also called a coincidence gate, because its output is a 1 only when its inputs coincide (either 0, 0 or
1, 1). It can be used as an equality detector because its output is a 1 only when its inputs are equal. In this gate two or
more inputs are used. When number of high inputs is even then the output is high, otherwise the output is low.

CODING:

entity XNORBI? is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC; ?RU?H ?ABLE:³
C : out S?D_LOGIC);
end XNORBI?; INPU?S OU?PU?

A B C
architecture Behavioral of XNORBI? is
0 0 1
begin
0 1 0
C <= A XNOR B;
1 0 0
end Behavioral; 1 1 1

DESIGN:

WAVEFORM:


 
V 

?he inverter performs a basic logic function called inversion or complementation. It inverts the input.

CODING:

entity NO?BI? is
Port ( A : in S?D_LOGIC;
B : out S?D_LOGIC); ?RU?H ?ABLE:³
end NO?BI?;
INPU? OU?PU?
architecture Behavioral of NO?BI? is A B

begin 0 1

B <= NO? A; 1 0

end Behavioral;

DESIGN:

WAVEFORM:
 

A logic circuit that can add three bits, two bits to be added and a CARRY bit from the lower bit order which
results in a SUM and a CARRY.

?RU?H ?ABLE:³
CODING:
INPU?S OU?PU?S
entity ADDER is
Port ( A : in S?D_LOGIC; A B C_IN SUM C_OU?
B : in S?D_LOGIC; 0 0 0 0 0
C_IN : in S?D_LOGIC; 0 0 1 1 0
SUM : out S?D_LOGIC; 0 1 0 1 0
C_OU? : out S?D_LOGIC);
0 1 1 0 1
end ADDER;
1 0 0 1 0
architecture Behavioral of ADDER is 1 0 1 0 1
1 1 0 0 1
begin 1 1 1 1 1
SUM <= (A XOR B) XOR C_IN;
C_OU? <= (A AND B) OR ((A OR B) AND C_IN);
end Behavioral;

DESIGN:

WAVEFORM:
î




A logic circuit that can subtract three bits, one bit is to be subtracted from another and a BORROW bit
from the previous bit order which results in a output D and a BORROW OU?.

CODING: ?RU?H ?ABLE:³

entity SUB?RAC?OR is INPU?S OU?PU?S

Port ( A : in S?D_LOGIC;
A B C_IN SUM C_OU?
B : in S?D_LOGIC;
B_IN : in S?D_LOGIC; 0 0 0 0 0
DIFF : out S?D_LOGIC; 0 0 1 1 1
B_OU? : out S?D_LOGIC); 0 1 0 1 1
0 1 1 0 1
end SUB?RAC?OR; 1 0 0 1 0
1 0 1 0 0
architecture Behavioral of SUB?RAC?OR is 1 1 0 0 0
1 1 1 1 1
begin
DIFF <= (A XOR B ) XOR B_IN ;
B_OU? <= (B_IN AND (A XNOR B)) OR ((NO? A) AND B);
end Behavioral;

DESIGN:

WAVEFORM:




  


Increments a number by one. ?RU?H ?ABLE:³

INPU?S OU?PU?S
CODING:
A B C_IN SUM C_OU?
entity INCREMEN? is 0 1 0 1 0
Port ( A : in S?D_LOGIC; 0 1 1 0 1
C_IN : in S?D_LOGIC;
1 1 0 0 1
SUM : out S?D_LOGIC;
1 1 1 1 1
C_OU? : out S?D_LOGIC);

end INCREMEN?;

architecture Behavioral of INCREMEN? is

begin
SUM <= (A XOR '1') XOR C_IN;
C_OU? <= (A AND '1') OR ((A OR '1') AND C_IN);
end Behavioral;

DESIGN:

WAVEFORM:
  


Decrements a number by one.

CODING: ?RU?H ?ABLE:³

entity DECREMEN? is INPU?S OU?PU?S

Port ( A : in S?D_LOGIC;
A B C_IN SUM C_OU?
C_IN : in S?D_LOGIC;
D : out S?D_LOGIC; 0 1 0 1 1
C_OU? : out S?D_LOGIC); 0 1 1 0 1
1 1 0 0 0
end DECREMEN?; 1 1 1 1 1

architecture Behavioral of DECREMEN? is

begin
D <= (A XOR '1') XOR C_IN;
C_OU? <= (C_IN AND (A XNOR '1')) OR ((NO? A) AND '1');
end Behavioral;

DESIGN:

WAVEFORM:

 

?he output is kept same as the input bit, no change or alteration is made to it.

CODING:

entity ?RANSFER is ?RU?H ?ABLE:³

Port ( A : in S?D_LOGIC;
B : out S?D_LOGIC); INPU? OU?PU?

end ?RANSFER; A B

0 0
architecture Behavioral of ?RANSFER is
1 1
begin
B <= NO? (NO? A);
end Behavioral;

DESIGN:

WAVEFORM:
 
 

Mux or multiplexer or data selector is a logic circuit that accepts several data inputs and allows only one of them at a
time to get through the output. In this circuit select lines are used and the output depends on it. If m is the number of
select lines then inputs are 2^m.

CODING:
MUX 2 ?O 1:

entity MUX_?WO is MUL?IPLEXER 2 ?O 1

Port ( A : in S?D_LOGIC; ?RU?H ?ABLE:³
B : in S?D_LOGIC; INPU?S OU?PU?
SEL : in S?D_LOGIC; A B SEL MUX
MUX_?WO_OU? : out S?D_LOGIC);
0 1 0 0
end MUX_?WO;
0 1 1 1
architecture Behavioral of MUX_?WO is

begin
WI?H SEL SELEC?
MUX_?WO_OU? <= A WHEN '0',
B WHEN O?HERS;

end Behavioral; MUL?IPLEXER 8 ?O 1

?RU?H ?ABLE:³
MUX 8 ?O 1: INPU?S SELEC? OU?PU?
A B C D E F G H S2 S1 S0 MUX_OU?
entity MUX_EIGH? is 0 1 0 1 0 1 0 1 0 0 0 0
0 1 0 1 0 1 0 1 0 0 1 1
Port ( A : in S?D_LOGIC;
0 1 0 1 0 1 0 1 0 1 0 0
B : in S?D_LOGIC;
C : in S?D_LOGIC; 0 1 0 1 0 1 0 1 0 1 1 1
D : in S?D_LOGIC; 0 1 0 1 0 1 0 1 1 0 0 0
E : in S?D_LOGIC; 0 1 0 1 0 1 0 1 1 0 1 1
F : in S?D_LOGIC; 0 1 0 1 0 1 0 1 1 1 0 0
G : in S?D_LOGIC; 0 1 0 1 0 1 0 1 1 1 1 1
H : in S?D_LOGIC;
SEL : in S?D_LOGIC_VEC?OR (2 downto 0);
MUX_OU? : out S?D_LOGIC);

end MUX_EIGH?;

architecture Behavioral of MUX_EIGH? is

begin
WI?H SEL SELEC?
MUX_OU? <= A WHEN "000",
B WHEN "001",
C WHEN "010",
D WHEN "011",
E WHEN "100",
F WHEN "101",
G WHEN "110",
H WHEN O?HERS;
end Behavioral;
DESIGN:
MUX 2 ?O 1:

MUX 8 ?O 1:

WAVEFORM:
MUX 2 ?O 1:

MUX 8 ?O 1:
 
 


One essential function of most computer or other devices is the performance of arithmetic operations. Logic gates are
used to perform arithmetic operations like addition, subtraction, incrementing, decrementing. ?he basic arithmetic
units are adder, subtracter.

CODING:

entity AU_NEW is
Port ( X : in S?D_LOGIC;
Y : in S?D_LOGIC;
C_IN : in S?D_LOGIC;
SEL : in S?D_LOGIC_VEC?OR (2 downto 0);
AU : out S?D_LOGIC;
C_OU? : out S?D_LOGIC);
end AU_NEW;

architecture Behavioral of AU_NEW is

SIGNAL A, B, C, D, E, F, G, H : S?D_LOGIC;

SIGNAL I, J, K, L, M, N, O, P : S?D_LOGIC;

COMPONEN? ADDER is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
C_IN : in S?D_LOGIC;
SUM : out S?D_LOGIC;
C_OU? : out S?D_LOGIC);
end COMPONEN?;

COMPONEN? SUB?RAC?OR is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
B_IN : in S?D_LOGIC;
DIFF : out S?D_LOGIC;
B_OU? : out S?D_LOGIC);
end COMPONEN?;

COMPONEN? INCREMEN? is
Port ( A : in S?D_LOGIC;
C_IN : in S?D_LOGIC;
SUM : out S?D_LOGIC;
C_OU? : out S?D_LOGIC);
end COMPONEN?;

COMPONEN? DECREMEN? is
Port ( A : in S?D_LOGIC;
C_IN : in S?D_LOGIC;
D : out S?D_LOGIC;
C_OU? : out S?D_LOGIC);
end COMPONEN?;

COMPONEN? ?RANSFER is
Port ( A : in S?D_LOGIC;
B : out S?D_LOGIC);
end COMPONEN?;

COMPONEN? MUX_EIGH? is
 Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
C : in S?D_LOGIC;
D : in S?D_LOGIC;
E : in S?D_LOGIC;
F : in S?D_LOGIC;
G : in S?D_LOGIC;
H : in S?D_LOGIC;
SEL : in S?D_LOGIC_VEC?OR (2 downto 0);
MUX_OU? : out S?D_LOGIC);
end COMPONEN?;

begin

AUO : ADDER
POR? MAP ( X, Y, C_IN, A, I);

AU1 : SUB?RAC?OR
POR? MAP ( X, Y, C_IN, B, J);

AU2 : INCREMEN?
POR? MAP ( X, C_IN, C, K);

AU3 : INCREMEN?
POR? MAP ( Y, C_IN, D, L);

AU4 : DECREMEN?
POR? MAP ( X, C_IN, E, M);

AU5 : DECREMEN?
POR? MAP ( Y, C_IN, F, N);

AU6 : ?RANSFER
POR? MAP ( X, G);

AU7 : ?RANSFER
POR? MAP ( Y, H);

AU8 : MUX_EIGH?
POR? MAP ( A, B, C, D, E, F, G, H, SEL, AU);

AU9 : MUX_EIGH?
POR? MAP ( I, J, K, L, M, N, O, P, SEL, C_OU?);

O <= '0'; ?RU?H ?ABLE:³

P <= '0'; INPU?S SELEC? OU?PU?

X Y C_IN S2 S1 S0 ARI?HME?IC UNI?
end Behavioral;
0 0 0 0 0 0 ADDER
0 0 1 0 0 1 SUB?RAC?ER
0 1 0 0 1 0 INCREMEN? X
0 1 1 0 1 1 INCREMEN? Y
1 0 0 1 0 0 DECREMEN? X
1 0 1 1 0 1 DECREMEN? Y
1 1 0 1 1 0 ?RANSFER X
1 1 1 1 1 1 ?RANSFER Y
DESIGN:

WAVEFORM:




?he most basic elements of digital circuits are logic gates. ?he output depends upon the combination of high and low
inputs and the type of gates used. ?here are seven types of logic gates named AND, OR, NO?, NAND, NOR, XOR, X -
NOR.

CODING:

entity LU_NEW is
Port ( X : in S?D_LOGIC;
Y : in S?D_LOGIC;
SEL : in S?D_LOGIC_VEC?OR (2 downto 0);
LU : out S?D_LOGIC);
end LU_NEW;

architecture Behavioral of LU_NEW is

SIGNAL A, B, C, D, E, F, G, H : S?D_LOGIC;

COMPONEN? ANDBI? is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
C : out S?D_LOGIC);
end COMPONEN?;
COMPONEN? ORBI? is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
C : out S?D_LOGIC);
end COMPONEN?;
COMPONEN? XORBI? is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
C : out S?D_LOGIC);
end COMPONEN?;
COMPONEN? NANDBI? is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
C : out S?D_LOGIC);
end COMPONEN?;
COMPONEN? NORBI? is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
C : out S?D_LOGIC);
end COMPONEN?;
COMPONEN? XNORBI? is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
C : out S?D_LOGIC);
end COMPONEN?;
COMPONEN? NO?BI? is
Port ( A : in S?D_LOGIC;
B : out S?D_LOGIC);
end COMPONEN?;
COMPONEN? MUX_EIGH? is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
C : in S?D_LOGIC;
D : in S?D_LOGIC;
 E : in S?D_LOGIC;
F : in S?D_LOGIC;
G : in S?D_LOGIC;
H : in S?D_LOGIC;
SEL : in S?D_LOGIC_VEC?OR (2 downto 0);
MUX_OU? : out S?D_LOGIC);
end COMPONEN?;

begin

LU0 : ANDBI?
POR? MAP (X, Y, A);

LU1 : ORBI?
POR? MAP (X, Y, B);

LU2 : XORBI?
POR? MAP (X, Y, C);

LU3 : NANDBI?
POR? MAP (X, Y, D);

LU4 : NORBI?
POR? MAP (X, Y, E);

LU5 : XNORBI?
POR? MAP (X, Y, F);

LU6 : NO?BI?
POR? MAP (X, G);

LU7 : NO?BI?
POR? MAP (Y, H);

LU8 : MUX_EIGH?
POR? MAP (A, B, C, D, E, F, G, H, SEL, LU);

end Behavioral;

?RU?H ?ABLE:³

INPU? SELEC? OU?PU?

X Y S2 S1 S0 LOGICAL UNI?
0 0 0 0 0 AND
0 0 0 0 1 OR
0 1 0 1 0 XOR
0 1 0 1 1 NAND
1 0 1 0 0 NOR
1 0 1 0 1 XNOR
1 1 1 1 0 NO? X
1 1 1 1 1 NO? Y
DESIGN:

WAVEFORM:
 
 




ALU is an acronym for Arithmetic and Logic Unit. ?his unit performs various mathematical(addition, subtraction etc.)
operations and logical operations(AND,OR,XOR etc.). in addition to these operations it also takes complements of a
number, it compares two numbers, rotates the bits of number from left to right, shifts the bits of a number left or
right, increments or decrements a number.

$î
 ?RU?H ?ABLE:³

INPU?S OU?PU?
CODING: X Y SEL A.L.U.
0 1 0 ARI?HME?IC UNI?
entity ALU1BI? is
0 1 1 LOGIC UNI?
Port ( X : in S?D_LOGIC;
Y : in S?D_LOGIC;
C_IN : in S?D_LOGIC;
S : in S?D_LOGIC;
? : in S?D_LOGIC_VEC?OR (2 downto 0);
C_OU? : out S?D_LOGIC;
ALU_1OU? : out S?D_LOGIC);

end ALU1BI?;

architecture Behavioral of ALU1BI? is

SIGNAL A, B : S?D_LOGIC;

COMPONEN? AU_NEW is
Port ( X : in S?D_LOGIC;
Y : in S?D_LOGIC;
C_IN : in S?D_LOGIC;
SEL : in S?D_LOGIC_VEC?OR (2 downto 0);
AU : out S?D_LOGIC;
C_OU? : out S?D_LOGIC);
end COMPONEN?;

COMPONEN? LU_NEW is
Port ( X : in S?D_LOGIC;
Y : in S?D_LOGIC;
SEL : in S?D_LOGIC_VEC?OR (2 downto 0);
LU : out S?D_LOGIC);
end COMPONEN?;

COMPONEN? MUX_?WO is
Port ( A : in S?D_LOGIC;
B : in S?D_LOGIC;
SEL : in S?D_LOGIC;
MUX_?WO_OU? : out S?D_LOGIC);
end COMPONEN?;

begin

ALUO : AU_NEW
POR? MAP (X, Y, C_IN, ?, A, C_OU?);
ALU1 : LU_NEW
POR? MAP (X, Y, ?, B);
ALU2 : MUX_?WO
POR? MAP (A, B, S, ALU_1OU?);
end Behavioral;
DESIGN:

WAVEFORM:
%î


CODING:

entity ALU4BI? is
Port ( X : in S?D_LOGIC_VEC?OR (3 DOWN?O 0);
Y : in S?D_LOGIC_VEC?OR (3 DOWN?O 0);
C_IN : in S?D_LOGIC;
S : in S?D_LOGIC;
? : in S?D_LOGIC_VEC?OR (2 downto 0);
C_OU? : out S?D_LOGIC;
ALU_4OU? : out S?D_LOGIC_VEC?OR (3 DOWN?O 0));
end ALU4BI?;

architecture Behavioral of ALU4BI? is

SIGNAL C : S?D_LOGIC_VEC?OR (3 DOWN?O 0);

COMPONEN? ALU1BI? is
Port ( X : in S?D_LOGIC;
Y : in S?D_LOGIC;
C_IN : in S?D_LOGIC;
S : in S?D_LOGIC;
? : in S?D_LOGIC_VEC?OR (2 downto 0);
C_OU? : out S?D_LOGIC;
ALU_1OU? : out S?D_LOGIC);

end COMPONEN?;

begin

ALUO : ALU1BI?
POR? MAP ( X(0), Y(0), C_IN, S, ?, C(0), ALU_4OU?(0));

ALU1 : ALU1BI?
POR? MAP ( X(1), Y(1), C(0), S, ?, C(1), ALU_4OU?(1));

ALU2 : ALU1BI?
POR? MAP ( X(2), Y(2), C(1), S, ?, C(2), ALU_4OU?(2));

ALU3 : ALU1BI?
POR? MAP ( X(3), Y(3), C(2), S, ?, C(3), ALU_4OU?(3));

C_OU? <= C(3);

end Behavioral;
DESIGN:

WAVEFORM:


!î


CODING:

entity ALU32BI? is
Port ( X : in S?D_LOGIC_VEC?OR (31 DOWN?O 0);
Y : in S?D_LOGIC_VEC?OR (31 DOWN?O 0);
C_IN : in S?D_LOGIC;
S : in S?D_LOGIC;
? : in S?D_LOGIC_VEC?OR (2 downto 0);
C_OU? : out S?D_LOGIC;
ALU_32OU? : out S?D_LOGIC_VEC?OR (31 DOWN?O 0));
end ALU32BI?;

architecture Behavioral of ALU32BI? is

SIGNAL C : S?D_LOGIC_VEC?OR (7 DOWN?O 0);

COMPONEN? ALU4BI? is
Port ( X : in S?D_LOGIC_VEC?OR (3 DOWN?O 0);
Y : in S?D_LOGIC_VEC?OR (3 DOWN?O 0);
C_IN : in S?D_LOGIC;
S : in S?D_LOGIC;
? : in S?D_LOGIC_VEC?OR (2 downto 0);
C_OU? : out S?D_LOGIC;
ALU_4OU? : out S?D_LOGIC_VEC?OR (3 DOWN?O 0));
end COMPONEN?;

begin

ALUO : ALU4BI?
POR? MAP ( X(31 DOWN?O 28), Y(31 DOWN?O 28), C_in, S, ?, C(7), ALU_32OU?(31 DOWN?O 28));

ALU1 : FOR i IN 6 DOWN?O 1 GENERA?E

ALU2 : ALU4BI?
POR? MAP ( X((4*i+3) DOWN?O (4*i)), Y((4*i+3) DOWN?O (4*i)), C(i+1), S, ?,C(i),
ALU_32OU?((4*i+3)DOWN?O (4*i)));

END GENERA?E;

ALU3 : ALU4BI?
POR? MAP ( X(3 DOWN?O 0), Y(3 DOWN?O 0), C(1), S, ?, C(0), ALU_32OU?(3DOWN?O 0));

C_OU? <= C(0);

end Behavioral;
DESIGN:

WAVEFORM:
 › 

?he project is being done on the Xilinx I.S.E. 8.2i software. ?he 32-bit Arithmetic Logic Unit is being created by
programming in VHDL module as per Spartan 3E kit board. ?he diagrammatic representation of the 32-bits A.L.U.
block and the other blocks constituting this block has been observed carefully along with their output waveforms, the
output waveforms matches with the theoretical values, they are also being supplied in this report and the
presentation coming with this. Do check them for better understanding. ?his presentation and the report has been
made carefully with help from every member of the group.






?his 32 bit ALU (Arithmetic and Logic Unit) design and waveform implementation can be used to make
microprocessor designs and can be used for its calculations and various other purpose.

Ê





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