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1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
CA3130, CA3130A
NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
CA3130 CA3130A
TEST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Common-Mode CMRR 70 90 - 80 90 - dB
Rejection Ratio
I+ VO = 0V, - 2 3 - 2 3 mA
RL = ∞
Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC
Unless Otherwise Specified
CA3130,
PARAMETER SYMBOL TEST CONDITIONS CA3130A UNITS
Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or ±22 mV
4 and 1
2
CA3130, CA3130A
Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC
Unless Otherwise Specified
CA3130,
PARAMETER SYMBOL TEST CONDITIONS CA3130A UNITS
Input Capacitance CI f = 1MHz 4.3 pF
Slew Rate: SR
NOTE:
3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.
Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25oC
Unless Otherwise Specified (Note 4)
Input Current II 2 2 pA
100 100 dB
NOTE:
4. Operation at 5V is not recommended for temperatures below 25oC.
3
CA3130, CA3130A
Schematic Diagram
Q1 Q2 Q3
D1
Z1 D2
8.3V Q4 Q5
D3
R1 D4
40kΩ R
2
5kΩ SECOND
STAGE
INPUT STAGE
NON-INV. D5 D6 (NOTE 5) D7 D8
INPUT
3 OUTPUT
+ STAGE Q8
INV.-INPUT Q6 Q7 OUTPUT
2
- 6
R3 R4
1kΩ 1kΩ
Q9 Q10
Q12
Q11
R5 R6
1kΩ 1kΩ
NOTE:
5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.
Application Information
Circuit Description ohmic load resistance presented to the amplifier is very high
Figure 1 is a block diagram of the CA3130 Series CMOS (e.g.,when the amplifier output is used to drive CMOS digital
Operational Amplifiers. The input terminals may be operated circuits in Comparator applications).
down to 0.5V below the negative supply rail, and the output Input Stage
can be swung very close to either supply rail in many
The circuit of the CA3130 is shown in the schematic diagram.
applications. Consequently, the CA3130 Series circuits are
It consists of a differential-input stage using PMOS field-effect
ideal for single-supply operation. Three Class A amplifier
transistors (Q6, Q7) working into a mirror-pair of bipolar
stages, having the individual gain capability and current
transistors (Q9, Q10) functioning as load resistors together
consumption shown in Figure 1, provide the total gain of the
with resistors R3 through R6. The mirror-pair transistors also
CA3130. A biasing circuit provides two potentials for
function as a differential-to-single-ended converter to provide
common use in the first and second stages. Terminal 8 can
base drive to the second-stage bipolar transistor (Q11). Offset
be used both for phase compensation and to strobe the
nulling, when desired, can be effected by connecting a
output stage into quiescence. When Terminal 8 is tied to the
100,000Ω potentiometer across Terminals 1 and 5 and the
negative supply rail (Terminal 4) by mechanical or electrical
potentiometer slider arm to Terminal 4. Cascade-connected
means, the output potential at Terminal 6 essentially rises to
PMOS transistors Q2, Q4 are the constant-current source for
the positive supply-rail potential at Terminal 7. This condition
the input stage. The biasing circuit for the constant-current
of essentially zero current drain in the output stage under the
source is subsequently described. The small diodes D5
strobed “OFF” condition can only be achieved when the
4
CA3130, CA3130A
through D8 provide gate-oxide protection against high-voltage At total supply voltages somewhat less than 8.3V, zener
transients, including static electricity during handling for Q6 diode Z1 becomes nonconductive and the potential,
and Q7. developed across series-connected R1, D1-D4, and Q1,
varies directly with variations in supply voltage.
CA3130
V+ Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in
7 accordance with supply-voltage variations. This variation
200µA 1.35mA 200µA 8mA results in deterioration of the power-supply-rejection ratio
(NOTE 5)
BIAS CKT. 0mA (PSRR) at total supply voltages below 8.3V. Operation at
(NOTE 7)
total supply voltages below about 4.5V results in seriously
+
degraded performance.
OUTPUT
3
AV ≈ AV ≈
Output Stage
INPUT AV ≈ 5X 6000X 30X 6
The output stage consists of a drain-loaded inverting
2
amplifier using CMOS transistors operating in the Class A
- V-
mode. When operating into very high resistance loads, the
4
output can be swung within millivolts of either supply rail.
CC Because the output stage is a drain-loaded amplifier, its gain
5 1 8 STROBE
is dependent upon the load impedance. The transfer
COMPENSATION
OFFSET (WHEN REQUIRED) characteristics of the output stage for a load returned to the
NULL negative supply rail are shown in Figure 2. Typical op amp
loads are readily driven by the output stage. Because large-
NOTES:
signal excursions are non-linear, requiring feedback for good
6. Total supply voltage (for indicated voltage gains) = 15V with input
waveform reproduction, transient delays may be
terminals biased so that Terminal 6 potential is +7.5V above Ter-
minal 4. encountered. As a voltage follower, the amplifier can achieve
7. Total supply voltage (for indicated voltage gains) = 15V with out-
0.01% accuracy levels, including the negative supply rail.
put terminal driven to either supply rail. NOTE:
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES 8. For general information on the characteristics of CMOS transis-
tor-pairs in linear-circuit applications, see File Number 619, data
sheet on CA3600E “CMOS Transistor Array”.
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)
17.5
second amplifier stage, consisting of bipolar transistor Q11 SUPPLY VOLTAGE: V+ = 15, V- = 0V
TA = 25oC
and its cascade-connected load resistance provided by 15
LOAD RESISTANCE = 5kΩ
PMOS transistors Q3 and Q5. The source of bias potentials
12.5 2kΩ
for these PMOS transistors is subsequently described. Miller
1kΩ
Effect compensation (roll-off) is accomplished by simply 10
500Ω
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable 7.5
unity-gain operation in most applications.
5
Bias-Source Circuit
2.5
At total supply voltages, somewhat above 8.3V, resistor R2
and zener diode Z1 serve to establish a voltage of 8.3V across 0
the series-connected circuit, consisting of resistor R1, diodes 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5
D1 through D4, and PMOS transistor Q1. A tap at the junction GATE VOLTAGE (TERMINALS 4 AND 8) (V)
5
CA3130, CA3130A
TO
with the CA3130. In addition, when “sinking” or “sourcing”
5V
significant output current the chip temperature increases,
7
5 2
causing an increase in the input current. In such cases, heat-
PA CA3130 6 sinking can also very markedly reduce and stabilize input
3 current variations.
8
2.5 VIN 4 0V Input Offset Voltage (VIO) Variation with DC Bias
TO and Device Operating Life
-10V
0 V- It is well known that the characteristics of a MOSFET device
-1 0 1 2 3 4 5 6 7 can change slightly when a DC gate-source bias potential is
INPUT CURRENT (pA)
applied to the device for extended time periods. The
FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE magnitude of the change is increased at high temperatures.
Users of the CA3130 should be alert to the possible impacts
Offset Nulling of this effect if the application of the device involves
Offset-voltage nulling is usually accomplished with a extended operation at high temperatures with a significant
100,000Ω potentiometer connected across Terminals 1 and differential DC bias voltage applied across Terminals 2 and
5 and with the potentiometer slider arm connected to 3. Figure 5 shows typical data pertinent to shifts in offset
Terminal 4. A fine offset-null adjustment usually can be voltage encountered with CA3130 devices (metal can
effected with the slider arm positioned in the mid-point of the package) during life testing. At lower temperatures (metal
potentiometer’s total range. can and plastic), for example at 85oC, this change in voltage
is considerably less. In typical linear applications where the
Input-Current Variation with Temperature differential voltage is small and symmetrical, these
The input current of the CA3130 Series circuits is typically incremental changes are of about the same magnitude as
5pA at 25oC. The major portion of this input current is due to those encountered in an operational amplifier employing a
leakage current through the gate-protective diodes in the input bipolar transistor input stage. The 2VDC differential voltage
circuit. As with any semiconductor-junction device, including example represents conditions when the amplifier output
op amps with a junction-FET input stage, the leakage current stage is “toggled”, e.g., as in comparator applications.
approximately doubles for every 10oC increase in
temperature. Figure 4 provides data on the typical variation of
input bias current as a function of temperature in the CA3130.
6
CA3130, CA3130A
6
DIFFERENTIAL DC VOLTAGE of Q8 and Q12 are driven increasingly negative with respect
(ACROSS TERMINALS 2 AND 3) = 2V
5 OUTPUT STAGE TOGGLED to ground, current flow through Q8 is increased and current
flow through Q12 is decreased accordingly.
4
Single-supply Operation: Initially, let it be assumed that the
3 value of RL is very high (or disconnected), and that the input-
2
terminal bias (Terminals 2 and 3) is such that the output
DIFFERENTIAL DC VOLTAGE terminal (No. 6) voltage is at V+/2, i.e., the voltage drops
1 (ACROSS TERMINALS 2 AND 3) = 0V across Q8 and Q12 are of equal magnitude. Figure 20 shows
OUTPUT VOLTAGE = V+ / 2
typical quiescent supply-current vs supply-voltage for the
0
0 500 1000 1500 2000 2500 3000 3500 4000
CA3130 operated under these conditions. Since the output
stage is operating as a Class A amplifier, the supply-current
TIME (HOURS)
will remain constant under dynamic operating conditions as
FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGE long as the transistors are operated in the linear portion of
SHIFT vs OPERATING LIFE their voltage-transfer characteristics (see Figure 2). If either
V+ Q8 or Q12 are swung out of their linear regions toward cut-off
7 (a non-linear region), there will be a corresponding reduction
CA3130 in supply-current. In the extreme case, e.g., with Terminal 8
3 +
Q8 swung down to ground potential (or tied to ground), NMOS
6 transistor Q12 is completely cut off and the supply-current to
Q12
RL series-connected transistors Q8, Q12 goes essentially to zero.
2 -
The two preceding stages in the CA3130, however, continue
4 to draw modest supply-current (see the lower curve in Figure
8 V- 20) even though the output stage is strobed off. Figure 6A
shows a dual-supply arrangement for the output stage that
FIGURE 6A. DUAL POWER SUPPLY OPERATION can also be strobed off, assuming RL = ∞ by pulling the
potential of Terminal 8 down to that of Terminal 4.
Wideband Noise
Power-Supply Considerations
From the standpoint of low-noise performance
Because the CA3130 is very useful in single-supply
considerations, the use of the CA3130 is most
applications, it is pertinent to review some considerations
advantageous in applications where in the source resistance
relating to power-supply current consumption under both
of the input signal is on the order of 1MΩ or more. In this
single-and dual-supply service. Figures 6A and 6B show the
case, the total input-referred noise voltage is typically only
CA3130 connected for both dual-and single-supply
23µV when the test-circuit amplifier of Figure 7 is operated
operation.
at a total supply voltage of 15V. This value of total input-
Dual-supply Operation: When the output voltage at Terminal referred noise remains essentially constant, even though the
6 is 0V, the currents supplied by the two power supplies are value of source resistance is raised by an order of
equal. When the gate terminals of Q8 and Q12 are driven magnitude. This characteristic is due to the fact that
increasingly positive with respect to ground, current flow reactance of the input capacitance becomes a significant
7
CA3130, CA3130A
factor in shunting the source resistance. It should be noted, with CMOS input logic, e.g., 10V logic levels are used in the
however, that for values of source resistance very much circuit of Figure 10.
greater than 1MΩ, the total noise voltage generated can be
The circuit uses an R/2R voltage-ladder network, with the
dominated by the thermal noise contributions of both the
output potential obtained directly by terminating the ladder
feedback and source resistors.
arms at either the positive or the negative power-supply
+7.5V terminal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single-pole double-throw switch to
terminate an arm of the R/2R network at either the positive
or negative power-supply terminal. The resistor ladder is an
0.01µF
Rs 7
assembly of 1% tolerance metal-oxide film resistors. The five
3 + NOISE
arms requiring the highest accuracy are assembled with
1MΩ 6 VOLTAGE series and parallel combinations of 806,000Ω resistors from
2 - OUTPUT
the same manufacturing lot.
4
8 30.1kΩ A single 15V supply provides a positive bus for the CA3130
1
0.01 follower amplifier and feeds the CA3085 voltage regulator. A
µF
“scale-adjust” function is provided by the regulator output
47pF -7.5V
control, set to a nominal 10V level in this system. The line-
voltage regulation (approximately 0.2%) permits a 9-bit
BW (-3dB) = 200kHz 1kΩ
TOTAL NOISE VOLTAGE (REFERRED accuracy to be maintained with variations of several volts in
TO INPUT) = 23µV (TYP) the supply. The flexibility afforded by the CMOS building
FIGURE 7. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED blocks simplifies the design of DAC systems tailored to
FOR WIDEBAND NOISE MEASUREMENTS particular needs.
8
CA3130, CA3130A
+7.5V +15V
0.01µF 0.01µF
7 7
3 +
3 + 10kΩ
10kΩ 6 6
2 - 2 -
4 2kΩ
4
8
5
1 1
0.01µF 25pF 100kΩ
8
-7.5V
CC = 56pF 56pF OFFSET
2kΩ ADJUST
2kΩ
BW (-3dB) = 4MHz
SR = 10V/µs 0.1µF
0.1µF
Top Trace: Output Signal; 2V/Div., 5µs/Div. Top Trace:Output; 5V/Div., 200µs/Div.
Center Trace: Difference Signa; 5mV/Div., 5µs/Div. Bottom Trace:Input Signal; 5V/Div., 200µs/Div.
Bottom Trace: Input Signal; 2V/Div., 5µs/Div.
FIGURE 9B. OUTPUT WAVEFORM WITH GROUND
FIGURE 8B. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING REFERENCE SINE-WAVE INPUT
SETTLING TIME (MEASUREMENT MADE WITH
FIGURE 9. SINGLE SUPPLY VOLTAGE FOLLOWER WITH
TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)
ASSOCIATED WAVEFORMS. (e.g., FOR USE IN
FIGURE 8. SPLIT SUPPLY VOLTAGE FOLLOWER WITH SINGLE-SUPPLY D/A CONVERTER; SEE FIGURE 9
ASSOCIATED WAVEFORMS IN AN6080)
9
CA3130, CA3130A
806K 750K
806K 1% 1%
1% PARALLELED
RESISTORS
10K
+15V
VOLTAGE
REGULATOR 62
+15V 7
1 + 3
OUTPUT
2 +10.010V CA3130 VOLTAGE
6 FOLLOWER
CA3085 8
- 2
3 LOAD 4
22.1k 5
6 1% 1
7 8
+ REGULATED
2µF 4 56pF
1K VOLTAGE 100K
- 25V ADJ
0.001µF OFFSET
3.83k NULL 2K
1%
0.1µF
FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130
R2
2kΩ +15V
0.01
R1 µF
2 - 7
4kΩ CA3130 6
3 + 1N914 0V
4 5.1kΩ
5
1
8 R3
PEAK
20pF 100kΩ ADJUST
OFFSET 2kΩ
ADJUST
0V
R2 R3
Gain = ------- = X = --------------------------------------
R1 R1 + R2 + R3
2
2KΩ R 2
R 3 = R 1 ------------------
X+X
For X = 0.5: ------------ = -------
1-X 4kΩ R 1 Top Trace: Output Signal; 2V/Div.
Bottom Trace: Input Signal; 10V/Div.
R 3 = 4kΩ ----------- = 6kΩ
0.75 Time base on both traces: 0.2ms/Div.
0.5
20VP-P Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V
1VP-P Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV
FIGURE 11. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
10
CA3130, CA3130A
6VP-P INPUT;
6VP-P INPUT; +7.5V
+7.5V BW (-3dB) = 360kHz
BW (-3dB) = 1.3MHz
0.3VP-P INPUT;
0.3VP-P INPUT; 0.01µF
0.01µF BW (-3dB) = 320kHz
BW (-3dB) = 240kHz 7 -DC
7 +DC 3 + OUTPUT
3 + OUTPUT 10kΩ CA3130 6
10kΩ CA3130 6
2 -
2 - 1N914
1N914
4 -
4 + 100
100 5µF
5µF kΩ +
kΩ - 0.01µF
0.01µF
2kΩ -7.5V
2kΩ -7.5V
FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT
FIGURE 12. PEAK-DETECTOR CIRCUITS
CURRENT
LIMIT
ADJ
3Ω
+
R2
1kΩ
IC3 1kΩ
CA3086 Q5 13
10 7 3 12 14
Q4 Q3 Q2 Q1
9 6 2 4
11 8 1 5
+ OUTPUT
20kΩ
0 TO 13V
390Ω 1kΩ AT
56pF
40mA
+
5µF
2.2kΩ 25V
0.01µF -
ERROR
1 AMPLIFIER
+
25µF 8
IC2 - 7
+20V CA3086 10 11 1, 2 - 2
INPUT Q4 Q1 6 CA3130
9 3 +
IC1 3
8, 7 5
Q2 30kΩ
Q3 Q5 14 4
6 4 100kΩ
R1
12 13 50kΩ
VOLTAGE
ADJUST 0.01
62kΩ µF
- -
REGULATION (NO LOAD TO FULL LOAD): <0.01%
INPUT REGULATION: 0.02%/V
HUM AND NOISE OUTPUT: <25µV UP TO 100kHz
11
CA3130, CA3130A
2N3055 Q2 1Ω
+ +
10kΩ
2N2102
1kΩ CURRENT
4.3kΩ Q1 LIMIT
1W ADJUST
Q3
3.3kΩ
1W
2N5294
+
43kΩ
+ 1000pF 100µF
100µF -
- 2.2kΩ
1 ERROR OUTPUT:
+55V + AMPLIFIER
8 0.1 TO 50V
INPUT IC2 5µF
- 2N2102 7 AT 1A
+ 3
CA3086 10, 11 1, 2
10kΩ
6 CA3130
Q4 Q1
9 3 Q5 14 IC1 - 2
Q4
8, 7 5
12 13 4
Q3 Q2 8.2kΩ
6 4
1kΩ 50kΩ
VOLTAGE
62kΩ ADJUST
- -
REGULATION (NO LOAD TO FULL LOAD): <0.005%
INPUT REGULATION: 0.01%/V
HUM AND NOISE OUTPUT: <250µVRMS UP TO 100kHz
12
CA3130, CA3130A
13
CA3130, CA3130A
R4
270kΩ INTEGRATOR
VOLTAGE-CONTROLLED C1
CURRENT SOURCE THRESHOLD
+7.5V HIGH - FREQ. DETECTOR
100pF ADJUST
7 +7.5V 3 - 30pF 150kΩ
IC1
IC2 +7.5V
3 + IO 7
C2 IC3 7
3kΩ
3kΩ 6 2 -
2 - CA3080A CA3130 6 3 +
4 (NOTE 10) 3 + 39kΩ CA3130 6
+7.5V 5 -7.5V
4
2 -
10MΩ 8 4
+7.5V 1 5
R2 -7.5V 1
100kΩ SLOPE 22kΩ
R3
SYMMETRY 10kΩ 56pF
100kΩ
ADJUST
FREQUENCY
-7.5V VOLTAGE R1 ADJUST AMPLITUDE
CONTROLLED 10kΩ (100kHz MAX) SYMMETRY
INPUT ADJUST
-7.5V
-7.5V
NOTE:
10. See file number 475 and AN6668 for technical information.
FIGURE 16. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)
+15V
0.01µF 14 2 11
1MΩ
1µF CA3600E
(NOTE 12) QP1 QP2 QP3
7
750kΩ
3 +
CA3130 13 1
2kΩ 6
INPUT 2 -
500µF
1µF
8 6 3 10 12
4 RL = 100Ω
(PO = 150mW
AT THD = 10%)
8 5
AV(CL) = 48dB
LARGE SIGNAL QN1 QN2 QN3
BW (-3 dB) = 50kHz
7 4 9
510kΩ
NOTES:
11. Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA3130.
12. See file number 619.
FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130
14
CA3130, CA3130A
140 1 3
80
2
130 2 -200
60 3
120 1
-300
40 4
110
100 20
90 0
101 102 103 104 105 106 107 108
80 FREQUENCY (Hz)
-100 -50 0 50 100
1 - CL = 9pF, CC = 0pF, RL = ∞
TEMPERATURE (oC) 2 - CL = 30pF, CC = 15pF, RL = 2kΩ
3 - CL = 30pF, CC = 47pF, RL = 2kΩ
4 - CL = 30pF, CC = 150pF, RL = 2kΩ
FIGURE 18. OPEN LOOP GAIN vs TEMPERATURE FIGURE 19. OPEN-LOOP RESPONSE
17.5
∞ 14
QUIESCENT SUPPLY CURRENT (mA)
LOAD RESISTANCE =
TA = 25oC OUTPUT VOLTAGE = V+/2
QUIESCENT SUPPLY CURRENT (mA)
10
10 25oC
8 125oC
7.5
6
5
OUTPUT VOLTAGE HIGH = V+ 4
OR LOW = V-
2.5
2
0
0
4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16
TOTAL SUPPLY VOLTAGE (V) TOTAL SUPPLY VOLTAGE (V)
FIGURE 20. QUIESCENT SUPPLY CURRENT vs SUPPLY FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE VOLTAGE
50 50
VOLTAGE DROP ACROSS PMOS OUTPUT
1 1
0.1 0.1
0.01 0.01
0.001 0.001
0.001 0.01 0.1 1.0 10 100 0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA) MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR
(Q8) vs LOAD CURRENT (Q12) vs LOAD CURRENT
15