SD 5.12 312278514120

DVD-Video Player Module MSD-512S
Contents Page
1 Technical Specs and Connection Facilities 2
2 Safety Instructions, Warnings, Notes,
and Service Hints 12
3 Directions for Use (Not Applicable) 14
4 Mechanical and Dismantling Instructions 14
5 Diagnostic Software, Trouble Shooting and Test
Instructions 15
6 Wiring, Block Diagrams
Block Diagram 25
Wiring Diagram 26
7 Electrical Diagrams and Print-Layouts Diagram PWB
MPEG Board: Decoder & Peripheral Circuits 27 33-34
MPEG Board: Memory Part 28 33-34
MPEG Board: Audio Part 29 33-34
MPEG Board: Video Part 30 33-34
MPEG Board: Power and Scart port 31 33-34
8 Alignments (Not Applicable) 35
9 Circuit Descriptions (Not Applicable) 35
10 Spare Parts List
Spare Parts List MSD-512S/00 41
Spare Parts List MSD-512S/ARG 44
Appendix: Datasheet ZiVA-5+
©
Copyright 2002 Philips consumer Electronics B.V. Eindhoven, The Netherlands,
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Published by Liu BZH 0367 Service BPAVC Printed in the Netherlands Subject to modification EN 3122 785 14120
EN 44 2 MSD-512S Technical specifications
1. Technical Specifications

MSD-512S/ 00/69/78/ARG
1.1 Specifications Overview
PLAYBACK SYSTEM AUDIO PERFORMANCE

DVD Video
DA Converter 24bit/192kHz
Video CD & SVCD
Signal-Noise (1KHz) 100dB
CD
Dynamic range(1KHz) >90dB
PICTURE CD
DVD fs 96 kHz 4Hz- 44kHz
MP3-CD
fs 48 kHz 4Hz- 22kHz
CD-R, CD-RW
SVCD fs 48 kHz 4Hz- 22kHz
DVD+R, DVD+RW
fs 44.1kHz 4Hz- 20kHz
CD/VCD fs 44.1kHz 4Hz- 20kHz
VIDEO PERFORMANCE
* CVBS 1Vpp --- 75
* S-VIDEO Y: 1.00Vpp --- 75 TV STANDARD (PAL/50Hz) (NTSC/60Hz)
C: 0.30Vpp --- 75
*Component video Y: 1.00Vpp --- 75 Number of lines 625 525
Pr : 0.7Vpp --- 75 Playback Multistandard (PAL/NTSC)
Pb: 0.7Vpp --- 75
CONNECTIONS
AUDIO FORMAT
Digital Mpeg/ AC-3/ DTS compressed Digital Video Output (Y/C) EH connector (4pin Black)
PCM 16, 20, 24 bits Audio Output(L+R) EH connector (3pin Black)
fs, 44.1, 48, 96 kHz Digital Output EH connector (3pin White)
MP3(ISO 9660) 24, 32, 56, 64, 96, 128, IEC958 for CDDA / LPCM/ MPEG1
256 kbps & variable IEC1937 for MPEG 2, Dolby
bit rate fs, 16, 22.05, Digital and DTS
24, 32, 44.1, 48 kHz I2C Bus EH connector (4pin White)
Analog Sound Stereo Service Connector EH connector (7pin White)
Power Supply
Power to Mpeg PWB can be applied via connector1615

+5VDC 1100 mA +/-5%
+12VDC 60 mA +/-10%
-12VDC 105 mA +/-10%
Power to Loader (A97ST)

+5VDC 530 mA +/-5%
+12VDC 200 mA +/-10%
Specifications subject to change without prior notice

Technical specifications MSD-512S 3 EN 44
1.2 Technical Specifications 2. Basic Audio/Video circuits and the output

connectors.
1.2.1 Introduction 3. ATAPI interface, both for A97S and A97ST.
4. Diagnostic interface.
MSD-512S use the same mpeg board for difference 5. Connectors for TV and DVD set used.
slash version, with A97S loader for DVD set and 6. JTAG interface.
with A97ST loader for TV combi, both of them have
the same technical specification. 1.2.2 Mechanical construction
The SD5.12 module shall contain: When the mpeg board is placed beside the loader,
1. LSI Logic ZiVA5M+ DVD decoder / host all mpeg board interfaces are located on the top
processor. side of the board, as shown below:
1.2.3 Key components for SD5.12

DVD back-end
Part No Manufacturer Description Remark
ZiVA-5M+ LSI Logic DVD back-end processor Basic function
MT48LC2M32B2TG-7 Micron 64Mbit SDRAM 32bit
M29W160DT/ Top level, TSOP48 package, for UI2002
ST Microelectronics 2Mbyte flash memory
M29W160ET s/w
74LVT573DB Philips Semiconductor D-type transparent latch 3.3V, SOT339-1 package
M24C64 ST Microelectronics 64Kbit I2C bus EEPROM --
AK4382A AKM 2-ch Audio DAC 2 channel, Diff output
Miscellaneous
Part No Manufacturer Description Remark
LD1117ADT18 ST Microelectronics 1.8V voltage regulator Adjust from 3.3V to 1.8V
LD1086D2T33 ST Microelectronics 3.3V voltage regulator Adjust from 5V to 3.3V
MC78L05ACD Motorola 5V voltage regulator Adjust from 12V to 5V
Note: This key component list should only be used as a rough indication to the content of the SD5.12 module. For
actual component used, always refer to the module’s official bomlist.
1.2.4 PCB specifications

The PCB of SD5.12 should be according to Lightning Stroke. Refer to the PCB’s Sheet 110.
The PCB size is 150x100mm, double layer, FR4 material.
1.2.5 Power supply and grounding concept

1.2.5.1 Power supply
To improve performance, multiple power supply and grounding are adopted. Additionally, the supply voltages to the
mpeg board are channeled through fusible resistors to comply with PCE safety requirements.
Power to Mpeg PWB can be applied via connector 1615.
Power name Rating Description Used by
+5VD +/-5% 1100 mA Digital power supply Digital circuits
+12VA +/-10% 60 mA Analog power supply Analog circuits
-12VA +/-10% 105 mA Analog power supply Analog circuits
Power to Loader (A97ST):
Power name Rating Description Used by
+5VL +/-5% 530 mA Digital power supply Loader
+12VL +/-10% 200 mA Spindle power supply Loader
To achieve good power supply isolation among analog and digital, the power supply to all sub-sections are originated
from different voltage regulators, supply lines or decoupled using ferrite beads.
1.2.5.2 Grounding
Ground name Description Used by
GNDD Digital parts ground Digital circuitry
GNDA Analog parts ground Analog circuitry (including audio and video)
In order to control EMC radiation:

• Bypass capacitors and ferrite beads or jumpers are placed at strategic locations.
• An uninterrupted ground strip is placed at every layer around the edges of the PCB, to reduce EMC leakage from
the edges.
• Screw mounting points to chassis are available at three corners of the PCB, with optional series capacitors or
jumpers to ground.
1.2.6 Interface pin assignments

Connector Pin Assignment Description
1603 1 M_I2C_DA Master I2C data, for master control, TV used
EH connector L_I2C_DA Slave I2C data, for slave control, TV used
Straight/vertical 2 M_I2C_CL Master I2C clock, for master control, TV used
L_I2C_CL Slave I2C clock, for slave control, TV used
3 GNDD Digital ground, for TV used
4 S_I2C_RDY I2C interrupt, for TV used
Note:This connector is used for I2C control signal for TV used, the configuration refer to the model mode slash version.

1619 1 Y_VID Y luma video
EH connector 2 GNDA Analog ground
Straight/vertical 3 C_VID C chroma video
4 GNDA Analog ground
Note: This connector is for Y/C for TV and DVD set used.

1620 1 GNDD Digital ground, for TV and DVD set used
EH connector 2 SPDIF SPDIF output, for TV and DVD set used
5VD Digital power supply, for DVD set used
3
Straight/vertical GNDD Digital ground, for TV used
Note: This connector is for SPDIF output, TV and DVD set used.

1621 1 R_OUT Right channel analog output
EH connector 2 GNDA SPDIF output
Straight/vertical 3 L_OUT Left channel analog output
Note: This connector is for analog 2-ch audio output, TV used.

1601 1 /LDRST ATAPI interface reset
Header 2.54mm 2 ATAPI_GND Ground
Straight / vertical 3 DD15 ATAPI bus bit 15
4 DD0 ATAPI bus bit 0
1601 10 DD3 ATAPI bus bit 3
Header 2.54mm 11 DD11 ATAPI bus bit 11
Straight / vertical 12 DD4 ATAPI bus bit 4
19 ATAPI_GND Ground
20 NC Not connected
21 DMARQ DMA request (not used)
22 ATAPI_GND Ground
23 LDS Data IO write
24 ATAPI_GND Ground
25 DUS Data IO read
26 ATAPI_GND Ground
27 /DTACK Data acknowledge
28 NC Not connected
29 DMACK DMA acknowledge (not used)
30 ATAPI_GND Ground
31 HIRQ1 Interrupt request
32 NC Not connected
33 UPA2 ATAPI address bus bit 1
34 NC Not connected
37 /IDE_CS0 IDE0 device select
38 /IDE_CS1 IDE1 device select
39 NC Not connected
40 ATAPI_GND Ground
Note: This is the ATAPI connector that connect to A97S and A97ST loader.

1600 1 TXD_SER TXD service UART
PH connector 2 SERVICE Service or normal mode select
Straight/vertical 3 RXD_SER RXD service UART
4 RTS_SER Not used (RTS service UART)
5 GNDD Digital ground
6 CTS_SER Not used (CTS service UART)
7 5VD Positive 5V (isolated from internal +5V by ferrite bead)
Note: This connector is contributed to Diagnostic purpose.

1605 1 STDY_CTRL Standby switch
EH connector 2 VFD_DATA VFD driver control signal (data, bi-direction)
Straight/vertical 3 VFD_CLK VFD driver control signal (clock, output)
4 VFD_CS VFD driver control signal
5 GNDD Digital ground
6 IR IR signal (optional)
Note: This connector is contributed to VFD driver purpose, for DVD used only.

1618 1 R_VID Red (V chroma) video
EH connector 2 GNDA Analog ground
Straight/vertical 3 B_VID Blue (U chroma) video
4 GNDA Analog ground
5 G_VID Green (Y luma) video
Note: This connector is for YUV or RGB output for TV and DVD set used. YUV and RGB share the same signals, can’t
output YUV and RGB at the same time.

1610 1 5VD 5V power supply for DVD used
EH connector 2 GNDD Digital ground
Straight/vertical 3 -12VA -12VA power supply for DVD used
Note: This connector is only for DVD used for video buffer purpose, it is optional.

1606 1 SCART-R Audio Out Right
SCART connector 2 N/u Audio In Right
3 SCART-L Audio Out Left + Right
4 GNDA Audio Ground
5 GNDA RGB Blue Ground
6 N/u Audio In Left + Mono1
7 BLUE RGB Blue
8 0/6/12 Audio/RGB switch/16:9
9 GNDA RGB Green Ground
10 N/u Clock Out
11 GREEN RGB Green
12 N/u Data Out
13 GNDA RGB Red Ground
14 GNDA Data Out
15 RED RGB Red/Chrominance
16 FBOUT Blanking Signal
17 GNDA Composite Video Ground
18 GNDA Blanking Signal Ground
19 CVBS Composite Video Out
20 N/u Composite Video In/Luminance
21 GNDA Ground/Shield (connected to chassis)
1.2.7 Signal specifications

This section defines the specifications of the signals at the module interface.
The audio and video signal specifications are only partially covered in this section. For the complete audio and video
signal specifications, refer to 0 1.2.13 Audio performance and 0 1.2.14 Analog video performance.
The signal specifications can be classified into the followings:
Signal type Description Definition

Absolute maximum rating:
VIN = -0.5V to 5.5V
VOUT = -0.5V to 5.5V
Parame
ter
Transistor-transistor logic (5V logic)
VIH (V)
TTL Caution:
Exceeding the absolute maximum rating will cause VIL (V)
damage to the module.
VOH (V)
VOL (V)
Low voltage transistor-transistor logic (3.3V logic) Absolute maximum rating:

VIN = -0.5V to 3.8V
LVTTL Caution: VOUT = -0.5V to 3.8V
Exceeding the absolute maximum rating will cause Maximum current drive: 4mA
Parame
ter
VIH (V)
VIL (V)
VOH (V)
VOL (V)
Signal type Description Definition

Inter-IC
I2C [I2C_SPEC]
All I2C signals at the module’s connectors are 5V levels.
Inter-IC sound
All I2S signals at the module’s connectors are at LVTTL

levels.
I2S [I2S_SPEC]
Caution:
Exceeding the absolute maximum rating will cause
VIN approximately 3V threshold, 6kohm
RS232_COMP RS232 compatible specifications resistance
VOUT = 0 to 5V, 1kohm output resistance
H = +5V ± 0.5V
H/L 5V logic states
L = 0V ± 0.5V
h = +3.3V ± 0.3V
h/l 3.3V logic states
l = 0V ± 0.3V
1.2.7.1 SPDIF out

Function: Digital audio output
Signal: SPDIFOUT
Type: TTL output (22ohm output resistor, in series)
See 0. 1.2.13 Audio performance.
1.2.7.2 Analog audio

Function: Analog audio output
Signal: L_OUT, R_OUT
See 0. 1.2.13 Audio performance.
1.2.7.3 Audio mute
Function: Audio mute control
Signal: MUTEC
Type: TTL output
Function MUTE (TTL output)

Mute off LOW
Mute on HIGH
1.2.7.4 Analog video

Function1: Analog video output without buffer (to connector for TV and DVD set, 75ohm resistors in series)
Signal: C_VID, YVID, G_VID, B_VID, R_VID
Function2: Analog video output with buffer (CVBS and RGB to SCART output)
Signal: CVBS_OUT, R_OUT, G_OUT, V_OUT
See 0. 1.2.14 Analog video performance.
1.2.7.5 Slow blanking SCART

Function: Slow blanking SCART
Signal: 0/6/12
Type: the output level refer to the last column.
Function SCART0 (LVTTL output) SCART1 (LVTTL output) 0/6/12(V)

TV display HIGH HIGH 0
TV display LOW HIGH 0
16:9 aspect ratio HIGH LOW 6
4:3 aspect ratio LOW LOW 12
0/6/12 signal is produced by SCART0 and SCART1, the related circuits refer to electrical diagrams.
1.2.7.6 I2C
Function: I2C bus
Signal: I2CSCL, I2CSDA
Type: I2C
1.2.7.7 DAC control bus

Function: DAC control bus
Signal: DAC_CLK, DAC_DATA, DAC_CS
Type: DAC_CLK output
DAC_DATA bi-directional
DAC-CS output
1.2.7.8 VFD bus ( for DVD set only)

Function: VFD bus
Signal: VFD_CLK, VFD_DATA, VFD_CS
Type: VFD_CLK output
VFD_DATA bi-directional
VFD_CS output
1.2.7.9 Service bus

Function: Service and diagnostic bus
Signal: TXD_SER, RXD_SER,
Type: RS232_COMP (TXD_SER output, RXD_SER input)
1.2.7.10 Service activation

Function: To activate service mode
Signal: SERVICE
Type: LVTTL input
Function SERVICE (LVTTL)
Service mode LOW (or short to ground)
Normal mode HIGH (or unconnected)
Note: This line is pulled to HIGH via 10kohm resistor.
A module reset is required to activate service mode.
1.2.7.11 Service +5V

Function: Positive 5V line in the Service connector
Signal: +5V_SER
Type: Power supply; this line is connected to 5VD through a ferrite bead
1.2.8 Software
The MPEG board software (also known as the application software) exist in flash memory, and it is dependent on the
module versions.
For flash memory versions, the software can be programmed via the DCU interface (JTAG interface). This interface is
exposed as 6 test points at the bottom of the module. The DCU interface method can be used even when the existing
content of the flash memory is undefined. Additionally, the software can be upgraded / reprogrammed via a “download
disc”. The download disc method requires that the flash memory already contain valid software.
1.2.9 Module control

Communication with the module in normal mode is via I2C bus.
For service and diagnostic of the module, the Service mode can be activated (using the Service interface).
1.2.10 Power supply requirements

Voltage name Output voltage Output current
Min Typ Max Vrip Off Play min Play-Typ Play-
(V) (V) (V) (Mvpp) (V) max
+5VD 4.75 5.00 5.25 50 <0.2 600 1200 1400
2
* +12VA 10.80 12.00 13.20 100 <0.5 10. 60 70
*1 *1 *1
-12VA -10.80 -12.00 -13.20 100 >0.5 -90 -140 -160
Notes :
*1
1. This current has already include the extra current request from test centre (FNAC).
*2
2. The 12VA switch will be shifted to MPEG board due to the architecture issue. So please reserve the switch in
the layout
3. Audible noise is not allowed at normal or standby mode.
4. A ceramic SMD capacitor of 22nF is required at the output of +/-12VA to reduce the impedance of output.
5. +5VD is for digital parts, +12VA/-12VA is for analog circuit of DVD player(TV need +12VA only).
1.2.11 Playability
Media Data type Remark
DVD-Video (SL, DL, SS, DS) DVD video
DVD-R (3.95 and 4.7GB) DVD video
DVD+RW DVD video
DVD+R DVD video
CDDA CD audio
CD-Bridge (CDROM data) VCD
CDR / CDRW CD audio, VCD
CDR / CDRW MP3 (ISO9660, Joliet) Finalized and unfinalized
CDR/CDRW CD-ROM data Software download disc
VCD VCD versions 1.0, 1.1 and 2.0
DVCD VCD
SVCD CVD, ChaoJi and Shinco SVCD Normally SVCD
Hybrid SACD CD audio and SACD CD layer
Disc diameter Remark

12cm
8cm
1.2.12 Access time

No Type Parameter Specification Test disc
17.01 No disc Standby state Æ no disc 2.0 s None
17.02 No disc No disc Æ open tray 2.0 s None
17.03 No disc Open tray Æ closed tray 2.0 s None
17.11 CDDA Tray open Æ play state 7.0 s SBC442 (7104 087 04861)
17.12 CDDA Stop state Æ play state 2.5 s SBC442 (7104 087 04861)
17.13 CDDA Access (track 1 – track 20) 2.0 s SBC442 (7104 087 04861)
17.21 VCD Tray open Æ play state (PBC) 8.0 s Philips Production VCD2.0 test disc (7104 099 36471)
17.22 VCD Stop state Æ play state (PBC) 3.0 s Philips Production VCD2.0 test disc (7104 099 36471)
17.31 DVD SL Tray open Æ play state 8.0 s MPTD CVP02.18A (7104 099 91691)
17.32 DVD SL Stop state Æ play state 3.0 s MPTD CVP02.18A (7104 099 91691)
17.33 DVD SL Access (title 1 – title 40) 2.5 s MPTD CVP02.18A (7104 099 91691)
17.34 DVD SL Play state Æ standby state 4.0 s MPTD CVP02.18A (7104 099 91691)
17.35 DVD SL Play state Æ open tray 3.0 s MPTD CVP02.18A (7104 099 91691)
17.41 DVD DL Tray open Æ play state 10.0 s Burn-in disc, LVP04.15 (7104 099 91141)
Note:
1. Open tray – tray fully open
2. No disc – when front panel display shows NO DISC
3. Play state – when sound/video starts, or when front panel display shows 0:00
4. Stop state – when disc not spinning (disc already in loader and TOC has been read)
5. Track/title change – from end of key press to next track/title play state
6. Standby state – when player is in standby mode (the module is actually power-off)
1.2.13 Audio performance

1.2.13.1 SPDIF out
Function: Digital audio output
Signal: SPDIFOUT
Type: Output according to IEC60958 or IEC61937, except at TTL levels (22ohm output resistor, in series)
Note: To meet the complete SPDIF specification, an external decoupling/drive circuit is necessary.
1.2.13.2 Analog audio

Function: Analog audio output
Signal: L_OUT, R_OUT
Performance: Reference is made to the [PQR-IMS].

All performance complies fully with PQR class III.
1.2.13.3 Audio connector

The audio connector for DVD used including Lt/Rt, Coaxial and SCART output.
1.2.14 Analog video performance

The video output standard follows the source material. The OSD can be switched between PAL and NTSC by the
application software.
The module has 5 analog video outputs in 4 format: CVBS, Y/C, and RGB (YUV).
For DVD set used, the output format including: CVBS, Y/C, YUV
Signal name Video format Remark

CVBS_OUT CVBS CVBS on mpeg board
Y_VID, C_VID Y/C For a/v board
Y_VID, B_VID, R_VID YUV(RGB) For a/v board
For TV used, the output format including: Y/C and YUV(RGB)

Signal name Video format
Y_VID, C_VID Y/C
R_VID, B_VID, G_VID YUV(RGB)
Note:
There are a 75ohm output resistor in series for Y/C and YUV (RGB) signals, RGB and YUV component video signals
shared the same lines. Therefore, the module is not able to output both RGB and YUV at the same time.
The video outputs comply fully with [PQR_IMS].

Although not mentioned in [PQR_IMS], RGB and YUV have similar specifications.
Superimposed DC level: 1.2V

Output impedance: 75ohm
Note:
The video performance complies fully with PQR class III. But the following specifications are better than [PQR_IMS]:
Signal-to-noise ratio: better than 65dB.
Video bandwidth: 8MHz +/-3dB
Copy Protection: CSS

WSS,
Closed Caption
Macro-vision Version 7.1.L.1 for NTSC/PAL interlaced video outputs
The analog video output connector including CVBS and SCART.

EN 44 12 MSD-512S Warnings, lasersafety instructions and notes
2. Safety Instructions, Warnings, Notes, and Service Hints

2.1 Safety Instructions 2.2 Warnings
2.1.1 General Safety 2.2.1 General
Safety regulations require that during a repair: All ICs and many other semiconductors are susceptible to
Connect the unit to the mains via an isolation transformer. electrostatic discharges (ESD, ). Careless handling
Replace safety components, indicated by the symbol , during repair can reduce life drastically. Make sure that,
only by components identical to the original ones. Any during repair, you are at the same potential as the mass of
other component substitution (other than original type) may the set by a wristband with resistance. Keep components
increase risk of fire or electrical shock hazard. and tools at this same potential.
Available ESD protection equipment:
Safety regulations require that after a repair, you must return – Complete kit ESD3 (small tablemat, wristband,
the unit in its original condition. Pay, in particular, attention to connection box, extension cable and earth cable) 4822
the following points: 310 10671.
Route the wires/cables correctly, and fix them with the – Wristband tester 4822 344 13999.
mounted cable clamps. Be careful during measurements in the live voltage section.
Check the insulation of the mains lead for external The primary side of the power supply (pos. 1005), including
damage. the heatsink, carries live mains voltage when you connect
Check the electrical DC resistance between the mains plug the player to the mains (even when the player is 'off'!). It is
and the secondary side: possible to touch copper tracks and/or components in this
1. Unplug the mains cord, and connect a wire between unshielded primary area, when you service the player.
the two pins of the mains plug. Service personnel must take precautions to prevent
2. Set the mains switch to the 'on' position (keep the touching this area or components in this area. A 'lightning
mains cord unplugged!). stroke' and a stripe-marked printing on the printed wiring
3. Measure the resistance value between the mains plug board, indicate the primary side of the power supply.
and the front panel, controls, and chassis bottom. Never replace modules, or components, while the unit is
4. Repair or correct unit when the resistance ‘on’.
measurement is less than 1 Mohm.
5. Verify this, before you return the unit to the customer/ 2.2.2 Laser
user (ref. UL-standard no. 1492).
6. Switch the unit ‘off’, and remove the wire between the
The use of optical instruments with this product, will
two pins of the mains plug.
increase eye hazard.
Only qualified service personnel may remove the cover or
2.1.2 Laser Safety attempt to service this device, due to possible eye injury.
Repair handling should take place as much as possible
This unit employs a laser. Only qualified service personnel may with a disc loaded inside the player.
remove the cover, or attempt to service this device (due to Text below is placed inside the unit, on the laser cover
possible eye injury). shield:
Laser Device Unit CAUTION VISIBLE AND INVISIBLE LASER RADIATI ON WHEN OPEN AVO ID EXPOSURE TO BEAM
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING VED ÅBNING UNDGÅ UDSÆTTELSE FOR STRÅLING
Type : Semiconductor laser ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING NÅR DEKSEL ÅPNES UNNGÅ EKSPONERING FOR STRÅLEN
VARNING SYNLIG OCH OSYNLIG LASERSTRÅLNING NÄR DENNA DEL ÄR ÖPPNAD BETRAKTA EJ STRÅLEN
VARO! AVATT AESSA OLET ALTTIINA NÄKYVÄLLE JA NÄKYMÄTT ÖMÄLLE LASER SÄTEILYLLE. ÄLÄ KAT SO SÄT EESEEN
GaAlAs VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEÖFFNET NICHT DEM STRAHL AUSSETSEN
DANGER VISIBLE AND INVISIBLE LASER RADIATI ON WHEN OPEN AVO ID DIRECT EXPOSURE TO BEAM
Wavelength : 650 nm (DVD) AT TENTION RAYO NNEMENT LASER VISIBLE ET INVISIBLE EN CAS D'OUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU
: 780 nm (VCD/CD)
Output Power : 20 mW
Figure 2-2
(DVD+RW writing)
: 0.8 mW
(DVD reading) 2.2.3 Notes
: 0.3mW
(VCD/CD reading) Dolby
Beam divergence : 60 degree Manufactered under licence from Dolby Laboratories. “Dolby”,
“Pro Logic” and the double-D symbol are trademarks of Dolby
Laboratories. Confidential Unpublished Works.
©1992-1997 Dolby Laboratories, Inc. All rights reserved.
Figure 2-3
Figure 2-1
Trusurround
TRUSURROUND, SRS and symbol (fig 2-4) are trademarks of
SRS Labs, Inc. TRUSURROUND technology is manufactured
Note: Use of controls or adjustments or performance of under licence frm SRS labs, Inc.
procedure other than those specified herein, may result in
hazardous radiation exposure. Avoid direct exposure to beam.
Figure 2-4
Warnings, lasersafety instructions and notes MSD-512S 13 EN 44
2.3 Service Hints
2.3.1 Handling Chip Components
CL 26532047_002.eps
050402
Figure 2-5 Handling Chip Components
2.3.2 ComPair
There is no ComPair available.
2.4 Service Tools
Test discs
– Audio signals disc 4822 397 30184
Torx screwdrivers
– Set (straight, T2 to T20 4822 395 50145
– Set (square, T10, T15, T20to T20 4822 395 50132
2.5 Revision Information
Service Manual Version : 1.0
Issue Date : Jun, 2003
Revision Information : N/A

EN 44 14 MSD-512S Dismantling instructions and exploded view
3. Directions for use

Not Applicable
4.1 Exploded view - Loader Assy
4.2 Dismantling instructions and exploded view -MPEG Assy
1. Uncover the top shield
Bottom shield
2. Remove the two screws
3. Unsolder the three joints

Diagnostic Software descriptions and troubleshooting MSD-512S 15 EN 44
5. Diagnostic software descriptions and troubleshooting

5.1 Introduction
5.1.1 Purpose
This chapter describes all interfaces from the
outside world to the diagnostic software, what is
needed to use these interfaces and how to access
them. This chapter will specify the software
requirements of the Diagnostic Software for the
SD5.12, SD5.2, and SD5.31 Modules (using LSI
Logic’s ZiVa5 backend processor). This also
includes support for players/sets that use the said
modules, whether I2C master or I2C slave.
5.1.2 Scope
This chapter has been realized within the framework Front Panel Key Usage:
of the product development of the Some of the nuclei used in the diagnostic software
DVD (or combi) player based on the SD5.12, SD5.2 require user intervention through the front panel
or SD5.31 module. It will only contain keys. The keys used are defined according to the
information relevant to the version 7.xx (Y) of the model and what is indicated in the [MRS_DSS] and
Diagnostic software. [SDD_DN].
5.1.3 Definitions and abbreviations 5.3 Description Of Interfaces
5.1.3.1 Definitions 5.3.1 Menu Interface

Control PC: The menu interface is part of the Level 2 / Second
Automatic test equipment, part of the production Line diagnostic mode. It is possible to control the
control system in the factory, to control the execution of the Diagnostic Nuclei via the menu
execution of Diagnostic Nuclei in the DVD player. interface.
Diagnostic Nucleus:
Part of the Diagnostic Software. Each nucleus 5.3.1.1 Set-up physical interface components
contains an atomic and software independent Hardware required:
diagnostic test, testing a functional part of the DVD • Service PC
player hardware on component level. • One free COM port on the Service PC
Script: • Special cable to connect DVD player to Service
Part of the Diagnostic Software. Each script PC
contains a sequence of Diagnostic Nuclei to be
executed. The service PC must have a terminal emulation
Service PC: program (e.g. OS2 WarpTerminal or Procomm /
PC used by a service- or repair-person to Windows Hyperterminal) installed and must have a
communicate with the Diagnostic Software in the free COM port (e.g. COM1). Activate the terminal
DVD player. emulation program and check that the port settings
for the free COM port are 19200 bps, 8 data bits, no
5.1.3.2 Abbreviations parity, 1 stop bit and no flow control. The free COM
FDS: Full Diagnostic Software port must be connected via a special cable to the
RS232 port of the DVD player. This special cable
will also connect the test pin, which is available on
the connector, to ground (i.e. activate test pin).
5.2 Overview of Interfaces
5.3.1.2 Activation
The table below shows an overview of the user Switch AC power of the player to ON and the
interfaces of the Diagnostic Software. The table is following text will appear on the screen of the
based on logical interface, interfaces as seen from terminal (program):
user perspective. A logical interface can use one or
more physical interface components. DVDv6 Diagnostic Software version 7.00 A
The DVD has only a single RS232 port, implying Front Panel Processor: SLAVE 2
that all interfaces using this port are mutually
exclusive. (M)enu, or (C)ommand ? [M]:@
In the next chapters the logical user interfaces are Note: for SD5.xx modules, the operating system
described in more detail including the exact use of outputs startup messages prior to starting the DSW
the physical interface components. at a baud rate equal to 38400. Because the terminal
emulation program running in the PC is set to 19200
baud, such startup messages may (or may not) be
seen as invalid characters on the terminal screen.
This is not considered as a problem in the software.
EN 44 16 MSD-512S Diagnostic Software descriptions and troubleshooting
The first line indicates that the Diagnostic software 5.3.1.4 Termination
has been activated and contains the version The menu interface can only be terminated by
number of the diagnostic. This is also an indication switching off AC power to the DVD player/module.
that the first basic nucleus (nucleus number 1) has
been executed successfully. The term “DVDv6”
implies that the DSW is running in the ZiVA5 5.3.2 Command Line Interface
platform (6th generation). Interpretation of the DSW The command line interface is part of the level 1
version is done as follows: diagnostic mode. The execution of Diagnostic
Nuclei can be controlled via a command line
(YY) Minor revision number, a two-digit number interface.
incremented for every release of a DSW variant.
5.3.2.1 Set-up physical interface components
(X) Major revision number, always fixed to 7
Hardware required:
• Control PC
• One free COM port on the Control PC
version X.YY Z • Special cable to connect DVD player to the
Control PC
The control PC must use the following port settings
for the used COM port: 19200 bps, 8 data bits, no
parity, 1 stop bit and no flow control. The control PC
(Z) DSW variant ID letter, identifies the module/player where is connected with a special cable to the RS232 port
this DSW was targeted to run: of the DVD player. Via the same connection the test
A – SD5.11, I2C Master module-based players
B – SD5.2, I2C Master module, used in DVD760 players
pin will be connected to ground.
C – SD5.2, I2C Master module, used in high-end SACD2003
players
D – SD5.12, I2C Slave module, used in MTV combi 5.3.2.2 Activation
applications
S – SD5.31, I2C Slave module, used in MTV combi After power on the following text will be sent to the
applications control PC
After switching ON the set with the special cable

The next line displays the result of the subsequent connected to the PC, the diagnostic software will
basic tests (the detection of the display type used ask the user for the mode of operation. Enter “C” to
by the panel). See [SDD_DN] for an explanation of select Command mode. The last line is the prompt
this nuclei. If not all these messages appear on the (“DD:>”). The diagnostic software is now ready to
terminal screen, then the related nucleus found an receive commands.
error. The last line is the prompt asking the user to
choose the interface format. If the Menu Interface is
DVDv6 Diagnostic Software version 7.00 A
chosen (enter ‘m’), the main menu will then appear.
For the layout of the menus, see appendix B. Front Panel Processor: SLAVE 2
(M)enu, or (C)ommand ? [M]:@ C Enter

To switch between interfaces, the DVD player DD:>
needs to be switched off and on again.
Note1: Some DVD players have no power-ON key, but can be Note: Some DVD players have no power-ON key,
turned on by connecting the power-cable. but can be turned on by connecting the power-
cable.
5.3.1.3 Usage
To select, type the number of the chosen menu-item 5.3.2.3 Usage
at the prompt. Each entry must be terminated with a The commands that can be given are the reference
<return>. Invalid selections will cause an error IDs of the test nuclei. A command must be
message by the Menu Handler. Example: terminated with a <return> character from the
control PC. When typing commands, the backspace
Select> 99 key can be used to make corrections.
Invalid menu choice, number out of range ER @
Press RETURN to continue...@ In case of typing errors in the command, an error
message is returned. Example:
Result and output of an activated (and terminated) nucleus will
be sent back to the service terminal according to the standard DD:>CompSdramWrR¿ (Nuclei name cannot be accepted)
layout as defined in Appendix C. Example: 0001 Unknown command ER @
DD:>
Select> 3
1300 OK @
Press RETURN to continue...@
If the command (the nucleus ID) is recognized, the
nucleus is executed. Results and outputs of an
After the user presses a key, the current menu is activated (and terminated) nucleus will be sent back
rebuilt on screen. to the control PC according to the standard layout
Pressing <return> at the prompt without any further as defined in Appendix C.
input at the terminal will return the user the parent
menu in the menu hierarchy. Example for a command without error:
DD:>13¿ (Execute PapAtapiEcho nuclei)

1300 OK @
DD:>
5.3.4.2.1 Set-up physical interface components

Example for a command with error: Hardware required:
DD:>13¿ • DVD player
1304 No response from ATAPI drive ER @
DD:> The DVD player is tested stand-alone: no other
equipment than the DVD player is needed.
5.3.2.4 Termination 5.3.4.2.2 Activation

The command line interface is terminated by The dealer script is activated by pressing and
switching off AC power from the DVD holding dealer script activation keys on the local
player/module. keyboard of the DVD player simultaneously during
power-on. The key used differs according to the
model used. Refer to the [MRS_DSS] for details on
5.3.3 UDE Interface (not available yet, applies only to the keys used.
SD5.2 modules)
5.3.4.2.3 Usage
5.3.3.1 Set-up physical interface components The test requires no user interaction. A number of
Hardware needed: nuclei will be run before a message is returned
• Control PC indicating if there is a failure in the DVD player.
• One free COM port on the Control PC During the execution of a script, a progress indicator
• Special cable to connect DVD player to Control is displayed on the local display of the DVD player.
PC
• UDE monitor tool running on the Control PC
5.3.3.2 Activation
Busy_0 7
To start the UDE interface, connect the RS232
cable to the Control PC in the correct manner. Then The counter at the right side of the display counts
start the PC, start the monitor tool and start the down from the number of nuclei to be run to zero. A
DVD player. Select the UDE-interface by typing ‘u’ full description of the contents of the dealer script is
at the first command prompt. Next, turn off the given in document [SDD_DSS].
monitor tool and turn on UDE monitor tool. The UDE At zero all nuclei from the script have been run and
monitor tool now takes-over all communication. the result (PASS/Error) is displayed on the local
The UDE interface can also be activated by sending display of the DVD player.
a character with the ASCII bit pattern <TBD> at the
first command prompt, when the user is asked to When the dealer script has been completed, the
choose an interface type. The command handler will results are displayed in the following manner:
then activate the UDE pass-through nucleus. The
character sent will be passed to this nucleus without
loss.
_PASS__
Note: Some DVD players have no power-ON key,
but can be turned on by connecting thepower-cable. _ERROR_
5.3.3.3 Termination
To terminate UDE pass-through mode, switch off
AC power to the DVD player/module 5.3.4.2.4 Termination
To turn off the dealer test, the DVD player must be
5.3.4 Script Interfaces (for I2C Master mode modules powered down.
only)
This interface is used during execution of the Player
Script and the Dealer Script to display output and 5.3.4.3 Player Script
error messages.
The local display will be used to display the output 5.3.4.3.1 Set-up physical interface components
and the error messages. Hardware needed:
• DVD player
5.3.4.1 Local Keyboard • television set, connected to the DVD player
The following keys on the local keyboard can be • 6 audio speakers
used as user input to control the execution of the • an external video source
Diagnostic Software Scripts.
5.3.4.3.2 Activation
• PLAY key The player script is activated by pressing and
• STOP key holding the player script activation keys on the local
• OPEN/CLOSE (EJECT) key keyboard of the DVD player simultaneously during
power-on. The key used differs according to the
Unless otherwise specified, all references to keys model used. Refer to the [MRS_DSS] for details on
mentioned in this document will be referring to the the keys used.
LOCAL FRONT PANEL keyboard.
5.3.4.3.3 Usage
5.3.4.2 Dealer Script The player test requires human interaction to decide
whether the nuclei give correct output, e.g. the user
needs to confirm the results of the display test. This
needs to be given through the local keyboard on the (EJECT) key) until the user presses PLAY key on
DVD player. The keys used for this purpose are the local keyboard to proceed to the next test. To
described with each test. indicate that a LED did not light up, the user must
press the STOP key.
Module test (with user interaction)
During the first phase of the dealer test, the three During LED test the local display looks something
main modules (Digital PWB, Display PWB and like this:
Basic Engine) are tested; some interaction from the
user is required.
Ledtest
1. Testing the Display PWB
This not only involves testing the local display and
keyboard, but also testing the remote control and
the leds. The display and local keyboard test are 5.3.4.3.3.3 The Keyboard Test
described here, for a description of the other tests During the keyboard test, the user needs to press
see documents [SDD_DN] and [SDD_DSS]. all the keys on the local keyboard one by one. On
the local display each key is represented by its scan
At the beginning of the tests for the player script, the code (a hexadecimal 2-digit code identifying the key
DSW version number will be indicated on the local to the DVD player).
display of the DVD. The display will look like Pressing a key will show its scan code on the local
display of the DVD player. The first hexadecimal
digit identifies the key pressed. The second
indicates how many times this particular key was
D-7 :12:B Example for DVD760 model detected. In case the key is pressed more than
once, the scan code is displayed on each key press,
with the second digit of its code increased each
time. The display of scan codes scrolls from right to
D-7 :00:C Example for Q75 model left, with the most recent scan code at the right. The
following example gives a possible layout of the
local display during the keyboard test:
Pressing the PLAY key will proceed to the front
panel S/W version display which is shown on the
local display of the DVD player. The display will look
like:
KB_:__:__
K02:21:A3
SLV__2 :22
To terminate the keyboard test, press the PLAY key
on the local keyboard of the DVD player and hold it
Press the PLAY key to proceed to the next test. for 1 (one) full second. The keyboard test will
terminate with a message on the local display. If the
5.3.4.3.3.1 The Display Test keyboard test was successful, you will see the
During the display test, different patterns will be following message:
shown on the local display of the DVD player. For a
specification of the patterns that will be shown on
display, see document [SDD_DN] or [SDD_DSS].
The user needs to step through these patterns
KB-PASS
using the OPEN/CLOSE (EJECT) key on the local
keyboard. If any of the displayed patterns is
incorrect, the user should press the STOP key to If the keyboard test was not successful, the
indicate that a fault was detected during this test. following message will be displayed:
The test patterns on display will be repeated in a
loop (stepped through using OPEN/CLOSE
(EJECT) key) until the user presses PLAY key on
the local keyboard to proceed to the next test.
KB-FAIL
5.3.4.3.3.2 The LED Test If the “KB-FAIL”- message is displayed, the player
Next is the LED test where the LEDs on the DVD test has failed. This is the end of the keyboard test.
player are lit. The LED test of a changer model is Press PLAY key on the local keyboard of the DVD
different from the LED test of a single disc model. player to proceed to the next test.
For a single disc model (non-changer): 5.3.4.3.3.4 The remote control test
To indicate that a LED did not light up, the user For the remote control test, the user must press a
must press the STOP key. Pressing PLAY key will key (any key) on the DVD’s remote control. The
let the user proceed to the next test. display at the start of the test looks as follows:
For a changer model:

Three test patterns on the LEDs will be repeated in
RC : :
a loop (stepped through using OPEN/CLOSE
When a remote control code has been received, its the user for confirmation. For a specification of the
scan code is displayed as follows: pictures, see document [SDD_DSS]. When the
picture has been put on screen, the local display
asks for confirmation from the user by displaying the
R10:01 :23 following message:
The PLAY key can be pressed to exit this test. APP :PIC1
However, if the user is required to test all keys on
the remote control, (s)he can continue to press the
remote control keys and these will all be displayed If the user presses PLAY key, he confirms the test;
on the local display. With a code table at hand this pressing STOP key will indicate a fault in the test.
test can be used to test the full functionality of the The user can proceed to the next test by pressing
DVD’s remote control. PLAY key on the local keyboard of the DVD player.
When the user has pressed PLAY key on the local Pressing the PLAY key on the local keyboard will
keyboard (NOT on the remote control!), the result of start the next test. A predefined sound will be
the remote control test is shown on the local display generated, and again the user is asked to confirm
as follows: this. At the same time, a colour bar pattern is
if successful, generated at the video outputs to test the SCART
outputs. For a specification of the sounds, see
document [SDD_DSS]. The local display looks as
RC-PASS follows:
if the test fails. SCR :DVD_

RC-FAIL Pressing the PLAY key and OPEN/CLOSE (EJECT)
key switches between [SCART DVD] and [SCART
LOOP]. Pressing the STOP key indicates test
Pressing PLAY key on the local keyboard again will failure. For the 1st sound test, the scart loop-
let us proceed to the next test. through [SCART LOOP] will be tested at the same
time. Subsequent sound tests will be numbered in
The P50 loop-back test (applies to models with ascending order. Pressing and holding the PLAY
double SCART connection) key for more than one second will start the next test.
We have 2 sound test nuclei available now.
For the P50 loop-back test, the user must first press
a key to decide if he wants to perform the test. The
display at the start of the test looks as follows: SCR:LOOP
P50-TEST The next nuclei tests the audio functionality of the
module by generating a 1Khz sinusoidal signal and
passing it to the audio outputs. The display looks as
If the user presses STOP key, then the P50 test will follows:
be skipped. If the user presses OPEN/CLOSE
(EJECT) key, the P50 test is performed and the
result is displayed as follows:
APP:SND2
if successful,
Pressing the STOP key on the local keyboard will

P50-PASS stop and mute the audio output.
Pressing PLAY key on the local keyboard of the
DVD player will take the user to the next test.
if test fails.
3. Testing the Basic Engine

P50-FAIL Most tests on the basic engine require user
interaction. When the basic engine tests are started,
the version of the basic engine present in the DVD
Press PLAY key to continue. player is shown on the local display, as follows:
2. Testing the Digital PWB module

The digital PWB is tested with a number of tests (for
B07:09:00
description of the tests, see [SDD_DSS]), among
which are picture and sound tests. The version number is displayed in decimal
The picture tests involve putting a predefined representation (the colon ‘:’ replacing the dot). If the
picture on the connected television set, and asking
version query fails on the basic engine, it will be

shown as:
BE-FOCS
BV-FAIL
By pressing OPEN/CLOSE (EJECT) key the user
confirms successful focusing by the basic engine;
When the user presses PLAY key on the local pressing STOP key indicates a fault in the focus
keyboard, the tests on the basic engine are started. function.
Pressing PLAY key on the local keyboard starts the
First, the tray operation is tested. The user can radial function; the local display looks as follows:
move the tray in and out by pressing the
OPEN/CLOSE (EJECT) key on the local keyboard.
The results need to be checked visually by the user,
the software cannot detect any faults. The local
BE-RADI
display looks as follows:
Again, pressing OPEN/CLOSE (EJECT) key
confirms the result. STOP key indicates an error.
BE-TRAY After pressing PLAY key on the local keyboard, the
grooves/jump test is started. As this is also a test
that cannot be checked by the software, the user
For changer mechanisms (DVD795, Yamaha needs to perform a visual test. The local display
C740/C940), when a tray OPEN operation is done, looks as follows:
the DSW first rotates the carousel by one slot in the
counterclockwise direction before opening the tray.
This allows the user to conveniently load and
unload discs from the tray. When loading discs,
BE-GROO
always place the disc at the upper left most slot in
the tray. By pressing OPEN/CLOSE (EJECT) key the next
grooves/jump position is taken. Switching through
Besides testing the tray, this test is also meant to the different positions is done in a cyclic manner.
give the user the opportunity to put a disc into the Press the PLAY key on the local keyboard to
DVD player for subsequent basic engine tests. proceed to the last basic engine test, the tray test.
Some of the following tests need a DVD disc in the This has been done at the beginning of the basic
DVD player to operate properly. Always put a DVD engine test but is repeated to enable the user to
disc into the DVD player during this test! At the remove the disc in the tray before proceeding. The
end of the basic engine tests, there is an local display will look as follows:
opportunity to remove it (before the loop tests start).
Press the PLAY key on the local keyboard to
proceed to the next test. BE-TRAY
The second test is the sledge test. The user is
asked to move the sledge by using the keys Press OPEN/CLOSE (EJECT) key to open the tray.
OPEN/CLOSE (EJECT) key on the local keyboard. Remove the disc in the tray.
This test needs to be checked visually by the user. The tray will be closed automatically (if needed)
The software cannot detect any faults. The local before proceeding to the next tests (by pressing
display during this test looks as follows: PLAY key on the local keyboard).
Read Error Log

BE-SLED The contents of the error log will be displayed on
1
the local display, as follows :
After pressing PLAY key on the local keyboard, the

disc motor will be tested next. The local display
looks as follows:
E15:01:0A
1
Note that this is an example only; no actual
BE-DISC errorcode is intended
The first two characters on the local display (“E”)

The user is required to listen if the disc motor is indicate that the read-out mode of the error log is
running. This must be confirmed by pressing activated. After the hyphen, 6 hexadecimal digits
OPEN/CLOSE (EJECT) key on the local keyboard. (one fault code) are displayed. To step through the
The STOP key is used to indicate that the disc different fault codes, the OPEN/CLOSE (EJECT)
motor is not running. key on the local keyboard can be used. The display
of fault codes is cyclic. If the error log does not
Pressing PLAY key on the local keyboard starts the contain any fault codes, all displayed error codes
focus test. The local display looks as follows during will be “E00:00:00”.
this test:
Note: Fault codes are usually 8 hex digits in length.

)DXOW\ OK )DXOW\
However, due to limitations in some of the displays,
only the last 6 hex digits are displayed. This is still )DXOW\ )DXOW\ OK
acceptable since all fault codes known so far have a
)DXOW\ )DXOW\ )DXOW\
value “00” in the first two digits.
To switch off the display of the error log, the PLAY After the hyphen the (decimal) number indicates the
key must be pressed on the local keyboard. number of times the loop test was performed.
The right side of the display shows an error code
Read Error Bits DNER (in decimal representation), which is built
The error bits are used to indicate that an error from a nucleus number (DN) and an error number
occurred once or more times. If an error has (ER). This code indicates the last nucleus that
occurred, the bit representing the error is set. To returned an error code. For explanation of this
read out this field of error bits, the local display is DNER code, see document [SDD_DN].
used. Only the numbers of the errors where the bit
is set will be displayed on the local display. The The loop test will run indefinitely until it is
layout on the local display is as follows2: terminated, which is done by switching off the power
to the DVD player.
End result of the player test is equal to the last
EB-___0A display shown above. It shows which module is
faulty and which nucleus caused the last error, as
well as how many loops were performed.
2
Note that this is an example only; no actual
errorbit is intended 5.3.4.3.4 Termination
To terminate the player test, switch off AC power to
The number of the set bits is displayed in a cyclic the DVD player/module.
manner. Scrolling through the set error bits can be
done with the OPEN/CLOSE (EJECT) key. Pressing
the PLAY key at the last bit number will display the 5.3.5 External Scripts
first bit number again while pressing the STOP key A script is a sequence of nucleus calls. Internal
button at the first bit number will display the last bit scripts (e.g. scripts built into the diagnostic software
number in the list. The representation of bit itself) are in the form of a C-language module.
numbers is decimal. However the customer cannot be expected to write
If no error bits are set, the number on the right side C-modules in order to create new scripts.
of the display will be “00” The scripts that can be made externally are
therefore in one of the following two forms:
Module Looptest
The module loop test is an infinite loop in which a 1. A Procomm or Telex script
number of nuclei are executed over and over again. Procomm or Telex can be used to write diagnostic
The nuclei run are the same as in the dealer test; scripts. The script language of both communication
user interaction is not required. During this loop test, packages contains possibilities for construction of
3
the display looks as follows : loops and branches in the scripts. Commands sent
will be exactly the same as described in the chapter
Display the 3-digit module “Command Interface”. The diagnostic software (the
010 23 bits together with the
current loop count.
engine) will receive normal RS232 commands and
processes these as defined, sending results of
these nuclei back over the RS232 line. In the
After one loop cycle: Display
the 3-digit module bits Terminal the Procomm or Telex script determines
010:5403 together with the last error
code which occurred in the
loop test for 1sec.
which command sequence is followed
2. An Asterix-script
Asterix-scripts are C-programs in which commands
3
Note that this is an example only; no actual are sent to the diagnostic software (the engine). The
display-layout is intended. construction of branches and loops is again located
in the remote machine, i.e. the Asterix machine.
The leftmost three digits indicate which of the DVD Commands sent will be exactly the same as
player’s modules is faulty; the explanation is in the described in the chapter “Command Interface”. The
following table: diagnostic software (the engine) will receive normal
RS232 commands and processes these as defined,
sending results of the called nuclei back over the
Module Bit' Indication for each module RS232 line. In the Asterix PC the C-program
Displayed determines which command sequence is followed.
value Basic Engine Digital PWB Display PWB
5.3.6 Layout of menus and submenus for the Service
000 OK OK OK
Terminal
001 OK OK )DXOW\ NOTE: a symbol “...” in the next menu layouts
indicates that that specific menu choice will invoke
010 OK )DXOW\ OK
the display of a submenu. This symbol will also be
011 OK )DXOW\ )DXOW\ used in the implementation of the menus (i.e. the
“...” will also appear in the user interface). The list is
)DXOW\ OK OK
exhaustive and is accurate as of version 7.00 S. For SACD players/modules only

Actual versions encountered could be slightly
different. MAIN > FURORE MENU
5.3.6.1 Main Menu 1. SDRAM Write/Read [63]

2. SDRAM Write/Read Fast [64]
MAIN MENU 3. Chip Revision ID [65]
1. Audio... 4. Set Output High [84a]
2. Video... 5. Set Output Low [84b]
3. Front Panel... 4. Reset Furore IC [83]
4. Basic Engine...
5. Processor Peripherals...
6. Error Log... MAIN > MISCELLANEOUS MENU
7. Miscellaneous...
1. Statistics Info...
5.3.6.2 First Level Submenus 2. Read DVD Application version [46]
MAIN > AUDIO MENU
1. Mute...
2. Pink Noise... 5.3.6.3 Second level submenus
3. Sine Wave...
4. Digital Ports... MAIN > AUDIO > MUTE MENU
5. Ext. DAC Board...
1. Mute On [19a]
2. Mute Off [19b]
MAIN > VIDEO MENU
1. Colourbar...
2. Scart... MAIN > AUDIO > PINK NOISE MENU
3. Digital Port...
1. Pink Noise On [20a]
For single-disc, I2C master modules only 2. Pink Noise Off [20b]
MAIN > FRONT PANEL MENU
1. Slave Processor...
2. VFT Display [30a] MAIN > AUDIO > SINE WAVE MENU
3. LCD Display [30b]
4. LCD BkLight [30c] 1. Audio Sine On [21a]
5. Keyboard [27] 2. Audio Burst On [21b]
6. LEDs [29]
7. Remote Control [28]
8. P50 Check [60]
For SACD modules/players only
For disc changer, I2C master modules only MAIN > AUDIO > EXT DAC BOARD MENU
MAIN > FRONT PANEL MENU 1. DAC Reset [79]

1. Slave Processor... 2. I2C Test...
2. VFT Display [30a] 3. Clock...
3. LCD Display [30b] 4. Audio...
4. LCD BkLight [30c] 5. Low Power Standby...
5. Keyboard [27] 6. DAC Mode...
6. LEDs...
7. Remote Control [28]
8. P50 Check [60]
MAIN > VIDEO > COLOURBAR MENU
1. Colourbar DENC On (PAL) [23a]

MAIN > BASIC ENGINE MENU 2. Colourbar DENC On (NTSC) [23c]
1. Reset [44] 3. Colourbar DENC/MPEG Off [23b]
2. Version [37] 4. Progressive Scan [24c]
3. Communications... 5. Set Video Out To RGB [61a]
4. Loader Mechanism... 6. Set Video Out To YUV [61b]
5. Special Diagnostics...
MAIN > PROCESSOR PERIPHERALS MENU

MAIN > VIDEO > SCART MENU
1. Clock...
1. I2C Scart IC Check [54]
2. Flash...
2. Scart To DVD [55a]
3. NVRAM...
3. Scart Pass Through [55b]
4. Processor Info [5]
4. Scart Pin 8 Low (0 to 2)V [25a]
5. Slave IIC Loopback Test [90]
5. Scart Pin 8 Mid (4.5 to 7)V [25b]
6. Scart Pin 8 Hi (9.5 to 12)V [25c]
MAIN > ERROR LOG MENU
1. Read Last Errors [31] MAIN > VIDEO > DIGITAL PORT MENU
2. Read Error Bits [32]
3. Reset Error Log [33] 1. Video Port Out 0xAA [17a]
For SACD players/modules only 2. Video Port Out 0x55 [17b]
For I2C master modules only

MAIN > PROCESSOR PERIPHERALS > NVRAM MENU
MAIN > FRONT PANEL > SLAVE PROCESSOR MENU
1. I2C NVRAM access [11]
1. Bus Comms Check [12] 2. NVRAM Config [34]
3. NVRAM Reset [35]
2. S/W Version [26] 4. NVRAM Modify [36]
5. NVRAM Read/Wr Test [15]
For disc changer, I2C master modules only
MAIN > MISCELLANEOUS > STATISTICS INFO MENU

MAIN > FRONT PANEL > LEDS MENU
1. Total Nr Of Times Tray Open [47a]
1. Test Front Panel LEDs [29] 2. Total Time Power On [47b]
2. I2C comm check IO Expander [29a] 3. Total Play-Time CDDA & VCD [47c]
4. Total Play-Time DVD [47d]
MAIN > BASIC ENGINE > COMMUNICATIONS MENU
1. ATAPI/UDE Echo [13]

2. UDE Pass-Through [14] 3.6.4 Third level submenus
For SACD players/modules only

For single-disc modules only
MAIN > AUDIO > EXT DAC BOARD > I2C TEST MENU
MAIN > BASIC ENGINE > MECHANISM MENU
1. I2C Test [66a]
1. Disc Motor... 2. I2C Enable Pin On [66b]
2. Laser... 3. I2C Enable Pin Off [66c]
3. Tray...
4. Focus...
5. Radial... For SACD players/modules only
6. Sledge...
7. Grooves... MAIN > AUDIO > EXT DAC BOARD > CLOCK MENU
1. Clock Internal [67a]

For disc changer, I2C master modules only 2. Clock External [67b]
3. Clock Upsampling 192k (963 only) [82a]
4. Clock Upsampling 96k (963 only) [82b]
MAIN > BASIC ENGINE > MECHANISM MENU 5. Clock Upsampling On (963 only) [82c]
6. Clock Upsampling Off (963 only) [82d]
1. Disc Motor...
2. Laser...
3. Changer Mechanism...
For SACD players/modules only
4. Focus...
5. Radial...
6. Sledge... MAIN > AUDIO > EXT DAC BOARD > AUDIO
7. Grooves...
1. Audio Pre-Mute On [68a]
2. Audio Pre-Mute Off [68b]
3. Audio Center On [69a]
MAIN > BASIC ENGINE > SPECIAL DIAGNOSTICS MENU
4. Audio Center Off [69b
1. Read FlashID [70]

2. ROM Checksum [71] For SACD players/modules only
3. Scratch Detector Test [72]
MAIN > AUDIO > EXT DAC BOARD > LOW POWER
For SACD players/modules only STANDBY
MAIN > PROCESSOR PERIPHERALS > PCM CLOCK MENU 1. Low Power Standby On [81a]
2 Low Power Standby Off [81b]
1. Ext PCM_CLK In CDDA Mode (11.3MHz) [7a]
2. Ext PCM_CLK In DVD Mode (12.3MHz) [7b]
3. Ext PCM_CLK In DVD96kHz Mode (24.6MHz) [7c] For SACD players/modules only
MAIN > AUDIO > EXT DAC BOARD > DAC MODE MENU
For NON-SACD players/modules only
1. DAC CDDA Mode [80a]
2. DAC DVD48 Mode [80b]
MAIN > PROCESSOR PERIPHERALS > PCM CLOCK MENU 3. DAC DVD96 Mode [80c]
4. DAC DSD Mode [80d]
1. Int PCM_CLK In CDDA Mode (11.3MHz) [8a]
2. Int PCM_CLK In DVD Mode (12.3MHz) [8b]
3. Int PCM_CLK In DVD96kHz Mode (24.6MHz) [8c]
MAIN > BASIC ENGINE > MECHANISM > DISC MOTOR
MENU
MAIN > PROCESSOR PERIPHERALS > FLASH MENU
1. Verify FLASH Checksum [6]
1. Disc Motor On [39a]
2. Show FLASH Checksum [62]
2. Disc Motor Off [39b]
3. Flash Write Access [10]
MAIN > BASIC ENGINE > MECHANISM > LASER MENU 3. Front Panel...
4. Basic Engine...
1. CD Laser On [58a] 5. Processor Peripherals...
2. CD Laser Off [58b] 6. Error Log...
3. DVD Laser On [58c] 7. Miscellaneous...
4 DVD Laser Off [58d]
Select> 4 <enter>
For single-disc players/modules only
MAIN > BASIC ENGINE MENU
MAIN > BASIC ENGINE > MECHANISM > TRAY MENU 1. Reset [44]
2. Version [37]
1. Tray Open [43b] 3. Communications...
2. Tray Close [43a] 4. Loader Mechanism...
5. Special Diagnostics...
For disc changer players/modules only Press Enter to go to Main Menu.
Select> 5 <enter>
MAIN > BASIC ENGINE > MECHANISM > CHANGER MENU
MAIN > BASIC ENGINE > SPECIAL DIAGNOSTICS MENU
1. Initialize [91a]
2. Tray Open [91b] 1. Read FlashID [70]
3. Tray Close [91c] 2. ROM Checksum [71]
4. Disc Clamp Down [91d] 3. Scratch Circuit [72]
5. Disc Clamp Up [91e]
6. Rotate CW <n> times [92a] Press Enter to go to Main Menu.
7. Rotate CCW <n> times [92b]
8. IO Expander I2C Comm [92c] Select> 1 <enter>
MAIN > BASIC ENGINE > MECHANISM > FOCUS MENU ------------------<bottom of screen>-------------------------
1. Focus On [38a] (load DVD first) Depending on the height of the screen, the text will
2. Focus Off [38b]
start scrolling off the top of the screen.
MAIN > BASIC ENGINE > MECHANISM > RADIAL MENU

5.3.6.6 Layout of Results diagnostic nuclei on
1. Radial Control On [40a] (load DVD first) control/service PC
2. Radial Control Off [40b] Results returned from a Diagnostic Nucleus to the
control/service PC will have a maximum length of
300 characters and are terminated by a ‘@’ and CR
MAIN > BASIC ENGINE > MECHANISM > SLEDGE MENU character (included in the string length)
1. Sledge Inwards [41a]
2. Sledge Outwards [41b] The result has the following layout:
<additional information><CR>
<number><string> [OK | ER] @<CR>
MAIN > BASIC ENGINE > MECHANISM > GROOVES (Uses
DVD) MENU The use of the “@” enables the Asterix system on
1. Jump To Inside Grooves [42a] the Control PC to parse the output string of each
2. Jump To Middle Grooves [42b]
3. Jump To Outside Grooves [42c]
nucleus into a database.
<additional information> are strings which contain a

number information which was produced during the
5.3.6.5 Screen layout with menus execution of the test nuclei. These include
When menus are used, no specific screen layout checksum values, progress indicators, etc.
can be given. Menu information will not be in a
special format, except for the layout as mentioned in <number> is a 4-digit decimal number padded with
the previous paragraphs. leading zeros if its value is less than 4 digits. The
A typical menu session can look as follows for a first two digits identify the generating nucleus (or
changer player’s diagnostics: group of nuclei) while the latter two digits indicate
the error number.
---------------<top of screen>---------------------------------
<string> is a text string containing information about
DVDv6 Diagnostic Software version 7.00 B the result of the Diagnostic Nucleus.
Slave Processor: SLAVE2
<number> and <string> are defined in [SDD_DN] in
(M)enu, or (C)ommand? [M]:@ <enter> the output sections of each Nucleus.
Press ENTER to go to main menu.
Examples:
CC:> <enter> 1. 0001 Unknown command ER @
2. 3100 OK @
MAIN MENU 3. 0901 Data line X is not connected to the DRAM ER @
4. Device ID: 0x01
1. Audio... Manufac ID: 0xC2
2. Video... 7000 OK @
Block and wiring diagrams MSD-512S 25 EN 43
6. Block and wring diagram
6.1 BLock diagram MSD-512S
MPEG BOARD
A TAPI connector ELINK connector
HRST 1 2 GND Flash
GND 1 2 +5V
HD (15 ) 3 4 H D (0 ) MEDUSACSn 3 4 +5V
1M x 16 M29W160
HD (14 ) 5 6 H D (1 ) A LE 5 6 SYSRSTn
2M x 16 M29W320
HD (13 ) 7 8 H D (2 ) UPA2 7 8 UPA3
ATAPI TSOP48
LOADER Connector
HD (12 )
HD (11 )
9 1 0 H D (3 )
11 12 HD (4 )
ELINK UPD15
UPD13
9 10 UPA1
11 12 UPD14
Connector
A97ST HD (10 )
HD (9 )
13 14 HD (5 )
15 16 HD (6 ) UPA [1:22 ]
UPD11
UPD9
13 14 UPD12
15 16 UPD10
HD (8 ) 17 18 HD (7 ) UPD [0:15 ] UPD8 17 18 GND
GND 19 20 SYSRSTn UPD6 19 20 UPD7
DMARQ 21 22 GND UDS UPD4 21 22 UPD5
LDS 23 24 GND FLASHCSn UPD2 23 24 UPD3
UPA [1:3 ] UDS 25 26 GND UPA [1:3 ] UPD0 25 26 UPD1
UPD [0:15 ] DTACKn 27 28 UPD [0:15 ] MEDUSAINTn 27 28 DTACKn
DTACKn DMACK 29 30 GND A LE LDS 29 30 UDS
LDS HIRQ1 31 32 Trans p arent latch LDS R/W 31 32 GND
UDS UPA2 33 34 74HCT573 UDS
HDMAC K UPA1 35 36 UPA3 74HCT573 SYSRSTn
HDMARQ IDECS0 37 38 IDECS1 74HCT573 DTACKn
LDRST 39 40 GND MEDUSAINTn
IDECS [0:1 ] MEDUSACSn
HCSn [3:4 ] R/W
HIRQ1 UPA [1:3 ]
UPD [0:15 ]
A LE
A TAPI Host interface
Clock
MA [0:11 ] Circuit
BA [0:1 ] SDRAM interface
SDRAM MD [0:31 ]
MCS0n
DECODER IC
MRASn
MCASn MCS1n
512K x 32 x 4
MWEn
LSI Logic
1M x 32 x 4 MCLK Ziva5
MDQM [0:3 ] SYSRSTn Reset
Circuit
MT48LC4M32B2TG-7
MT48LC2M32B2TG-7-TR
GPIO I2C I2C A nalo g Di g ital A udio I2S Service and JTAG bus

(misc ) Master Slave video audio X CLK dia g nostic p ort RST
GPIO SCL SCL VDAC [0:4 ] SPDIF BCLK RTS1 TDO
IR SD A SD A LRCLK RXD1 TDI
A DATA0 TXD1 TMS
CTS1 TCK
Module interface bus
SCL
SD A Audio DAC
AK4382
NVRAM
64K bits
Analog Audio output
Block and wiring diagrams MSD-512S 26 EN 43
6. Block and wring diagram
6.2 Wiring diagram MSD-512S
1608
Lt/Rt/CVBS/COAX con
For /00 stroke version: 1606
8001 3104 311 06311 CBLE HR 3P4/340/3P HR WH SCART connector
8002 3104 311 06301 CBLE HR 7P/340+220/3P+4P HR BK
8003 3139 131 01841 CBLE HR-BK 3P/140/3P HR-BK
8004 3139 131 03151 CBLE HR 03P/180/03P HR (BRAIDED)
8005 3139 131 02841 CBLE HR-BK 06P/600/08P HR-BK 8003
1621 Lt/Rt
8006 3141 010 21592 CWAS 40RK/40RK 400 SHIELD 28S
For /69 stroke version: 8004
8001 3139 131 02691 CBLE HR 04P/400/03P HR 1620 SPDIF
8002 3139 131 02612 CBLE HR 06P/480/04P HR FERR
8003 3139 131 02321 CBLE HR-BK 3P/400/3P HR-BK 26OS BK 8002
8004 3139 131 03151 CBLE HR 03P/180/03P HR (BRAIDED) 1619 1618
8005 3139 131 02841 CBLE HR-BK 06P/600/08P HR-BK
8006 3141 010 21592 CWAS 40RK/40RK 400 SHIELD 28S Y/C RGB
1610 Power
For /78 stroke version:
8006 3141 010 21901 CWAS 40RK/40RK 400 28S
8001
For /ARG stroke version: 1603
8006 3141 010 21901 CWAS 40RK/40RK 400 28S I2C
From Power Supply
1611
8006 JTAG
MPEG SD5.12
ATAPI
1601 1620
E-link
LOADER
A97ST
1600 VFD driver 1615 PSU

Service 1615
8005
Electrical Diagrams and Print-layouts MSD-512S 27 EN 44
Electrical Diagrams MPEG Board SD5.12
1 2 3 4 5 6 7 8
3V3
M 1 Decoder & Peripheral Circuits 2625

100n
2626
100n
2627
100n
2628
100n
2629
100n
2630
100n
2631
100n
2632
100n
2633
100n
GNDD
2634
100n
2635
100n
2636
100n
2637
100n
2638
100n
2639
100n
2640
100n
DA_XCK 3615 33R PLL_3V3
33R VFD_DATA
DA_LRCK 3616 33R 1V8
33R VFD_CLK
REF_GND
33R VFD_CS
A DA_BCK 3617 33R V3V3 A
DAC_DATA
DA_DATA0 3618 33R REF_3V3 1600 C1 3666 F5
DAC_CLK
180R/1%
DAC_CS
PLL_GND 2641 2642 2643 2644 2645 1611 D2 3667 F6
3p
3p
VID_COMP
2617
2618
MUTE
5601 100n 100n 100n 100n 100n 2601 C1 3668 E6
3669
TP19 2602 D1 3669 A5
VID_C
VID_Y
VID_U
VID_V
IEC958 3648 33R 1V8 DGND 3V3 GNDD 2603 E1 3679 B1
3V3 TP16
13.5MHz GNDA 2604 F1 3685 B2
4k7
4k7
4k7
4k7
4k7
D3V3 GNDD 2605 B2 3686 C2
135 1K/1%
136 3650
3V3 5VD 2606 B2 3724 F5
22p
22p
22p
22p
22p
115 3881
114 3882
113 3883
TP24
2607 B2 3725 F5
GNDD 2608 B2 3881 A6
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
109
108
107
106
105
119
118
117
116
112
110
111
0R
0R
4k7
4k7
3626
3627
3628
3629
3630
2612 B2 3882 A6
2605
2606
2607
2608
2612
2613 B1 3883 A6
3603
3604
7602 2614 E3 3911 C3
IEC958
BCK
VDAC_VDD0
VDAC_VDD1
VDAC_VDD3
VDAC_VDD4
VDAC_DVSS
HSYNC/IRQ2
VDAC_DVDD
XOUT
VDAC_Ref
XCK
XIN/VCLK216BP
XVSS
XVDD
LRCK
VDAC_RefVSS
VDAC_RefVDD
VCLK
VDAC_0
VDAC_1
VDAC_2
VDAC_3
VDAC_4
GNDP
VDDP
GNDP
VDDP
VDAC_0B
VDAC_1B
VDAC_2B
VDAC_3B
VDAC_4B
GND
VDD
VDAV_VDD2
ADATA3
ADATA2
ADATA1
ADATA0
VDATA0
VDATA1
VDATA2
VDATA3
VDATA4
VDATA5
VDATA6
VDATA7
AVDD1
AVDD2
AVSS1
AVSS2
M24C64-WMN6T 2617 A4 3912 C3
1 8 2613 S_I2C_CL GNDD 5VD 3V3 2618 A4 3913 C3
3613
3611
E0 VCC
100n GNDD S_I2C_DA 157 104 2619 F2 3914 D3
DAI_DAT A VDD25
2 7 TP6 GNDD SCART1 158 103 2620 F2 5600 C1
E1 /WC DAI_BCK/SYSCLKBP GND25 GNDD MDATA31
B M_I2C_CL SCART0 159
DAI_LRCK/IEC958BP MD31
102 2621 F3 5601 A4 B
3 6 TP7 M_I2C_CL 3631 68R 160 101 MDATA30 2622 F3 7600 C5
E2 SCL 12C_CL MD30
M_I2C_DA M_I2C_DA 68R 161 100 MDATA29 2623 F3 7602 B1
12C_DA MD29
4 5 /LDRST 3632 162 99 MDATA28 2624 F3 7603 B1
VSS SDA RTS1 MD28
5VD RxD_SER 163 98 2625 A4 7604 C2
RXD1 VDD25 3V3 MDQM3
TxD_SER 164 97 2626 A4 7605 D1
TXD1 MDQM3
3685 4k7
GNDD 5VD 165 96 2627 A4 7606 E1

3679 1k CTS1 GND25 GNDD MDATA27
166 95 2628 A4 7607 F1
GNDD GNDP MD27
TP1 7603 167 94 MDATA26 2629 A4
3640 3V3 VDDP MD26
BC847B /LDRST DMARQ 168 93 MDATA25 2630 A5
SDDAT A7 MD25
TxD_SER 169 92 MDATA24 2631 A5
100R 3635 3633 SDDAT A6 MD24
170 91 2632 A5
2601
MDATA23
3686 SDDAT A5 MD23
1n5
1600 4k7 5VD 171 90 MDATA22 2633 A5

3912 0R
3911 0R
3638 4k7 SDDAT A4 MD22
172 89 2634 A5
3634 4k7
MDATA21
1 4k7 GNDD GND MD21
TP3 GNDD 173 88 MDATA20 2635 A5
2 4k7 1V8 VDD MD20
GNDD SERVICE GNDD 174 87 2636 A6
3 SDDAT A3 VDD25 3V3 MDQM2
TP4 3V3 175 86 2637 A6
4 SDDAT A2 MDQM2
3641 RxD_SER DMACK 176 85 2638 A6
5 SDDAT A1 GND25 GNDD MDATA19
C 6 TP5 3642 10k
177
SDDAT A0 MD19
84 2639 A6 C
7604 178 83 MDATA18 2640 A6
7 SDREQ MD18
179 82 MDATA17 2641 A6
10k SDEN MD17
FB
PH-7P 180 81 2642 A6

3643
MDATA16
3644 BC847B GNDD GNDP MD16
6k8
181 80 2643 A7
3V3 VDDP VDD 1V8
5VD 182 79 2644 A7
10k SDERROR GND GNDD MDATA15
5600
GNDD 183 78 2645 A7

SDCLK MD15
GNDD HIRQ1 3913 184 77 MDATA14 3603 B1
3645 VSYNC/HIRQ1 7600 MD14
4k7 185 76 MDATA13 3604 B1
5VD 10k RTS2 MD13
186 75 MDATA12 3611 B2
5VD 4k7 RXD2 MD12
HIRQ1 187 74 3613 B2
TXD2 VDD25 3V3 MDQM1
UPA[21..1] S_I2C_RDY 3914 188 ZIVA5 73 3615 A2
CTS2 MDQM1
189 72 3616 A2
5VD VNW GND25 GNDD MDATA11
F3V3 ALE 3649 33R 190 71 3617 A2
ALE MD11
/IDE_CS1 191 70 MDATA10 3618 A2
HCS4 MD10
/IDE_CS0 192 69 MDATA9 3626 B3
HCS3 MD9
/MEDUSA_CS 193 68 MDATA8 3627 B3
HCS2 MD8
7605 194 67 MDATA7 3628 B3
2602 20 HCS1 MD7
D VCC CLK
11 /FLASH_CS 195
HCS0 MD6
66 MDATA6 3629 B3 D
100n 1 196 65 MDATA5 3630 B3
OC 1611 3V3 VDDP MD5
GNDD 10 TP8 TRST 197 64 MDATA4 3631 B3
GND 1 TRST MD4
UPA20 19 2 UPA1 TP9 TDO 198 63 3632 B3
1Q 1D 2 TDO VDD25 3V3 MDQM0
UPA21 18 3 UPA2 5VD TP10 SERVICE 199 62 3633 C2
2Q 2D 3 TDI MDQM0
17 4 TP11 TMS 200 61 3634 C2
3Q 3D 4 TMS GND25 GNDD MDATA3
16 5 TP12 TCK 201 60 3635 C2
4Q 4D 3637 5 TCK MD3
15 6 TP13 202 59 MDATA2 3636 E2
5Q 5D 10k 6 RESET MD2
14 7 203 58 MDATA1 3637 D2
6Q 6D PH-6P BUSCLK MD1
13 8 GNDD 204 57 MDATA0 TP15 3638 C1
7Q 7D GND MD0 33R /SD_CLK
12 9 TP14 205 56 3653 3640 B1
8Q 8D 1V8 VDD MCLK
/SYS_RST 206 55 3641 C1
HA3 VDD25 3V3
74LVT573DB 207 54 3642 C1
HA2 GND25 GNDD
208 53 3643 C1
2614 GNDP MWE 3668A
HDTACK
7606 /MWE 3644 C1
HREAD
GND25
VDD25
GND25
VDD25
2603 20
HIRQ0
IRRX1
MRAS
MCAS
VDDP
VDDP
GNDP
VDDP
GNDP
HUDS
11 GNDD 3645 C2
MCS0
MCS1
HLDS
MA10
MA11
ALE 100n
HD15
HD14
HD13
HD12
HD10
HD11
GND
VDD
VCC CLK 33R
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
HA1
HD9
HD8
HD7
HD6
HD5
HD4
HD3
HD2
HD1
HD0
BA1
BA0
100n 1 3648 A2
OC
GNDD 10 GNDD 3649 D4
GND
E UPA12 19
1Q 1D
2 UPD8 3650 A5 E
UPA13 18 3 UPD9 3651 F4
2Q 2D
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
11
1
2
3
4
5
6
7
8
9
UPA14 17 4 UPD10 UPA3 3636A 33R 3668B 33R /MCAS 3652 F4

3Q 3D
UPA15 16 5 UPD11 3668C 33R /MRAS 3653 E7
4Q 4D
UPA16 15 6 UPD12 UPA2 3636B 33R 3668D 33R /MCS0 3658 E6
5Q 5D
14 7 GNDD 3658 33R 3659 E6
33R
33R
UPA17 UPD13 BA0

33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
6Q 6D
UPA18 13 8 UPD14 3V3 3V3 3V3 1V8 3V3 3659 33R BA1 3660 F4
7Q 7D
UPA19 12 9 UPD15 UPA1 3636C 33R 3661 F4
8Q 8D
3V3 3662 F4
74LVT573DB 3663 F4
3664A
3664D
3665A
3665D
3666A
3666D
3667A
MADDR113667D
3664B
3664C
3665B
3665C
3666B
3666C
3667B
MADDR103667C
/DTACK 3724
/MEDINT 3725
3664 F5
7607 3665 F5
2604 20
MADDR9
MADDR8
MADDR7
MADDR6
MADDR5
MADDR4
MADDR3
MADDR2
MADDR1
MADDR0
11
VCC CLK
100n 1 V3V3 PLL_3V3
UDS
LDS
R/W
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
OC
IR
GNDD 10
GND
UPA4 19 2 UPD0
1Q 1D
UPA5 18 3 UPD1 2619 2620 2621 2622 2623 2624
2Q 2D
17 4
3660A
3660D
3661A
3661D
3662A
3662D
3663A
3663D
3660B
3660C
3661B
3661C
3662B
3662C
3663B
3663C
UPA6
3Q 3D
UPD2 100n 100n 100n 100n 100n 100n
F UPA7 16
4Q 4D
5 UPD3 F
UPA8 15 6 UPD4 GNDA PLL_GND
5Q 5D
UPA9 14 7 UPD5
UPD15
UPD14
UPD13
UPD12
UPD11
UPD10
6Q 6D
UPD9
UPD8
UPD7
UPD6
UPD5
UPD4
UPD3
UPD2
UPD1
UPD0
UPA10 13 8 UPD6
7Q 7D
UPA11 12 9 UPD7
8Q 8D
74LVT573DB
GNDD 3651 4.7K
F3V3
3652 4.7K
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
M 2 Memory Part 2661

2669 100n
SD3V3
2680 100n
F3V3 100n 100n 1601 E2 5640 F3
100n 2670 2679
37
A GNDD 1602 E4 5641 E3 A
7610 2671 100n 2678 100n 1603 C7 5642 E3
UPA1 25 29 UPD0 1605 A6 5643 E3
A0 DQ0
VCC
UPA2 24 31 UPD1 2672 100n 2677 100n 1610 E7 5644 E3
A1 DQ1
UPA3 23 33 UPD2 1621 D7 5645 E3
A2 DQ2 100n 100n
UPA4 22 35 UPD3 2673 2676 2609 B2 5646 E3
A3 DQ3
UPA5 21 38 UPD4 2661 A2 5647 E3
A4 DQ4
UPA6 20 40 UPD5 TP29 1605 2662 C1 5648 E3
A5 DQ5
15
29
43
81
75
55
35
49
41
19 42 STDY_CTRL 5660 FB 2663 D1 5651 F3
9
UPA7 UPD6
A6 DQ6 1
UPA8 18 44 UPD7 7611 2690 2664 F5 5660 A6
A7 DQ7
UPA9 8 30 UPD8 GNDD GNDD 100p TP30 2665 E4 5661 B6
A8 DQ8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VFD_DATA 5661 FB
VDD
VDD
VDD
VDD
UPA10 7 32 UPD9 2667 D3 5662 B6
A9 DQ9 2
UPA11 6 34 UPD10 MADDR0 25 2691 2668 C3 5663 B6
A10 DQ10 A0
UPA12 5 36 UPD11 MADDR1 26 2 MDATA7 22p TP31 2669 A4 5664 B6
A11 DQ11 A1 DQ0 5662 FB
UPA13 4 39 UPD12 MADDR2 27 4 MDATA6 VFD_CLK 2670 A4 5711 C6
A12 DQ12 A2 DQ1 3
UPA14 3 41 UPD13 MADDR3 60 5 MDATA5 2692 2671 A4 5712 C6
A13 DQ13 A3 DQ2
UPA15 2 43 UPD14 MADDR4 61 7 MDATA4 22p TP32 2672 A4 5713 C6
A14 DQ14 A4 DQ3 5663 FB
UPA16 1 45 UPD15 MADDR5 62 8 MDATA3 VFD_CS 2673 A4 5714 C6
A15 DQ15/A-1 A5 DQ4 4
B UPA17 48
A16
MADDR6 63
A6 DQ5
10MDATA2 2693 2676 A4 5772 C6 B
UPA18 17 15 MADDR7 64 11MDATA1 22p TP33 2677 A4 6604 D1
A17 RY/BY A7 DQ6
UPA19 16 MADDR8 65 13MDATA0 2678 A4 7608 C5
A18 A8 DQ7 5
UPA20 3696 9 MADDR9 66 74MDATA31 3919 2679 A4 7609 C5
0R A19 0R A9 DQ8
103694 UPA21 MADDR1024 76MDATA30 TP34 2680 A4 7610 A2
NC/A20 A10 DQ9 5664 FB
/FLASH_CS 26 13 MADDR1121 77MDATA29 IR 2681 C7 7611 B4
/CE NC3 A11 DQ10 S_I2C_DA 6
R/W 28 143692 47R 79MDATA28 2683 C7 7612 D2
/OE NC4 12V DQ11 2694
UDS 11 BA0 22 80MDATA27 3606 EH-6P 2690 B6
/WE 2609 BA0 DQ12 3800 100p
/SYS_RST 12 BA1 23 82MDATA26 2691 B6
VSS1
VSS2
/RST BA1 DQ13 5k6

47 100n 83MDATA25 2692 B6
F3V3 /BYTE DQ14 GNDD
GNDD MDQM0 16 85MDATA24 7609 BSN20 2693 B6
M29W160DT-70N1 DQM0 DQ15
/MCS0 MDQM3 71 31MDATA8 2694 B6
2662 DQM1 DQ16
MDQM1 28 33MDATA9 2833 C7
DQM2 DQ17
27
46
100n
MDQM2 59 34MDATA10 2839 E6
3906 DQM3 DQ18
GNDD 36MDATA11 2849 D6
100R DQ19
37MDATA12 2895 E6
DQ20 TP25
/MCS0 20 39MDATA13 FB 2896 E6
/CS DQ21 S_DA_O 5713
40MDATA14 FB 3606 B6
DQ22 M_I2C_DA 5714
C 2668 /MWE 17
/WE DQ23
42MDATA15 3918 22p 1603 3608 C6 C
5VD 3V3 18 45MDATA16 2833 TP26 1 3654 E6
10p /MCAS
/CAS DQ24 M_I2C_CL 5711 FB
/MRAS 19 47MDATA17 FB 3655 E6
/RAS DQ25 S_I2C_CL S_CL_O 5712
GNDD 48MDATA18 2 3692 B2
67
DQ26
50MDATA19 2681 22p
TP27 3694 B2
CKE DQ27 3799 3608
3904 3903 /SD_CLK 68 51MDATA20 3 3696 B1
0R CLK DQ28 TP28
53MDATA21 5k6 3698 C1
DQ29 S_I2C_RDY
14 54MDATA22 7608 BSN20 4 3699 D2
10k
3907 NC DQ30 5772 FB 2683
30 56MDATA23 3700 D1
3905 3698 3902 100R NC DQ31 22p EH-4P
57 3915 3701 D1
NC
3704
4k7 69 3V3 3704 D3
2663 3699 NC
70 0R 3799 C5
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
/SYS_RST
47U/10V NC GNDD
VSS
VSS
VSS
VSS
2667 73 3916 3917 3800 B5
3700 1k NC
GNDD 7612 10p SD3V3 5VD 3902 C2
MT48LC2M32B2TG-7 3903 C1
6604
BAS316
10k BC847B GNDD

GNDD 3904 C1
3701
86
72
58
44
84
78
12
32
52
38
46
6
10k
3905 C1
GNDD 3906 C3
D 3907 C3 D
GNDD 3915 D6
3916 D6
3917 D6
3918 C5
3919 B5
TP57 1621 5617 D6
Rt 5617 0R
22p 1 5618 E6
5VD 2849 TP58 5621 E1
2665 2 5622 E1
1601 TP59
FB 100n 0R 5623 E1
5621 1 2
Lt 5618 2002-07-12
3 5624 E1
UPD15 5622 FB 5648 FB UPD0 2839 22p
3 4 GNDD EH-3P 5625 E1
UPD14 5623 FB 5647 FB UPD1
FB 5 6 FB 1602 5626 E1
UPD13 5624 5646 UPD2 GNDA
FB 7 8 FB 5627 E1
UPD12 5625 5645 UPD3 1 2
FB 9 10 FB
/MEDUSA_CS 5628 E1
UPD11 5626 5644 UPD4 3 4 TP60
FB 11 12 FB
ALE /SYS_RST 3654 5629 E1
UPD10 5627 5643 UPD5 5 6
FB 13 14 FB
UPA2 UPA3 5VD 1610 5630 E1
UPD9 5628 5642 UPD6 7 8
E FB 15 16 FB
UPD15 UPA1 0R 1 5631 E1 E
UPD8 5629 17 18 5641 UPD7
UPD13
9 10 UPD14 2895 22p TP61 5632 E1
11 12
FB 19 20 UPD11 UPD12 2 5633 E1
DMARQ 5630 13 14 TP62
FB 21 22 UPD9 UPD10
22p 5634 E1
LDS 5631 15 16 2896
FB 23 24 UPD8 3 5635 E1
UDS 5632 17 18 GNDD EH-3P
FB 25 26 UPD6 UPD7 3655 5636 E1
/DTACK 5633 19 20
FB 27 28 UPD4 UPD5 -12VA 5637 F1
DMACK 5634 21 22
FB 29 30 UPD2 UPD3 0R 5638 F1
HIRQ1 5635 23 24
FB 31 32 UPD0 UPD1
UPA2 5636 25 26
FB 33 34 FB
/MEDINT /DTACK
UPA1 5637 5640 UPA3 27 28
FB 35 36 FB
LDS UDS
/IDE_CS0 5638 5651 /IDE_CS1 29 30
37 38 R/W
/LDRST 31 32
39 40
HEADER 20X2 HEADER-32P 2664
100n
GNDD
GNDD
F F
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
M 3 Audio Part
Lt_OUT
A A
Rt_OUT
1608 B7
3910
+12VA_ 1 2723 B2
REF_1
2752 E2
5k1 1% 2768 2755 C6
2756 B6
8
100n
GNDA 2757 C2
3734 3780 7626A
5VA 3 2760 B4
4k7 1% 2769 1 2761 C4
3777 200R 1% 470p2 2762 C5
5k1 1%
14
2770 LM833D 2763 C4
7620 3n3 TP42 2764 B4
DAC_CS 6 16 2767 2760 3766 470R Lt 3 1608B 2765 B3
CSN DZFL
4
VDD
DAC_CLK 7 15 GNDA 100n 100u TP44 2766 B4
CCLK DZFR 3778 2766 -12VA 3767 2756
DAC_DATA 8 GNDA 3765 1 2767 B4
CDTI 100k 680p
12 200R 1% 3779 390p 2k7 L 2768 A4
AOUTL+ 3776
B DA_XCK 1
MCLK AOUTL-
11 7628 GNDA 2769 B4 B
DA_LRCK 4 4k7 1% 5k1 1% BC817-25 2770 B3
LRCK
DA_BCK 2 10 GNDA 2771 C4
BICK AOUTR+ 3784
PDN
VSS
DA_DATA0 3 9 2840 C2
SDTI AOUTR- REF_2 7626B
5k1 1% 2841 C2
3771 3773
5 LM833D 2915 E2
3737 AK4382A
4k7 1% 2764 7 3612 D4
5VA 3774 200R 1%
13
5
470p
6 3614 D4
4k7 2723 5k1 1%
GNDA 2765 3734 A3
3n3 TP43 3737 B2
47u 2761 3763
GNDA 470R Rt 2 1608A 3741 D3
7627B GNDA 100u 3747 E2
3772 2763 3764 3762
5 2755 1 3748 E2
100k
+12VA_ 1 7 200R 1% 3770 390p 2k7 680p R 3750 E3
REF_2 3775
6 7633 GNDA 3751 E3
LM833 BC817-25 3752 D3
MUTEC
5602 4k7 1% 5k1 1%
+12VA GNDA 3753 C3
FB 6629 3754 C3
2757
C BAS316 3757 C4 C
3759 2762 3758 C4
3884 100n 3757 6601 0R
GNDA 100u 3759 C5
8
10k 7627A 6k8 BAS316 3762 C6

5VA
3 GNDA 3763 C5
3758 7629
1 3764 C5
2841 3885 2 REF_1 BC857B
2840 3753 3765 B5
47u 100n 10k 2k2
1k 2771 3766 B5
LM833
3754 7630 47u 3767 B6
BC857B 3770 C3
4
GNDA GNDA 1k GNDA 3771 B3

7631 6603 3772 C3
MUTE
3741 7632 3773 B3
3612 3614 BAS316 3774 B3
4k7 68k 220k 3775 C3
BC847B
BC847B 3776 B3
3777 B3
3778 B3
3752
GNDA -12VA
D 3779 B3 D
TP40 3780 A3
4k7
MUTEC 3784 B3
3884 C2
3885 C2
3910 A3
5602 C2
6601 C4
6603 D4
6629 C4
7620 B2
7624 E2
7626 B4
7627 C2
7628 B5
7629 C5
7630 C4
7631 D3
E 3747
7632 D3 E
SPDIF 7633 C5
22R
5VD
2752
100n
5
GNDD 7624
3748 2915 3750 TP35
IEC958 2 4 5 1608C
100R 100n 330R TP36
1 4
3751 COAX
91R
74HCT1G125
GNDA
3
GNDD
F F
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
M 4 Video Part +5V_VID

+5V_VID -12VA
1618
1619
1620
2783
D5
D5
E5
A2
3827
3828
3829
3830
D3
D3
D3
D4
2785 A2 3831 E1
A 3804 3806 2786 A2 3832 E1 A
2900 2901 2783 68k 470R 2787 A2 3833 E2
2848
100n
3807 7640B
470p 10p 10p 7652 3864 2790 C2 3834 E3
7640A BC847BPN
2k2 2792 C2 3835 E3
3801 5715 5702 2787 100R TP63
VID_COMP 3860 3865 2793 C2 3836 E3
BC847BPN BC847B CVBS_OUT_AV 6 1608D
2u2 2u2 2u2 100R 2794 C2 3837 E3
0R 3808 3810 Y_VID 68R 6621 2795 C3 3838 E3
3802 3803 3805 2821 4
Y_VID +5V_VID -12VA BZX284-C15 2798 D2 3839 E3
75R 1% 75R 1% 47k 220R 68R 3785 220p CVBS
2902 2785 2786 2800 D2 3840 E4
3809 75R 1% 3861 GNDA CVBS
390p 470p 390p 2801 D2 3841 B1
100R 2802 D2 3842 B1
220R 3723 7653 3866 GNDA
GNDA 2803 D3 3843 B2
GNDA 2k2 2806 E2 3844 B3
0R 3867
BC847B CVBS_OUT 2808 E2 3845 B3
2809 E2 3846 B3
68R
+5V_VID +5V_VID -12VA 2810 E2 3847 B3
2811 E3 3848 B3
2814 B2 3849 B3
B 3844 3846 2816 B2 3850 B4 B
2903 2904 2814 68k 470R 7655 3870
G_VID 2817 B2 3860 A4
2819
100n
3847 7644B 680R
470p 10p 10p 2818 B2 3861 A4
7644A BC847BPN 3871 2825
BC847B G_OUT 2819 B3 3864 A5
3841 5716 5704 2818 100R
VID_C
470u 2821 A5 3865 A5
BC847BPN 68R
2u2 2u2 2u2 2825 B5 3866 B5
0R 3848 3850 +5V_VID -12VA
C_VID 2838 E5 3867 B5
3842 3843 3845 2848 A3 3870 B5
75R 1% 75R 1% 47k 220R 68R 3786
2905 2816 2817 2853 C5 3871 B5
3849 75R 1%
390p 820p 390p B_VID
7657 3874 2857 C5 3874 B5
680R 2900 A1 3875 C5
220R 3715
GNDA 3875 2857 2901 A2 3876 C5
BC847B B_OUT
0R GNDA 2902 A2 3877 C5
68R 470u 2903 B1 5615 E5
+5V_VID +5V_VID -12VA 2904 B2 5665 E1
2905 B2 5666 D1
2906 C1 5667 C1
3814 3816 2907 C2 5702 A2
2906 2907 2790 68k 470R 7658 3876
C R_VID 2908 C2 5704 B2 C
2795
100n
3817 7641B 680R

470p 10p 10p 2909 D1 5706 C2
7641A BC847BPN 3877 2853
BC847B R_OUT 2910 D2 5708 D2
3811 5717 5706 2794 100R
VID_Y
470u 2911 D2 5710 E2
BC847BPN 68R
2u2 2u2 2u2 2912 E1 5715 A2
0R 3818 3820 G_VID 2913 E2 5716 B2
3812 3813 3815 2914 E2 5717 C2
75R 1% 75R 1% 47k 220R 68R 3787
2908 2792 2793 3646 E5 5718 D2
5667 3819 75R 1%
390p 820p 390p 3647 E5 5719 E2
0R TP45 3712 E3 6621 A5
220R 3714 1618 EH-5P
GNDA R_VID 3713 E3 7640 A3
1
0R GNDA TP46 3714 D3 7641 C3
3715 C3 7642 D3
2
TP47 3723 B3 7643 E3
+5V_VID B_VID 3781 E4 7644 B3
3
TP48 3785 A4 7652 A5
3786 B4 7653 B4
3824 3826 4
TP49 3787 C4 7655 B4
D 2909 2910 2798 68k 470R G_VID 3788 D4 7657 B4 D
2803
100n
3827 7642B 5
10p 10p 10p TP50 3801 A1 7658 C4
7642A BC847BPN 1619
Y_VID 3802 A1
3821 5718 5708 2802 100R 1
VID_U TP51 3803 A2
BC847BPN
2u2 2u2 2u2 3804 A3
0R 3828 3830 2
B_VID TP52 3805 A3
3822 3823 3825 C_VID EH-4P 3806 A3
75R 1% 75R 1% 47k 220R 68R 3788 3
2911 2800 2801 TP53 3807 A3
5666 3829 75R 1%
390p 820p 390p 3808 A3
4
0R 3809 A3
220R 3713
GNDA GNDA 3810 A4
0R GNDA 3811 C1
3812 C1
+5V_VID 3813 C2
3814 C3
TP54 3815 C3
3834 3836 1620
TP55 3816 C3
2912 2913 2806 68k 470R 0R 1
SPDIF 5615 3817 C3
100n
2811
3837 7643B
E 470p 10p 10p 7643A BC847BPN 2838 22p
2
3818 C3 E
TP56 3819 C3
3831 5719 5710 2810 100R 3646
VID_V 3820 C4
BC847BPN 3 EH-3P
2u2 2u2 2u2 3821 D1
0R 3838 3840 0R
R_VID GNDD 3822 D1
3832 3833 3835 3647
3823 D2
75R 1% 75R 1% 47k 220R 68R 3781 5VD
2914 2808 2809 3824 D3
5665 3839 75R 1% 0R
390p 820p 390p 3825 D3
0R 3826 D3
220R 3712
GNDA
0R GNDA
F F
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
M 5 Power & Scart port 5742

+5V_VID
5770 FB 3
7673
LD1117ADT18TR
2
TP79
1V8
FB 1206
A 2892 2868 2883 2881 2880 1606 D5 3909 E2 A
47u 100n 100n 220u/6.3V 100n 1615 A1 3920 C4
1
2754 D4 3921 B2
GNDA 2759 D4 5741 B1
5744 GNDD 2822 C2 5742 A2
5VD 5747 FB 5751
FB 2823 C2 5744 A2
F3V3 REF_3V3
2871 FB 2824 C2 5745 A2
7622
1206 2884 2850 F4 5747 A3
100n 2879
TP64 LD1086D2T33 TP78 100u 100n 2852 F3 5748 B3
1615 5745
+5VD GNDD 3 2 3.3V 2854 E4 5749 B3
1 5748 FB 5752
FB
1206 GNDD REF_GND 2855 E4 5750 B3
2893 SD3V3 PLL_3V3
2866 2867 1206 FB 2856 E3 5751 A4
100n 100u 220u 2886 2878 2859 D4 5752 B4
2
1
100U 100n 2861 C1 5753 B4
GNDD 2862 C1 5755 C1
5749 FB GNDD 5753 PLL_GND 2864 B2 5756 D1
3 3V3 D3V3
1206 FB 2866 B1 5757 C1
TP65 2888 2889 2877 2867 B1 5758 C1
B 4 100u 100n 5750 100n 2868 A2 5770 A3 B
FB 6611 2869 C5 5771 B1
TP80
TP66 GNDD GNDD BAS316 DGND 2870 C5 6605 F4
V3V3
12V 5741 FB +12V 2871 A2 6606 E4
5 3716
1206 2890 2891 2873 B2 6607 E4
TP67 2864 2873 47u 100n 0R 2874 C4 6608 E4
100n 220u 2877 B4 6609 E3
6
TP68 -12VA GNDA 7675 2878 B4 6610 E4
FB 3921
5771 GNDD BC327-25 TP81 2879 A4 6611 B4
0603 3880 2880 A4 7614 D3
7 33R +12VA
2862 2881 A4 7615 D3
3720 3920
TP69 100u 2883 A3 7616 E3
3717 3719 1k 3722 +12VA_ 1
STDY_CTRL 0R 2874 2884 A3 7622 A2
8 3721 33R
10K 1K 10k BC807-25 100n 2916 2886 B3 7650 F2
EH-8P 2861
100n GNDA 10k 10u 2888 B3 7651 F2
3718 7670 7671
2889 B3 7670 C3
56K BC847B BC847B
GNDA 2890 B3 7671 C3
7674
5755 GNDD 7676 TP82 2891 B3 7673 A3
MC78L05ACD
C 8
IN OUT
1
5VA
2892 A2 7674 C4 C
FB 2893 B2 7675 B4
GNDD GNDD GNDD 4 5 2869 2870 2916 C5 7676 C4
GNDA NC1 NC2
5758 100n 47u 3673 E3
2822 GND 3674 F4
2823
FB GNDA 3675 E3
100n
100n 3676 E3
REF_GND
2
3
6
7
2824 3677 E3
5757 GNDA GND1
100n 3678 D3
FB GNDA 3680 D3
3681 D3
PLL_GND
5756 3682 D3
3716 B4
FB GNDD GND3 GND2 3717 C2
3718 C2
DGND TP71
Rt_OUT
3678 3719 C2
1606 3720 C3
3682 470R 3769 3721 C3
3894 MUTEC 2759
D 100k SCART-R
1
3722 C4 D
3888 2k7 680p 3760 D4
GNDD 0R 0R 3895
7614 3769 D4
2
BC817-25 TP72 3851 F1
3896 0R 3680 GNDA
Lt_OUT SCART-L 3852 F1
3889 3
3853 F1
0R 3897 3681 470R 3760
MUTEC 2754 3854 E2
0R 100k 4
680p 3855 F1
3890 3898 0R 2k7 220p
2859 3856 F1
5
7615 3857 F2
0R 0R 3899 6608
BC817-25 GNDA 3858 F2
3891 6
3859 F1
0R PDZ15BTP73
TP70 B_OUT 3862 E2
0R 220R 7
0612 3673 3880 C2
3901 0/6/12 3888 D1
2856 6609 8
3889 D1
3908 0R PDZ15B 220p
220p 2855 3890 D1
3893 9
3891 E1
0R 3909 6607
E 0R 10
3893 E1 E
GNDA 3894 D1
0R PDZ15BTP74
GNDD GNDA G_OUT 3895 D2
11
+5V_VID 6610 3896 D1
GNDD GNDA 3897 D2
3677 12
PDZ15B 3898 D1
+12VA 47k 3675 2854 220p 3899 E2
22k 13
3901 E2
3676 7616B 6606
3862 3854 3908 E1
BC847BPN 14
5VD 470R
3858 1k PDZ15BTP75
220R 15
3851 3674 TP77
7616A 2852 FBOUT
10k 16
GNDA BC847BPN 100n
3852 7650 75R 2850
SCART1 10k
BC847B 17
GNDA 220p
3853 18k R_OUT 6605
18
5VD
PDZ15BTP76
F GNDD 3857 CVBS_OUT
19 F
3855 470R
10k 20
3856 7651
SCART0 10K
BC847B 21
3859 18k
SCART
GNDD GNDA
1 2 3 4 5 6 7 8
Personal Notes: Personal Notes:

Layout MPEG MSD-512 Components Side
1600 B1 1619 E8 2723 C7 2771 D7 2800 F7 2817 E7 2850 G9 2869 B7 2893 F3 2908 F7 3611 C5 3635 C2 3648 C6 3665 E3 3682 D9 3716 G2 3741 D7 3760 E9 3776 C7 3799 C6 3811 F7
1601 A2 1620 B9 2752 A8 2783 D7 2801 F7 2818 E7 2852 E9 2870 B7 2895 A8 2909 F6 3612 D7 3636 C4 3653 F4 3666 E4 3685 B2 3717 G1 3747 B8 3763 C8 3777 B7 3800 C6 3812 E6
1602 B4 1621 B9 2759 D9 2785 D7 2802 F7 2819 E8 2853 G9 2871 E1 2896 B8 2910 F7 3613 C5 3637 B2 3654 A8 3667 E3 3686 C2 3718 H1 3748 B8 3764 C9 3778 B8 3801 E6 3813 F7
1603 A7 2612 B8 2760 B8 2786 D7 2803 F8 2821 A9 2854 F9 2873 G2 2900 E6 2911 F7 3614 D7 3639 B1 3655 B8 3668 F4 3698 B5 3719 H1 3750 B8 3765 B9 3779 B8 3802 E6 3814 F8
1605 C1 2663 B5 2761 C8 2787 D7 2806 G7 2822 G1 2855 F9 2881 F6 2901 E7 2912 G6 3615 D6 3640 C1 3658 F4 3673 E9 3699 A5 3720 G2 3751 B8 3766 B8 3780 B8 3803 D7 3815 F8
1606 F9 2683 B7 2762 D7 2790 F7 2808 G7 2823 G9 2856 E9 2883 F2 2902 D7 2913 G7 3616 D6 3641 C5 3659 F4 3674 E9 3700 B6 3721 H2 3752 C7 3770 C8 3781 G8 3804 E8 3816 F8
1608 B10 2690 C1 2763 C8 2792 F7 2809 G7 2824 B1 2857 F9 2884 E2 2903 E6 2914 G7 3617 D6 3642 C2 3660 C4 3675 E9 3704 G4 3722 G2 3753 D7 3771 C7 3784 C7 3805 D8 3817 F8
1610 A8 2691 D1 2765 C7 2793 F7 2810 G7 2825 F9 2859 E9 2886 F3 2904 E7 2915 B8 3618 C6 3644 B2 3661 D4 3676 E9 3712 G8 3723 E8 3754 D7 3772 C8 3785 E8 3806 D8 3818 F8
1611 A6 2692 D1 2766 B8 2794 F7 2811 G8 2838 B9 2862 H2 2888 E3 2905 E7 2916 C8 3630 C6 3645 B5 3662 D4 3677 E9 3713 F8 3724 D2 3757 C7 3773 C8 3786 E8 3807 D8 3820 F8
1615 E1 2693 D1 2769 B8 2795 F8 2814 E7 2840 D8 2866 E1 2890 F6 2906 E7 3603 C5 3633 B5 3646 A9 3663 D4 3678 C8 3714 F8 3725 D2 3758 D7 3774 C7 3787 F8 3808 D8 3821 F6
1618 F8 2694 D1 2770 C7 2798 F7 2816 E7 2848 E8 2867 E2 2892 H7 2907 F7 3604 C5 3634 B5 3647 A9 3664 E4 3680 B8 3715 E8 3734 B7 3759 C7 3775 C7 3788 F8 3810 E8 3822 E6
3823 F7 3881 F6 5645 B3 6631 B7

3824 F8 3882 F6 5646 B3 6633 B7
3825 F7 3883 F6 5647 B2 7600 D4
3826 F8 3902 B5 5648 B2 7602 C5
3827 F8 3904 A5 5651 B5 7603 C2
3828 F8 3905 A5 5660 C1 7604 B1
3830 F8 3908 H6 5661 D1 7605 C3
3831 G6 3910 C7 5662 D1 7606 D3
3832 E6 3911 C5 5663 D1 7607 D3
3833 G7 3912 C5 5664 D1 7608 C6
3834 G8 3913 C5 5702 E7 7609 C6
3835 G8 3914 C5 5704 E7 7610 C3
3836 G8 3915 C6 5706 F7 7611 F5
3837 G8 3916 B6 5708 F7 7612 B6
3838 G8 3918 C6 5710 G7 7614 C9
3840 G8 3919 C6 5711 B7 7615 D9
3841 E6 3920 C8 5712 B7 7616 E9
3842 E6 3921 H3 5713 B7 7620 B7
3843 E7 5600 B1 5714 B7 7622 F2
3844 E8 5601 D6 5715 E7 7624 B8
3845 E8 5615 B9 5716 E7 7626 B8
3846 E8 5617 C9 5717 F7 7627 D8
3847 E8 5618 B8 5718 F7 7628 B9
3848 E8 5621 B2 5719 G7 7629 D7
3850 E8 5622 B2 5741 F1 7630 D7
3851 C6 5623 B2 5742 E1 7631 D7
3852 C6 5624 B3 5744 E1 7632 D7
3853 C6 5625 B3 5745 E1 7633 C9
3854 B6 5626 B3 5747 E2 7640 D8
3855 C6 5627 B3 5748 F3 7641 F8
3856 C6 5628 B3 5749 E2 7642 F8
3857 B6 5629 B4 5770 F2 7643 G8
3858 B6 5630 B4 5771 F1 7644 E8
3859 C6 5631 B4 5772 B7 7650 C6
3861 E8 5632 B4 6601 C7 7651 C6
3862 B6 5633 B4 6603 D8 7652 D8
3864 E8 5634 B4 6604 B6 7653 E8
3865 D8 5635 B4 6605 G9 7655 F8
3866 E9 5636 B4 6606 F9 7657 F8
3867 E9 5637 B4 6607 F9 7658 G8
3870 F9 5638 B5 6608 E9 7670 H1
3871 E9 5640 B4 6609 D9 7671 H2
3874 F8 5641 B4 6610 E9 7673 G6
3875 F8 5642 B3 6611 G2 7674 B7
3876 G8 5643 B3 6621 A9 7675 G2
3877 G8 5644 B3 6629 C7 7676 G2
Layout MPEG MSD-512 Copper Side
2601 C1 2609 C2 2622 E6 2630 D5 2638 D5 2661 D2 2671 F4 2681 B7 2833 B7 2877 D6 3626 D6 3649 C4 3694 C2 3819 F8 3888 D6 3897 C7 3917 C6 5753 D5
2602 C3 2613 C5 2623 D5 2631 E4 2639 D4 2662 D3 2672 G5 2754 E9 2839 A10 2878 D6 3627 D6 3650 D6 3696 C2 3829 F8 3889 B6 3898 C7 5602 C8 5755 E6
2603 D3 2614 C4 2624 D6 2632 E4 2640 D4 2664 B4 2673 G4 2755 C9 2841 C8 2879 D6 3628 D6 3651 D2 3701 B6 3839 G8 3890 B7 3899 C7 5665 E6 5756 E6
2604 D3 2617 D6 2625 D4 2633 E5 2641 C4 2665 B4 2676 F5 2756 B9 2849 B10 2880 F6 3629 D6 3652 D2 3737 C7 3849 E8 3891 H6 3901 G6 5666 E6 5757 D5
2605 D6 2618 D6 2626 D4 2634 E4 2642 E5 2667 F4 2677 F4 2757 D8 2861 F1 2889 E3 3631 C6 3669 D6 3762 C9 3860 E8 3893 F6 3903 B5 5667 E6 5758 D5
2606 D6 2619 E6 2627 E4 2635 F6 2643 E4 2668 F4 2678 F4 2764 C8 2864 F2 2891 E6 3632 C6 3679 C1 3767 B9 3880 C8 3894 B8 3906 F4 5750 E6 6630 C6
2607 D6 2620 E6 2628 E5 2636 E5 2644 C5 2669 G4 2679 F4 2767 C8 2868 G7 3606 C6 3638 C2 3681 D9 3769 D9 3884 C8 3895 B8 3907 F4 5751 D5 6632 A7
2608 C6 2621 E6 2629 E5 2637 D6 2645 D6 2670 G4 2680 F5 2768 C8 2874 B7 3608 C6 3643 C1 3692 C2 3809 D8 3885 C8 3896 E6 3909 G6 5752 D5 6634 B7
TP1 C1 TP47 F8
TP3 C1 TP48 E7
TP4 D5 TP49 F8
TP5 B1 TP50 E8
TP6 C5 TP51 B7
TP7 C5 TP52 E8
TP8 B6 TP53 G7
TP9 B6 TP54 C4
TP10 B6 TP55 B9
TP11 B6 TP56 A9
TP12 B6 TP57 B10
TP13 B6 TP58 F8
TP14 B5 TP59 A9
TP15 F4 TP60 A8
TP16 D6 TP61 A6
TP19 C6 TP62 A8
TP24 E6 TP63 C9
TP25 A7 TP64 E2
TP26 A7 TP65 D4
TP27 D1 TP66 F1
TP28 A7 TP67 H3
TP29 C1 TP68 F1
TP30 D1 TP69 F1
TP31 D1 TP70 A8
TP32 D1 TP71 D9
TP33 D3 TP72 E9
TP34 D1 TP73 F9
TP35 B9 TP74 F9
TP36 F8 TP75 F9
TP40 C9 TP76 E9
TP42 B9 TP77 F10
TP43 C9 TP78 F3
TP44 C8 TP79 F6
TP45 F8 TP80 E6
TP46 G8 TP81 B7
Circuit descriptions and List of abbreviations MSD-512S 35 EN 44
8. Alignments
No electrical alignments available
9. Circuit descriptions and list of abbreviations

9.1 Decoder IC ZiVATM-5M
Refer to Appendix A for details
9.2 Hardware & Software Interface
9.2.1 Introduction
This document defines the hardware software interface (HSI) for the DVD-SD5.11 (2) module.
SD5.11 (2) use the same mpeg board for difference slash version, but with POS Mars4.3 loader named at SD5.11 and
with A97S&A97ST named at SD5.12. So the back-end s/w must support SD5.11 and SD5.12 separately, this
documentation named SD5.11 (2).
The SD5.11 (2) module contains of:

• LSI Logic ZiVA5+ back-end DVD decoder / host processor
• AK4382A for audio DAC
• ATAPI interface to POS Mars4.3 (SD5.11) or A97S&A97ST (SD5.12) loader
• Basic A/V output and SCART output
• Audio (Lt/Rt and SPDIF) output connectors and Video (YUV&S-Video) output connectors for TV and other used
• Master/Slave I2C output connector for TV used
• Diagnostic connector
• JTAG interface
9.2.2 Hardware configurations

9.2.2.1 Configuration matrix
The SD5.11 (2) module is to be used in various end products. The hardware configurations for these products might
have some differences, depending on features or functions that need to be implemented. Therefore, the hardware is
prepared to have various stuffing options. The following is the hardware configuration matrix:
Configuration Function 1 Function 2 Detection
Flash Flash Auto-detect

Back-end code memory
2MByte 2M Byte -
32bit 32bit -
Back-end SDRAM
64Mbit 64Mbit Auto-detect
I2C EEPROM I2C EEPROM -
NVRAM
32/64kbit 32/64Kbit Auto-detect
Module mode Master Slave Software build
Note:
1. "Detection" column in the table above indicates the recommended method for the software to detect the module's
hardware configuration at boot up.
2. Different software will be used for some hardware configurations. Hence, detection by software is not required.
Instead, the software should be separately built and the configurations can be selected via compiler switches.
9.2.2.2 Module mode

The SD5.11(2) module has two I2C buses. The Master I2C is using software I2C via GPIO ports & the Slave uses
hardware I2C because of its speed.
The master I2C bus is used to control all on-board devices eg. NVRAM, etc… & the Slave I2C bus is used to connect to
an external processor eg. TV micro-p which acts as the I2C Master controller. An additional signal, I2C Int, is used to
flag to the external processor when data is available in the Slave mode.
9.2.2.3 Configuration by LOR (Latch On Reset)

The host processor, ZiVA5+, has a number of Latch On Reset (LOR) pins that can be used for setting particular
modes/features upon power-up. The following pins are shown:
EN 44 36 MSD-512S Circuit descriptions and List of abbreviations
ZIVZ-5 LOR Pins

Feature vs Pin
148 150 151 154 155 156 162 164 187 185
PLL Atapi
Host Drive
LOR Feature X’tal Sel Bypass Master/
Sel System Clock Speed Sel Chip Mode Sel
Sel Slave
Master
PCM PCM PCM PCM IDE Diags Master
Normal Function LRCK IEC958 I2C,
Lt/Rt Lo/Ro Ls/Rs C/Sw Reset TXD I2C Clk
SDA
Set To:- Hi Hi Lo Lo Hi Lo Hi Lo Hi Hi
LOR Function on Low drive 13.5Mhz Use Int Muxed A/D Master Atapi
Power-up I/O 121.50Mhz X’tal PLL (Async Master Mode) Master
Note:
1. Other LOR pins are not provisioned with pull-up or pull-down resistors. Hence, the default settings are used.
2. LOR function to be checked on final layout
3. System Clock Setting can be adjusted as shown:
154 151 150 Value Set

0 0 0 108.0MHz
System clock (clk_speed_sel) 0 0 1 121.5MHz
0 1 0 135.0MHz
0 1 1 148.5MHz
9.2.2.4 Configuration description
Back-end code memory

2MB Flash is used to store the back-end software. The Flash is Top-boot & TSOP48 footprint. Devices supported are:
12NC Part No Manufacturer Description

9322 165 50668 M29W160DT-70N1T ST Microelectronics 1Mbit x 16 flash memory (2MB)
9322 178 20668 MX29LV160TTC-70TR Macronix 1Mbit x 16 flash memory (2MB)
Back-end SDRAM
Since the width of ZiVA5+ SDRAM bus is 32-bit, one TSOP86 footprint for 32-bit SDRAM is connected in parallel.
12NC Part No Manufacturer Size

9322 176 03668 K4S643232E-TC70T Samsung 2Mbit x 32 (64Mbit)
9322 168 09685 MT48LC2M32B2TG-7 Micron 2Mbit x 32 (64Mbit)
NVRAM
The NVRAM to be used is a serial I2C bus EEPROM. This device is connected to the master I2C bus. A 32kbit or
64kbit device can be used, depending on the software and feature requirements. The parts to be supported are given
below:
12NC Part No Manufacturer Size

9322 156 81668 M24C32-WMN6TNKSA ST Microelectronics 32kbit NVRAM
9322 106 84668 AT24C32N-10SI-1.8 T&R Atmel 32kbit NVRAM
9322 165 31668 24LC32AT-I/SN Microchip 32kbit NVRAM
9322 151 00668 BR24C32F-E2 Rohm 32kbit NVRAM
9322 130 41668 M24C64-WMN6T ST Microelectronics 64kbit NVRAM
E-link daughter card

The E-link daughter card is used for software development only. An interface is prepared on the module to interface to
this board.
9.2.3 DVD host processor ZiVA5+
The DVD host processor used in SD5.11 is ZiVA5+ from LSI Logic.
9.2.3.1 Chip selects
CS# Device
0 Flash memory
1 N/u
2 E-Link daughter card
3 IDE0
4 IDE1
9.2.3.2 Interrupts
ZiVA5+ external interrupt pins:
HIRQ# Device
0 E-Link daughter card
1 ATAPI
2 N/u
Note: 1. All interrupt pins are connected to pull-up resistors.
9.2.3.3 GPIO assignments
GPIO Pin Assignment Type Application

0_1 28 GPIO0_1 I IR receiver control signal (Reserved)

1_1 115 VDATA0 IO VFD driver signal, DATA
1_2 114 VDATA1 O VFD driver signal, CLK
1_3 113 VDATA2 O VFD driver signal, CS
1_4 110 VDATA3 O DAC control signal, CS
1_5 109 VDATA4 O DAC control signal, CLK
1_6 108 VDATA5 O DAC control signal, DATA
1_7 107 VDATA6 O Mute the audio (final analog stage)
1_8 106 VDATA7 O N/u
1_9 116 HIRQ2n I N/u
1_10 184 HIRQ1n I ATAPI interrupt
1_11 192 HCS3n O IDE0 chip select
1_12 191 HCS4n O IDE1 chip select

2_10 161 IDC_DA IO Hardware I2C, SDA
2_11 160 IDC_CL IO Hardware I2C, SCL
2_12 185 RTS2 O Software I2C, SCL
2_13 188 CTS2 O I2CRDY
2_14 187 TXD2 O Software I2C, SDA
2_15 186 RXD2 I N/u

3_11 162 GPIO3_11 O IDE reset
3_12 165 GPIO3_12 O N/u
3_13 164 TXD1 O Diagnostic UART TXD
3_14 163 RXD1 I Diagnostic UART RXD
3_15 193 HCS2n O E-Link chip select

GPIO4_1 / PCM audio LtRt data output
4_1 150 ADATA0 IO
4_2 151 ADATA1 O N/u

4_5 156 IEC958 O SPDIF (digital audio) output
4_6 159 GPIO4_6 O Scart0
4_7 158 GPIO4_7 O Scart1
4_8 157 DAI_DATA I N/u

5_1 177 SDDATA0 I N/u
5_4 174 SDDATA3 I n/u
5_6 170 SDDATA5 I DMACK, IDE DMA acknowledge
5_8 168 SDDATA7 I DMARQ, IDE DMA request
5_9 178 SDREQ O n/u
5_10 182 SDERROR I N/u
5_11 179 SDEN I N/u
5_12 183 SDCLK I N/u
Service I Option 1: Diagnostic mode select
5_13 199 TDI I Option 2: ZiVA5+ JTAG TDI
5_14 200 TMS I ZiVA5+ JTAG TMS
9.2.3.4 GPIO assignments description
9.2.3.4.1 IR (pin28)
Function: IR receiver signal
Type: Input
This signal is from IR receiver that located in the front panel, the signal carry RC-6 code. The back-end s/w must be
decoded this signal for the remote control issues & optional.
For UI2002 firmware, it is reserved. For Turnkey version firmware, it is used for IR signal decode.
9.2.3.4.2 VFD driver control signal (pin115, 114, 113)
Function: VFD driver control signals

Signal: VFD_DATA, VFD_CLK, VFD_CS
Type: SIO serial bus
These signals are SIO serial bus, refer to the VFD driver specification for the detail information.
If don’t use IR signal for the remote controller purpose, the VFD driver can decode RC-6 code internal and communicate
with ZiVA5+ by the SIO serial bus.
9.2.3.4.3 DAC control signal (pin108, 109, 110)
Function: Audio DAC control signals

Signal: DAC_CS, DAC_DATA, DAC_CLK
Type: SIO serial bus
These signals are SIO serial bus, refer to the audio DAC specification for the detail information.
9.2.3.4.4 MUTE (pin107)
Function: Mute the audio at the final analog stage

Type: Push-pull output
State Function Boot up default

LOW Mute OFF
HIGH Mute ON 9
This is a global audio mute, which block the final analog stage, and affect all channels simultaneously. The main
objective of this signal is to prevent switching noise at the audio output as the player changes its mode of operation.
Apart from this global mute, additional audio mute should be applied to all stages of the audio path where possible. For
example, the decoder should apply digital mute to the audio stream as needed. Note that this global mute does not
provide adequate attenuation to normal audio signals and should not be used as an alternative to digital mute.
9.2.3.4.5 I2CRDY (pin188)

Function: Data available for transmission in slave I2C bus

LOW No data 9
HIGH Data available
This signal is used in conjunction with the slave I2C bus & is optional. Its use makes the Slave protocol more robust.
9.2.3.4.6 SCL1, SDA1 (pin185, 187)
Function: Secondary I2C

Type: Open-drain IO
This I2C bus is only required when the SD module is operating in slave mode. The secondary I2C bus is a software
implementation using GPIO, and cannot handle high data rate.
9.2.3.4.7 SCART0, SCART1 (pin159, 158)
Function: Slow blanking SCART

SCART0 SCART1 Function 0_6_12V (at SCART connector) Boot up default

HIGH HIGH TV display 0V
LOW HIGH TV display 0V
HIGH LOW 16:9 aspect ratio +6V
LOW LOW 4:3 aspect ratio +12V 9
The SCART0 AND SCART1 signals are converted to the 0_6_12V voltages by external circuitry.
9.2.3.4.8 Service (pin199)
Function: Select diagnostic or application software

Type: input

LOW Diagnostic (service) mode
HIGH Normal (player application) mode 9
The state of this pin is sampled upon reset of the ZiVA5+, by the boot code. Once the Diagnostic or Normal mode is
selected, this pin is not used again. This pin is pulled to 5VD via a 10kohm resistor.
9.2.3.5 Audio DAC
The table shows the DAC’s supported, and the clock selection should be comply with spec of ZiVA5+ and DAC.
12NC Part No Manufacturer Description

9322 177 09685 AK4382A AKM 2-Ch, Diff DAC
9.2.3.6 Video DAC
The Table below shows the Multiplexed nature of the ZiVA5+ internal Video Dac’s & the jumper options on the pcb to
cater for the different O/P configurations:
Mode Mode DAC1 DAC2 DAC3 DAC4 DAC5

1 SCART RGB CVBS CVBS G B R
2 Y/C Y C
3 SCART Y/C + RGB Y C G B R
4 Non-component CVBS C Y
5 Component CVBS C Y Pb Pr
6 480P Y Pb Pr
For DVD set used, it should support mode1 and mode 5, according to the slash version definitions.
For TV used, the back-end s/w should support mode2,3 or mode 5, but for the current product, it must use mode 2 to
reduce EMI and temperature issue.
9.2.4 Addresses of I2C devices
Part No Device I2C address

5.11 Module Slave Module 1 1 1 0 0 0 1 (71H)
24C32/64 NVRAM 1 0 1 0 0 0 0 (50H)
9.3 List of abbreviations

MPEG Motion picture expert group
Term Meaning MPEG1 / MPEG standard used by VCD and DVD
10
1 kbit / kb 2 bit MPEG2
1 Mbit / Mb 220 bit MP3 Informal audio codex, which employs audio
10 portion of MPEG1, MPEG2 and others
1 kByte /kB 2 Byte (1 Byte = 8 bit)
20 MSB Most significant bit
1MByte / MB 2 Byte (1 Byte = 8 bit)
mA Milli-ampere
AC-3 Old term for Dolby Digital ®
NTSC Video standard defined by National
ADC Analog to digital converter Television Standards Committee
ASD Architecture and standard design NVRAM Non-volatile random access memory
AV Audio video OSD On-screen display
CD Compact disc PAL Phase alternation line (video standard)
CDDA Compact disc digital audio PCB Printed circuit board
CDROM Compact disc read-only memory PCM Pulse code modulation
CVBS Composite video blanking and PS Power supply
synchronization signal
DAC Digital to analog converter RAM Random access memory
DENC Digital encoder RGB Red green and blue color space
DRAM Dynamic random access memory ROM Read-only memory
DTS Digital Theatre Sound ® SACD Super audio compact disc
DVD Digital versatile disc SDRAM Synchronous dynamic random access
memory
DVD back- DVD digital (MPEG, etc) decoder part SD module Standard design module
end
SRAM Static random access memory
DVD front- DVD servo part (was previously referred as
end Basic Engine) TTL Transistor-transistor logic (5V logic)
EMC Electromagnetic compatibility UART Universal asynchronous receiver transmitter
I2C Inter-IC (Philips patented communication V Volts
bus) VCD Video compact disc
I2S Inter-IC sound
Y/C S-video (luma and chroma) format
IC Integrated circuit
YCbCr Color space defined by Recommendation
IO Input output ITU-R BT.601
IRQ Interrupt request YUV Luma and chroma video component
(actually should be YCbCr)
KOK Karaoke
LFE Low frequency (sub-woofer) effect
LPCM Linear pulse code modulation
LSB Least significant bit
LVTTL Low voltage transistor-transistor logic (3.3V
logic)
MLP Meridian Lossless Packing
Spare Parts List MSD-512S 41 EN 44
2628 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2629 2238 586 59812 CER2 0603 Y5V50V 100NP80M
3141 019 22761 MSD-512S/00 MONO ASSY 2630 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2631 2238 586 59812 CER2 0603 Y5V50V 100NP80M
0100 3139 121 27221 TOP SHIELD MPEG BOARD 2632 2238 586 59812 CER2 0603 Y5V50V 100NP80M
0101 3139 121 27211 BTM SHIELD MPEG BOARD 2633 2238 586 59812 CER2 0603 Y5V50V 100NP80M
1003 3141 018 03924 PBAS MPEG SD5.12 2634 2238 586 59812 CER2 0603 Y5V50V 100NP80M
8001 3139 131 02841 CBLE HR-BK 06P/600/08P HR-BK 2635 2238 586 59812 CER2 0603 Y5V50V 100NP80M
8002 3104 311 06311 CBLE HR 3P4/340/3P HR WH 2636 2238 586 59812 CER2 0603 Y5V50V 100NP80M
8003 3104 311 06301 CBLE HR 7P/340+220/3P+4P HR BK 2637 2238 586 59812 CER2 0603 Y5V50V 100NP80M
8004 3139 131 03151 CBLE HR 03P/180/03P HR (BRAIDED) 2638 2238 586 59812 CER2 0603 Y5V50V 100NP80M
8005 3139 131 01841 CBLE HR-BK 3P/140/3P HR-BK 2639 2238 586 59812 CER2 0603 Y5V50V 100NP80M
8006 3141 010 21592 CWAS 40RK/40RK 400 SHIELD 28S 2640 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2641 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2642 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2643 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2644 2238 586 59812 CER2 0603 Y5V50V 100NP80M
3141 019 22771 MSD-512S/69 MONO ASSY
2645 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2661 2238 586 59812 CER2 0603 Y5V50V 100NP80M
0100 3139 121 27221 TOP SHIELD MPEG BOARD
2662 2238 586 59812 CER2 0603 Y5V50V 100NP80M
0101 3139 121 27211 BTM SHIELD MPEG BOARD
2663 4822 124 81286 47UF20% 16V
1003 3141 018 03924 PBAS MPEG SD5.12
2667 4822 122 33741 10PF10%NP0 50V
8001 3139 131 02691 CBLE HR 04P/400/03P HR
2668 4822 122 33741 10PF10%NP0 50V
8002 3139 131 02612 CBLE HR 06P/480/04P HR FERR
2669 2238 586 59812 CER2 0603 Y5V50V 100NP80M
8003 3139 131 02321 CBLE HR-BK 3P/400/3P HR-BK 26OS
2670 2238 586 59812 CER2 0603 Y5V50V 100NP80M
8004 3139 131 03151 CBLE HR 03P/180/03P HR (BRAIDED)
2671 2238 586 59812 CER2 0603 Y5V50V 100NP80M
8005 3139 131 02841 CBLE HR-BK 06P/600/08P HR-BK
2672 2238 586 59812 CER2 0603 Y5V50V 100NP80M
8006 3141 010 21592 CWAS 40RK/40RK 400 SHIELD 28S
2673 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2676 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2677 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2678 2238 586 59812 CER2 0603 Y5V50V 100NP80M
3141 018 03924 PBAS MPEG SD5.12 2679 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2680 2238 586 59812 CER2 0603 Y5V50V 100NP80M
Various 2681 4822 122 33761 22PF 5%NP0 50V
2723 4822 124 81286 47UF20% 16V
1600 4822 267 10618 B7B-PH-K (7P) 2752 2238 586 59812 CER2 0603 Y5V50V 100NP80M
1601 2422 025 17357 CON BM V 40P M 2.54 440094 B 2755 4822 126 13909 680PF 10% X7R 50V
1603 4822 267 10565 4P 2756 4822 126 13909 680PF 10% X7R 50V
1611 2422 025 08149 CON BM V 6P M 2.00 PH B 2757 2238 586 59812 CER2 0603 Y5V50V 100NP80M
1615 2422 025 12482 CON BM V 6P M 2.50 EH B 2760 4822 124 81286 47UF20% 16V
1619 4822 267 10565 4P 2761 4822 124 81286 47UF20% 16V
1620 4822 267 10735 B3B-EH-A 2762 4822 124 23052 100UF20% 16V
1621 2422 025 16382 CON BM V 03P M 2.50 EH-K 2763 4822 126 14315 390PF 5% NP0 50V 0603
2764 4822 126 14315 390PF 5% NP0 50V 0603
2765 5322 126 11579 3,3NF10%X7R 63V
Capacitors 2766 4822 126 14315 390PF 5% NP0 50V 0603
2768 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2601 4822 126 14247 CER2 0603 X7R 50V 1N5 COL R 2769 4822 126 14315 390PF 5% NP0 50V 0603
2602 2238 586 59812 CER2 0603 Y5V50V 100NP80M 2770 5322 126 11579 3,3NF10%X7R 63V
2603 2238 586 59812 CER2 0603 Y5V50V 100NP80M 2771 4822 124 81286 47UF20% 16V
2604 2238 586 59812 CER2 0603 Y5V50V 100NP80M 2783 4822 122 33741 10PF10%NP0 50V
2605 4822 122 33761 22PF 5%NP0 50V 2785 3198 016 38210 CER1 0603 NP0 25V 820P COL
2606 4822 122 33761 22PF 5%NP0 50V 2786 4822 126 14315 390PF 5% NP0 50V 0603
2607 4822 122 33761 22PF 5%NP0 50V 2787 4822 124 22652 2,2UF20% 50V
2608 4822 122 33761 22PF 5%NP0 50V 2814 4822 122 33741 10PF10%NP0 50V
2612 4822 122 33761 22PF 5%NP0 50V 2816 3198 016 38210 CER1 0603 NP0 25V 820P COL
2613 2238 586 59812 CER2 0603 Y5V50V 100NP80M 2817 4822 126 14315 390PF 5% NP0 50V 0603
2614 2238 586 59812 CER2 0603 Y5V50V 100NP80M 2818 4822 124 22652 2,2UF20% 50V
2617 3198 016 33380 CER1 0603 NP0 50V 3P3 COL 2819 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2618 3198 016 33380 CER1 0603 NP0 50V 3P3 COL 2822 4822 051 30008 0R00 JUMPER
2619 2238 586 59812 CER2 0603 Y5V50V 100NP80M 2823 2238 586 59812 CER2 0603 Y5V50V 100NP80M
2620 2238 586 59812 CER2 0603 Y5V50V 100NP80M 2824 4822 051 30008 0R00 JUMPER
2621 2238 586 59812 CER2 0603 Y5V50V 100NP80M 2833 4822 122 33761 22PF 5%NP0 50V
2622 2238 586 59812 CER2 0603 Y5V50V 100NP80M 2838 4822 126 14226 82PF 5% NP0 50V 0603
2623 2238 586 59812 CER2 0603 Y5V50V 100NP80M 2840 4822 124 23052 100UF20% 16V
EN 44 42 MSD-512S Spare Parts List
2867 4822 124 23052 100UF20% 16V 3686 4822 051 30472 4K70 5% 0,062W
2869 2238 586 59812 CER2 0603 Y5V50V 100NP80M 3698 4822 051 30472 4K70 5% 0,062W
2870 4822 124 81286 47UF20% 16V 3699 4822 051 30102 1K00 5% 0,062W
2871 2238 586 59812 CER2 0603 Y5V50V 100NP80M 3700 4822 051 30103 10K00 5% 0,062W
2873 4822 124 40196 220UF20% 16V 3701 4822 051 30103 10K00 5% 0,062W
2874 2238 586 59812 CER2 0603 Y5V50V 100NP80M 3704 4822 051 30103 10K00 5% 0,062W
2878 2238 586 59812 CER2 0603 Y5V50V 100NP80M 3724 4822 051 30339 33R00 5% 0,062W
2879 2238 586 59812 CER2 0603 Y5V50V 100NP80M 3725 4822 051 30339 33R00 5% 0,062W
2880 2238 586 59812 CER2 0603 Y5V50V 100NP80M 3734 5322 117 13026 4K7 1% 0.063W 0603 RC22H
2881 4822 124 23052 100UF20% 16V 3737 4822 051 30472 4K70 5% 0,062W
2883 2238 586 59812 CER2 0603 Y5V50V 100NP80M 3741 4822 051 30472 4K70 5% 0,062W
2884 4822 124 23052 100UF20% 16V 3747 4822 117 12139 22R 5% 0,062W
2886 4822 124 23052 100UF20% 16V 3748 4822 051 30101 100R00 5% 0,062W
2888 4822 124 23052 100UF20% 16V 3752 4822 051 30472 4K70 5% 0,062W
2889 2238 586 59812 CER2 0603 Y5V50V 100NP80M 3753 4822 051 30102 1K00 5% 0,062W
2890 4822 124 81286 47UF20% 16V 3754 4822 051 30102 1K00 5% 0,062W
2891 2238 586 59812 CER2 0603 Y5V50V 100NP80M 3757 4822 051 30682 6K80 5% 0,062W
2892 4822 124 81286 47UF20% 16V 3758 4822 051 30222 2K20 5% 0,062W
2893 4822 124 23052 100UF20% 16V 3759 4822 051 30008 0R00 JUMPER
2902 4822 126 14315 390PF 5% NP0 50V 0603 3762 4822 051 30103 10K00 5% 0,062W
2905 4822 126 14315 390PF 5% NP0 50V 0603 3763 4822 051 30101 100R00 5% 0,062W
2916 4822 124 11947 10UF 20% 16V 3764 4822 051 30272 2K70 5% 0,062W
3765 4822 051 30272 2K70 5% 0,062W
3766 4822 051 30101 100R00 5% 0,062W
Resistors 3767 4822 051 30103 10K00 5% 0,062W
3770 2322 704 65102 RST SM 0603 RC22H 5K1 PM1
3604 4822 051 30008 0R00 JUMPER 3771 5322 117 13026 4K7 1% 0.063W 0603 RC22H
3611 4822 051 30472 4K70 5% 0,062W 3772 2322 704 62001 RST SM 0603 RC22H 200R PM1 R
3613 4822 051 30472 4K70 5% 0,062W 3773 2322 704 62001 RST SM 0603 RC22H 200R PM1 R
3615 4822 051 30339 33R00 5% 0,062W 3775 5322 117 13026 4K7 1% 0.063W 0603 RC22H
3616 4822 051 30339 33R00 5% 0,062W 3776 5322 117 13026 4K7 1% 0.063W 0603 RC22H
3617 4822 051 30339 33R00 5% 0,062W 3778 2322 704 62001 RST SM 0603 RC22H 200R PM1 R
3618 4822 051 30339 33R00 5% 0,062W 3779 2322 704 65102 RST SM 0603 RC22H 5K1 PM1
3628 4822 051 30472 4K70 5% 0,062W 3780 2322 704 62001 RST SM 0603 RC22H 200R PM1 R
3629 4822 051 30472 4K70 5% 0,062W 3784 2322 704 65102 RST SM 0603 RC22H 5K1 PM1
3633 4822 051 30472 4K70 5% 0,062W 3785 5322 117 13055 75R 1% 0.063W 0603 RC22H
3635 4822 051 30472 4K70 5% 0,062W 3786 5322 117 13055 75R 1% 0.063W 0603 RC22H
3636 4822 117 13576 NETW 4 X 33R 5% 1206 3799 5322 117 13031 5K6 1% 0.063W 0603 RC22H
3637 4822 051 30103 10K00 5% 0,062W 3800 5322 117 13031 5K6 1% 0.063W 0603 RC22H
3638 4822 051 30472 4K70 5% 0,062W 3801 4822 051 30008 0R00 JUMPER
3639 4822 051 30103 10K00 5% 0,062W 3802 5322 117 13055 75R 1% 0.063W 0603 RC22H
3640 4822 051 30101 100R00 5% 0,062W 3803 5322 117 13055 75R 1% 0.063W 0603 RC22H
3642 4822 051 30103 10K00 5% 0,062W 3804 4822 051 30683 68K00 5% 0,062W
3643 4822 051 30682 6K80 5% 0,062W 3805 4822 117 12925 47K 1% 0.063W 0603
3644 4822 051 30103 10K00 5% 0,062W 3806 4822 051 30471 470R00 5% 0,062W
3645 4822 051 30103 10K00 5% 0,062W 3807 4822 051 30101 100R00 5% 0,062W
3646 4822 051 30008 0R00 JUMPER 3808 4822 051 30221 220R00 5% 0,062W
3648 4822 051 30339 33R00 5% 0,062W 3809 4822 051 30221 220R00 5% 0,062W
3649 4822 051 30339 33R00 5% 0,062W 3810 4822 051 30689 68R 5% 0,063W 0603 RC21 RST SM
3650 5322 117 13018 1K0 1% 0.063W 0603 RC22H 3841 4822 051 30008 0R00 JUMPER
3651 4822 051 30472 4K70 5% 0,062W 3842 5322 117 13055 75R 1% 0.063W 0603 RC22H
3652 4822 051 30472 4K70 5% 0,062W 3843 5322 117 13055 75R 1% 0.063W 0603 RC22H
3653 4822 051 30339 33R00 5% 0,062W 3844 4822 051 30683 68K00 5% 0,062W
3658 4822 051 30339 33R00 5% 0,062W 3845 4822 117 12925 47K 1% 0.063W 0603
3659 4822 051 30339 33R00 5% 0,062W 3846 4822 051 30471 470R00 5% 0,062W
3660 4822 117 13576 NETW 4 X 33R 5% 1206 3847 4822 051 30101 100R00 5% 0,062W
3661 4822 117 13576 NETW 4 X 33R 5% 1206 3848 4822 051 30221 220R00 5% 0,062W
3662 4822 117 13576 NETW 4 X 33R 5% 1206 3849 4822 051 30221 220R00 5% 0,062W
3663 4822 117 13576 NETW 4 X 33R 5% 1206 3850 4822 051 30689 68R 5% 0,063W 0603 RC21 RST SM
3664 4822 117 13576 NETW 4 X 33R 5% 1206 3880 4822 051 30008 0R00 JUMPER
3665 4822 117 13576 NETW 4 X 33R 5% 1206 3884 4822 117 13632 100K 1% 0603 0.62W
3666 4822 117 13576 NETW 4 X 33R 5% 1206 3885 4822 117 13632 100K 1% 0603 0.62W
3667 4822 117 13576 NETW 4 X 33R 5% 1206 3888 4822 051 30008 0R00 JUMPER
3668 4822 117 13576 NETW 4 X 33R 5% 1206 3889 2238 586 59812 CER2 0603 Y5V50V 100NP80M
3669 5322 117 13061 180R 1% 0.063W 0603 RC22H 3890 2238 586 59812 CER2 0603 Y5V50V 100NP80M
3679 4822 051 30102 1K00 5% 0,062W 3891 4822 051 30008 0R00 JUMPER
3685 4822 051 30472 4K70 5% 0,062W 3893 4822 051 30008 0R00 JUMPER
Spare Parts List MSD-512S 43 EN 44
3894 2238 586 59812 CER2 0603 Y5V50V 100NP80M 5753 2422 549 43062 IND FXD SM EMI 100MHZ 600R R
3895 4822 051 30008 0R00 JUMPER 5755 2422 549 43062 IND FXD SM EMI 100MHZ 600R R
3901 4822 051 30008 0R00 JUMPER
3903 4822 051 30008 0R00 JUMPER
3906 4822 051 30101 100R00 5% 0,062W Diodes
3907 4822 051 30101 100R00 5% 0,062W
3908 4822 051 30008 0R00 JUMPER 6601 4822 130 11397 BAS316
3909 4822 051 30008 0R00 JUMPER 6603 4822 130 11397 BAS316
3910 2322 704 65102 RST SM 0603 RC22H 5K1 PM1 6604 4822 130 11397 BAS316
3911 4822 051 30008 0R00 JUMPER 6629 4822 130 11397 BAS316
3912 4822 051 30008 0R00 JUMPER 6630 4822 130 11397 BAS316
3915 4822 051 30008 0R00 JUMPER 6631 4822 130 11522 UDZ15B
3920 4822 051 30151 150R00 5% 0,062W 6632 4822 130 11522 UDZ15B
6633 4822 130 11522 UDZ15B
6634 4822 130 11522 UDZ15B
Coils & Crystal Quartz
5600 2422 549 43062 IND FXD SM EMI 100MHZ 600R R Transistors & Intergate Circuits
5601 3141 018 80781 CRYSTAL 13.5MHZ
5602 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7600 9322 195 06671 IC SM ZIVA-5M (LLC0) Y
5615 2422 549 45618 IND FXD 0603 EMI 100MHZ 60R R 7602 9322 130 41668 IC SM M24C64-WMN6 (ST00) R
5617 2422 549 45618 IND FXD 0603 EMI 100MHZ 60R R 7603 5322 130 60159 BC846B
5618 2422 549 45618 IND FXD 0603 EMI 100MHZ 60R R 7604 5322 130 60159 BC846B
5621 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7605 9351 707 10112 IC SM 74LVT573DB (PHS0) L
5624 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7608 9965 000 04199 BSN20
5625 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7609 9965 000 04199 BSN20
5626 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7610 3141 017 40951 IC M29W160DT-SD5.12
5627 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7611 9322 180 36671 IC SM MT48LC4M32B2TG-7 (MRN0) Y
5628 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7612 5322 130 60159 BC846B
5629 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7620 9322 177 09685 IC SM AK4382AVT (AKM0) R
5631 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7622 3141 018 51741 IC LD1086D2T33 (ST00)
5632 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7624 9352 456 80115 74HCT1G125GW
5633 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7626 4822 209 30095 LM833D
5635 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7627 4822 209 30095 LM833D
5643 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7640 9340 425 30115 TRA SIG SM BC847BPN (PHSE) R
5644 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7644 9340 425 30115 TRA SIG SM BC847BPN (PHSE) R
5645 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7673 9322 167 69668 IC SM LD1117ADT18 (ST00) R
5646 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 7674 4822 209 33411 MC78L05ACD
5647 2422 549 43062 IND FXD SM EMI 100MHZ 600R R
5702 4822 157 10586 2,2UH 10% 0805 3141 019 22751 MSD-512S LOADER ASSY
5704 4822 157 10586 2,2UH 10% 0805 (For MSD-512S/00 & /69)
5715 4822 157 10586 2,2UH 10% 0805
5716 4822 157 10586 2,2UH 10% 0805 0103 3139 121 27201 DVD TOP SHIELD
5712 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 0104 3139 121 27191 DVD BOTTOM PLATE
5713 2422 549 43062 IND FXD SM EMI 100MHZ 600R R 1004 3141 018 03881 DVD LOADER MODULE A97ST
EN 44 44 MSD-512S Spare Parts List
MSD-512S/78
1001 3141 018 03881 DVD LOADER MODULE A97ST (ACTIMA)

1003 3141 018 03924 PBAS MPEG SD5.12
1005 3141 010 21901 CWAS 40RK/40RK 400 28S
MSD-512S/ARG
0100 3139 121 27221 TOP SHIELD MPEG BOARD

0101 3139 121 27211 BTM SHIELD MPEG BOARD
1001 3141 018 03881 DVD LOADER MODULE A97ST (ACTIMA)
1003 3141 018 03924 PBAS MPEG SD5.12
1005 3141 010 21901 CWAS 40RK/40RK 400 28S
TECHNICAL
MANUAL
ZiVA®-5+
Stream Data Port
(ZiVA-5 for Philips Electronics, N.V.)
May 2002
Advance
LSI Logic Confidential
®
This document is advance. As such, it describes a product under development.

This information is intended to help you evaluate the product. LSI Logic reserves
the right to change or discontinue this proposed product without notice.
This document contains proprietary information of LSI Logic Corporation. The

information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB06-000415-00, Advance Edition (May 2002)

This document describes LSI Logic Corporation’s Rel. 02 and will remain the
official reference source for all revisions/releases of this product until rescinded
by an update. This on-line document may supersede the printed version of this
document.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
Copyright © 2002 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design and ZiVA are trademarks or registered trademarks of
LSI Logic Corporation. SPARC and microSPARC are registered trademarks of
SPARC International, Inc. Products bearing SPARC trademarks are based on an
architecture developed by Sun Microsystems, Inc. Motorola and Coldfire are
registered trademarks of Motorola Inc. PowerPC is a trademark of International
Business Machines Corporation. Windows, Windows NT, and MSDN are
trademarks of Microsoft Corporation. All other brand and product names may be
trademarks of their respective companies.
EJV
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html
ii
Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.
Preface
This document describes a nonstandard pinout and block diagram for the
ZiVA®-5+ device. This pinout is based on the requirements of Philips
Electronics, N.V., to accommodate the use of a UDE loader, a digital
audio receiver, and an analog-to-digital converter (ADC).
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive. Signals that are active
LOW are denoted by an overbar, as in HCS0.
Hexadecimal numbers are indicated by the prefix “0x” —for example,

0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
The following notational conventions are used in this manual:
Notation Example Meaning and Use
courier typeface .nwk file Names of commands, files, signals, symbols, pins, parts,
directories, modules, and macrocells are shown in cou-
rier typeface.
bold typeface fd1sp In a command line, keywords are shown in bold, non-
italic typeface. Enter them exactly as shown.
italics module In command lines and names italics indicate user vari-
ables. Italicized text must be replaced with appropriate
user-specified items. Enter items of the type called for,
using lower case.
italic underscore full_pathname When an underscore appears in an italicized string, enter

a user-supplied item of the type called for with no
spaces.
ZiVA-5+ Stream Data Port Advance Technical Manual iii

Notation Example Meaning and Use
Initial Capital letters Undo Names of menu commands, options, check buttons, text
Edit buttons, options buttons, text boxes, list boxes, etc., are
Apply shown in text with Initial Capital lettering to avoid mis-
reading. These elements may appear on your screen in
all lower case.
brackets [version] You may, but need not, select one item enclosed within
brackets. Do not enter the brackets.
bar les | les.out You may select one (but not more than one) item from a
list separated by bars. Do not enter the bar.
braces {property | -all} You must select one (but not more than one) item
enclosed within braces. Do not enter the braces.
ellipses option... In command formats, elements preceding ellipses may

be repeated any number of times. Do not enter the
ellipses. In menu items, if an ellipsis appears an item,
clicking that item brings up a dialog box.
vertical dots . Vertical dots indicate that a portion of a program or listing

. has been omitted from the text.
.
semicolon, and other Use as shown in the text.

punctuation
Revision History
Date Part No. Description
May 2002 DB06-000415-00 Advanced Draft - First Issue
iv Preface
Contents
Chapter 1 Introduction
1.1 Features 1-1
1.2 Block Diagram 1-7
Chapter 2 Pin and Signal Descriptions

2.1 Pin Descriptions 2-1
2.2 Signal Descriptions 2-12
2.2.1 Latch On Reset (LOR) Signals 2-23
2.2.2 Latch On Reset Signal Descriptions 2-24
2.2.3 Pin Multiplexing 2-26
Chapter 3 Specifications
3.1 Electrical Characteristics 3-1
3.1.1 General Electrical Characteristics 3-1
3.1.2 Electrical Characteristics Summary 3-4
3.2 AC Timing Diagrams 3-8
3.2.1 Global Interface Timing 3-8
3.2.2 SDRAM Timing Diagrams 3-9
3.2.3 Async Master Personality Module Timing 3-12
3.2.4 IDE Personality Module Timing 3-14
3.2.5 IDC Interface AC Timing 3-17
3.2.6 PCM Audio Interface AC Timing 3-17
3.2.7 I2S Bus Timing 3-18
3.2.8 UART Timing 3-19
3.2.9 Video Interface AC Timing 3-19
3.2.10 SPI Interface AC Timing 3-23
3.3 Package Mechanical Dimensions 3-25
3.4 Package Marking 3-27
ZiVA-5+ Stream Data Port Advance Technical Manual v

vi Contents
Figures
1.1 Block Diagram 1-7
1.2 Enhanced Block Diagram 1-8
2.1 ZiVA-5+ Processor Pinout (208-pin PQFP) 2-2
3.1 Input Rise and Fall Timing Diagram 3-8
3.2 SYSCLK Timing Diagram 3-8
3.3 SDRAM Output Load 3-10
3.4 SDRAM Write Timing Waveform 3-11
3.5 SDRAM Read Timing Waveform 3-11
3.6 Async Master Timing 3-12
3.7 IDE PIO Data Transfer Cycle 3-14
3.8 Single-word DMA Transfer 3-16
3.9 Data Transfers on the IDC Bus 3-17
3.10 PCM Interface AC Timing 3-18
3.11 I2S Bus Timing 3-18
3.12 UART Receiver Timing 3-19
3.13 Horizontal Synchronization Waveform 3-19
3.14 VSYNC and HSYNC Master Mode Waveform 3-20
3.15 NTSC Active Horizontal Line Input Timing 3-20
3.16 NTSC Active Horizontal Line Output Timing 3-20
3.17 PAL Active Horizontal Line Input Timing 3-21
3.18 PAL Active Horizontal Line Output Timing 3-21
3.19 ITU-R BT.656 Video Output Timing 3-21
3.20 Video Interface Encoder Mastering AC Timing Diagram 3-22
3.21 Video Interface Decoder Mastering AC Timing Diagram 3-22
3.22 ITU-R BT.656 Interlaced Video Input Timing 3-22
3.23 SPI Serial Data Clocking 3-24
3.24 SPI Timing 3-24
3.25 208-pin PQFP Package Mechanical Dimensions 3-26
3.26 ZiVA5+ Variant Marking 3-27
ZiVA-5+ Stream Data Port Advance Technical Manual vii

viii ZiVA-5+ Stream Data Port Advance Technical Manual

Tables
1.1 ZiVA-5M+ Features 1-4
1.2 ZiVA-5P+ Features 1-5
1.3 ZiVA5X+ Features 1-6
2.1 ZiVA-5+ Processor Pin List 2-3
2.2 ZiVA-5+ Processor Pin Descriptions 2-12
2.3 Pins with Schmidt Trigger Inputs 2-22
2.4 Latch on Reset Pins 2-23
2.5 Sysclk Selection Options 2-26
2.6 Multiplexed Signal Assignments 2-27
3.1 Absolute Maximum Ratings 3-1
3.2 Recommended Operating Conditions 3-2
3.3 DC Characteristics 3-3
3.4 ZiVA-5+ Electrical Characteristic Summary,
Arranged by Signal Name 3-4
3.5 Global Interface AC Timing Parameters 3-8
3.6 SDRAM Timing Parameters 3-9
3.7 Async Master Timing Parameters 3-13
3.8 PIO Data Transfer Cycle Times 3-15
3.9 Single-word DMA Transfer Cycle Times 3-16
3.10 IDC Interface Timing Parameters 3-17
3.11 PCM Audio Interface Timing Parameters 3-18
3.12 Video Interface Timing Parameters 3-23
3.13 SPI Interface Timing Parameters 3-25
ZiVA-5+ Stream Data Port Advance Technical Manual ix

x
Chapter 1
Introduction
This section introduces the ZiVA-5+ features and functionality. It contains

the following sections:
• Section 1.1, “Features,” page 1-1

• Section 1.2, “Block Diagram,” page 1-7
1.1 Features
Building from the feature-rich and mature ZiVA A/V core, the ZiVA-5 DVD
System Processor incorporates powerful new features based on the
integration of many DVD system components.
• High-performance 32-bit SPARC CPU with DSP Extensions

The ZiVA-5 incorporates a high-performance 32-bit SPARC host
CPU for audio processing and special features. The SPARC CPU
incorporates dual execution units with dual instruction issue
operating at speeds up to 148.5 MHz, making it a superior platform
for applications development. The SPARC CPU is designed to act as
the system host processor, thus removing the requirement for an
external host CPU with associated memory.
• Track Buffer Processor
An integrated Track Buffer Processor parses, frames, and performs
error processing on all DVD and CD sector types. It also manages
the track buffer in ZiVA-5 unified local memory, thereby reducing
memory requirements of the DVD drive.
• Flexible DVD Drive Interface
The DVD drive input of the ZiVA-5 device is highly configurable and
can support most serial stream and parallel stream type drives, as
well as EIDE (ATAPI) drives. The combination of this flexible interface
ZiVA-5+ Stream Data Port Advance Technical Manual 1-1

with the SPARC CPU, many on-chip peripherals, and General

Purpose I/O (GPIO) pins enables direct interface to DVD drive servo
electronics for overall lower cost and better performing systems.
• High-performance 32-bit 2-D Graphics Processor
ZiVA-5 includes a high-performance 32-bit 2-D graphics processor
that can be used for ergonomic, next-generation graphical user
interfaces (GUIs) as well as graphics-based applications, including
Internet browsers, games, picture browsers, and other third party
applications.
• Enhanced Video Encoder with High Precision Video DACs
ZiVA-5 incorporates an enhanced video encoder with five 54 MHz
high precision video DACs to provide high-quality video. The video
encoder supports PAL, NTSC, RGB, SCART, interlaced 480I and
progressive 480P YPbPr components, and is fully programmable for
color saturation, contrast, brightness, and sharpness. The video
encoder is compliant with both Macrovision 7.1.L.1 for interlaced
video (PAL, NTSC) and Macrovision AGC 1.03 for Progressive scan
(480P).
• On-chip Peripherals
On-chip peripherals include Inter-Device Communications (IDC)
master/slave interface, two standard UARTs, SPI, and a direct multi-
mode infrared (IR) input. All peripheral interfaces can be configured
as GPIO pins for added flexibility.
• Copy Protection
In addition to CSS, ZiVA-5 provides Copy Protection for Pre-recorded
Media (CPPM), Copy Protection for Recorded Media (CPRM), and
audio watermark detection, all of which are required for DVD-Audio.
It is fully compatible with DVD-Video, DVD-Audio, Chaoji-VCD (CVD),
SuperVCD, VCD, CD-DA, and CD-ROM formats such as MP3.
• Unified Memory Architecture
The Unified Memory Architecture (UMA) ensures the lowest possible
system memory cost by replacing various memory subsystems with
a single subsystem. ZiVA-5 also has a flexible bus interface for
glueless connection to a number of device types including EIDE,
Flash memory, ROM, and RAM.
1-2 Introduction
• C-Ware Software Development Platform

ZiVA-5 provides a platform for applications development based on
C-Cube’s modular, component-based middleware (C-Ware) that
enables reuse of applications across LSI Logic SPARC-based
products. The Real Time Operating System (RTOS) component of
C-Ware is Wind River’s VxWorks, used in conjunction with Wind
River’s Tornado II software development environment. By enabling
software reuse, design cycles are considerably shortened and
advanced features can be quickly enabled.
Features 1-3
Table 1.1 ZiVA-5M+ Features
Video
Decoding Standards MPEG-1, MPEG-2
Compressed 720 x 480 @ 30 Hz, 720 x 576 @ 25 Hz

Resolutions 480 x 576 @ 25 Hz
352 x 480 @ 30 Hz, 352 x 576 @ 25 Hz
352 x 240 @ 30 Hz, 352 x 288 @ 25 Hz
Formats NTSC, PAL, CCIR 601/656
Compatibility DVD, DVD-VR, Chaoji VCD, VideoCD, S-VCD
Content Protection CSS
Graphics Processor Multiple planes/color modes, mixing, cursor, scaling
Audio
Decoding Standards MPEG-1 and -2, Layers I, II, and III (MP3), MPEG-2 5.1, Dolby Digital
Class A, DTS, Pro Logic, and HDCD
Input Channel IDS, IEC958
Output Channels 2-channel to 8-channel PCM output and IEC-1937/1958
Content Protection N/A
Sample Rates MPEG-1, MPEG-2, Dolby Digital, DTS
System
Compressed Data Input 8-bit DVD, Serial DVD, Serial CD w/Subcode, 16-bit Host and ATAPI
Peripheral Interfaces Two 16550 UARTs, SPI, IR, IDC, IEC 958 inputs, GPIO, Asynchronous Bus
Interfaces
DVD Drive ATAPI, UDE, VSTEM and other parallel/serial interfaces
Memory 32 to 128 Mbits SDRAM, 32 bits wide
Physical
Operating Voltage 3.3-V I/O (5-V tolerant), 1.8-V core
Clock Frequencies Input Frequency = 13.5 MHz, Operating = up to 148.5 MHz
Packaging 208-pin PQFP
1-4 Introduction
Table 1.2 ZiVA-5P+ Features
Video

352 x 480 @ 30 Hz, 352 x 576 @ 25 Hz
352 x 240 @ 30 Hz, 352 x 288 @ 25 Hz
Formats NTSC, PAL, 480P, CCIR 601/656
Compatibility DVD, DVD-VR, Chaoji VCD, VideoCD, S-VCD
Audio
Class A, DTS, Pro Logic, and HDCD
Content Protection N/A
Sample Rates MPEG-1, MPEG-2, Dolby Digital, DTS
System
Compressed Data Input 8-bit DVD, Serial DVD, Serial CD w/Subcode, 16-bit Host, and ATAPI
Peripheral Interfaces Two 16550 UARTs, SPI, IR, IDC, IEC 958 Inputs, GPIO, Asynchronous Bus
Interfaces
DVD Drive ATAPI, UDE, VSTEM and other parallel/serial interfaces
Physical
Features 1-5
Table 1.3 ZiVA5X+ Features
Video

352 x 480 @ 30 Hz, 352 x 576 @ 25 Hz
352 x 240 @ 30 Hz, 352 x 288 @ 25 Hz
Formats NTSC, PAL, 480P, CCIR 601/656
Compatibility DVD, DVD-VR, Chaoji VCD, VideoCD, S-VCD, DVD Audio
Audio
Class A, MLP, DTS, Pro Logic, and HDCD
Content Protection Watermark detection and CPPM for DVD-Audio
Sample Rates MPEG-1, MPEG-2, Dolby Digital, DTS and DVD-Audio up to 192 kHz
System
Compressed Data Input 8-bit DVD, serial DVD, serial CD w/ subcode, 16-bit host and ATAPI
Peripheral Interfaces Two 16550 UARTs, SPI, IR, IDC, IEC 958 inputs, GPIO, Asynchronous Bus
Interfaces
DVD Drive ATAPI, UDE, VSTEM, and other parallel/serial interfaces
Physical
1-6 Introduction
1.2 Block Diagram

Figure 1.1 shows a high-level block diagram of the ZiVA-5 functionality.
Figure 1.1 Block Diagram
SDRAM (64/128Mbits)
SDRAM Controller
CCIR 656
DVD Drive Track Buffer Decryption Multi-Plane NTSC/PAL/480P Digital Video
Parallel/Serial Processor
2D Video Encoder Composite
ZiVA Graphics with Five 10-bit Y/R
Audio A/V Core Engine TrueScan Video C
IDS Stereo In De-Interfacer DACs Cr/Pr/G
Input Unit
Cb/Pb/B
32-bit SPARC Audio IEC958/1937

Microprocessor Output
+Audio DSP Unit LPCM 8-ch
Audio Out
Bus Interface Unit
Phase
JTAG
Lock
Interface
UARTs IR ASYNC BUS IDC EIDE GPIO SPI Loop
13.5 MHz Crystal
Block Diagram 1-7

Figure 1.2 Enhanced Block Diagram
MDQM[3:0]
MA[11:0]
MD[31:0] 60-57
MWE
MCLK
BA[1:0]
MRAS
MCAS
MCS[1:0] 50 49
71-64
78-75
84-81
95-88
102-99
73 62
97 86
33-42
46 45
53
56
47 48
51
52
RERR 168
NVERR 169
32 44 55 63
LR_CLK 179 74 87 98 104 VDD25
SDATA 182 SDRAM Controller
Advance
Block Diagram

BIT_CLK 183 31 43 54 61
Track Buffer 72 85 96 103 GND25
SUBCODE_SYNC 170
V4SUBCODE 171 Processor 116 HSYNC
IIS_ERROR 174 NTSC/PAL/480P 105 VCLK
BIT_CLK 175 Video Encoder 106-110 113-115 VDATA[7:0]
Decryption
LR_CLK 176 184 VSYNC
SDATA 177 Multi Plane
SDREQ 178 2D
VDAC_[4B:0B]
117 120 123 126 129
Graphics
DAI_DATA 157 VDAC_[4:0]
119 122 125 128 131
DAI_BCK 158 Audio Input ZiVA A/V Engine 135 VDAC_REF
Copyright © 2002 by LSI Logic Corporation. All rights reserved.
DAI_LRCK 159
Unit Core Video DACs 118 121 124 127 130 VDD_VDAC[4:0]
133 VDAC_DVDD
10-bit
134 VDAC_REFVDD
BUSCLK 203 132 VDAC_DVSS
HCS[4:0] 191-195 136 VDAC_REFVSS
HA[3:1] 206 207 2
HD[15:0] 3-11 14-19 22 150 151 154 155 ADATA[3:0]
HOST
HDTACK 23
Copy 32-bit SPARC 149 BCK
HIRQ0 24 Interface Audio Output 148 LRCK
HUDS/HLDS 25 26 Engine Microprocessor Unit 147 XCK
HREAD 27 +Audio DSP 156 IEC958
ALE 190
197 TRST
198 TDO
IR JTAG 199 TDI
IRRX 28
Interface 200 TMS
Control 201 TCK
RESET 202
VDDP 12 20 111 152 167 181 196 Memory 138 XOUT

VDD 30 80 145 173 205 139 XIN
GNDP 13 21 112 153 166 180 208 Phase Lock 140 XVDD
GND 29 79 146 172 204 Loop 137 XVSS
VNW 189 UARTs IDC GPIO SPI 142 143 A_VDD[2:1]
141 144 AVSS[2:1]
162 RTS1
160 IDC_CL
163 RXD1
164 TXD1
165 CTS1
185 RTS2
186 RXD2
187 TXD2
188 CTS2
161 IDC_DA
185
186
187
188
GPIO
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_CS
1-8
Chapter 2
Pin and Signal
Descriptions
This section lists the ZiVA-5+ pin-out and signal descriptions. It contains
the following sections:
• Section 2.1, “Pin Descriptions,” page 2-1

• Section 2.2, “Signal Descriptions,” page 2-12
2.1 Pin Descriptions

The ZiVA-5+ processor is packaged in a 208-pin Plastic Quad Flat Pack
(PQFP) package. Figure 2.1 shows the pin-out and Table 2.1 lists the pin
number, pin name, I/O voltage and I/O type.

Figure 2.1 ZiVA-5+ Processor Pinout (208-pin PQFP)
SDDATA5/HDMACK/SUBCODE_SYNC
SDDATA6/HXCVR_EN/NVERR
SDDATA7/HDMARQ/RERR
SDDATA3/IIS_ERROR
DAI_LRCK/IEC958BP
SDDATA2/BIT_CLK
SDDATA4/V4SYNC
SDDATA1/LR_CLK
SDERROR/SDATA
RXD2/SPI_MISO
SDCLK/BIT_CLK
SDDATA0/SDATA
TXD2/SPI_MOSI
RTS2/SPI_CLK
SDEN/LR_CLK
VSYNC/HIRQ1
CTS2/SPI_CS
DAI_DATA
DAI_BCK
BUSCLK
IDC_DA
SDREQ
IDC_CL
RESET
VDD33
VDD33
VDD33
GNDP
GNDP
GNDP
HCS0
HCS1
HCS2
HCS3
HCS4
RXD1
TRST
CTS1
TXD1
RTS1
VNW
GND
GND
VDD
TMS
TDO
VDD
TCK
HA2
HA3
ALE
TDI
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VDD33 1 156 IEC958
HA1 2 155 ADATA3
HD15 3 154 ADATA2
HD14 4 153 GNDP
HD13 5 152 VDD33
HD12 6 151 ADATA1
HD11 7 150 ADATA0
HD10 8 149 BCK
HD9 9 148 LRCK
HD8 10 147 XCK
HD7 11 146 GND
VDD33 12 145 VDD
GNDP 13 144 AVSS1
HD6 14 143 AVDD1/2
HD5 15 142 AVSS2/3
HD4 16 141 AVDD3
HD3 17 140 XVDD
HD2 18 139 XIN
HD1 19 138 XOUT
VDD33 20 137 XVSS
GNDP 21 136 VSS_REFVSS
HD0 22 ZiVA-5+ Processor 135 VDAC_REF
VDAC_REFVDD
HDTACK 23 134
HIRQ0 24 Top View 133 VDAC_DVDD
HUDS 25 132 VDAC_DVSS
HLDS 26 131 VDAC_0
HREAD 27 130 VDAC_VDD0
IRRX1 28 129 VDAC_0B
GND 29 128 VDAC_1
VDD 30 127 VDAC_VDD1
GND25 31 126 VDAC_1B
VDD25 32 125 VDAC_2
MA9 33 124 VDAC_VDD2
MA8 34 123 VDAC_2B
MA7 35 122 VDAC_3
MA5 37 120 VDAC_3B
MA4 38 119 VDAC_4
MA2 40 117 VDAC_4B
MA1 41 116 HSYNC
MA0 42 115 VDATA0
GND25 43 114 VDATA1
VDD25 44 113 VDATA2
MA10 45 112 GNDP
MA11 46 111 VDD33
BA1 47 110 VDATA3
BA0 48 109 VDATA4
MCS0 49 108 VDATA5
MCS1 50 107 VDATA6
MRAS 51 106 VDATA7
MCAS 52 105 VCLK
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
MWE
GND25
VDD25
MCLK
MD0
MD1
MD2
MD3
GND25
MDQM0
VDD25
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
GND25
MDQM1
VDD25
MD12
MD13
MD14
MD15
GND
VDD
MD16
MD17
MD18
MD19
GND25
MDQM2
VDD25
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
GND25
MDQM3
VDD25
MD28
MD29
MD30
MD31
GND25
VDD25
2-2 Pin and Signal Descriptions

Table 2.1 lists the 208 ZiVA-5+ pins in numerical order and shows the
name for each pin.
Table 2.1 ZiVA-5+ Processor Pin List
Pin
Number Pin Name I/O Voltage I/O Type
1 VDD33 3.3 V –
2 HA1 3.3 V1 I/O
3 HD15 3.3 V1 I/O
4 HD14 3.3 V1 I/O
5 HD13 3.3 V1 I/O
6 HD12 3.3 V1 I/O
7 HD11 3.3 V1 I/O
8 HD10 3.3 V1 I/O
9 HD9 3.3 V1 I/O
10 HD8 3.3 V1 I/O
11 HD7 3.3 V1 I/O
12 VDD33 3.3 V1 –
13 GNDP Ground –
14 HD6 3.3 V1 I/O
15 HD5 3.3 V1 I/O
16 HD4 3.3 V1 I/O
17 HD3 3.3 V1 I/O
18 HD2 3.3 V1 I/O
19 HD1 3.3 V1 I/O
20 VDD33 3.3 V –
21 GNDP Ground –
(Sheet 1 of 9)
Pin Descriptions 2-3

Table 2.1 ZiVA-5+ Processor Pin List (Cont.)
Pin
22 HD0 3.3 V1 I/O
23 HDTACK 3.3 V1 I/OD
24 HIRQ0 3.3 V1 I
25 HUDS 3.3 V1 O
26 HLDS 3.3 V1 O
27 HREAD 3.3 V1 O
28 IRRX1/GPIO_0[1] 3.3 V1 I
29 GND Ground –
30 VDD 1.8 V –
31 GND25 Ground –
32 VDD25 3.3 V –
33 MA9 3.3 V O
34 MA8 3.3 V O
35 MA7 3.3 V O
36 MA6 3.3 V O
37 MA5 3.3 V O
38 MA4 3.3 V O
39 MA3 3.3 V O
40 MA2 3.3 V O
41 MA1 3.3 V O
42 MA0 3.3 V O
43 GND25 Ground –
44 VDD25 3.3 V –
45 MA10 3.3 V O
(Sheet 2 of 9)

Pin
46 MA11 3.3 V O
47 BA1 3.3 V O
48 BA0 3.3 V O
49 MCS0 3.3 V O
50 MCS1 3.3 V O
51 MRAS 3.3 V O
52 MCAS 3.3 V O
53 MWE 3.3 V O
54 GND25 Ground –
55 VDD25 3.3 V –
56 MCLK – O
57 MD0 3.3 V I/O
58 MD1 3.3 V I/O
59 MD2 3.3 V I/O
60 MD3 3.3 V I/O
61 GND25 Ground –
62 MDQM0 3.3 V O
63 VDD25 3.3 V –
64 MD4 3.3 V I/O
65 MD5 3.3 V I/O
66 MD6 3.3 V I/O
67 MD7 3.3 V I/O
68 MD8 3.3 V I/O
69 MD9 3.3 V I/O
(Sheet 3 of 9)

Pin
70 MD10 3.3 V I/O
71 MD11 3.3 V I/O
72 GND25 Ground –
73 MDQM1 3.3 V O
74 VDD25 3.3 V –
75 MD12 3.3 V I/O
76 MD13 3.3 V I/O
77 MD14 3.3 V I/O
78 MD15 3.3 V I/O
79 GND Ground –
80 VDD 1.8 V –
81 MD16 3.3 V I/O
82 MD17 3.3 V I/O
83 MD18 3.3 V I/O
84 MD19 3.3 V I/O
85 GND25 Ground –
86 MDQM2 3.3 V O
87 VDD25 3.3 V –
88 MD20 3.3 V I/O
89 MD21 3.3 V I/O
90 MD22 3.3 V I/O
91 MD23 3.3 V I/O
92 MD24 3.3 V I/O
93 MD25 3.3 V I/O
(Sheet 4 of 9)

Pin
94 MD26 3.3 V I/O
95 MD27 3.3 V I/O
96 GND25 Ground –
97 MDQM3 3.3 V O
98 VDD25 3.3 V –
99 MD28 3.3 V I/O
100 MD29 3.3 V I/O
101 MD30 3.3 V I/O
102 MD31 3.3 V I/O
103 GND25 Ground –
104 VDD25 3.3 V –
105 VCLK 3.3 V1 I/O
106 VDATA7/GPIO_1[8] 3.3 V1 I/O
107 VDATA6/GPIO_1[7] 3.3 V1 I/O
108 VDATA5/GPIO_1[6] 3.3 V1 I/O
109 VDATA4/GPIO_1[5] 3.3 V1 I/O
110 VDATA3/GPIO_1[4] 3.3 V1 I/O
111 VDD33 3.3 V –
112 GNDP Ground –
113 VDATA2/GPIO_1[3] 3.3 V1 I/O
114 VDATA1/GPIO_1[2] 3.3 V1 I/O
115 VDATA0/GPIO_1[1] 3.3 V1 I/O
116 HSYNC/HIRQ2/GPIO_1[9] 3.3 V1 I/O
117 VDAC_5B Analog O
(Sheet 5 of 9)

Pin
118 VDAC_VDD5 3.3 V Analog –
119 VDAC_5 Analog O
122 VDAC_4 Analog O
125 VDAC_3 Analog O
128 VDAC_2 Analog O
131 VDAC_0 Analog O
132 VDAC_DVSS Ground –
133 VDAC_DVDD 3.3 V –
134 VAC_REFVDD 3.3 V –
135 VDAC_REF Analog I
136 VDAC_REFVSS Ground –
137 XVSS Ground –
138 XOUT Analog –
139 XIN Analog –
140 XVDD 3.3 V –
141 AVSS2 Ground –
(Sheet 6 of 9)

Pin
142 AVDD2 3.3 V –
143 AVDD1 3.3 V –
144 AVSS1 Ground –
145 VDD 1.8 V –
146 GND Ground –
147 XCK 3.3 V1 I/O
148 LRCK 3.3 V1 O
149 BCK 3.3 V1 O
150 ADATA0/GPIO_4[1] 3.3 V1 O
151 ADATA1/GPIO_4[2] 3.3 V1 O
152 VDD33 3.3 V –
153 GNDP Ground –
154 ADATA2/GPIO_4[3] 3.3 V1 O
155 ADATA3/GPIO_4[4] 3.3 V1 O
156 IEC958/GPIO_4[5] 3.3 V1 O
157 DAI_DATA/GPIO_4[8] 3.3 V1 I
158 DAI_BCK/GPIO_4[7] 3.3 V1 I
159 DAI_LRCK/iec958bp/GPIO_4[6] 3.3 V1 I
160 IDC_CL/GPIO_2[11] 3.3 V1 OD
161 IDC_DA/GPIO_2[10] 3.3 V1 OD
162 RTS1/GPIO_3[11] 3.3 V1 O
163 RXD1/GPIO_3[14] 3.3 V1 I
164 TXD1/GPIO_3[13] 3.3 V1 O
165 CTS1/GPIO_3[12] 3.3 V1 I
(Sheet 7 of 9)

Pin
166 GNDP Ground –
167 VDD33 3.3 V –
168 SDDATA7/HDMARQ/RERR/GPIO_5[8] 3.3 V1 I
169 SDDATA6/HXCVR_EN/NVERR/ 3.3 V1 I

GPIO_5[7]
170 SDDATA5/HDMACK/SUBCODE_SYNC/ 3.3 V1 I

GPIO_5[6]
171 SDDATA4/V4SUBCODE/GPIO_5[5] 3.3 V1 I
172 GND Ground –
173 VDD 1.8 V –
174 SDDATA3/IIS_ERROR/GPIO_5[4] 3.3 V1 I
175 SDDATA2/BIT_CLK/GPIO_5[3] 3.3 V1 I
176 SDDATA1/LR_CLK/GPIO_5[2] 3.3 V1 I
177 SDDATA0/SDATA/GPIO_5[1] 3.3 V1 I
178 SDREQ/GPIO_5[9] 3.3 V1 O
179 SDEN/LR_CLK/GPIO_5[11] 3.3 V1 I
180 GNDP Ground –
181 VDD33 3.3 V –
182 SDERROR/SDATA/GPIO_5[10] 3.3 V1 I
183 SDCLK/BIT_CLK/GPIO_5[12] 3.3 V1 I
184 VSYNC/HIRQ1/GPIO_1[10] 3.3 V1 I/O
185 RTS2/SPI_CLK/GPIO_2[12] 3.3 V1 O
186 RXD2/SPI_MISO/GPIO_2[15] 3.3 V1 I
187 TXD2/SPI_MOSI/GPIO_2[14] 3.3 V1 O
188 CTS2/SPI_CS/GPIO_2[13] 3.3 V1 I
(Sheet 8 of 9)

Pin
189 VNW2 5V –
190 ALE 3.3 V1 O
191 HCS4/GPIO_1[12] 3.3 V1 I
192 HCS3/GPIO_1[11] 3.3 V1 I
193 HCS2/GPIO_3[15] 3.3 V1 I
194 HCS1 3.3 V1 I/O
195 HCS0 3.3 V1 I/O
196 VDD33 3.3 V –
197 TRST 3.3 V1 I
198 TDO 3.3 V1 O
199 TDI/GPI5[14] 3.3 V1 I
200 TMS/GPI5[13] 3.3 V1 I
201 TCK 3.3 V1 I
202 RESET 3.3 V1 I
203 BUSCLK 3.3 V1 I
204 GND Ground –
205 VDD 1.8 V –
206 HA3 3.3 V1 I
207 HA2 3.3 V1 I
208 GNDP Ground –
(Sheet 9 of 9)
1. 5 V-tolerant.
2. The ZiVA-5+ core operates at 1.8 V + 5%. Most I/O interface pins can be
5 V-tolerant depending on the voltage applied to VNW.

2.2 Signal Descriptions

Table 2.2 lists the pin name, pin number, type, and description of each
signal.
Table 2.2 ZiVA-5+ Processor Pin Descriptions
Pin
Number Name Type1 Description
System Services
203 BUSCLK I/O Synchronous Input/Output Signal Clock

When set as an input, this pin requires an external
clock that synchronizes internal ZiVA-5+ logic to
external bus events. All the synchronous bus signals
input to the ZiVA-5+ are latched on the rising edge of
BUSCLK.
When set as an output, the internal halfsysclk is
present on this pin. The halfsysclk timing, however, is
delayed sufficiently to compensate for the external
delay of the ZiVA-5+ I/O cell and external loading.
This ensures that the setup and hold time
requirements for synchronous signals are always
relative to the signal present on the BUSCLK pin and
not the internal halfsysclk.
202 RESET I Active Low Reset. Assert for at least 5 milliseconds in

the presence of clock to reset the entire chip.
105 VCLK I/O Video clock that outputs 27 MHz
138 XOUT O Crystal output. When the internal DCXO is used, a

13.5-MHz crystal should be connected between this
pin and the XIN pin.
139 XIN I Crystal input. When the internal DCXO is used, a

13.5-MHz crystal should be connected between this
pin and the XOUT pin. When an external oscillator or
VCXO is used, its output should be connected to this
pin.
Power and Ground
189 VNW Power 5-V supply voltage for 5 V-tolerant input signals
(Sheet 1 of 10)

Table 2.2 ZiVA-5+ Processor Pin Descriptions (Cont.)
Pin
1, 12, 20, VDD33 Power 3.3-V supply voltage for I/O signals
111, 152,
167, 181,
196
32, 44, 55, VDD25 Power 3.3-V supply voltage for SDRAM I/O signals
63, 74, 87,
98, 104
140 XVDD Power 3.3-V Crystal interface power
30, 80, VDD Power 1.8-V supply voltage for core logic
145, 173,
205
118, 121, VDAC_VDD[5:1] Power 3.3-V Analog Video DAC Power

124, 127,
130
133 VDAC_DVDD Power 3.3-V Digital supply for 5 DACs
142, 143 AVDD[2:1] Power 3.3-V Analog PLL Power
134 VDAC_REFVDD Power 3.3-V Analog Video Reference Voltage
13, 21, GNDP Ground Ground for I/O signals

112, 153,
166, 180,
208
29, 79, GND Ground Ground for core logic

146, 172,
204
31, 43, 54, GND25 Ground Ground for SDRAM I/O signals
61, 72, 85,
96, 103
132 VDAC_DVSS Ground Digital VSS for DACs
141, 144 AVSS[2:1] Ground Analog PLL Ground
136 VDAC_REFVSS Ground Video Analog Ground
137 XVSS Ground Crystal interface ground
(Sheet 2 of 10)
Signal Descriptions 2-13

Pin
Host Interface
191-193 HCS[4:2] O Host chip select. Host asserts HCS to select the
processor for a read or write operation. The falling
edge of this signal triggers the read or write operation.
GPIO_1[12], 1[11], I/O General Purpose I/Os 1[12], 1[11 and 3[15],
3[15] respectively.
194, 195 HCS[1:0] O Host chip select. Host asserts HCS to select the
processor for a read or write operation. The falling
edge of this signal triggers the read or write operation.
206, 207, 2 HA[3:1] O Host (muxed address) address bus. 3-bit address bus
selects one of eight host interface registers. These
signals are not muxed in ATAPI mode.
3-11, 14- HD[15:0] I/O HD[15:0] is the 16-bit (muxed address and data) host
19, 22 data bus. MSB of the 32-bit word is written first. The
host also reads and writes the decoder internal
registers and local SDRAM/ROM via HA[7:0]. These
signals are not muxed for ATAPI mode.
23 HDTACK/WAIT OD/I Host Data Transfer Acknowledge
24 HIRQ0 I Host interrupt. Open drain signal, must be pulled-up

via 4.7 kΩ or 3.3 kΩ to 3.3 volts. Driven high for 10 ns
before 3-state.
25 HUDS/UWE O Host Upper Data Strobe. Host high byte data,

HD[15:8], is valid when this pin is active.
26 HLDS/LWE O Host Lower Data Strobe. Host low byte data, HD[7:0],
is valid when this pin is active.
27 HREAD O Read/write strobe
190 ALE O Address latch enable
(Sheet 3 of 10)

Pin
Parallel DVD/CD or Serial CD Interface
168 SDDATA7 I Compressed data from DVD DSP. Bit 7. In parallel

mode, bit 7 is the first (earliest in time) bit in the
bitstream, while bit 0 is the last bit.
HDMARQ I Host DMA Request
RERR I Receiver Error input from SAA7812 or CS8415
GPIO_5[8] I/O General Purpose I/O 5[8]
169 SDDATA6 I Compressed data from DVD DSP. Bit 6
HXCVR_EN I ATAPI Transceiver Enable
NVERR I No Validity Receiver Indicator input from SAA7812 or

CS8415
HDMACK I Host DMA Acknowledge
SUBCODE_SYNC I Sync input from SAA7812
V4SUBCODE I V4 input from SAA7812
IIS_ERROR I FLAG input from SAA7812
(Sheet 4 of 10)

Pin
BIT_CLK I BCLK input from SAA7812 or OSCLK input from

CS8415
LR_CLK I WCLK input from SAA7812 or OLRCK input from

CS8415
177 SDDATA0 I In serial mode, bit 0 should be used as the input, with
the unused bits either used as GPIOs or tied to
ground.
SDATA I DATA input from SAA7812 or SDOUT input from

CS8415
183 SDCLK I Data clock. The maximum frequency is 37.125 MHz

for parallel mode, and 74.25 MHz for serial mode. The
polarity of this signal is programmable.
BIT_CLK I OSCLK input from CS8415 or bit clock input from an

ADC
182 SDERROR I Error in input data. This signal carries the error bit
associated with the channel data type (if set, the byte
is corrupted).
SDATA I SDOUT input from CS8415 or audio serial data input

from an ADC
(Sheet 5 of 10)

Pin
179 SDEN I Data enable. Assertion indicates that data on

SDDATA[7:0] is valid. The polarity of this signal is
programmable.
LR_CLK I OLRCK input from CS8415 or left/right clock input

input from an ADC
178 SDREQ O Bitstream request. processor asserts SDREQ to

indicate that the bitstream input buffer has available
space.
SDRAM Interface
50, 49 MCS[1:0] O Memory chip select for SDRAM.
52 MCAS O Active LOW SDRAM Column Address Strobe
51 MRAS O Active LOW SDRAM Row Address Strobe
97, 86, 73, MDQM[3:0] O These pins are the byte masks corresponding to
62 MD[7:0], [15:8], [23:16] and [31:24]. They allow for
byte reads/writes to SDRAM.
46, 45, 33- MA[11:0] O SDRAM Address

42
102-99, MD[31:0] I/O SDRAM Data

95-88,
84-81, 78-
75, 71-64,
60-57
53 MWE O SDRAM Write Enable. Specifies transaction to

SDRAM: read (=1) or write (=0)
56 MCLK O SDRAM Clock
47, 48 BA[1:0] O SDRAM bank select
(Sheet 6 of 10)

Pin
Analog Video Output
117, 120, VDAC_(5B:1B] Analog O Video DAC Bias Bits[4:0]

123, 126,
129
119 VDAC_5 Analog O DAC video output. Macrovision encoded
135 VDAC_REF Analog I Video DACs Reference Resistor. Connecting to pin

136 through a 1.18 K +/- 1% resistor is required.
105 VCLK I/O System clock that drives internal PLLs. ZiVA-5+ 27-
MHz TTL oscillator. (See description of VCLK for
Digital Video Output.) Also optional video clock for
internal PLLs or external encoder.
Digital Video Input/Output
116 HSYNC I/O Horizontal sync. The decoder begins outputting pixel
data for a new horizontal line after the falling (active)
edge of HSYNC.
HIRQ2 I Host Interrupt Request 2
105 VCLK I/O Video clock. Clocks out data on VDATA[7:0]. Clock is
typically 27 MHz.
106-110, VDATA[7:0] I/O Video data bus. Byte serial CbYCrY data synchronous
113-115 with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder samples VDATA
for boot configuration parameters.
GPIO_1[8:1] I/O General Purpose I/Os 1[8:1]
(Sheet 7 of 10)

Pin
184 VSYNC I/O Vertical sync. Bi-directional, the decoder outputs the
top border of a new field on the first HSYNC after the
falling edge of VSYNC. VSYNC can accept vertical
synchronization or top/bottom field notification from an
external source. (VSYNC HIGH = bottom field.
VSYNC LOW = top field) Used for CCIR-601.
HIRQ1 I Host Interrupt Request 1
Audio Interface
155, 154, ADATA[3:0] O PCM Data Out. Eight channels. Serial audio samples
151, 150 relative to BCK and LRCK.
GPIO_4[4:1] I/O General Purpose I/Os 4[4:1]
149 BCK O PCM Bit Clock. This audio bit clock provides the serial
shift clock for audio data. BCK can be either 48 or 32
times the sampling frequency.
148 LRCK O PCM Sample Clock. Identifies the channel for each
sample. The polarity is programmable.
147 XCK I/O Audio system clock input or output. BCK and LRCK
are derived from this clock.
156 IEC958 O PCM data out (IEC-958 format) or compressed data

out (IEC-1937 format).
Digital Mic In
157 DAI_DATA I PCM data (stereo) input.
158 DAI_BCK I PCM sample clock. Also slaves to external audio

clock.
(Sheet 8 of 10)

Pin
159 DAI_LRCK I PCM left/right clock.
IEC958BP I IEC958 input bypass
IR
28 IRRX I IR Remote Receive. This input connects to an

integrated (photo diode, band pass, demodulator) IR
receiver.
IDC
160 IDC_CL OD Serial clock signal for IDC data transfer. It should be
pulled up to the positive supply voltage (depending on
the device) using an external pull-up resistor.
161 IDC_DA OD Serial data signal for IDC data transfer. It should be
pulled up to the supply voltage using an external pull-
up resistor.
UART1
162 RTS1 O Ready to send, UART1
163 RXD1 I Receive data, UART1
164 TXD1 O Transmit data, UART1
165 CTS1 I Clear to send, UART1
(Sheet 9 of 10)

Pin
UART2
185 RTS2 O Ready to send, UART2
SPI_CLK O Serial Peripheral Interface Clock
186 RXD2 I Receive data, UART2
SPI_MISO I Serial Peripheral Interface - Master In Slave Out
187 TXD2 O Transmit data, UART2
SPI_MOSI O Serial Peripheral Interface - Master Out Slave In
188 CTS2 I Clear to send, UART2
SPI_CS O Serial Peripheral Interface Strobe
JTAG
197 TRST I Test reset. BST reset. Resets the TAP controller. This
signal must be pulled low.
198 TDO O Test data Out. BST serial data output.
199 TDI I Test data In. BST serial data chain input.
GPI_5[14] I General Purpose Input pin 0
200 TMS I Test mode select. Controls state of test access port
(TAP) controller.
GPI_5[13] I General Purpose Input pin 1
201 TCK I Test clock. Boundary scan test (BST) serial data
clock.
(Sheet 10 of 10)
1. I - input; O - output; OD - open drain; PU - requires external pull-up resistor.

Table 2.3 lists the pins that have Schmidt Trigger inputs.
Table 2.3 Pins with Schmidt Trigger Inputs
Pin Number Pin Name Pin No. Pin Name
2-11 HA1, HA[15:7] 165 CTS1
14-19 HD[6:1] 168-171, 174-177 SDDATA[70]
22 HD0 178 SDREQ
23 HDTACK 179 SDEN
24 HIRQ0 182 SDERROR
25 HUDS 183 SDCLK
26 HLDS 184 VSYNC
27 HREAD 185 RTS2
28 IRRX1 186 RXD2
106-110 VDATA[7:3] 187 TXD2
113-115 VDATA[2:0] 188 CTS2
116 HSYNC 191 HCS4
147 XCK 192 HCS3
150, 151, 154, 155 ADATA[0:3] 193 HCS2
156 IEC958 194 HCS1
157 DAI_DATA 195 HCS0
158 DAI_BCK 197 TRST
159 DAI_LRCK 199 TDI
160 IDC_CL 200 TMS
161 IDC_DA 201 TCK
162 RTS1 202 RESET
163 RXD1 206 HA3
164 TXD1 207 HA2

2.2.1 Latch On Reset (LOR) Signals

There are a number of Latch On Reset (LOR) pins on the ZiVA-5+ that
are used to enable particular modes and/or features of the part. The
latch on reset pins used on the ZiVA-5+ are shown in Table 2.4.
All LOR pins are input-only pins that have weak internal pull-up or pull-
down resistors. The latching signal is not a clock signal but rather an
asynchronous version of the reset signal. The state for the LOR pins is
held in a transparent latch that is transparent while the asynchronous
reset is asserted and becomes opaque when the synchronous reset is
deasserted.
LOR pins are programmed by adding either weak pull-up resistors (= 1)

or weak pull-down resistors (= 0) to these pins. These resistors should
be weak enough that they can be over driven in normal operation.
The LOR pins are all multiplexed with other signal functions. The timing
of the LOR function requires that all other functions allow a minimum of
21 system clock (sysclk) cycles after the rising (positive) edge of the
reset pulse (active low) before using the LOR pins for the other signal
function(s).
Table 2.4 Latch on Reset Pins
Pin Number LOR Name
148 host_drive_sel
150 clk_speed_sel0
151 clk_speed_sel1
154 clk_speed_sel2

Table 2.4 Latch on Reset Pins
Pin Number LOR Name
155 xtal_sel
156 bypass_sel
162 chip_mode_sel1
164 chip_mode_sel0
185 Reserved1
187 chip_mode_sel2
1. Although reserved for future use, this pin must be tied high. A 10K resistor
is recommended, but variations in loads may require adjustments.
2.2.2 Latch On Reset Signal Descriptions

The following sections briefly describe the Latch On Reset (LOR) signals
used by the ZiVA-5+ device.
2.2.2.1 Chip Mode Selection (chip_mode_sel[2:0])
The chip mode selection pins determine the ZiVA-5+ device’s operating
mode. These should always be configured to the Async Mode (110) as
follows:
bit 2 = 1
bit 1 = 1
bit 0 = 0
The chip mode selection pins are multiplexed as follows:
bit 2 is multiplexed with TXD2

bit 1 is multiplexed with RTS1
bit 0 is multiplexed with TXD1
2.2.2.2 Host Drive Selection (host_drive_sel)
The host_drive_sel signal goes to the host interface I/Os to select high
drive or low drive I/Os. When latched at 0, high drive I/Os are used; when
latched at 1, low drive I/Os are used. This signal is also multiplexed with
LRCK.

It is recommended that the host_drive_sel signal should always be

latched at 1 to enable the low drive I/Os.
2.2.2.3 Clock Generation LOR Signals
The PLL subsystem is responsible for generating the system, video, and
audio clocks for the chip. This is achieved using three PLLs and a
handful of support logic. The primary system clock, sysclk, runs at 108.0,
121.5, 135, or 148.5 MHz. sysclk can be locked to either a pullable
external 13.5-MHz crystal or an external 27-MHz VCXO. A clock at half
the selected rate, halfsysclk, is generated by dividing sysclk. Three video
clocks are generated by/derived from the video PLL, a 27-MHz clock
named clk_27, a 54-MHz clock named clk_54, and a 216-MHz clock
named clk_216. The video PLL can either share the same reference as
the system clock PLL or use a separate 27-MHz/54-MHz clock source
(e.g. a digitizer). The audio PLL generates aclk, which can cover a wide
range of oversampling rates due to the use of high resolution fractional
synthesis. Like the video PLL, the audio PLL can either share the same
reference as the system clock PLL or use an external 27-MHz/54-MHz
reference.
2.2.2.4 Internal Reference Frequency Selection (xtal_sel)
The internal reference source is selected via the LOR signal xtal_sel
(ADATA[3]). When latched at 1, the Digital Controlled Crystal Oscillator
(DCXO) is enabled and a 13.5-MHz crystal is expected to be connected
between the XIN and XOUT pins. When xtal_sel is latched at 0, an
external 27-MHz clock reference is expected at the XIN pin.
2.2.2.5 Sysclk (clk_speed_sel[2:0])
The sysclk PLL is always locked to the signal on the XIN pin (whether
the signal is produced by the internal DCXO or an external oscillator).
The sysclk frequency is determined at reset by the LOR signals
clk_speed_sel[2:0] (ADATA[1:3] pins). Table 2.5 shows the relationship
between clk_speed_sel[2:0] and sysclk. Since these values are latched
on reset, the chip must be reset in order to change the sysclk frequency.

Table 2.5 Sysclk Selection Options
clk_speed_sel[2:0] sysclk in MHz
001 121.5
010 135.0
011 148.5
2.2.3 Pin Multiplexing

Various I/O signals of the ZiVA-5+ are multiplexed, depending on which
external interfaces are implemented (implementing one interface may
preclude the use of another interface).
Other signals share pins with the Latch On Reset (LOR) signals. The
LOR signals set configurations parameters for the ZiVA-5+ device when
the device is reset. However, LOR signals do not interfere with normal
operation of any interfaces or signals.
2.2.3.1 Primary And Secondary Signals
The signals being multiplexed can be classified in terms of primary and

secondary signals assigned to a particular set of pins. The scheme is
package-dependent.
• The primary signals are those that are active when a primary signal
is taken out of reset (by toggling the corresponding reset bit in a
reset register).
• The secondary signals can be made active by holding the primary
signal in reset and selecting the secondary signal (by setting the
corresponding select bit in a configuration register).
Table 2.6 shows the multiplexed primary and secondary signals of the
ZiVA-5+.
The primary and secondary signals are selected by firmware header

files. The scheme for selecting a particular signal is based on setting the
corresponding bit(s) in these registers. In these registers there may be
1-, 2-, or 3-bit fields dedicated to selecting among muxed signals by

setting them to specific values. As an example, the signals VDATA[7:0]

could be configured through firmware as GPIO signals.
Table 2.6 Multiplexed Signal Assignments
Primary Pin Secondary Secondary Secondary

Signal Name Number Signal Name Signal Direction Signal Module
ADATA[0] 150 clk_speed_sel0 Input PLL
GPIO_4 [1] Input/Output
ADATA[3] 155 xtal_sel Input PLL
CTS1 165 GPIO_3 [12] Input/Output
CTS2 188 SPI_CS Output SPI
DAI_BCK 158 GPIO_4 [7] Input/Output
DAI_DATA 157 GPIO_4 [8] Input/Output
DAI_LRCK 159 IEC958BP Input Audio
HCS[2] 193 GPIO_3 [15] Input/Output
HSYNC 116 HIRQ2 Input BIU
IDC_CL 160 GPIO_2 [11] Input/Output
IDC_DA 161 GPIO_2 [10] Input/Output
IEC958 156 bypass_sel Input PLL
IRRX1 28 GPIO_0 [1] Input/Output
LRCK 148 host_drive_sel Input BIU
RTS1 162 chip_mode_sel1 Input BIU, SRM

Table 2.6 Multiplexed Signal Assignments (Cont.)

RTS2 185 SPI_CLK Output SPI
busclk_sel0 Input BIU
RXD1 163 GPIO_3 [14] Input/Output
RXD2 186 SPI_MISO Input SPI
SDCLK 183 BIT_CLK Input
SDDATA[0] 177 GPIO_5 [1] Input/Output
SDATA Input
LR_CLK Input
BIT_CLK Input
IIS_ERROR Input
V4SUBCODE Input
SUBCODE_SYNC Input
HDMACK Output BIU
NVERR Input
HXCVR_EN Output BIU
RERR Input
HDMARQ Input BIU
SDEN 179 GPIO_5 [11] Input/Output
LR_CLK Input
SDERROR 182 GPIO_5 [10] Input/Output
SDATA Input
SDREQ 178 GPIO_5 [9] Input/Output

Table 2.6 Multiplexed Signal Assignments (Cont.)

TDI 199 GPI_5 [14] Input
TMS 200 GPI_5 [13] Input
TXD1 164 chip_mode_sel0 Input BIU, SRM
TXD2 187 SPI_MOSI Output SPI
chip_mode_sel2 Input BIU, SRM
VDATA[0] 115 board_id_lor0 Input SRM
VSYNC 184 HIRQ1 Input/Output BIU


Chapter 3
Specifications
This section describes the electrical characteristics, AC timing

parameters/diagrams and package dimensions of the ZiVA-5+ device. It
contains the following sections:
• Section 3.1, “Electrical Characteristics,” page 3-1

• Section 3.2, “AC Timing Diagrams,” page 3-8
• Section 3.3, “Package Mechanical Dimensions,” page 3-25
• Section 3.4, “Package Marking,” page 3-27
3.1 Electrical Characteristics
3.1.1 General Electrical Characteristics
Table 3.1 Absolute Maximum Ratings
Parameters Value1 Units
VDD Supply Voltage −0.3 to 3.465 V
VDDA Analog Supply Voltage −0.3 to 4.65 V
VIN Input Voltage −0.3 to 5.5 V
VOUT Output Voltage −0.3 to VDD +0.3 V
TSTG Storage Temperature Range −55 to 150 °C
TAmb Ambient Temperature Range (device) −0 to 60 °C
TSLD Reflow Soldering Temp. 200° C for five seconds –

max.
1. Exposure to stresses beyond those listed in this table can result in device unreliability, permanent
damage, or both.

Table 3.2 Recommended Operating Conditions
Values1
Parameters Min Typ. Max Units
VDD Supply Voltage 1.71 1.8 1.89 V
VDDA Analog Supply Voltage 3.135 3.30 3.465 V
VNW 5-V Supply Voltage for 5 V-tolerant signals – 5.00 – V
VDD33 3.3-V Supply Voltage for I/O signals 3.135 3.30 3.465 V
VDD25 3.3-V Supply Voltage for SDRAM I/O signals 3.135 3.30 3.465 V
XVDD 3.3-V Crystal interface power 3.135 3.30 3.465 V
VDD_VDAC Analog Video DAC power 3.135 3.30 3.465 V
VDAC_DVDD 3.3-V Digital Supply Voltage for Video DACs 3.135 3.30 3.465 V
VDAC_REFVDD 3.3-V Analog Reference Voltage 3.135 3.30 3.465 V
TAMB Ambient Temperature (Device) 0 – 60 °C

1. Typical 5% on VDD supply. For normal device operation, adhere to these limits. Sustained oper-
ation at conditions exceeding these values, even if they are within the absolute maximum rating
limits, might result in permanent device damage or impaired device reliability. Device functionality
to stated DC and AC limits is not guaranteed if conditions exceed recommended operating condi-
tions.
3-2 Specifications
Table 3.3 DC Characteristics
Parameters Test Conditions Min Typ. Max Units
VIH High-Level Input Voltage1 VDD = Max 2.4 – 3.45 V
VIL Low-Level Input Voltage1 VDD = Min – – 0.8 V
VOH High-Level Output VDD = Min, 2.4 – – V

Voltage IOH = drive level of specific signal
shown in Table 3.4.
VOL Low-Level Output Voltage VDD = Min – – 0.5 V

IOL = drive level of specific signal
shown in Table 3.4.
IIH High-Level Input Current VDD = Max, VIN = VDD – – 10 µA
IIL Low-Level Input Current VDD = Max, VIN = 0 V −10 – – µA
IINU Input Current with Pull-up VIN = VSS -70 -225 µA

Resistor
IOZ Output Leakage Current Hi-Z output driven to 0 V and 5.25 V −10 – +10 µA
IOZM Output Leakage Current, Hi-Z output driven to 0 V and VDD −10 – +10 µA
SDRAM pins
CIN Input Capacitance1 – 10 – pF
COUT Output Capacitance1 – 12 – pF
CI/O I/O Pin Capacitance1 – 12 – pF
PD Power Dissipation VDD Nominal @ 25 °C, – 2.1 – W

Internal clock = 135 MHz
1. Not 100% tested, guaranteed by design characteristics.
Electrical Characteristics 3-3

3.1.2 Electrical Characteristics Summary

Table 3.4 summarizes the electrical characteristics of ZiVA-5+ signals,
including their direction (input, output, or input/output), their terminations,
and their drive and voltage tolerance.
Table 3.4 ZiVA-5+ Electrical Characteristic Summary,

Arranged by Signal Name
Schmitt
Trigger
Signal Name Direction (if shown) Drive V. Tolerance
ADATA [3:0] Output yes 6 ma 5V
AVDD [3:1] – – – –
AVSS [3:1] – – – –
BA [1:0] Output – 15 ma 3.3 V
BCK Output – 6 ma 5V
BUSCLK Input/Output – 12 ma 5V
CTS1 Input yes 6 ma 5V
CTS2 Input yes 6 ma 5V
DAI_BCK Input yes 6 ma 5V
DAI_DATA Input yes 6 ma 5V
DAI_LRCK Input yes 6 ma 5V
DATA_EN Output yes 6 ma 5V
HA[3:1] Input/Output yes 6 ma 5V
HCS[1:0] Input/Output yes 6 ma 5V
HCS[3:2] Output yes 6 ma 5V
HCS 4 Output yes 6 ma 5V
HD[15:0] Input/Output yes 6 ma 5V
HDMACK Output – 6 ma 5V
(Sheet 1 of 4)
3-4 Specifications

Arranged by Signal Name (Cont.)
Schmitt
Trigger
HDMARQ Input yes 6 ma 5V
HDTACK I/OD1 yes 6 ma 5V
HIRQ0 Input/Output yes 6 ma 5V
HIRQ1 Input/Output yes 6 ma 5V
HLDS Input/Output yes 6 ma 5V
HREAD Input/Output yes 6 ma 5V
HSYNC Input/Output yes 6 ma 5V
HUDS Input/Output yes 6 ma 5V
HXCVR_EN Output yes 6 ma 5V
IDC_CL I/OD yes 6 ma 5V
IDC_DA I/OD yes 6 ma 5V
IEC958 Output yes 6 ma 5V
IRRX1 Input yes 3 ma 5V
LRCK Output – 6 ma 5V
MA [11:0] Output – 15 ma 3.3 V
MCAS Output – 15 ma 3.3 V
MCLK Output – 36 ma 3.3 V
MCS[1:0] Output – 15 ma 3.3 V
MD[31:0] Input/Output – 15 ma 3.3 V
MDQM[3:0] Output – 15 ma 3.3 V
MRAS Output – 15 ma 3.3 V
MWE Output – 15 ma 3.3 V
(Sheet 2 of 4)


Schmitt
Trigger
RESET Input yes 3 ma 5V
RTS1 Output yes 6 ma 5V
RTS2 Output yes 6 ma 5V
RXD1 Input yes 6 ma 5V
RXD2 Input yes 6 ma 5V
SDCLK Input yes 6 ma 5V
SDDATA [7:0] Input yes 6 ma 5V
SDEN Input yes 6 ma 5V
SDERROR Input yes 6 ma 5V
SDREQ Output yes 6 ma 5V
SPI_CLK Output – 6 ma 5V
SPI_CS Output – 6 ma 5V
SPI_MISO Input – 6 ma 5V
SPI_MOSI Output – 6 ma 5V
TCK Input yes 3 ma 5V
TDI Input yes 3 ma 5V
TDO Output – 3 ma 5V
TMS Input yes 3 ma 5V
TRST Input yes 3 ma 5V
TXD1 Output yes 6 ma 5V
TXD2 Output yes 6 ma 5V
VCLK Input/Output – 12 ma 5V
(Sheet 3 of 4)
3-6 Specifications

Schmitt
Trigger
VDAC_[4:0] Output – – –
VDAC_[4B:0B] – – – –
VDAC_DVDD – – – –
VDAC_DVSS – – – –
VDAC_REF Input – – –
VDAC_REFVDD – – – –
VDAC_REFVSS – – – –
VDAC_VDD [4:0] – – – 3.3 V
VDATA [7:0] Input/Output yes 6 ma 5V
VDDCDL – – – –
VNW – – – –
VSYNC Input/Output yes 6 ma 5V
XCK Input/Output yes 12 ma 5V
XIN Input – – –
XOUT Output – – –
XVDD – – – –
XVSS – – – –
(Sheet 4 of 4)
1. I/OD = Input / open drain output.

3.2 AC Timing Diagrams
3.2.1 Global Interface Timing

Table 3.5, Figure 3.1, and Figure 3.2 specify AC timing parameters for
ZiVA-5+ signals on the global interface or parameters that apply to
signals on all interfaces.
Figure 3.1 Input Rise and Fall Timing Diagram
90% 90%
Input
10% 10%
A1 A1
Figure 3.2 SYSCLK Timing Diagram
A2
SYSCLK
A3 A4
Table 3.5 Global Interface AC Timing Parameters
Timing Value
Symbol Description Min Max Unit
A1 Input rise and fall time 3 – ns
A2 Reference input frequency (for TBD MHz

all NTSC and PAL modes)
A3 SYSCLK HIGH pulse width 0.45 * A2 0.55 * A2 ns
A4 SYSCLK LOW pulse width 0.45 * A2 0.55 * A2 ns
3-8 Specifications
3.2.2 SDRAM Timing Diagrams

This section gives SDRAM device AC timing specifications. This
specification is defined for 100 MHz, 0, 0 clock tap settings, and 50-pf
loading. The timing values in Table 3.6 assume a load on each output
from the ZiVA-5+ SDRAM interface, as shown in Figure 3.3. Timing
diagrams for the SDRAM interface are shown in Figure 3.4 and
Figure 3.5.
Table 3.6 SDRAM Timing Parameters1
Symbol Mnemonic Description Min Max Unit
D1 tCK MCLK cycle 10 – ns
D2 tCH MCLK HIGH 3.5 – ns
D3 tCL MCLK LOW 3.5 – ns
D4 MCLK Programmable Delay = (X/256) • N/A N/A ns

D1
D5 tASU MCS[2:0), MRAS, MCAS, MWE, 2.5 – ns

MS[11:0], BA[1:0] MDQM[3:0] Setup
Time relative to MCLK
D6 tAH MCS[2:0), MRAS, MCAS, MWE, 2 – –

MS[11:0], BA[1:0] MDQM[3:0] Hold Time
relative to MCLK
D7 tDS MD[31:0] in setup 2.5 – ns
D8 tDH MD[31:0] in hold 2.5 – ns

1. The timing parameters specified in this table are based on the clock tap settings of 0 for both
SDRAM_CLK_OUT and SDRAM_CLK_IN. Changing the tap setting changes the timing parame-
ters. Please see application note TD10-1055 to recalculate parameters.
AC Timing Diagrams 3-9

Figure 3.3 SDRAM Output Load

1.4 V
50 Ω
Z = 50 Ω
Output
50 pF
The timing of the SDRAM input and output clock (MCLK) is controlled by
fields within the SDRAM Clock Control register (SCC). The values
programmed into these fields are used to set the relative offset between
the clock on the external pin and the internal SYSCLK.
The three fields and the timing that they affect are:
• OutClkTapSel - This field sets the delay when MCLK is used as an

output during Single Data Rate writes.
• InClkTapSel - This field sets the delay when MCLK is used as an
input during Single Data Rate reads. It is also used to control the
output clock timing during Double Data Rate (DDR) writes.
• DDRTapSel - This field sets the delay between the MDQS signal and
the device strobe signal that is used to sample data read from
SDRAM in DDR mode only.
By programming these clock tap settings, the read and write timings can
be customized to accommodate all variations of SDRAM and board
design timing differences.
3-10 Specifications
Figure 3.4 SDRAM Write Timing Waveform
D1
D2 D2
D3
MCLK
(OutTapSel=0)
MCLK
(OutTapSel=X)
D5
MCS[2:0], MRAS, D4
MCAS, MWE,
MA[11:0], Stable
BA[1:0],
MDQM[3:0] D5
D4
MD[31:0] (Write) Stable
Figure 3.5 SDRAM Read Timing Waveform
D1
D2 D2
D3
MCLK
(OutTapSel=0)
MCLK
(OutTapSel=X)
MCS[2:0], D5
MRAS, MCAS, D4
MWE, MA[11:0], Stable
BA[1:0],
MDQM[3:0] D7
D6
MD[31:0] (Read)
Stable
InClkTapSel=0
D8
MD[31:0] (Read) Stable
InClkTapSel=Y

3.2.3 Async Master Personality Module Timing

Timing for the Async Master Personality Module is shown in Figure 3.6;
the timing parameters are described in Table 3.7.
Figure 3.6 Async Master Timing
BUSCLK
ADDR
AS_n
1 1 1
R/W_n
CSO BH CSO BH CSO BH
CSOUT_n
DSO DSO DSO
UDS_n/LDS_n
DATA
DT DT DT BDT
DTack_n
68K Mode Read 68K Mode Write 68K Mode Burst Read
3-12 Specifications
Table 3.7 Async Master Timing Parameters
Range of
Parameter Values Description
CSO 0–7 clocks Delay from Addr and R/W stable to fall of CS. For write cycles, Data is
driven out along with fall of CS.
DSO 0–7 clocks Delay from Addr and R/W stable to fall of data strobes (UDS and LDS or
OE, WEH and WEL).
DT 0–63 clocks For self-timed accesses, delay from Addr and R/W stable to HDTACK or
asserted or WAIT deasserted. For self-timed accesses, HDTACK is
pulsed low for one clock, then brought high for one clock before being
3-stated whereas WAIT is driven low at the start of the cycle then brought
high for one clock before being deasserted. On a read cycle, data is
latched in at the end of the clock cycle where HDTACK is asserted or
WAIT deasserted. For device-paced HDTACK transfers.
For device-paced WAIT transfers, this value indicates the amount of time
to wait before sampling the WAIT pin for cycle completion.
BDT 0–3 clocks For self-timed burst accesses, delay from end of previous data transfer
phase to assertion of HDTACK or deassertion of WAIT for next phase.
BH 0–15 clocks Added delay from end of cycle (CS and data strobes deasserted) to start
of next cycle. During the BH time, Addr and R/W are held stable and all
other signals are held inactive. On a write cycle, the Data bus is also
driven with the write data for the BH time.
AH 0–1 clock Multiplexed address hold time from fall of HTS to Addr/Data change.
In the case of device-paced transfer, the peripheral generates the

acknowledge signal after the MPM has placed all control signals on the
external Host Bus. The external acknowledge signal is used as an input
to generate an internal DTACK_n signal in either synchronous or
asynchronous mode.
Some devices require the host to wait an indefinite time for the transfer
to complete. These devices drive the HDTACK or WAIT signal
themselves, instead of relying on the host to self-time the transfer.
Besides these programmable parameters, the following additional timing

parameters are assumed by default according to the processor:
• The time between address valid and assertion of AS_n is one

BUSCLK period.

• In case of writing, the R/W_n pin is made low one BUSCLK period
after putting a valid address.
• The AS_n is negated along with negation of data strobe signals.
• In case of reading, the R/W_n pin is made high along with putting a
valid address on the ADDR bus.
3.2.4 IDE Personality Module Timing

Figure 3.7 shows the timing diagram for the PIO data transfer cycle;
Table 3.8 describes the timing parameters. Figure 3.8 shows the timing
diagram for a single-word PMA transfer cycle; Table 3.9 describes the
timing parameters.
Figure 3.7 IDE PIO Data Transfer Cycle
t0
CS0/CS1
t9
t8
t1 t2
DIOR/DIOW
Data (Write)
t3 t4
Data (Read)
t5 t6
t7
t6z
IOCS16
IORDY1
tA
IORDY2
tRD
IORDY3
3-14 Specifications
Table 3.8 PIO Data Transfer Cycle Times
Typical
Symbol Description Timing Value Units
t0 PIO Data Transfer Cycle Time 240 ns
t1 Data/Address Setup Time before 30 ns

DIOR/DIOW
t2 DIOR/DIOW Assertion Time 100 ns
t3 Setup Time to DIOW 20 ns
t4 Data Hold Time after deassertion of DIOW 15 ns
t5 Data Setup Time to DIOR 20 ns
t6 Data Hold Time after DIOR 5 ns
t6z Data 3-state Time after DIOR 30 ns
t7 IOCS16 Delay Time from CS 40 ns
t8 IOCS16 Hold Time after CS 30 ns
t9 CS Hold Time after deassertion of 10 ns

DIOR/DIOW
tA DIOR/DIOW delay to IORDY 0 ns
tRD IORDY Hold Time after assertion of data 0 ns

Figure 3.8 Single-word DMA Transfer
ta
DMARQ
tb
DMACK
tc ti
DICR/DIOW
td
HD[15:0] (Read)
te tf
HD[15:0] (Write)
tg th
Table 3.9 Single-word DMA Transfer Cycle Times
Symbol Description Mode1 Units
ta Single-word DMA Data Transfer Cycle Time (min) 480 ns
tb DMACK to DMARQ Delay Time (max) 100 ns
tc DMACK to DIOR/DIOW Delay Time (min) 0 ns
td DIOR/DIOW Assertion Time (min) 240 ns
te Data Delay from Assertion of DIOR/DIOW (Read) 150 ns

(max)
tf Data Hold from Deassertion of DIOR/DIOW 5 ns

(Read) (min)
tg Data Setup Time before Deassertion of 100 ns

DIOR/DIOW (Write) (min)
th Data Hold Time after Deassertion of DIOR/DIOW 30 ns

(Write) (min)
ti DMACK Hold Time after Deassertion of 0 ns

DIOR/DIOW (min)
3-16 Specifications
3.2.5 IDC Interface AC Timing

This section shows the timing for the inter-device communication (IDC)
interface. Figure 3.9 shows the data transfers on the IDC bus; Table 3.10
shows the IDC interface timing parameters.
During write operations, data transfers are relative to the IDCSCL output.
During read operations, data transfers are relative to the IDCSCL input.
Figure 3.9 Data Transfers on the IDC Bus
IDC_DA D7 D6 D5 D4 D3 D2 D1 D0
t1 t2 t3
IDC_CL
Table 3.10 IDC Interface Timing Parameters
Typical Timing Value
Symbol Description Standard 100 kHz Fast 400 kHz
t1 Data setup time before clock (master) 2552 ns 600 ns
t2 Data hold time after clock (master) 2623 ns 100 ns
t3 Clock period 10180 ns 2600 ns
t4 Value programmed into the IDC Clock 0x66 0x19

Register 0 or 1 (0x98C or 0x09CC)1
1. t4 is the value that must be programmed into the IDC Clock Register 0 or 1 (0x98C or 0x09CC) to
get the timing shown in parameter t3.
3.2.6 PCM Audio Interface AC Timing

Figure 3.10 shows the PCM Audio Interface timing. Symbols used in this
drawing are explained in Table 3.11.

Figure 3.10 PCM Interface AC Timing
P1
P2 P3
SDCLK
LRCK
P4 P5 P6
DAI_LRCK
Table 3.11 PCM Audio Interface Timing Parameters
Symbol Description Min Typ Max Units
P1 Clock Period 300 244 – ns
P2 Clock Low Time 120 – 134 ns
P3 Clock High Time 120 – 134 ns
P4 Output Delay – – 50 ns
P5 Input Setup 10 – – ns
P6 Input Hold 10 – – ns
3.2.7 I2S Bus Timing

Figure 3.11 shows the timing on the I2S bus. When the AUDIO_CONFG
parameter is set for IDS output, the LRCK polarity field in the
AUDIO_DAC_MODE parameter must be set to high during right channel.
Figure 3.11 I2S Bus Timing
One Sample, T = 1/fs

DA_BCK
DAI_LRCK Left Channel

Right Channel
DA_DATA MSB LSB MSB LSB MSB
16 or 24 Bits
3-18 Specifications
3.2.8 UART Timing

Figure 3.12 shows typical UART timing.
Figure 3.12 UART Receiver Timing
RXD [2:1] Start Data Bits (5-8) Parity Stop
3.2.9 Video Interface AC Timing

This section shows functional and AC timing for the ZiVA-5+ video
interface. All timing parameters are described in Table 3.12.
Figure 3.13 through Figure 3.18 shows the input and output functional
waveforms for NTSC and PAL formats. Figure 3.19 through Figure 3.22
shows the AC timing for the video interface signals; Table 3.12 describes
the AC timing parameters.
Note: VSYNCH is not shown in these figures, due to its relatively

long period.
Figure 3.13 Horizontal Synchronization Waveform
VCLK In (27 MHz)
HSYNC
Last First Left Last Left (Active)
Right Border Border
Border Pixel Of Pixel Of
Pixel Of Line N+1 Line N+1
Line N
VDATA[7:0] Crbor. Ybor. Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3
Note: “Boxed” values indicate interpolated pixels when interpolating horizontally.

Figure 3.14 VSYNC and HSYNC Master Mode Waveform
HSYNC
3 HSYNC 2.5 HSYNC
Periods Periods
VSYNC
Top Field Bottom Field
Note: Top field means the field that starts with the first line from the top of the screen, while bottom
field begins with the second line from the top of the screen.
Figure 3.15 NTSC Active Horizontal Line Input Timing

1 2 3 118 119 120 121 242 243 244 245
VCLK
DECHSYNC
VDIN[7:0] Cb Y Cr Y
Figure 3.16 NTSC Active Horizontal Line Output Timing

1 2 3 118 119 120 121 242 243 244 245
VCLK
ENCHSYNC
VDOUT[7:0] Cb Y Cr Y
3-20 Specifications
Figure 3.17 PAL Active Horizontal Line Input Timing

1 2 3 118 119 120 121 262 263 264 265
VCLK
DECHSYNC
VDIN[7:0] Cb Y Cr Y
Figure 3.18 PAL Active Horizontal Line Output Timing

1 2 3 118 119 120 121 262 263 264 265
VCLK
ENCHSYNC
VDOUT[7:0] Cb Y Cr Y
Figure 3.19, showing ITU-R BT.656 video output timing, is shown first
because that is the standard most designers will use. Other timing
diagrams for legacy products are shown in Figure through Figure 3.22.
Figure 3.19 ITU-R BT.656 Video Output Timing
V1
V2 V3
VCLK
V4 V5
VDATA[7:0]

Figure 3.20 Video Interface Encoder Mastering AC Timing Diagram
V1
V2 V3
VCLK
V6
ENCVSYNC, V7
ENCHSYNC,
VDIN[7:0]
V9
V8
DECVSYNC,
DECHSYNC,
VDOUT[7:0]
Figure 3.21 Video Interface Decoder Mastering AC Timing Diagram
V1
V2 V3
VCLK
V6
V7
DECVSYNC,
DECHSYNC,
VDIN[7:0]
V9
V8
ENCVSYNC,
ENCHSYNC,
VDOUT[7:0]
Figure 3.22 ITU-R BT.656 Interlaced Video Input Timing
V1
V2 V3
VCLK
V4 V5
VDATA[7:0]
3-22 Specifications
Table 3.12 Video Interface Timing Parameters
Units (ns)
Symbol Description Min Typ Max
V1 VCLK1 Period 34 37 41
V2 VCLK1 Low Time 17 18.5 20
V3 VCLK1 High Time 17 18.5 20
V4 VDATA Interlaced Output Setup to VCLK 5 – –
V5 VDATA Interlaced Output Hold from VCLK 4 – 7
V6 Encoder HSYNC, VSYNC and Video Data Input Setup Time 7

before VCLK
V7 Encoder HSYNC, VSYNC and Video Data Input Hold Time 3

after VCLK, Encode Mode
V8 Decoder HSYNC, VSYNC and Video Data Input Setup Time 25

before VCLK, Encode Mode
V9 Decoder HSYNC, VSYNC and Video Data Input Hold Time 2 7

after VCLK, Encode Mode
1. VCLK frequency is 27 MHz with a 45/55% duty cycle.
3.2.10 SPI Interface AC Timing

Figure 3.23 shows typical SPI Interface data clocking. Figure 3.24 shows
typical SPI Interface timing. Table 3.13 defines the parameters and lists
the values used in Figure 3.24.

Figure 3.23 SPI Serial Data Clocking
1 2 3 4 5 6 7 8
SPI_CLK
tr tC
tf th1
SPI_CS
SPI_DI MSB 6 5 4 3 2 1 LSB
SPI_DO MSB 6 5 4 3 2 1 LSB Note 1.
Note: 1. Not defined, but normally the MSB of previous character received.
Figure 3.24 SPI Timing
tr tc tf
SPI_CLK
tsu1 th1
SPI_CS
tsu2 tCS
th2
SPI_DI
td1 td2 td3
SPI_DO
3-24 Specifications
Table 3.13 SPI Interface Timing Parameters
Symbol Parameter1 Min2 Typ2 Max2 Units
tc SPI_CLK Cycle Time 0.062 – – µsec
tdty SPI_CLK Duty Cycle Tolerance 40 50 60 %
tjitter SPI_CLK Period Jitter Tolerance 120 – 120 ns
tr Rise Time, SPI_CLK – – 25 ns
tf Fall Time, SPI_CLK – – 25 ns
td1 Delay Time, SPI_CLK fall to SPI_DOUT Active – – 20 ns
td2 Delay Time, SPI_CLK Fall to SPI_DOUT Transition – – 20 ns
td3 Delay Time, SPI_CS Rise to SPI_DOUT 3-state – – 20 ns
tsu1 Setup time, SPI_CS to SPI_CLK Fall 25 – – ns
th1 Hold time, SPI_CS to SPI_CLK Rise 20 – – ns
tsu2 Setup time, SPI_DIN to SPI_CLK Rise 25 – – ns
th2 Hold time, SPI_DIN to SPI_CLK Rise 20 – – ns
tCS Delay Time between Chip Selects 220 – – ns

1. VD = 3.13 to 5.25 V TA = 0 to 70 °C, CL = 20 pF
2. All timing is referenced to the 50% level of the waveform. Input test levels are VIH - VI/O - 0.4V, VIL
= 0.4V
3.3 Package Mechanical Dimensions

The ZiVA-5+ is available in the 208-pin Plastic Quad Flat Pack (PQFP)
package, which is shown in Figure 3.25.
Package Mechanical Dimensions 3-25

Figure 3.25 208-pin PQFP Package Mechanical Dimensions

D
D1
P
D1
D
Dimensions in Millimeters1 (Inches)

Symbol Min. Typ. Max.
A – – 4.10 (0.161)
C A1 0.00 – 0.50 (.020)
A2 A2 3.15 (0.124) 3.50 (0.138) 3.85 (0.152)
A B 0.15 (0.006) 0.22 (0.009) 0.30 (0.012)
C 0.09 (0.004) 0.15 (0.006) 0.25 (0.010)
D 30.35 (1.195) 30.6 (1.205) 30.85 (1.215)
A1 D1 27.90 (1.098) 28.00 (1.102) 28.10 (1.106)
L 0.30 (0.012) 0.50 (0.020) 0.75 (0.030)
θ L L1 – 1.30 (0.051) –
L1 P – 0.50 (0.020) –
θ 0 – 10 deg.
1. The metric (millimeter) values are the controlling dimensions, and
should be used for PC board design.
3-26 Specifications
3.4 Package Marking

Some of the ZiVA-5+ devices receive additional marking as shown in
Figure 3.26.
Figure 3.26 ZiVA5+ Variant Marking
LSI
ZiVA™-5
B0 __
F YYWW
ASSY-LOT
COUNTRY
ZiVA-5P+ devices do not get any additional marking. ZiVA-5M+ devices

are marked with an “M” immediately behind the Silicon Revision marking
(B0 M). ZiVA-5X+ devices are marked with an “X” immediately behind
the Silicon Revision marking (B0 X).
Package Marking 3-27

3-28 Specifications

SD 5.12 312278514120

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DVD-Video Player Module MSD-512S

Appendix: Datasheet ZiVA-5+

1. Technical Specifications

PLAYBACK SYSTEM AUDIO PERFORMANCE

Power to Mpeg PWB can be applied via connector1615

Power to Loader (A97ST)

Specifications subject to change without prior notice

1.2 Technical Specifications 2. Basic Audio/Video circuits and the output

1.2.3 Key components for SD5.12

1.2.4 PCB specifications

1.2.5 Power supply and grounding concept

Power to Mpeg PWB can be applied via connector 1615.

Power name Rating Description Used by

+5VD +/-5% 1100 mA Digital power supply Digital circuits

+12VA +/-10% 60 mA Analog power supply Analog circuits

-12VA +/-10% 105 mA Analog power supply Analog circuits

Power to Loader (A97ST):

Power name Rating Description Used by

+5VL +/-5% 530 mA Digital power supply Loader

+12VL +/-10% 200 mA Spindle power supply Loader

In order to control EMC radiation:

1.2.6 Interface pin assignments

Connector Pin Assignment Description

Connector Pin Assignment Description

Connector Pin Assignment Description

Connector Pin Assignment Description

Connector Pin Assignment Description

Connector Pin Assignment Description

Connector Pin Assignment Description

Connector Pin Assignment Description

Connector Pin Assignment Description

1.2.7 Signal specifications

Signal type Description Definition

Low voltage transistor-transistor logic (3.3V logic) Absolute maximum rating:

Signal type Description Definition

All I2S signals at the module’s connectors are at LVTTL

1.2.7.1 SPDIF out

1.2.7.2 Analog audio

Function MUTE (TTL output)

1.2.7.4 Analog video

See 0. 1.2.14 Analog video performance.

1.2.7.5 Slow blanking SCART

Function SCART0 (LVTTL output) SCART1 (LVTTL output) 0/6/12(V)

1.2.7.7 DAC control bus

1.2.7.8 VFD bus ( for DVD set only)

1.2.7.9 Service bus

1.2.7.10 Service activation

1.2.7.11 Service +5V

1.2.9 Module control

1.2.10 Power supply requirements

Disc diameter Remark

1.2.12 Access time

1.2.13 Audio performance

1.2.13.2 Analog audio

Performance: Reference is made to the [PQR-IMS].

1.2.13.3 Audio connector

1.2.14 Analog video performance

Signal name Video format Remark

For TV used, the output format including: Y/C and YUV(RGB)

The video outputs comply fully with [PQR_IMS].

Superimposed DC level: 1.2V

Copy Protection: CSS

The analog video output connector including CVBS and SCART.