EE116B : VLSI Systems Design (Mani Srivastava) Winter 2001

Practice Problems on Pararasitics & Interconnects

Solutions
Notes:
For all problems assume the following parameters for MOS transistors: V tn = 0.75 V ,
µn ε o x µp ε ox
Vtp = –0.75 V , k n' = ------------- = 21 µA ⁄ V2 , and k p' = ------------- = 7 µA ⁄ V2 . Also assume that
to x t ox
the supply rails and the logic levels at the inputs are set at 0V and 3.3V.

Q 1. (10.0 points)
In order to drive a large capacitance (C L = 20 pF) from a minimum-size gate (with input capaci-
tance, C i = 10fF), a designer decides to introduce a two-staged buffer as shown in the figure
below. Assume that the propagation delay of a minimum-size inverter (loaded by an identical
gate) is given by t p0 = 70 ps. Also, assume that the input capacitance of a gate is proportional to
its size. Determine the sizing of the two additional buffer stages that will minimize the propaga-
tion delay as well as the value of the minimum delay.

A 1.
Ci = 10 fF
CL = 20 pF = 20000 fF = 2000 * Ci

From class, the best case would be when the delay is equally distributed among the three stages.
This is achieved by gradually scaling up by a constant factor u, i.e. stage 2 is u times larger than
stage 1, and stage 3 is u times larger than stage 2, and C L is u times larger than stage 3.

u3 = 2000, or u = 12.6.

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Therefore, the two additional stages will have transistors whose W/L’s are 12.6 and 12.6*12.6 =
158.7 times larger than those in the minimum sized gate.

The delay through the new buffer = 3utp0 = 3*12.6*70 ps = 2646 ps.
This is much less than the original (signe stage) delay of 2000*70 ps = 140000 ps.

Q 2. (3.5+3.5+4+4 = 15.0 points)

The figure below shows a clock distribution network. Each straight segment of the clock net-
work (between the nodes) is 5mm long, 3µm wide, and is implemented in polysilicon. At each
of the terminal nodes resides a load capacitance of 100 fF. Polysilicon has parallel-plate capaci-

100 fF

100 fF

100 fF

R 100 fF

tance to substrate of 0.058 fF/µm2, fringing capacitance to substrate of 0.043 fF/µm, and sheet
resistance of 10 Ω/square.

a. Determine the average current of the clock driver, given a voltage swing on the clock lines of
5 V and a maximum delay (for the output to reach 90% of the final value) of 5 nsec between
clock source and destination node R. For this part, you may ignore the resistance and inductance
of the clock distribution network.

b. Unfortunately the resistance of the polysilicon cannot be ignored. Assume that each straight
segment of the network can be modeled as Π-network as shown below. Draw the equivalent cir-
cuit and annotate the values of resistors and capacitors.
R

The Π-network model

C/2 C/2 for a distributed RC line

c. Determine the dominant time-constant of the clock response at node R.

d. Assume now that the interconnect technology get scaled in the following way: the width of
the wires and the oxide thickness decrease with a factor 2, the height of the wire remains con-

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stant, while its length doubles. The load capacitance of the fanout decreases with a factor of 2 as
well. Determine the speed-up or slow-down. You should use a single wire segment for this anal-
ysis (consisting of a straight wire connected to a load).

A 2.
a.
Iaverage = C total × ∆
-----V
--
∆t
5 × 0.9 Volt
= ( 4 × 100 fF + 7 × Cwire segment ) × ---------------------------
5 nsec
5 × 0.9 Volt
= ( 400 fF + 7 × ( 5 mm × 3 µm × 0.058 fF/µm 2 + 2 × 5 mm × 0.043 fF/µm ) ) × ---------------------------
5 nsec
5 × 0.9 Volt
= ( 400 fF + 7 × ( 870 fF + 430 fF) ) × ---------------------------
5 nsec
5 × 0.9 Volt
= 9500 fF × ---------------------------
5 nsec
= 8.55 mA

b.
As shown above,
C ws = C wire segment = ( 870 + 430 ) fF = 1300 fF

Also,
Rws = Rwire segment = 5--------------
mm × 10Ω ⁄ square = 16.667 kΩ
3 µm

This gives rise to the following equivalent circuit:

c.
Using the Penfield-Rubenstein-Horowitz approach dicussed in the class, the dominant time con-
stant at node R is given by
τ = 1.5C ws ( Rws + 2Rws ) + ( 0.5C ws + 100 fF ) ( Rws + Rws + 2Rws + 3Rws )
= 9.5C ws Rws + 7Rws × 100 fF
= 9.5 × 1300 fF × 16.667 kΩ + 7 × 100 fF × 16.667 kΩ
= 217.5 ns

d. Consider a straight wire of length L and width W driving a load C L . Before scaling, the wire
resistance and capacitance are given by

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R ws
100 fF + 0.5*Cws

R ws R ws

R ws 1.5*C ws
100 fF + 0.5*Cws

Rw s Rws
0.5*C ws 1.5*C ws
100 fF + 0.5*Cws
R ws
1.5*Cws

100 fF + 0.5*Cws

R old = Rs ×  -----
L
W
C old = 0.058 × L × W + 2 × 0.043 × L

After scaling, the wire resistance and capacitance are:

 
 2L 
Rnew = Rs ×  ---------- = 4 × R old
W 
  -2--  

Cnew = ( 0.058 × 2 ) × ( 2L ) ×  ---  + 2 × 0.043 × (2 × L ) = 2 × C old

W
 2

The slow-down is given by:

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EE116B : VLSI Systems Design (Mani Srivastava) Winter 2001

τ new
Slow-down = ----------
τ old
C
Rnew  C new + ------L
2
= ------------------------------------------
Rold ( C old + C L )
C
4Rold  2C old + ------L
 2
= ----------------------------------------------
Rold ( Cold + C L )
CL
8 + 0.5 ----------
C old
= ---------------------------
-
CL
1 + ----------
C old
For CL > 14Cold there would be a speed up, otherwise a slow-down.

For a single wire segment,

C old = 0.058 × L × W + 2 × 0.043 × L
= 0.058 × 5 mm × 3 µm + 2 × 0.043 × 5 mm
= 1300 fF

while C L = 100 fF ..
100
8 + 0.5 ------------
1300 = 7.5 .
Plugging in the numbers, one sees that there is a slow-down by a factor of -----------------------------
100
1 + ------------
1300

Q 3. (5+5+5 = 15.0 points)

To connect a processor to an external memory, an off-chip connection is necessary as shown in
the figure below. The copper wire on the board, which is 15 cm long, acts as a transmission line
with characteristic impedance of 100 Ω. The memory input pins represent a very high imped-
ance, which can be considered infinite. The bus driver is a CMOS inverter, consisting of very
large devices of (120/1.2) for NMOS and (360/1.2) for PMOS. You may also assume that the
on-resistance of the minimum-size devices (1.8/1.2 and 5.4/1.2, for NMOS and PMOS respec-
tively) equals 10 kΩ, and scales proportionately with the size of the transistors.

a. Determine the time it takes for a change in signal to propagate from the source to destination
(the time of flights). The wire inductance per unit length equals 75E-8 H/m.

b. Given the driver device sizes defined above, determine how long it will take the output signal
to come and stay within 10% of its final value. You can model the driver as a voltage source

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with the driving device acting as series source resistance. Determine the reflection coefficients
on both the source and destination ends and draw the lattice diagram for the transmission line.
Assume a supply and step voltage of 5V.

c. Resize the device dimensions of the driver to minimize the transmission line delay. Determine
the minimum time and derive the sizes for the NMOS and PMOS transistors.

A 3.
Given:

wire length L = 0.15 m

characteristic impedance Z0 = 100 Ω
load impedance ZL = infinity
inductane per unit length l = 75E-8 H/m

a. time for signal propagation from source to destination = L/v

= L/(Z0/l) = 0.15/(100/75E-8) m/s = 1.125 ns
b.
Source impedance ZS = R NMOS,on (= RPMOS,on) = 10 kΩ/(120/1.8) = 150 Ω
Reflection coefficient at source = (150-100)/(150+100) = 0.2
Reflection coefficient at destination = 1

The lattice diagram till destination voltage is within 10% of its final value (i.e. between 4.5V and

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5.5V) is:

Vsource V dest
5V * 100/(150+100) = 2V
2V
0V + 2V * (1+1) = 4V
2V
2V + 2V * (1+0.2) = 4.4V
0.4V
4V + 0.4 * (1+1) = 4.8V
0.4V

As one can see, it takes 3 trips through the wire before the output is within 10% of its final value,
or 3.375 ns.

c.
To get the least transmission line delay, the source impedance should be matched with the char-
acteristic impedance of the line. In other words, the NMOS and the PMOS should have on resis-
tance of 100 Ω. Since 1.8/1.2 and 5.4/1.2 sized NMOS and PMOS have on resistance of 10 kΩ, we
will get the desired performance with NMOS and PMOS of size 180/1.2 and 540/1.2 respectively.
As described in the class, in this case the output will reach the desired value after one propaga-
tion delay of the waveform, i.e. 1.125 ns.

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