5 4 3 2 1

D D

DJ1 Calpella UMA Schematics Document

Arrandale
C
Intel PCH C

2010-04-23
REV : X01
B B

DY : Nopop Component

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Cover Page Rev
A3
DJ1 Calpella UMA X01
Date: Monday, April 26, 2010 Sheet 1 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

CPU DC/DC
DJ1 UMA Block Diagram INPUTS
ISL62882
OUTPUTS
47,48

+PWR_SRC +VCC_CORE 39
Project code : 91.4EK01.001
SYSTEM DC/DC
PCB P/N : 48.4EK19.0SB TPS51218 49
INPUTS OUTPUTS
D
Revision : 10212-SB +PWR_SRC +1.05V_VTT
D

Clock Generator
SLG8SP585 SYSTEM DC/DC
RT8205BGQW 46
7 Intel CPU INPUTS OUTPUTS
DDRIII 800/1066 Channel A DDRIII Slot 0 +5V_ALW2
+PWR_SRC +3.3V_RTC_LDO
18
800/1066 +5V_ALW
Arrandale +3.3V_ALW
+15V_ALW

DDRIII 800/1066 Channel B DDRIII Slot 1 SYSTEM DC/DC

19
800/1066 RT8207GQW 50
INPUTS OUTPUTS
+1.5V_SUS
8,9,10,11,12,13,14 +PWR_SRC +0.75V_DDR_VTT
+V_DDR_REF
10/100 NIC RJ45
ATHEROS CONN SYSTEM DC/DC
PCIE x 1 AR8152/AR8151 TPS51611 53
C C

DMIx4 FDIx4x2(UMA) INPUTS OUTPUTS

I/O Board
Connector
CRT RGB CRT
Left Side: +PWR_SRC +CPU_GFX_CORE
55 PCIE x 1
USB x 1
MAXIM CHARGER
LCD LVDS(Dual Channel) BQ24745
54 USB 2.0 x 2 INPUTS OUTPUTS
Intel Mini-Card +DC_IN +PWR_SRC
76 802.11a/b/g +PBATT
PCIE 26
PCH SYSTEM DC/DC
APL5930 51
CardReader
INPUTS OUTPUTS
SD/MMC/MS/ 14 USB 2.0/1.1 ports
Realtek USB2.0 +3.3V_ALW +1.8V_RUN
MS Pro/xD High Definition Audio
71 RTS5138 USB 2.0 x 1
SATA ports (6) USB 2.0 CAMERA 54
32
PCIE ports (8) SYSTEM DC/DC
Switches 42
LPC I/F
B
USB 2.0 x 1
INPUTS
26 OUTPUTS B
ACPI 1.1 Bluetooth 73 +1.5V_SUS +1.5V_RUN
PCI/PCI BRIDGE +5V_ALW +5V_RUN
Azalia AZALIA +3.3V_ALW +3.3V_RUN

CODEC USB 2.0 x 2 Right Side:

Internal Analog MIC
92HD79B1 LPC Bus USB x 2 63
PCB LAYER
20,21,22,23,24,25,26,27,28
L1: Top
30 L2: VCC
L3: Signal
KBC L4: Signal
HP1 SPI L5 GND
NUVOTON
SATA

SATA

L6: Bottom
SPI

NPCE781BA0DX 37
MIC IN

A <Core Design> A
2CH SPEAKER
Flash ROM Flash ROM Touch Int. Thermal
HDD ODD
4MB 62 256kB 62 PAD KB EMC2102 Wistron Corporation
59 59 39 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
68 68 25 Taipei Hsien 221, Taiwan, R.O.C.

Title
Block Diagram
Size Document Number Rev
Fan A3 X01
58 DJ1 Calpella UMA
Date: Monday, April 19, 2010 Sheet 2 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

D D

+PWR_SRC TPS51116
Adapter
1000mA 16825mA
ISL62882 TPS51218 TPS51611
AO4407A +V_DDR_REF +0.75V_DDR_VTT +1.5V_SUS
Charger 48000mA 24800mA 22000mA
BQ24745 +VCC_CORE +1.05V_VTT +CPU_GFX_CORE

Battery +PBATT
AO4468

3500mA
+1.5V_RUN
C C

TPS51125
11145mA
82mA 10330mA
+3.3V_RTC_LDO
+3.3V_ALW
+15V_ALW +5V_ALW2 +5V_ALW

AO4468
G547F2P81U-GP AO4468 G547F2P81U-GP AO3403 APL5930
6661mA
2000mA 6330mA 2000mA 300mA 1761mA
+3.3V_RUN
+5V_USB1 +5V_RUN +5V_USB2 +3.3V_LAN +1.8V_RUN

B B

SI3456DDV RTS5159

2000mA 300mA
+LCDVDD +3.3V_RUN_CARD

Power Shape

Regulator LDO Switch

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Power Block Diagram Rev
A3
DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 3 of 90
5 4 3 2 1

forum.hocvienit.vn
 A B C D E

PCH SMBus Block Diagram

KBC SMBus Block Diagram
+5V_RUN

+3.3V_ALW +3.3V_RUN

 
SRN10KJ-5-GP
+3.3V_RUN
1

SRN2K2J-1-GP

SRN2K2J-1-GP
TouchPad Conn. 1

PSDAT1 TPDATA
 TPDATA TPDATA
DIMM 1 PSCLK1 TPCLK
 TPCLK TPCLK
SMBCLK PCH_SMB_CLK
 PCH_SMBCLK SCL
SMBDATA PCH_SMB_DATA
  PCH_SMBDATA SDA
+KBC_PWR

18

SMBus Address:A0
DMN66D0LDW-7-GP

DIMM 2 SRN4K7J-8-GP
PCH_SMBCLK SCL

 PCH_SMBDATA SDA 19 SRN100J-3-GP Battery Conn.

SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB
SMBus Address:A4 SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB SMBus address:16

Clock
Generator BQ24745
PCH_SMBCLK
 PCH_SMBDATA
SCLK
SDATA
KBC SCL

SDA SMBus address:12

7

SMBus address:D2
NPCE781BA0DX
2 +3.3V_RUN 2

PCH +3.3V_ALW Minicard 

+3.3V_ALW

 PCH_SMBCLK
WLAN
SMB_CLK
+3.3V_RUN
SRN4K7J-8-GP
 PCH_SMBDATA SRN4K7J-8-GP 
SMB_DATA 76
Thermal
SRN2K2J-1-GP
 THERM_SCL SCL
SMBus address:7A
 THERM_SDA SDA

SML0CLK SML0_CLK

SML0DATA SML0_DATA

XDP GPIO61/SCL2 KBC_SCL1
DMN66D0LDW-7-GP
GPIO62/SDA2 KBC_SDA1

+3.3V_RUN

 PCH
SML1DATA/GPIO75
SRN2K2J-1-GP SML1CLK/GPIO58

L_DDC_CLK LDDC_CLK

L_DDC_DATA LDDC_DATA

LCD CONN 23

3 3

+3.3V_RUN +5V_CRT_RUN

 
+3.3V_RUN
SRN2K2J-1-GP SRN2K2J-1-GP


CRT_DDC_CLK GMCH_DDCCLK
  DDC_CLK_CON

CRT_DDC_DATA GMCH_DDCDATA
  DDC_DATA_CON CRT CONN
DMN66D0LDW-7-GP

23

4 4

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS Block Diagram

Size Document Number Rev
A2 DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 4 of 90
A B C D E

forum.hocvienit.vn
 A B C D E

Thermal Block Diagram Audio Block Diagram

1 1

SPKR_PORT_D_L-

SPKR_PORT_D_R+ SPEAKER

Codec
DP1 EMC2102_DP1
ALC269Q_VB5
SC470P50V3JN-2GP
MMBT3904-3-GP HP1_PORT_B_L HP
HP1_PORT_B_R
2
DN1 EMC2102_DN1
OUT 2

Place near CPU

Thermal and PCH.

EMC2102
DP2 EMC2102_DP1

MMBT3904-3-GP
HP0_PORT_A_L MIC
HP0_PORT_A_R

DN2 EMC2102_DN1 VREFOUT_A_OR_F IN

System Sensor(UMA only)

3 3

DP3 EMC2102_DP3

MMBT3904-3-GP
SC470P50V3JN-2GP

DN3 EMC2102_DN3

Put under CPU. PORTC_L

PORTC_R
Analog
VREFOUT_C MIC

4 4
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 5 of 90
A B C D E

forum.hocvienit.vn
 A B C D E

PCH Strapping Processor Strapping

Calpella Schematic Checklist Rev.0_7 Calpella Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with Embedded DisplayPort.
8.2-k- 10-k weak pull-up resistor. DisplayPort
4 Presence 0: Enabled - An external Display Port device is
4
INIT3_3V# Weak internal pull-down. Do not pull high. connected to the Embedded Display Port.
GNT3#/ Default Mode: Internal pull-up. CFG[3] PCI-Express Static 1: Normal Operation. 1
GPIO55 Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
pull-down resistor).
CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
INTVRMEN High (1) = Integrated VRM is enabled Configuration 0: Bifurcation enabled
Low (0) = Integrated VRM is disabled Select
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1#/GPIO51 required. CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0
Temporarily used Connect to GND with 3.01K Ohm/5% resistor
Boot from PCI: Connect GNT1# to ground with 1-k
pull-down resistor. Leave GNT0# Floating. for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
Boot from LPC: Connect both GNT0# and GNT1# to ground with samples. MoW and sighting report].
1-k pull-down resistor. For a common motherboard design (for AUB and CFD),
GNT2#/ Default - Internal pull-up. the pull-down resistor should be used. Does not
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers impact AUB functionality.
only. Not for mobile/desktops).

GPIO33 Default: Do not pull low.

Disable ME in Manufacturing Mode: Connect to ground with 1-k
pull-down resistor.
3 3
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull- up resistor.
Disable iTPM: Left floating, no pull-down required.
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up
resistor.
Disable Danbury: Connect to ground with 4.7-k weak pull-down
resistor.
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.
/GPIO[33] High (1) : Flash Descriptor Security will be in effect.
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC Weak internal pull-down. Do not pull high.
GPIO15 Weak internal pull-down. Do not pull high.
GPIO8 Weak internal pull-up. Do not pull low.
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
2 2

PCIE Routing USB Table

USB
Pair Device
LANE2 MiniCard WLAN 0 USB0 (I/O Board)
1 X
LANE3 LAN 2 USB2
3 USB3
4 X
5 WLAN (I/O Board)
6 X
7 X
8 X
1 <Core Design>
1
9 BLUETOOTH
10 CARD READER Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
11 CAMERA Taipei Hsien 221, Taiwan, R.O.C.

12 X Title

13 X
Size Document Number
Table of Content Rev
A3
DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 6 of 90

A B C D E

forum.hocvienit.vn
 5 4 3 2 1

SSID = CLOCK

+3.3V_RUN
+3.3V_RUN_SL585 +1.05V_VTT
D
+1.05V_RUN_SL585_IO D

1 R708 2
0R0603-PAD-1-GP 1 R709 2
0R0603-PAD-1-GP
1

1
C701 C702 C703 C704 C705 C707 C708

1
C709 C710 C711 C712
DY DY
SC1U10V2KX-1GP

SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
DY
2

SC1U10V2KX-1GP

SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

2
+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO

+3.3V_RUN
R701
1 2 CPU_STOP#

2K2R2J-2-GP

C C

24

17

29

15

18
1

5
U701

VDD_CPU

VDD_SRC

VDD_REF

VDD_DOT

VDD_27

VDD_SRC_IO

VDD_CPU_IO
2 3 CLK_MCH_DREFCLK1# 4 6
23 DREFCLK# 0R4P2R-PAD 1 CLK_MCH_DREFCLK1 DOT_96# 27MHZ
4 3 DOT_96 27MHZ_SS 7
23 DREFCLK RN701
23 CLKIN_DMI# 2 3 CLK_IN_DMI# 14 SRC_2#
RN

23 CLKIN_DMI 0R4P2R-PAD 1 4 CLK_IN_DMI 13 16 CPU_STOP#

RN702 SRC_2 CPU_STOP# CK_PW RGD
CKPWRGD/PD# 25
23 CLK_PCIE_SATA# 2 3 CLK_PCIE_SATA1# 11 30 FSC 2 1 CLK_PCH_14M 23
SRC_1/SATA# REF_0/CPU_SEL
RN
RN

23 CLK_PCIE_SATA 0R4P2R-PAD 1 4 CLK_PCIE_SATA1 10

RN703 SRC_1/SATA R703
DY

1
23 CLK_CPU_BCLK# 1 4 CLK_CPU_BCLK1# 22 28 CLK_XTAL_IN 33R2J-2-GP
CPU_0# XTAL_IN
RN

23 CLK_CPU_BCLK 0R4P2R-PAD 2 3 CLK_CPU_BCLK1 23 27 CLK_XTAL_OUT EC701

RN704 CPU_0 XTAL_OUT SC4D7P50V2CN-1GP

2
19 CPU_1# SDA 31
20 CPU_1 SCL 32

VSS_SATA
VSS_CPU

VSS_SRC

VSS_DOT
VSS_REF

VSS_27 PCH_SMBDATA
PCH_SMBDATA 18,19,23,76
PCH_SMBCLK
GND

PCH_SMBCLK 18,19,23,76

B SLG8SP585VTR-GP B
33

26

21

12

FSC 0 1
+1.05V_VTT
133MHz
X701 SPEED 100MHz
CLK_XTAL_IN 1 2 CLK_XTAL_OUT (Default)
2
1

C714 X-14D31818M-37GP R704 +3.3V_RUN_SL585

SC12P50V2JN-3GP C715
82.30005.901 SC12P50V2JN-3GP DY 4K7R2J-2-GP
2

A <Core Design> A
1

R705
FSC 10KR2J-3-GP
G Wistron Corporation
1

VR_CLKEN# 47
. .
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2

CK_PW RGD D Taipei Hsien 221, Taiwan, R.O.C.

.
.
.

R707
10KR2J-3-GP S Title

Q701 Clock Generator SLG8SP585

1

Size Document Number Rev

2N7002E-1-GP
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 7 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1
SSID = CPU

Main:62.10053.601
2nd :62.10040.611
D 3rd :62.10055.321 PEG_IRCOMP_R R8011 2 49D9R2F-GP
D
CPU1A 1 OF 9 EXP_RBIAS R8021 2 750R2F-GP
PEG_ICOMPI B26
PEG_ICOMPO A26
22 DMI_PTX_CRXN0 A24 B27

AUBURNDALE
DMI_RX0# PEG_RCOMPO
22 DMI_PTX_CRXN1 C23 A25
DMI_RX1# PEG_RBIAS
22 DMI_PTX_CRXN2 B22
DMI_RX2#
22 DMI_PTX_CRXN3 A21 DMI_RX3# PEG_RX0# K35
J34
PEG_RX1#
22 DMI_PTX_CRXP0 B24 J33
DMI_RX0 PEG_RX2#
22 DMI_PTX_CRXP1 D23 G35
DMI_RX1 PEG_RX3#

DMI
22 DMI_PTX_CRXP2 B23 G32
DMI_RX2 PEG_RX4#
22 DMI_PTX_CRXP3 A22 F34
DMI_RX3 PEG_RX5#
F31
PEG_RX6#
22 DMI_CTX_PRXN0 D24 D35
DMI_TX0# PEG_RX7#
22 DMI_CTX_PRXN1 G24 DMI_TX1# PEG_RX8# E33
22 DMI_CTX_PRXN2 F23 C33
DMI_TX2# PEG_RX9#
22 DMI_CTX_PRXN3 H23 DMI_TX3# PEG_RX10# D32
B32
PEG_RX11#
22 DMI_CTX_PRXP0 D25 DMI_TX0 PEG_RX12# C31
22 DMI_CTX_PRXP1 F24 B28
DMI_TX1 PEG_RX13#
22 DMI_CTX_PRXP2 E23 DMI_TX2 PEG_RX14# B30
22 DMI_CTX_PRXP3 G23 A31
DMI_TX3 PEG_RX15#
J35
PEG_RX0
H34
PEG_RX1
C 22 FDI_TXN0 E22
PEG_RX2
H33
F35
C
FDI_TX0# PEG_RX3
22 FDI_TXN1 D21 G33
FDI_TX1# PEG_RX4
22 FDI_TXN2 D19 E34
FDI_TX2# PEG_RX5
22 FDI_TXN3 D18 FDI_TX3# PEG_RX6 F32

Intel(R) FDI
22 FDI_TXN4 G21 FDI_TX4# PEG_RX7 D34
22 FDI_TXN5 E19 FDI_TX5# PEG_RX8 F33
22 FDI_TXN6 F21 B33
FDI_TX6# PEG_RX9
22 FDI_TXN7 G18 D31
FDI_TX7# PEG_RX10
A32
PEG_RX11
PEG_RX12 C30
22 FDI_TXP0 D22 A28
FDI_TX0 PEG_RX13

PCI EXPRESS -- GRAPHICS

22 FDI_TXP1 C21 B29
FDI_TX1 PEG_RX14
22 FDI_TXP2 D20 A30
FDI_TX2 PEG_RX15
22 FDI_TXP3 C18
FDI_TX3
22 FDI_TXP4 G22 L33
FDI_TX4 PEG_TX0#
22 FDI_TXP5 E20 M35
FDI_TX5 PEG_TX1#
22 FDI_TXP6 F20 M33
FDI_TX6 PEG_TX2#
22 FDI_TXP7 G19 M30
FDI_TX7 PEG_TX3#
L31
PEG_TX4#
22 FDI_FSYNC0 F17 K32
FDI_FSYNC0 PEG_TX5#
22 FDI_FSYNC1 E17 FDI_FSYNC1 PEG_TX6# M29
PEG_TX7# J31
22 FDI_INT C17 FDI_INT PEG_TX8# K29
H30
PEG_TX9#
22 FDI_LSYNC0 F18 H29
FDI_LSYNC0 PEG_TX10#
22 FDI_LSYNC1 D17 FDI_LSYNC1 PEG_TX11# F29
E28
PEG_TX12#
PEG_TX13# D29
D27
B PEG_TX14#
PEG_TX15#
C26 B
PEG_TX0 L34
M34
PEG_TX1
PEG_TX2 M32
PEG_TX3 L30
PEG_TX4 M31
K31
PEG_TX5
M28
PEG_TX6
H31
PEG_TX7
PEG_TX8 K28
PEG_TX9 G30
G29
PEG_TX10
F28
PEG_TX11
PEG_TX12 E27
PEG_TX13 D28
C27
PEG_TX14
PEG_TX15 C25

A <Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (PCIE/DMI/FDI)
Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 8 of 90

5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1
Processor Compensation Signals
SSID = CPU DDR_RST_GATE 25

RN
+1.05V_VTT CPU1B 2 OF 9 C915
Processor Pullups

1
1 2 H_COMP3 AT23 SCD047U16V2ZY-1GP
R901 20R2F-GP COMP3 BCLK_CPU_P_R
BCLK A16 1 4 RN901 BCLK_CPU_P 25
R902 1 2 49D9R2F-GP H_CATERR# 1 2 H_COMP2 AT24 B16 BCLK_CPU_N_R 2 3 0R4P2R-PAD +1.5V_SUS
BCLK_CPU_N 25

AUBURNDALE

2
R903 20R2F-GP COMP2 BCLK#

MISC
CLOCKS
1 2 H_COMP1 G16 AR30 BCLK_ITP_P

1
COMP1 BCLK_ITP

RN
R933 1 2 68R2-GP H_PROCHOT# R905 49D9R2F-GP AT30 BCLK_ITP_N
H_COMP0 BCLK_ITP# R934
1 2 AT26 COMP0 Q901
R906 49D9R2F-GP E16 PEG_CLK_R 1 4 RN903 1KR2J-1-GP
PEG_CLK CLK_EXP_P 23
R904 1 2 68R2-GP H_CPURST# PEG_CLK#_R 3 0R4P2R-PAD
DY D16 2 CLK_EXP_N 23 G

. .
PEG_CLK#
D TPAD14-GP TP901 1 SKTOCC#_R AH24 D

2
SKTOCC#
A18 D DDR3_DRAMRST# 18,19

.
.
.
DPLL_REF_SSCLK
DPLL_REF_SSCLK# A17
H_CATERR# AK14 S
CATERR#

1
THERMAL
C903
SM_DRAMRST# +1.05V_VTT 2N7002E-1-GP SCD1U10V2KX-5GP
F6

2
SM_DRAMRST# RN905
25 H_PECI AT15 PECI
AL1 SM_RCOMP_0 4 1 1 2
SM_RCOMP0
AM1 SM_RCOMP_1 3 2 R935 DY 0R2J-2-GP
SM_RCOMP1

RN
AN1 SM_RCOMP_2
SM_RCOMP2 SRN10KJ-5-GP
47 H_PROCHOT# AN26
PROCHOT# PM_EXTTS#0_C
AN15 1 4 PM_EXTTS#0 18
PM_EXT_TS0# PM_EXTTS#1_C
AP15 2 3 PM_EXTTS#1 19
PM_EXT_TS1# 0R4P2R-PAD

DDR3
MISC
25,37,42 H_THERMTRIP# AK15 RN906
THERMTRIP#
SM_DRAMRST# 1 2
AT28 XDP_PRDY#
PRDY# XDP_PREQ# R988
AP27
PREQ# 100KR2J-1-GP
PM_EXTTS#0_C 53
AN28 XDP_TCLK
H_CPURST# TCK XDP_TMS
AP26 RESET_OBS# TMS AP28

PWR MANAGEMENT
AT27 XDP_TRST#
TRST#

JTAG & BPM

AL15 AT29 XDP_TDI_R
22 H_PM_SYNC PM_SYNC TDI
AR27 XDP_TDO_R DDR3 Compensation Signals
TDO XDP_TDI_M
AR29
TDI_M XDP_TDO_M SM_RCOMP_0 R907 1
AN14 AP29 2 100R2F-L1-GP-U
VCCPWRGOOD_1 TDO_M
C AN25 H_DBR#_R 1 R909 2 XDP_DBRESET# SM_RCOMP_1 R910 1 2 24D9R2F-L-GP
C
VCCPW RGOOD DBR#
25,42 H_PW RGD 1 R908 2 AN27
0R0402-PAD VCCPWRGOOD_0 0R0402-PAD SM_RCOMP_2 R911 1 2 130R2F-1-GP
AJ22 XDP_OBS0
BPM0#
22 PM_DRAM_PW RGD 1 R912 2 VDDPW RGOOD_R AK13 SM_DRAMPWROK BPM1# AK22 XDP_OBS1
0R0402-PAD AK24 XDP_OBS2
BPM2# XDP_OBS3
AJ24
BPM3# XDP_OBS4
49 H_VTTPW RGD AM15 AJ25
VTTPWRGOOD BPM4# XDP_OBS5
AH22
BPM5# XDP_OBS6
BPM6# AK23
H_PW RGD_XDP AM26 AH23 XDP_OBS7
TAPPWRGOOD BPM7# +1.05V_VTT
R913
1 2 PLT_RST#_R AL14 XDP_TMS 1 2
21,37,70,76 PLT_RST# RSTIN# R914 DY 51R2J-2-GP
1

XDP_TDI_R
1K6R2F-GP R915 R916
1
DY 2
51R2J-2-GP
750R2F-GP XDP_PREQ#
+3.3V_RUN R917
1
DY 2
51R2J-2-GP
2

R919 R920 XDP_TCLK

1119 R918
1
DY 2
51R2J-2-GP
S3 circuit 1.1k 0.75k
No Stuff
Normal 1.27k 3k
U927
1
B
VCC 5 R977
+1.5V_RUN 2
B XDP1
37,42,49 VTT_PW RGD A
Y
4 VTT_PW RGD_R3 1 2 VDDPW RGOOD_R B
XDP_TDI_R XDP_TDI XDP_TRST#
NP1 3 1
DY 2
1

GND 1K6R2F-GP R921 0R2J-2-GP

61

1
R919 1 2
1K1R2F-GP 62 74LVC1G08GW -1-GP XDP_TDO_M 1 2 XDP_TDO R923
DY XDP_PREQ# 3 4 R922 DY 0R2J-2-GP 51R2J-2-GP

1
XDP_PRDY# 5 6 R978
2

7 8 R924

2
VDDPW RGOOD_R XDP_OBS0
XDP_OBS1
9
11
10
12
37 VDDPW RGOOD_KBC 1
DY 2 0R0402-PAD
1

13 14 1K6R2F-GP

2
R937 XDP_OBS2 XDP_TDI_M
750R2F-GP XDP_OBS3
15
17
16
18
1
R925 DY 2
0R2J-2-GP
19 20
21 22 XDP_TDO_R 1 R926 2
2

23 24 +1.05V_VTT
25 26 0R0402-PAD
XDP_OBS4 27 28 Scan Chain Stuff --> R921, R924, R926 JTAG MAPPING
XDP_OBS5 29
DY 30
31 32 (Default) No Stuff --> R922, R925
XDP_OBS6 33 34 C901 1 CPU Only Stuff --> R921, R922
+1.05V_VTT XDP_OBS7 SCD1U16V2KX-3GP
35 36
DY No Stuff --> R924, R926, R925

1
37 38
2

H_PW RGD H_CPUPW RGD_XDP BCLK_ITP_P R928 GMCH Only Stuff --> R926, R925
1
R927 1 DY 2
2 1KR2J-1-GP PM_PW RBTN#_XDP
39
41
40
42 BCLK_ITP_N 51R2J-2-GP
22 PM_PW RBTN#_R R929 DY 0R2J-2-GP 43 44 No Stuff --> R921, R922, R924
H_PW RGD_XDP PCIE_CLK_XDP_P XDP_RST#_R H_CPURST#
1
DY 2 45 46 1
DY 2
2

R930 0R2J-2-GP 47 48 R931 1KR2J-1-GP XDP_DBRESET# 22

49 50
A <Core Design>
A
1

C902 51 52 XDP_TDO
23 SML0_DATA
SCD1U16V2KX-3GP XDP_TRST#
DY 23 SML0_CLK 53 54
XDP_TDI
55 56
Wistron Corporation
2

XDP_TCLK 57 58 XDP_TMS
59 60 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
63 Taipei Hsien 221, Taiwan, R.O.C.
64
XDP_RST#_R Title
NP2 1
R932 DY0R2J-2-GP
2 PLT_RST# 21,37,70,76
CPU (THERMAL/CLOCK/PM )
PAD-60P-GP Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 9 of 90

5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = CPU CPU1D 4 OF 9

CPU1C 3 OF 9

AUBURNDALE
AUBURNDALE
W8 M_CLK_DDR2 19
M_B_DQ[63..0] SB_CK0
19 M_B_DQ[63..0] SB_CK0# W9 M_CLK_DDR#2 19
AA6 M_CLK_DDR0 18 M_B_DQ0 B5 M3 M_CKE2 19
SA_CK0 M_B_DQ1 SB_DQ0 SB_CKE0
SA_CK0# AA7 M_CLK_DDR#0 18 A5 SB_DQ1
M_A_DQ[63..0] P7 M_B_DQ2 C3
18 M_A_DQ[63..0] SA_CKE0 M_CKE0 18 SB_DQ2
M_A_DQ0 A10 M_B_DQ3 B3 V7 M_CLK_DDR3 19
M_A_DQ1 SA_DQ0 M_B_DQ4 SB_DQ3 SB_CK1
D C10 SA_DQ1 E4 SB_DQ4 SB_CK1# V6 M_CLK_DDR#3 19 D
M_A_DQ2 C7 M_B_DQ5 A6 M2 M_CKE3 19
M_A_DQ3 SA_DQ2 M_B_DQ6 SB_DQ5 SB_CKE1
A7 SA_DQ3 SA_CK1 Y6 M_CLK_DDR1 18 A4 SB_DQ6
M_A_DQ4 B10 Y5 M_CLK_DDR#1 18 M_B_DQ7 C4
M_A_DQ5 SA_DQ4 SA_CK1# M_B_DQ8 SB_DQ7
D10 SA_DQ5 SA_CKE1 P6 M_CKE1 18 D1 SB_DQ8
M_A_DQ6 E10 M_B_DQ9 D2
M_A_DQ7 SA_DQ6 M_B_DQ10 SB_DQ9
A8 SA_DQ7 F2 SB_DQ10 SB_CS0# AB8 M_CS#2 19
M_A_DQ8 D8 M_B_DQ11 F1 AD6 M_CS#3 19
M_A_DQ9 SA_DQ8 M_B_DQ12 SB_DQ11 SB_CS1#
F10 SA_DQ9 SA_CS0# AE2 M_CS#0 18 C2 SB_DQ12
M_A_DQ10 E6 AE8 M_CS#1 18 M_B_DQ13 F5
M_A_DQ11 SA_DQ10 SA_CS1# M_B_DQ14 SB_DQ13
F7 SA_DQ11 F3 SB_DQ14
M_A_DQ12 E9 M_B_DQ15 G4 AC7 M_ODT2 19
M_A_DQ13 SA_DQ12 M_B_DQ16 SB_DQ15 SB_ODT0
B7 H6 AD1 M_ODT3 19
M_A_DQ14 SA_DQ13 M_B_DQ17 SB_DQ16 SB_ODT1
E7 AD8 M_ODT0 18 G2
M_A_DQ15 SA_DQ14 SA_ODT0 M_B_DQ18 SB_DQ17
C6 AF9 M_ODT1 18 J6
M_A_DQ16 SA_DQ15 SA_ODT1 M_B_DQ19 SB_DQ18
H10 J3
M_A_DQ17 SA_DQ16 M_B_DQ20 SB_DQ19
G8 SA_DQ17 G1 SB_DQ20
M_A_DQ18 K7 M_B_DQ21 G5 D4 M_B_DM0
M_A_DQ19 SA_DQ18 M_B_DQ22 SB_DQ21 SB_DM0 M_B_DM1
J8 SA_DQ19 J2 SB_DQ22 SB_DM1 E1
M_A_DQ20 G7 M_B_DQ23 J1 H3 M_B_DM2
M_A_DQ21 SA_DQ20 M_B_DQ24 SB_DQ23 SB_DM2 M_B_DM3
G10 SA_DQ21 J5 SB_DQ24 SB_DM3 K1
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ25 K2 AH1 M_B_DM4
M_A_DQ23 SA_DQ22 SA_DM0 M_A_DM1 M_B_DQ26 SB_DQ25 SB_DM4 M_B_DM5
J10 SA_DQ23 SA_DM1 D7 L3 SB_DQ26 SB_DM5 AL2 M_B_DM[7..0] 19
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ27 M1 AR4 M_B_DM6
M_A_DQ25 SA_DQ24 SA_DM2 M_A_DM3 M_B_DQ28 SB_DQ27 SB_DM6 M_B_DM7
M6 SA_DQ25 SA_DM3 M7 K5 SB_DQ28 SB_DM7 AT8 M_B_DQS#[7..0] 19
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ29 K4
M_A_DQ27 SA_DQ26 SA_DM4 M_A_DM5 M_B_DQ30 SB_DQ29
L9 AM7 M_A_DM[7..0] 18 M4
M_A_DQ28 SA_DQ27 SA_DM5 M_A_DM6 M_B_DQ31 SB_DQ30
L6 AN10 N5 M_B_DQS[7..0] 19
M_A_DQ29 SA_DQ28 SA_DM6 M_A_DM7 M_B_DQ32 SB_DQ31
K8 AN13 M_A_DQS#[7..0] 18 AF3
C M_A_DQ30 SA_DQ29 SA_DM7 M_B_DQ33 SB_DQ32 C
N8 AG1 M_B_A[15..0] 19
M_A_DQ31 SA_DQ30 M_B_DQ34 SB_DQ33 M_B_DQS#0
P9 AJ3 D5
M_A_DQ32 SA_DQ31 M_B_DQ35 SB_DQ34 SB_DQS0# M_B_DQS#1
AH5 SA_DQ32 M_A_DQS[7..0] 18 AK1 SB_DQ35 SB_DQS1# F4
M_A_DQ33 AF5 M_B_DQ36 AG4 J4 M_B_DQS#2
M_A_DQ34 SA_DQ33 M_A_DQS#0 M_B_DQ37 SB_DQ36 SB_DQS2# M_B_DQS#3
AK6 SA_DQ34 SA_DQS0# C9 M_A_A[15..0] 18 AG3 SB_DQ37 SB_DQS3# L4
M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ38 AJ4 AH2 M_B_DQS#4
M_A_DQ36 SA_DQ35 SA_DQS1# M_A_DQS#2 M_B_DQ39 SB_DQ38 SB_DQS4# M_B_DQS#5
AF6 SA_DQ36 SA_DQS2# J9 AH4 SB_DQ39 SB_DQS5# AL4
M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ40 AK3 AR5 M_B_DQS#6
M_A_DQ38 SA_DQ37 SA_DQS3# M_A_DQS#4 M_B_DQ41 SB_DQ40 SB_DQS6# M_B_DQS#7
AJ7 AH7 AK4 AR8
SA_DQ38 SA_DQS4# SB_DQ41 SB_DQS7#
DDR SYSTEM MEMORY A

M_A_DQ39 AJ6 AK9 M_A_DQS#5 M_B_DQ42 AM6

SA_DQ39 SA_DQS5# SB_DQ42

DDR SYSTEM MEMORY - B

M_A_DQ40 AJ10 AP11 M_A_DQS#6 M_B_DQ43 AN2
M_A_DQ41 SA_DQ40 SA_DQS6# M_A_DQS#7 M_B_DQ44 SB_DQ43
AJ9 AT13 AK5
M_A_DQ42 SA_DQ41 SA_DQS7# M_B_DQ45 SB_DQ44
AL10 SA_DQ42 AK2 SB_DQ45
M_A_DQ43 AK12 M_B_DQ46 AM4
M_A_DQ44 SA_DQ43 M_B_DQ47 SB_DQ46
AK8 SA_DQ44 AM3 SB_DQ47
M_A_DQ45 AL7 M_B_DQ48 AP3 C5 M_B_DQS0
M_A_DQ46 SA_DQ45 M_A_DQS0 M_B_DQ49 SB_DQ48 SB_DQS0 M_B_DQS1
AK11 C8 AN5 E3
M_A_DQ47 SA_DQ46 SA_DQS0 M_A_DQS1 M_B_DQ50 SB_DQ49 SB_DQS1 M_B_DQS2
AL8 SA_DQ47 SA_DQS1 F9 AT4 SB_DQ50 SB_DQS2 H4
M_A_DQ48 AN8 H9 M_A_DQS2 M_B_DQ51 AN6 M5 M_B_DQS3
M_A_DQ49 SA_DQ48 SA_DQS2 M_A_DQS3 M_B_DQ52 SB_DQ51 SB_DQS3 M_B_DQS4
AM10 M9 AN4 AG2
M_A_DQ50 SA_DQ49 SA_DQS3 M_A_DQS4 M_B_DQ53 SB_DQ52 SB_DQS4 M_B_DQS5
AR11 AH8 AN3 AL5
M_A_DQ51 SA_DQ50 SA_DQS4 M_A_DQS5 M_B_DQ54 SB_DQ53 SB_DQS5 M_B_DQS6
AL11 SA_DQ51 SA_DQS5 AK10 AT5 SB_DQ54 SB_DQS6 AP5
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ55 AT6 AR7 M_B_DQS7
M_A_DQ53 SA_DQ52 SA_DQS6 M_A_DQS7 M_B_DQ56 SB_DQ55 SB_DQS7
AN9 SA_DQ53 SA_DQS7 AR13 AN7 SB_DQ56
M_A_DQ54 AT11 M_B_DQ57 AP6
M_A_DQ55 SA_DQ54 M_B_DQ58 SB_DQ57
AP12 AP8
M_A_DQ56 SA_DQ55 M_B_DQ59 SB_DQ58
AM12 SA_DQ56 AT9 SB_DQ59
M_A_DQ57 AN12 M_B_DQ60 AT7
M_A_DQ58 SA_DQ57 M_A_A0 M_B_DQ61 SB_DQ60
AM13 SA_DQ58 SA_MA0 Y3 AP9 SB_DQ61
B M_A_DQ59 M_A_A1 M_B_DQ62 B
AT14 W1 AR10
M_A_DQ60 SA_DQ59 SA_MA1 M_A_A2 M_B_DQ63 SB_DQ62 M_B_A0
AT12 AA8 AT10 U5
M_A_DQ61 SA_DQ60 SA_MA2 M_A_A3 SB_DQ63 SB_MA0 M_B_A1
AL13 AA3 V2
M_A_DQ62 SA_DQ61 SA_MA3 M_A_A4 SB_MA1 M_B_A2
AR14 V1 T5
M_A_DQ63 SA_DQ62 SA_MA4 M_A_A5 SB_MA2 M_B_A3
AP14 AA9 V3
SA_DQ63 SA_MA5 M_A_A6 SB_MA3 M_B_A4
SA_MA6 V8 SB_MA4 R1
T1 M_A_A7 19 M_B_BS0 AB1 T8 M_B_A5
SA_MA7 M_A_A8 SB_BS0 SB_MA5 M_B_A6
SA_MA8 Y9 19 M_B_BS1 W5 SB_BS1 SB_MA6 R2
18 M_A_BS0 AC3 U6 M_A_A9 19 M_B_BS2 R7 R6 M_B_A7
SA_BS0 SA_MA9 M_A_A10 SB_BS2 SB_MA7 M_B_A8
18 M_A_BS1 AB2 AD4 R4
SA_BS1 SA_MA10 M_A_A11 SB_MA8 M_B_A9
18 M_A_BS2 U7 SA_BS2 SA_MA11 T2 SB_MA9 R5
U3 M_A_A12 19 M_B_CAS# AC5 AB5 M_B_A10
SA_MA12 M_A_A13 SB_CAS# SB_MA10 M_B_A11
SA_MA13 AG8 19 M_B_RAS# Y7 SB_RAS# SB_MA11 P3
T3 M_A_A14 19 M_B_W E# AC6 R3 M_B_A12
SA_MA14 M_A_A15 SB_WE# SB_MA12 M_B_A13
18 M_A_CAS# AE1 V9 AF7
SA_CAS# SA_MA15 SB_MA13 M_B_A14
18 M_A_RAS# AB3 P5
SA_RAS# SB_MA14 M_B_A15
18 M_A_W E# AE9 SA_WE# SB_MA15 N1

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)
Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 10 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = CPU

CPU1E 5 OF 9

AJ13

AUBURNDALE
RSVD#AJ13
D RSVD#AJ12 AJ12 D

AP25 RSVD#AP25
AL25 RSVD#AL25 RSVD#AH25 AH25
AL24 RSVD#AL24 RSVD#AK26 AK26
AL22 RSVD#AL22
AJ33 RSVD#AJ33 RSVD#AL26 AL26
AG9 RSVD#AG9 RSVD_NCTF#AR2 AR2
M27 RSVD#M27
CFG0 L28 AJ26
TP1116 SA_DIMM_VREF# RSVD#L28 RSVD#AJ26
PCI-Express Configuration Select 1 J17 SA_DIMM_VREF# RSVD#AJ27 AJ27
1

TP1117 1 SB_DIMM_VREF# H17

R1101 SB_DIMM_VREF#
G25 RSVD#G25
3KR2F-GP 1:Single PEG
DY CFG0
G17
E31
RSVD#G17
0:Bifurcation enabled E30
RSVD#E31
2

RSVD#E30

RSVD#AL28 AL28
CFG0 AM30 AL29
CFG0 RSVD#AL29
AM28 CFG1 RSVD#AP30 AP30
AP31 CFG2 RSVD#AP32 AP32
CFG3 AL32 AL27
CFG3 CFG4 CFG3 RSVD#AL27
AL30 CFG4 RSVD#AT31 AT31
CFG3 - PCI-Express Static Lane Reversal AM31 CFG5 RSVD#AT32 AT32
1

AN29 CFG6 RSVD#AP33 AP33

R1102 CFG7 AM32 AR33
3KR2J-2-GP CFG7 RSVD#AR33
DY 1 :Normal Operation AK32 CFG8
CFG3 AK31

RESERVED
C
0 :Lane Numbers Reversed AK28
CFG9
C
2

CFG10
15 -> 0, 14 -> 1, ... AJ28 CFG11
AN30 CFG12 RSVD#AR32 AR32
AN32 CFG13
AJ32 CFG14
AJ29 CFG15 RSVD_TP#E15 E15
AJ30 CFG16 RSVD_TP#F15 F15
AK30 CFG17 KEY A2
H16 RSVD_TP#H16 RSVD#D15 D15
RSVD#C15 C15
RSVD#AJ15 AJ15
RSVD#AH15 AH15
CFG4
CFG4 - Display Port Presence B19 RSVD#B19
1

A19 RSVD#A19
R1103
3KR2F-GP 1:Disabled; No Physical Display Port
DY CFG4
A20
B20
RSVD#A20
attached to Embedded Display Port RSVD#B20
AA5
2

RSVD_TP#AA5
0:Enabled; An external Display Port U9 RSVD#U9 RSVD_TP#AA4 AA4
device is connected to the Embedded T9 RSVD#T9 RSVD_TP#R8 R8
AD3
Display Port AC9
RSVD_TP#AD3
AD2
RSVD#AC9 RSVD_TP#AD2
AB9 RSVD#AB9 RSVD_TP#AA2 AA2
RSVD_TP#AA1 AA1
RSVD_TP#R9 R9
RSVD_TP#AG7 AG7
RSVD_TP#AE3 AE3

CFG7 V4
RSVD_TP#V4
CFG7(Reserved) - Temporarily used for early RSVD_TP#V5 V5
1

N2
R1104 Clarksfield samples. RSVD_TP#N2
B
3KR2F-GP
J29 RSVD#J29 RSVD_TP#AD5 AD5 VSS (AP34) can be left NC is B
DY CFG7 Clarksfield (only for early samples pre-ES1) -
J28 RSVD#J28 RSVD_TP#AD7 AD7
W3 CRB implementation; EDS/DG
RSVD_TP#W3
Connect to GND with 3.01K Ohm/5% resistor. W2 recommendation to GND.
2

RSVD_TP#W2
RSVD_TP#N3 N3
RSVD_TP#AE5 AE5
Note: Only temporary for early CFD sample RSVD_TP#AD9 AD9
(rPGA/BGA) [For details please refer to the
WW33 MoW and sighting report]. VSS AP34
For a common M/B design (for AUB and CFD),
the pull-down resistor shouble be used. Does
not impact AUB functionality.

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

CPU (RESERVED) Rev

DJ1 Calpella UMA X01

Date: Friday, April 16, 2010 Sheet 11 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = CPU CPU1F 6 OF 9

AUBURNDALE
+VCC_CORE
+1.05V_VTT
PROCESSOR CORE POWER
AG35 AH14
VCC VTT0
AG34 AH12
VCC VTT0

1
AG33 AH11 C1216 C1201 C1202 C1217 C1218 C1203 C1219 C1204 C1205
+VCC_CORE 48A AG32
VCC
VCC
VTT0
VTT0 AH10
DY DY DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP
AG31 J14

2
VCC VTT0
D AG30 VCC VTT0 J13 D
AG29 VCC VTT0 H14
C1206 C1207 C1208 C1209 C1220 C1210 AG28 H12
VCC VTT0
1

1
AG27 G14
VCC VTT0
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
AG26 G13
VCC VTT0
AF35 G12
DY DY DY
2

2
VCC VTT0
AF34 G11
VCC VTT0
AF33 VCC VTT0 F14
AF32 VCC VTT0 F13
AF31 F12 +1.05V_VTT
VCC VTT0
AF30 VCC VTT0 F11
AF29
VCC VTT0
E14
C1222
The decoupling capacitors, filter
AF28 VCC VTT0 E12
recommendations and sense resistors on the

1
AF27 D14 C1211 C1221
VCC VTT0

SC10U6D3V5MX-3GP
AF26 D13 CPU/PCH Rails are specific to the CRB
VCC VTT0 DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
1.1V RAIL POWER
C1212 C1213 C1214 C1215 C1223 C1224 AD35 D12

2
VCC VTT0
1

1 AD34 VCC VTT0 D11 Implementation. Customers need to follow the

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
AD33 C14 recommendations in the Calpella Platform
VCC VTT0
AD32 C13
DY DY
2

VCC VTT0 Design Guide.

AD31 C12
VCC VTT0
AD30 C11
VCC VTT0
AD29 B14
VCC VTT0
AD28 VCC VTT0 B12
AD27 VCC VTT0 A14
AD26 A13
VCC VTT0
AC35 VCC VTT0 A12
AC34 A11
VCC VTT0
AC33
C1225 C1226 C1227 C1229 C1230 C1231 C1232 VCC +1.05V_VTT
AC32 VCC
1

AC31 VCC
SC10U6D3V5KX-1GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

AC30 AF10
DY AC29
VCC VTT0
AE10
2

VCC VTT0 C1234

AC28 VCC VTT0 AC10

1
CPU CORE SUPPLY
C AC27 AB10 C1233 C
VCC VTT0

SC10U6D3V5MX-3GP
AC26 Y10
VCC VTT0

SC10U6D3V5KX-1GP
AA35 W10
DY

2
VCC VTT0
AA34 VCC VTT0 U10
AA33 T10
VCC VTT0
AA32 VCC VTT0 J12
AA31 J11
VCC VTT0
AA30 VCC VTT0 J16
C1235 C1236 C1237 C1238 C1240 C1241 C1242 AA29 J15
VCC VTT0
1

AA28 VCC
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

AA27
VCC
AA26
DY DY
2

VCC
Y35
Y34
VCC Please note that the VTT Rail
VCC
Y33
Y32
VCC Values are Auburndale
VCC
C1243 Y31
VCC VTT=1.05V; Clarksfield
1

Y30
VCC
VTT=1.1V
SC10U6D3V5KX-1GP

Y29 VCC
Y28
2

VCC
2010/04/19 Y27
VCC
Y26
X01 VCC
V35 AN33 PSI# 47
VCC PSI#
V34
VCC
V33 H_VID[6..0] 47
VCC H_VID0
V32 VCC VID0 AK35
V31 AK33 H_VID1
VCC VID1 H_VID2
V30 POWER AK34
VCC VID2 H_VID3
V29 AL35
VCC VID3
V28
VCC CPU VIDS VID4
AL33 H_VID4
V27 AM33 H_VID5
VCC VID5 H_VID6
V26 VCC VID6 AM35
U35 VCC PROC_DPRSLPVR AM34 PM_DPRSLPVR 47
B U34 B
VCC
U33 VCC
U32
VCC H_VTTVID1 TP1201TPAD14-GP
U31 G15 1
VCC VTT_SELECT
U30
VCC
U29
VCC H_VTTVID1 = Low, 1.1V
U28
VCC H_VTTVID1 = High, 1.05V
U27 VCC
U26 +VCC_CORE
VCC
R35
VCC
R34 VCC

1
R33
VCC R1201
R32 VCC ISENSE AN35 IMVP_IMON 47
R31 100R2F-L1-GP-U
VCC
R30
VCC
R29

2
VCC
SENSE LINES

R28 AJ34 VCC_SENSE 47

VCC VCC_SENSE
R27 AJ35 VSS_SENSE 47
VCC VSS_SENSE
R26
VCC

1
P35 VCC
P34 B15 VTT_SENSE 49 R1204
VCC VTT_SENSE TP_VSS_SENSE_VTT 1 100R2F-L1-GP-U
P33 VCC VSS_SENSE_VTT A15
P32 TP1202TPAD14-GP
VCC
P31

2
VCC
P30 VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

CPU (VCC_CORE) Rev
DJ1 Calpella UMA X01
5 forum.hocvienit.vn 4 3 2
Date: Thursday, April 22, 2010 Sheet
1
12 of 90
 5 4 3 2 1

SSID = CPU +1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN

1
DYC1376 DYC1377 DYC1378 DYC1379
SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP

2
+1.5V_SUS +1.5V_SUS +1.5V_SUS +1.5V_SUS
+CPU_GFX_CORE

22A CPU1G 7 OF 9
425302_425302_Calpella_S3PowerReduction_WhitePape
AT21

AUBURNDALE
VAXG1
D
C1325 C1328 C1323 C1326 C1324 C1309 C1312
AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE 53 Revision 0.7 D

SENSE
LINES
AT18 AT22

1
VAXG3 VSSAXG_SENSE VSS_AXG_SENSE 53
AT16 VAXG4

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
2010/04/19 AR21 VAXG5
AR19

2
X01 VAXG6

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
AR18 VAXG7

SC10U6D3V5MX-3GP
AR16 VAXG8 GFX_VID0 AM22 GFX_VID0 53
AP21 VAXG9 GFX_VID1 AP22 GFX_VID1 53

GRAPHICS VIDs
AP19 VAXG10 GFX_VID2 AN22 GFX_VID2 53
AP18 AP23
VAXG11 GFX_VID3 GFX_VID3 53
AP16 VAXG12 GFX_VID4 AM23 GFX_VID4 53
AN21 VAXG13 GFX_VID5 AP24 GFX_VID5 53

GRAPHICS
AN19 AN24 GFX_VID6 53
VAXG14 GFX_VID6
AN18
VAXG15 R1305
AN16 2 1 4K7R2J-2-GP
VAXG16
AM21 AR25 GFX_VR_EN 53
VAXG17 GFX_VR_EN
AM19 VAXG18 GFX_DPRSLPVR AT25 GFX_DPRSLPVR 53
AM18 AM24 GFX_IMON_C 1 DY 2 GFX_IMON 53
VAXG19 GFX_IMON R1304 0R2J-2-GP
AM16 VAXG20
AL21
VAXG21
AL19 VAXG22 +1.5V_RUN
Please note that the VTT Rail AL18
AL16
VAXG23
3A
VAXG24
Values are: Auburndale VTT=1.05V AK21
AK19
VAXG25 VDDQ
AJ1
AF1
VAXG26 VDDQ

1
C1301 C1302 C1303 C1304 C1305 C1306 C1307

- 1.5V RAILS
Clarksfield VTT=1.1V AK18
VAXG27 VDDQ
AE7
DY

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
AK16 AE4 TC1301
VAXG28 VDDQ SE330U2D5VDM-2GP
AJ21 AC1

2
VAXG29 VDDQ
AJ19 AB7
C VAXG30 VDDQ C
AJ18 AB4
VAXG31 VDDQ
AJ16 Y1
VAXG32 VDDQ
AH21 VAXG33 VDDQ W7
AH19 W4
VAXG34 VDDQ
AH18 VAXG35 VDDQ U1
AH16 VAXG36 VDDQ T7
VDDQ T4

POWER
VDDQ P1
N7
+1.05V_VTT VDDQ
VDDQ N4

DDR3
VDDQ L1
J24 H1
VTT1 VDDQ

FDI
J23 VTT1
C1308 H25
VTT1
1

SC10U6D3V5KX-1GP

P10
2

VTT1 +1.05V_VTT
VTT1 N10
L10
VTT1
K10
VTT1 C1310 C1311

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
+1.05V_VTT
18A

2
1.1V
J22
VTT1
K26 J20
VTT1 VTT1
J27 VTT1 VTT1 J18
+1.05V_VTT

PEG & DMI

C1313 C1315 J26 H21
1

C1314 VTT1 VTT1

J25 VTT1 VTT1 H20
B B
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

H27 H19
VTT1 VTT1 C1316
G28
SC10U10V5KX-2GP

DY
2

VTT1

1
SC10U6D3V5KX-1GP
G27
VTT1 C1317
G26
F26
VTT1 DY SC10U6D3V5MX-3GP

2
VTT1
E26 VTT1 VTT1 L26

1.8V
E25 L27
VTT1 VTT1
VTT1 M26 1.35A +1.8V_RUN

1
C1318 C1319 C1320 C1321

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC4D7U6D3V5KX-3GP
C1322

SC2D2U6D3V3KX-GP
SC10U6D3V5MX-3GP

2
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

CPU (VCC_GFXCORE) Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 13 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = CPU
CPU1H 8 OF 9 CPU1I 9 OF 9

AT20 AE34
VSS VSS
AT17 AE33

AUBURNDALE

AUBURNDALE
VSS VSS
AR31 AE32 K27
VSS VSS VSS
AR28 VSS VSS AE31 K9 VSS
AR26 VSS VSS AE30 K6 VSS
AR24 VSS VSS AE29 K3 VSS
D AR23 VSS VSS AE28 J32 VSS D
AR20 VSS VSS AE27 J30 VSS
AR17 VSS VSS AE26 J21 VSS
AR15 VSS VSS AE6 J19 VSS
AR12 VSS VSS AD10 H35 VSS
AR9 VSS VSS AC8 H32 VSS
AR6 VSS VSS AC4 H28 VSS
AR3 VSS VSS AC2 H26 VSS
AP20 VSS VSS AB35 H24 VSS
AP17 AB34 H22
VSS VSS VSS
AP13 VSS VSS AB33 H18 VSS
AP10 VSS VSS AB32 H15 VSS
AP7 AB31 H13
VSS VSS VSS
AP4 AB30 H11
VSS VSS VSS
AP2 AB29 H8
VSS VSS VSS
AN34 AB28 H5
VSS VSS VSS
AN31 VSS VSS AB27 H2 VSS
AN23 AB26 G34
VSS VSS VSS
AN20 VSS VSS AB6 G31 VSS
AN17 AA10 G20
VSS VSS VSS
AM29 VSS VSS Y8 G9 VSS
AM27 Y4 G6
VSS VSS VSS
AM25 VSS VSS Y2 G3 VSS
AM20 W35 F30
VSS VSS VSS
AM17 VSS VSS W34 F27 VSS
AM14 W33 F25
VSS VSS VSS
AM11 W32 F22
VSS VSS VSS
AM8 W31 F19
VSS VSS VSS
AM5 W30 F16
C VSS VSS VSS C
AM2 W29 E35
VSS VSS VSS
AL34 W28 E32
AL31
AL23
VSS
VSS
VSS
VSS VSS
VSS
VSS
W27
W26
E29
E24
VSS
VSS
VSS
VSS
AL20 VSS VSS W6 E21 VSS
AL17 VSS VSS V10 E18 VSS
AL12 VSS VSS U8 E13 VSS
AL9 VSS VSS U4 E11 VSS
AL6 U2 E8
VSS VSS VSS
AL3 VSS VSS T35 E5 VSS
AK29 VSS VSS T34 E2 VSS VSS_NCTF#AR34 AR34
AK27 T33 D33 B34
VSS VSS VSS VSS_NCTF#B34
AK25 VSS VSS T32 D30 VSS VSS_NCTF#B2 B2

AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35
AK20 T31 D26

A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35,
VSS VSS VSS
AK17 VSS VSS T30 D9 VSS
AJ31 T29 D6 B1 TP_MCP_VSS_NCTF1 1 TP1403
VSS VSS VSS VSS_NCTF#B1 TP_MCP_VSS_NCTF2 TP1404
AJ23 T28 D3 A35 1
VSS VSS VSS VSS_NCTF#A35 TP_MCP_VSS_NCTF3 TP1406
AJ20 VSS VSS T27 C34 VSS VSS_NCTF#AT1 AT1 1
AJ17 T26 C32 AT35 TP_MCP_VSS_NCTF4 1 TP1405
VSS VSS VSS VSS_NCTF#AT35
AJ14 T6 C29 AT33
VSS VSS VSS RSVD_NCTF#AT33
AJ11 R10 C28 AT34
VSS VSS VSS RSVD_NCTF#AT34
AJ8 VSS VSS P8 C24 VSS RSVD_NCTF#AP35 AP35
AJ5 VSS VSS P4 C22 VSS RSVD_NCTF#AR35 AR35
AJ2 VSS VSS P2 C20 VSS RSVD_NCTF#AT3 AT3
AH35 N35 C19 AR1
VSS VSS VSS RSVD_NCTF#AR1
AH34 N34 C16 AP1
VSS VSS VSS RSVD_NCTF#AP1
AH33 VSS VSS N33 B31 VSS RSVD_NCTF#AT2 AT2
AH32 VSS VSS N32 B25 VSS RSVD_NCTF#C1 C1
AH31 N31 B21 A3

NCTF TEST PIN:

B VSS VSS VSS RSVD_NCTF#A3 B
AH30 N30 B18 C35
VSS VSS VSS RSVD_NCTF#C35
AH29 N29 B17 B35
VSS VSS VSS RSVD_NCTF#B35
AH28 N28 B13 A34
VSS VSS VSS RSVD_NCTF#A34
AH27 N27 B11 A33
VSS VSS VSS RSVD_NCTF#A33
AH26 N26 B8
VSS VSS VSS
AH20 VSS VSS N6 B6 VSS
AH17 VSS VSS M10 B4 VSS
AH13 VSS VSS L35 A29 VSS
AH9 VSS VSS L32 A27 VSS
AH6 L29 A23
VSS VSS VSS
AH3 VSS VSS L8 A9 VSS
AG10 VSS VSS L5
AF8 VSS VSS L2
AF4 K34
VSS VSS
AF2 K33
VSS VSS
AE35 K30
VSS VSS

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)
Size Document Number Rev
DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 14 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 15 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 16 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 17 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = MEMORY M_A_DM[7..0] 10

M_A_DQS#[7..0] 10

M_A_DQS[7..0] 10
DM1
M_A_A[15..0] 10
M_A_A0 98 NP1 Note:
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2 If SA0 DIM0 = 0, SA1_DIM0 = 0
96
M_A_A3 A2 SA0_DIM0
95 110 M_A_RAS# 10 SO-DIMMA SPD Address is 0xA0
M_A_A4 A3 RAS#
92 113 M_A_WE# 10
A4 WE#
M_A_A5 91
A5 CAS#
115 M_A_CAS# 10 SA1_DIM0 SO-DIMMA TS Address is 0x30
M_A_A6 90
M_A_A7 A6
86 114 M_CS#0 10
A7 CS0#

3
4
M_A_A8 89
A8 CS1#
121 M_CS#1 10 If SA0 DIM0 = 1, SA1_DIM0 = 0
D M_A_A9 85 RN1801 D
M_A_A10 107
A9
73 SRN10KJ-5-GP
SO-DIMMA SPD Address is 0xA2
A10/AP CKE0 M_CKE0 10
M_A_A11 84 74 M_CKE1 10 SO-DIMMA TS Address is 0x32
M_A_A12 A11 CKE1
83
M_A_A13 A12
119 101 M_CLK_DDR0 10

2
1
M_A_A14 A13 CK0
80 103 M_CLK_DDR#0 10
M_A_A15 A14 CK0#
78
A15
10 M_A_BS2 79 102 M_CLK_DDR1 10
A16/BA2 CK1
104 M_CLK_DDR#1 10
CK1#
109
10 M_A_BS0 BA0 M_A_DM0
108 11
10 M_A_BS1 BA1 DM0 M_A_DM1
10 M_A_DQ[63..0] 28
M_A_DQ0 DM1 M_A_DM2
5 46
M_A_DQ1 DQ0 DM2 M_A_DM3
7 63
M_A_DQ2 DQ1 DM3 M_A_DM4
15 136
M_A_DQ3 DQ2 DM4 M_A_DM5
17 153
M_A_DQ4 DQ3 DM5 M_A_DM6
4 170
M_A_DQ5 DQ4 DM6 M_A_DM7
6 187
M_A_DQ6 DQ5 DM7
16
M_A_DQ7 DQ6 SODIMM0_1_SMB_DATA_R R1804
18 200 1 2 0R0402-PAD PCH_SMBDATA 7,19,23,76
M_A_DQ8 DQ7 SDA SODIMM0_1_SMB_CLK_R R1805
21 202 1 2 0R0402-PAD PCH_SMBCLK 7,19,23,76
M_A_DQ9 DQ8 SCL
23
M_A_DQ10 DQ9 +3.3V_RUN
33 198 PM_EXTTS#0 9
M_A_DQ11 DQ10 EVENT#
35
M_A_DQ12 DQ11
22 199
M_A_DQ13 DQ12 VDDSPD
24
M_A_DQ14 DQ13 SA0_DIM0
34 197
DQ14 SA0

1
M_A_DQ15 36 201 SA1_DIM0
M_A_DQ16 DQ15 SA1 C1801 C1802
39
M_A_DQ17 41
DQ16
77 SCD1U10V2KX-5GP DY SC2D2U10V3KX-1GP

2
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 +1.5V_SUS
53 125
M_A_DQ20 DQ19 NC#/TEST
40
M_A_DQ21 DQ20
42 75
M_A_DQ22 DQ21 VDD1
50 76
M_A_DQ23 DQ22 VDD2
52 81
M_A_DQ24 DQ23 VDD3
M_A_DQ25
57
DQ24 VDD4
82 SODIMM A DECOUPLING
59 87
M_A_DQ26 DQ25 VDD5 +1.5V_SUS
67 88
M_A_DQ27 DQ26 VDD6
69 93
M_A_DQ28 DQ27 VDD7
56 94
M_A_DQ29 DQ28 VDD8
C 58 99 C
M_A_DQ30 DQ29 VDD9
68 100
M_A_DQ31 DQ30 VDD10
70 105
M_A_DQ32 DQ31 VDD11 TC1801 C1803 C1804 C1805 C1806 C1807 C1808 C1809 C1810
129 106
DQ32 VDD12

1
SE330U2D5VDM-2GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
M_A_DQ33 131 111
M_A_DQ34 DQ33 VDD13
M_A_DQ35
141
DQ34 VDD14
112 DY DY DY DY DY DY
143 117

2
+V_DDR_REF M_A_DQ36 DQ35 VDD15
130 118
M_A_DQ37 DQ36 VDD16
132 123
M_A_DQ38 DQ37 VDD17
140 124
M_A_DQ39 DQ38 VDD18
142
DQ39
1

C1818 M_A_DQ40 147 2

C1817 SC2D2U10V3KX-1GP C1826 M_A_DQ41 DQ40 VSS
149 3
SCD1U10V2KX-5GP DY SCD1U10V2KX-5GP M_A_DQ42 157
DQ41 VSS
8
2

M_A_DQ43 DQ42 VSS

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
159 9
M_A_DQ44 DQ43 VSS
146 13
DQ44 VSS

1
C1813

C1814

C1815

C1816
M_A_DQ45 148 14 Layout Note:
M_A_DQ46 DQ45 VSS
158 19
M_A_DQ47 DQ46 VSS Place these Caps near
160 20

2
M_A_DQ48 DQ47 VSS
163 25 SO-DIMMA.
M_A_DQ49 DQ48 VSS
165 26
M_A_DQ50 DQ49 VSS
175 31
M_A_DQ51 DQ50 VSS
177 32
M_A_DQ52 DQ51 VSS
164 37
M_A_DQ53 DQ52 VSS
166 38
M_A_DQ54 DQ53 VSS
174 43
M_A_DQ55 DQ54 VSS
176 44
M_A_DQ56 DQ55 VSS
181 48
M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
191 54
M_A_DQ59 DQ58 VSS
193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ61 DQ60 VSS
182 61
M_A_DQ62 DQ61 VSS
192 65
M_A_DQ63 DQ62 VSS
194 66
DQ63 VSS
71
M_A_DQS#0 VSS
10 72
M_A_DQS#1 DQS0# VSS
27 127
M_A_DQS#2 DQS1# VSS
45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
135 134
B M_A_DQS#5 DQS4# VSS B
152 138
M_A_DQS#6 DQS5# VSS
169 139
M_A_DQS#7 DQS6# VSS
186 144
DQS7# VSS
145
M_A_DQS0 VSS
12 150
M_A_DQS1 DQS0 VSS
29 151
M_A_DQS2 DQS1 VSS
47 155
M_A_DQS3 DQS2 VSS
64 156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
+0.75V_DDR_VTT Place these caps 188
DQS7 VSS
168
172
close to VTT1 and VSS
116 173
10 M_ODT0 ODT0 VSS
VTT2. 120 178
10 M_ODT1 ODT1 VSS
179
VSS
+V_DDR_REF 126 184
VREF_CA VSS
1 185
VREF_DQ VSS
C1820

C1821

C1822

C1823
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

189
VSS
1

30 190
9,19 DDR3_DRAMRST# RESET# VSS
DY DY VSS
195
196
2

VSS
+0.75V_DDR_VTT 203 205
VTT1 VSS
204 206
VTT2 VSS

H =5.2mm DDR3-204P-46-GP

62.10017.P11

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1
Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 18 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = MEMORY DM2

M_B_A0 98 NP1 M_B_DM[7..0] 10

M_B_A1 A0 NP1 +3.3V_RUN
97 NP2
M_B_A2 A1 NP2
96 M_B_DQS#[7..0] 10
M_B_A3 A2 SA0_DIM1
95 110 M_B_RAS# 10
A3 RAS#

3
4
M_B_A4 92 113 M_B_WE# 10
M_B_A5 A4 WE# RN1901
91 115 M_B_CAS# 10 M_B_DQS[7..0] 10
M_B_A6 A5 CAS#
90 SRN10KJ-5-GP
M_B_A7 A6
86 114 M_CS#2 10 M_B_A[15..0] 10
M_B_A8 A7 CS0#
89 121 M_CS#3 10
M_B_A9 A8 CS1#
85

2
1
M_B_A10 A9
107 73 M_CKE2 10
M_B_A11 A10/AP CKE0
84 74 M_CKE3 10
M_B_A12 A11 CKE1 SA1_DIM1
83
M_B_A13 A12
119 101 M_CLK_DDR2 10
M_B_A14 A13 CK0
80 103 M_CLK_DDR#2 10
M_B_A15 A14 CK0#
78
A15
D 79 102 M_CLK_DDR3 10 D
10 M_B_BS2 A16/BA2 CK1
104 M_CLK_DDR#3 10
CK1#
10 M_B_BS0 109
BA0 M_B_DM0
108 11
10 M_B_BS1 BA1 DM0 M_B_DM1
10 M_B_DQ[63..0] 28
M_B_DQ0 DM1 M_B_DM2
5 46
M_B_DQ1 DQ0 DM2 M_B_DM3
7 63
M_B_DQ2 DQ1 DM3 M_B_DM4
15 136
M_B_DQ3 DQ2 DM4 M_B_DM5
17 153
M_B_DQ4 DQ3 DM5 M_B_DM6
4 170
M_B_DQ5 DQ4 DM6 M_B_DM7
6 187
M_B_DQ6 DQ5 DM7
16
M_B_DQ7 DQ6 SODIMM1_1_SMB_DATA_R R1904
18 200 1 2 0R0402-PAD PCH_SMBDATA 7,18,23,76
M_B_DQ8 DQ7 SDA SODIMM1_1_SMB_CLK_R R1905
21 202 1 2 0R0402-PAD PCH_SMBCLK 7,18,23,76
M_B_DQ9 DQ8 SCL
23
M_B_DQ10 DQ9 +3.3V_RUN
33 198 PM_EXTTS#1 9
M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11
22 199
M_B_DQ13 DQ12 VDDSPD
24
DQ13

1
M_B_DQ14 34 197 SA0_DIM1
M_B_DQ15 DQ14 SA0 SA1_DIM1 C1901 C1902
M_B_DQ16
36
DQ15 SA1
201
SCD1U10V2KX-5GP
DY SC2D2U10V3KX-1GP
39

2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1
51 122
M_B_DQ19 DQ18 NC#2 +1.5V_SUS
53 125
M_B_DQ20 DQ19 NC#/TEST
40
M_B_DQ21 DQ20
42 75
M_B_DQ22 DQ21 VDD1
50 76
M_B_DQ23 DQ22 VDD2
52 81
M_B_DQ24 DQ23 VDD3
57 82
M_B_DQ25 DQ24 VDD4
59 87
M_B_DQ26 DQ25 VDD5
67 88
M_B_DQ27 DQ26 VDD6
69 93
M_B_DQ28 DQ27 VDD7
56 94
+V_DDR_REF M_B_DQ29 DQ28 VDD8
58 99
M_B_DQ30 DQ29 VDD9
68 100
M_B_DQ31 DQ30 VDD10
70 105
M_B_DQ32 DQ31 VDD11
129 106
DQ32 VDD12
1

C1924 M_B_DQ33 131 111

C1923 SC2D2U10V3KX-1GP C1925 M_B_DQ34 DQ33 VDD13
141 112
SCD1U10V2KX-5GP SCD1U10V2KX-5GP M_B_DQ35 DQ34 VDD14
143 117
DY
2

M_B_DQ36 DQ35 VDD15

C 130 118 C
M_B_DQ37 DQ36 VDD16
132 123
M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18
142
M_B_DQ40 DQ39
147 2
M_B_DQ41 DQ40 VSS
M_B_DQ42
149
DQ41 VSS
3 SODIMM B DECOUPLING
157 8
M_B_DQ43 DQ42 VSS +1.5V_SUS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
M_B_DQ46 DQ45 VSS
158 19
M_B_DQ47 DQ46 VSS
160 20
M_B_DQ48 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS C1905 C1906 C1907 C1908 C1909 C1910 C1911 C1912
165 26
DQ49 VSS

1
SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
M_B_DQ50 175 31
M_B_DQ51 DQ50 VSS
M_B_DQ52
177
DQ51 VSS
32
DY DY DY
164 37

2
M_B_DQ53 DQ52 VSS
166 38
M_B_DQ54 DQ53 VSS
174 43
M_B_DQ55 DQ54 VSS
176 44
M_B_DQ56 DQ55 VSS
181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
180 60
M_B_DQ61 DQ60 VSS
182 61
DQ61 VSS

1
C1915

C1916

C1917

C1918
M_B_DQ62 192 65 Layout Note:
M_B_DQ63 DQ62 VSS
194 66
DQ63 VSS Place these Caps near
71

2
M_B_DQS#0 VSS
10 72 SO-DIMMB.
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
M_B_DQS2 DQS1 VSS
47 155
B M_B_DQS3 DQS2 VSS B
64 156
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
10 M_ODT2 ODT0 VSS
120 178
10 M_ODT3 ODT1 VSS
179
VSS
+V_DDR_REF 126 184
VREF_CA VSS
1 185
VREF_DQ VSS
189
+0.75V_DDR_VTT VSS
30 190
9,18 DDR3_DRAMRST# RESET# VSS
195
VSS
196
VSS
203 205
VTT1 VSS
204 206
VTT2 VSS
Place these caps
C1919

C1920

C1921

C1922
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

H = 9.2mmDDR3-204P-43-GP
1

close to VTT1 and

VTT2. DY DY
62.10017.N71
2

Note:
SO-DIMMB SPD Address is 0xA4 SO-DIMMB is placed farther from
SO-DIMMB TS Address is 0x34 the Processor than SO-DIMMA

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM2
Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 19 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = PCH

D D

U2001D 4 OF 10
37 PCH_VGA_BLEN T48 L_BKLTEN SDVO_TVCLKINN BJ46
54 PCH_LCDVDD_EN T47 L_VDD_EN SDVO_TVCLKINP BG46

54 PCH_LBKLT_CTL Y48 BJ48

L_BKLTCTL SDVO_STALLN
SDVO_STALLP BG48
54 LDDC_CLK_PCH LDDC_CLK_PCH AB48
LDDC_DATA_PCH L_DDC_CLK
54 LDDC_DATA_PCH Y45 BF45
L_DDC_DATA SDVO_INTN
BH45
LCTRL_CLK SDVO_INTP
AB46
LCTRL_DATA L_CTRL_CLK
V48
L_CTRL_DATA
LIBG AP39 T51
TPAD14-GP TP2001 LVD_IBG SDVO_CTRLCLK
1LVDS_VBG AP41 T53

1
LVD_VBG SDVO_CTRLDATA
R2003 R2002 AT43 LVD_VREFH
1 PCH_LCDVDD_EN Place near PCH 2K37R2F-GP
2
DY AT42
LVD_VREFL DDPB_AUXN
BG44
BJ44
100KR2J-1-GP DDPB_AUXP
AU38

2
DDPB_HPD

LVDS
54 PCH_LVDSA_TXC# AV53 LVDSA_CLK#
54 PCH_LVDSA_TXC AV51 BD42
LVDSA_CLK DDPB_0N
BC42
DDPB_0P
54 PCH_LVDSA_TX0# BB47 BJ42
LVDSA_DATA#0 DDPB_1N
BA52 BG42

Digital Display Interface

54 PCH_LVDSA_TX1# LVDSA_DATA#1 DDPB_1P
C AY48 BB40 C
Impedance:85 ohm 54 PCH_LVDSA_TX2#
AV47
LVDSA_DATA#2 DDPB_2N
BA40
+3.3V_RUN LVDSA_DATA#3 DDPB_2P
DDPB_3N AW38
54 PCH_LVDSA_TX0 BB48 BA38
LVDSA_DATA0 DDPB_3P
54 PCH_LVDSA_TX1 BA50 LVDSA_DATA1
54 PCH_LVDSA_TX2 AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
AB49
4
3
2
1

DDPC_CTRLDATA
RN2002 AP48 LVDSB_CLK#
SRN2K2J-4-GP AP47 LVDSB_CLK DDPC_AUXN BE44
BD44
DDPC_AUXP
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49
5
6
7
8

LCTRL_DATA LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
LDDC_CLK_PCH AT53 BD40
LCTRL_CLK LVDSB_DATA#3 DDPC_0P
BF41
LDDC_DATA_PCH DDPC_1N
AY51 LVDSB_DATA0 DDPC_1P BH41
AT48 BD38
LVDSB_DATA1 DDPC_2N
AU50 BC38
LVDSB_DATA2 DDPC_2P
AT51 BB36
LVDSB_DATA3 DDPC_3N
DDPC_3P BA36
Close to ball <600mil
55 PCH_CRT_BLUE AA52 U50
CRT_BLUE DDPD_CTRLCLK
55 PCH_CRT_GREEN AB53 U52
CRT_GREEN DDPD_CTRLDATA
55 PCH_CRT_RED AD53 CRT_RED
Need Level Shift BC46
B DDPD_AUXN B
V51 BD46
5
6
7
8

55 PCH_CRT_DDCCLK CRT_DDC_CLK DDPD_AUXP

V53 AT38
RN2005 55 PCH_CRT_DDCDATA CRT_DDC_DATA DDPD_HPD
SRN150F-1-GP BJ40
DDPD_0N
55 PCH_CRT_HSYNC Y53 BG40
CRT_HSYNC DDPD_0P
CRT SMBUS 55 PCH_CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
BG38
4
3
2
1

DDPD_1P
Close PCH 1
2.5V Tolerance
2 CRT_IREF AD48
CRT DDPD_2N BF37
BH37
R2001 1KR2J-1-GP DAC_IREF DDPD_2P
AB51 BE36
CRT_IRTN DDPD_3N
DDPD_3P BD36
+3.3V_RUN
IBEXPEAK-M-GP-NF
1
2

RN2003
SRN2K2J-1-GP
4
3

PCH_CRT_DDCCLK
PCH_CRT_DDCDATA

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (LVDS/CRT/DDI)
Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 20 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

RN2101
PCI_DEVSEL#
PCI_IRDY#
1
2
10
9 PCI_REQ2#
+3.3V_RUN SSID = PCH H40
U2001E
AD0
5 OF 10
NV_CE#0 AY9
PCI_SERR# 3 8 INT_PIRQD# N34 BD1
INT_PIRQC# PCI_STOP# AD1 NV_CE#1
4 7 C44 AD2 NV_CE#2 AP15
+3.3V_RUN 5 6 INT_PIRQA# A38 BD8
AD3 NV_CE#3
C36 AD4
SRN8K2J-2-GP-U J34 AV9
AD5 NV_DQS0
A40 AD6 NV_DQS1 BG8
D45
AD7
E36 AD8 NV_DQ0/NV_IO0 AP7
RN2102 H48 AP6
PCI_PERR# AD9 NV_DQ1/NV_IO1
1 10 +3.3V_RUN E40 AD10 NV_DQ2/NV_IO2 AT6
D PCI_REQ0# 2 9 INT_PIRQB# C40 AT9 D
PCI_REQ3# PCI_PLOCK# AD11 NV_DQ3/NV_IO3
3 8 M48 AD12 NV_DQ4/NV_IO4 BB1
PCI_FRAME# 4 7 PCI_REQ1# M45 AV6
PCI_TRDY# AD13 NV_DQ5/NV_IO5
+3.3V_RUN 5 6 F53 AD14 NV_DQ6/NV_IO6 BB3
M40 AD15 NV_DQ7/NV_IO7 BA4
SRN8K2J-2-GP-U

NVRAM
M43 AD16 NV_DQ8/NV_IO8 BE4
J36 AD17 NV_DQ9/NV_IO9 BB6
+3.3V_RUN K48 BD6
+3.3V_RUN AD18 NV_DQ10/NV_IO10
F40 AD19 NV_DQ11/NV_IO11 BB7
RN2103 C42 BC8 Danbury Technology:
INT_PIRQF# AD20 NV_DQ12/NV_IO12
1 8 K46 AD21 NV_DQ13/NV_IO13 BJ8 Disabled when Low.
2 7 INT_PIRQH# U2101 M51 BJ6 Enable when High.
INT_PIRQG# AD22 NV_DQ14/NV_IO14
3 6 1 J52 BG6 TP2100
INT_PIRQE# B AD23 NV_DQ15/NV_IO15
4 5 5 K51 TP2101
VCC PCI_PLTRST# AD24 NV_ALE
2 L34 BD3 1
SRN10KJ-7GP 9,37,70,76 PLT_RST# 4
DY A
F42
AD25 NV_ALE
AY6 NV_CLE 1
Y AD26 NV_CLE
GND 3 J40 AD27 TP2102
G46
74LVC1G08GW -1-GP AD28 NV_RCOMP
F44 AD29 NV_RCOMP AU2 1
M47
AD30

PCI
1 2 H36 AD31 NV_RB# AV7
R2104 0R0402-PAD

1
J50 C/BE0# NV_WR#0_RE# AY8
C2101
DY SC220P50V2KX-3GP
G42
H47
C/BE1# NV_WR#1_RE#
AY5

2
C/BE2#
G34
C/BE3# NV_WE#_CK0
AV11 USB
BF5
INT_PIRQA# NV_WE#_CK1
G38
PIRQA# Pair Device
INT_PIRQB# H51
C INT_PIRQC# PIRQB# C
B37
PIRQC# USBP0N
H18 USB_PN0 76 0 USB0 (I/O Board)
INT_PIRQD# A44 J18 USB_PP0 76
PIRQD# USBP0P
USBP1N A18 1 X
PCI_REQ0# F51 C18
PCI_REQ1# REQ0# USBP1P
A46 REQ1#/GPIO50 USBP2N N20 USB_PN2 63 2 USB2
PCI_REQ2# B45 P20 USB_PP2 63
PCI_REQ3# REQ2#/GPIO52 USBP2P
M53 REQ3#/GPIO54 USBP3N J20 USB_PN3 63 3 USB3
BOOT BIOS Strap USBP3P L20 USB_PP3 63
TPAD14-GP TP2116 1 PCI_GNT0# F48 F20 4 X
PCI_GNT#1 PCI_GNT#0 BOOT BIOS Location TPAD14-GP TP2117 PCI_GNT1# GNT0# USBP4N
1 K45 GNT1#/GPIO51 USBP4P G20
TPAD14-GP TP2103 1 PCI_GNT2# F36 A20 USB_PN5 76 5 WLAN (I/O Board)
PCI_GNT3# GNT2#/GPIO53 USBP5N
0 0 LPC H53
GNT3#/GPIO55 USBP5P
C20 USB_PP5 76
USBP6N M22 6 X
0 1 Reserved INT_PIRQE# B41 N22
INT_PIRQF# PIRQE#/GPIO2 USBP6P
K53 PIRQF#/GPIO3 USBP7N B21 7 X
1 0 PCI INT_PIRQG# A36 D21
INT_PIRQH# PIRQG#/GPIO4 USBP7P
A48
PIRQH#/GPIO5 USBP8N
H22 8 X
1 1 SPI(Default) USBP8P J22

USB
TPAD14-GP TP2108 1 PCIRST# K6 E22 USB_PN9 73 9 BLUETOOTH
PCIRST# USBP9N
F22 USB_PP9 73
PCI_SERR# USBP9P
E44
SERR# USBP10N
A22 USB_PN10 32 10 CARD READER
PCI_PERR# E50 C22 USB_PP10 32
PERR# USBP10P
USBP11N G24 USB_PN11 54 11 CAMERA
USBP11P H24 USB_PP11 54
PCI_IRDY# A42 L24 12 X
IRDY# USBP12N
H44 M24
PCI_DEVSEL# PAR USBP12P
F46 DEVSEL# USBP13N A24 13 X
PCI_FRAME# C46 C24
FRAME# USBP13P
B PCI_PLOCK# B
D49
PLOCK# USB_RBIAS_PN
B25 1 2
PCI_STOP# USBRBIAS# R2106
D41
PCI_TRDY# STOP# 22D6R2F-L1-GP
C48 D25
TRDY# USBRBIAS
TPAD14-GP TP2115 1 PCH_PME# M7 PME# USB_OC#0_1
OC0#/GPIO59 N16 USB_OC#0_1 63
PCI_PLTRST# D5 J16 USB_OC#2_3 USB_OC#2_3 63
PLTRST# OC1#/GPIO40 USB_OC#4_5
OC2#/GPIO41 F16
R2110 2 122R2J-2-GP PCLK_FW H_R N52 L16 USB_OC#6_7
70
23
PCLK_FW H
CLK_PCI_FB
DY 2 1 CLK_PCI_FB_R P53
CLKOUT_PCI0 OC3#/GPIO42
E14 USB_OC#8_9
CLKOUT_PCI1 OC4#/GPIO43
37 PCLK_KBC R2108 22R2J-2-GP 2 1 PCLK_KBC_R P46 CLKOUT_PCI2 OC5#/GPIO9 G16 USB_OC#10_11
R2111 22R2J-2-GP P51 F12 USB_OC#12_13
CLKOUT_PCI3 OC6#/GPIO10 SMC_W AKE_SCI#_R
P48 T15
CLKOUT_PCI4 OC7#/GPIO14

IBEXPEAK-M-GP-NF

A16 swap override Strap/Top-Block

Swap Override jumper

PCI_GNT#3 Low = A16 swap

override/Top-Block
Swap Override enabled
High = Default

A RN2104 <Core Design> A

USB_OC#10_11 1 10 +3.3V_ALW
USB_OC#12_13 2 9 USB_OC#4_5
USB_OC#8_9 3 8 USB_OC#6_7
R2109 USB_OC#0_1 4 7 USB_OC#2_3 Wistron Corporation
PCI_GNT3# SMC_W AKE_SCI#_R 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1 DY 2 +3.3V_ALW 5 6
Taipei Hsien 221, Taiwan, R.O.C.
4K7R2J-2-GP SRN10KJ-L3-GP
Title

PCH (PCI/USB/NVRAM)
Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 21 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = PCH
U2001C 3 OF 10
FDI_RXN0 BA18 FDI_TXN0 8
BC24 BH17 +3.3V_ALW
8 DMI_CTX_PRXN0 DMI0RXN FDI_RXN1 FDI_TXN1 8
8 DMI_CTX_PRXN1 BJ22 BD16 FDI_TXN2 8
DMI1RXN FDI_RXN2
8 DMI_CTX_PRXN2 AW20 BJ16 FDI_TXN3 8 RN2201
DMI2RXN FDI_RXN3 PM_RI#
8 DMI_CTX_PRXN3 BJ20 BA16 FDI_TXN4 8 1 8
DMI3RXN FDI_RXN4 SUS_PW R_ACK
FDI_RXN5 BE14 FDI_TXN5 8 2 7
8 DMI_CTX_PRXP0 BD24 BA14 FDI_TXN6 8 PM_BATLOW #_R 3 6
DMI0RXP FDI_RXN6 AC_PRESENT_EC
8 DMI_CTX_PRXP1 BG22 DMI1RXP FDI_RXN7 BC12 FDI_TXN7 8 4 5
D 8 DMI_CTX_PRXP2 BA20 DMI2RXP D
8 DMI_CTX_PRXP3 BG20 BB18 FDI_TXP0 8 SRN10KJ-6-GP
DMI3RXP FDI_RXP0
FDI_RXP1 BF17 FDI_TXP1 8
8 DMI_PTX_CRXN0 BE22 DMI0TXN FDI_RXP2 BC16 FDI_TXP2 8
8 DMI_PTX_CRXN1 BF21 DMI1TXN FDI_RXP3 BG16 FDI_TXP3 8
8 DMI_PTX_CRXN2 BD20 AW16 FDI_TXP4 8 PCIE_W AKE# R2202 1 2 1KR2J-1-GP
DMI2TXN FDI_RXP4
8 DMI_PTX_CRXN3 BE18 DMI3TXN FDI_RXP5 BD14 FDI_TXP5 8
FDI_RXP6 BB14 FDI_TXP6 8
8 DMI_PTX_CRXP0 BD22 DMI0TXP FDI_RXP7 BD12 FDI_TXP7 8
8 DMI_PTX_CRXP1 BH21
DMI1TXP
8 DMI_PTX_CRXP2 BC20 DMI2TXP
8 DMI_PTX_CRXP3 BD18 DMI3TXP FDI_INT BJ14 FDI_INT 8
R2203

DMI
FDI
BF13 FDI_FSYNC0 8 PCH_RSMRST# 1 2
+1.05V_VTT FDI_FSYNC0
BH25
R2204 DMI_ZCOMP 10KR2J-3-GP
BH13 FDI_FSYNC1 8
DMI_IRCOMP_R FDI_FSYNC1
1 2 BF25 DMI_IRCOMP
BJ12 FDI_LSYNC0 8
49D9R2F-GP FDI_LSYNC0
+3.3V_RUN BG14
FDI_LSYNC1 FDI_LSYNC1 8

1
R2205
10KR2J-3-GP

9 XDP_DBRESET# 2 T6 J12 PCIE_W AKE# 76

SYS_RESET# WAKE#
C C
M6 Y1 PM_CLKRUN#
SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# 37

System Power Management

37 PM_PW ROK R2207 1 2 0R0402-PAD PM_PW RGD B17 PWROK
R2208 1 2 10KR2J-3-GP
K5 P8 PM_SUS_STAT# 1
MEPWROK SUS_STAT#/GPIO61 TP2201TPAD14-GP

R2209 1 2 10KR2J-3-GP LAN_RST#1 A10 F3 PCH_SUSCLK R2219 1 2 0R2J-2-GP PCH_SUSCLK_2102 39

LAN_RST# SUSCLK/GPIO62
R2220 1 2 10R2J-2-GP PCH_SUSCLK_KBC 37
9 PM_DRAM_PW RGD PM_DRAM_PW RGD D9 E4 PCH_SLP_S5# 1
DRAMPWROK SLP_S5#/GPIO63 TP2202
TPAD14-GP
37 PCH_RSMRST# R2210 1 2 0R0402-PAD
PM_RSMRST#_R C16 H7 PM_SLP_S4#_R R2211 1 2 0R0402-PAD PM_SLP_S4# 37,50
RSMRST# SLP_S4#

37 SUS_PW R_DN_ACK R2218 1 2 0R0402-PAD

SUS_PW R_ACK M1 P12 PM_SLP_S3#_R R2212 1 2 0R0402-PAD PM_SLP_S3# 37,42,50,51
SUS_PWR_DN_ACK/GPIO30 SLP_S3#
9 PM_PW RBTN#_R

37 PM_PW RBTN# 1 2 PM_PW RBTN#_R P5 K8 SIO_SLP_M#_R 1

R2213 0R0402-PAD PWRBTN# SLP_M# TP2203TPAD14-GP

37 AC_PRESENT_EC R2216 1 AC_PRESENT

2 0R0402-PAD P7 N2 PM_SLP_DSW # 1
ACPRESENT/GPIO31 TP23 TP2204TPAD14-GP

PM_BATLOW #_R A6 BJ10 H_PM_SYNC

B BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 9 B

PM_RI# F14 F6 PM_SLP_LAN# 1

RI# SLP_LAN#/GPIO29 TP2205TPAD14-GP

IBEXPEAK-M-GP-NF

+3.3V_RUN

PM_CLKRUN# 1 2
1

Option to " Disable " clkrun. R2215 R2214

A
10KR2J-3-GP
DY 10KR2J-3-GP
<Core Design> A
Pulling it down will keep the clks running.
Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (DM I/FDI/PM)

Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 22 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = PCH
+3.3V_ALW +3.3V_ALW

R2301
U2001B 2 OF 10 10KR2J-3-GP

1
2
3
4

1
2
BG30 B9 PCH_GPIO11 2 1 +3.3V_ALW RN2301 RN2302
PERN1 SMBALERT#/GPIO11
BJ30 SRN2K2J-2-GP SRN2K2J-1-GP
PERP1 PCH_SMB_CLK
BF29 PETN1 SMBCLK H14
BH29 PETP1
C8 PCH_SMB_DATA

8
7
6
5

4
3
SMBDATA
D 76 PCIE_RXN2 AW30 PERN2 R2302 D
76 PCIE_RXP2 BA30 PERP2
C2305 SCD1U10V2KX-5GP 1 2 PCIE_C_TXN2 BC30 J14 TPM_ID1 2 1 SML0_CLK KBC_SCL1 PCH_SMB_CLK
76 PCIE_TXN2 C2306 SCD1U10V2KX-5GP 1 2 PCIE_C_TXP2 BD30
PETN2 WLAN SML0ALERT#/GPIO60 +3.3V_ALW
76 PCIE_TXP2 PETP2 SML0_CLK 10KR2J-3-GP SML0_DATA KBC_SDA1 PCH_SMB_DATA
SML0CLK C6 SML0_CLK 9
AU30

SMBus
76 PCIE_RXN3 PERN3
AT30 G8 SML0_DATA
76 PCIE_RXP3 PERP3 SML0DATA SML0_DATA 9
C2303 SCD1U10V2KX-5GP 1 2 PCIE_C_TXN3 AU32
76 PCIE_TXN3 C2304 SCD1U10V2KX-5GP 1 2 PCIE_C_TXP3 AV32
PETN3 LAN R2303
76 PCIE_TXP3 PETP3 LPD_SPI_INTR#
M14 2 1 +3.3V_ALW
SML1ALERT#/GPIO74
BA32 PERN4
BB32 E10 KBC_SCL1 10KR2J-3-GP
PERP4 SML1CLK/GPIO58 KBC_SCL1 37
BD32
PETN4 KBC_SDA1 +3.3V_RUN
BE32 G12 KBC_SDA1 37
PETP4 SML1DATA/GPIO75

PCI-E*
BF33
PERN5 CL_CLK RN2303
BH33 PERP5 CL_CLK1 T13 1

Controller
BG32 TP2301TPAD14-GP 2 3
PETN5 CL_DATA 1
BJ32 PETP5 CL_DATA1 T11 1 4
TP2302TPAD14-GP

Link
BA34 T9 CL_RST# 1 SRN2K2J-1-GP
PERN6 CL_RST1# TP2303TPAD14-GP
AW34
PERP6
BC34 PETN6
BD34 R2304
PETP6 PEG_CLKREQ#
PEG_A_CLKRQ#/GPIO47 H1 2 1 +3.3V_ALW Q2301
AT34
PERN7 10KR2J-3-GP PCH_SMB_DATA
AU34 6 1 PCH_SMBDATA 7,18,19,76
PERP7
AU36 AD43
PETN7 CLKOUT_PEG_A_N
AV36 AD45 5 2
C PETP7 CLKOUT_PEG_A_P C
BG34 AN4 CLK_EXP_N CLK_EXP_N 9 4 3
PERN8 CLKOUT_DMI_N

PEG
BJ34 AN2 CLK_EXP_P CLK_EXP_P 9
PERP8 CLKOUT_DMI_P DMN66D0LDW -7-GP
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. BG36
PETN8
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN BJ36 PETP8
CLKOUT_DP_N/CLKOUT_BCLK1_N AT1 PCH_SMBCLK 7,18,19,76
CLKOUT_DP_P/CLKOUT_BCLK1_P AT3
AK48 PCH_SMB_CLK
CLKOUT_PCIE0N
AK47
CLKOUT_PCIE0P

From CLK BUFFER

AW24 CLKIN_DMI# CLKIN_DMI# 7
PCIE_CLK_RQ0# CLKIN_DMI_N CLKIN_DMI
P9 PCIECLKRQ0#/GPIO73 CLKIN_DMI_P BA24 CLKIN_DMI 7

AM43 AP3 CLK_CPU_BCLK# CLK_CPU_BCLK# 7

CLKOUT_PCIE1N CLKIN_BCLK_N CLK_CPU_BCLK
AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_CPU_BCLK 7
PCIE_CLK_RQ1# U4
PCIECLKRQ1#/GPIO18
RN

F18 DREFCLK# DREFCLK# 7

CLKIN_DOT_96N DREFCLK
E18 DREFCLK 7
RN2309 CLK_PCIE_MINI1R# CLKIN_DOT_96P
76 CLK_PCIE_MINI1# 1 4 AM47
0R4P2R-PAD CLK_PCIE_MINI1R CLKOUT_PCIE2N
76 CLK_PCIE_MINI1 2 3 AM48
CLKOUT_PCIE2P CLK_PCIE_SATA#
CLKIN_SATA_N/CKSSCD_N AH13 CLK_PCIE_SATA# 7
76 MINI1_CLK_REQ# MINI1_CLK_REQ# N4 AH12 CLK_PCIE_SATA CLK_PCIE_SATA 7
PCIECLKRQ2#/GPIO20 CLKIN_SATA_P/CKSSCD_P
RN

RN2304 1 4 CLK_PCIE_LAN1# AH42 P41 CLK_PCH_14M

76 CLK_PCIE_LAN# CLKOUT_PCIE3N REFCLK14IN CLK_PCH_14M 7
76 CLK_PCIE_LAN 0R4P2R-PAD 2 3 CLK_PCIE_LAN1 AH41 CLKOUT_PCIE3P
2 1 PCIE_CLK_RQ3# A8 J42 CLK_PCI_FB CLK_PCI_FB 21
B R2305 10KR2J-3-GP PCIECLKRQ3#/GPIO25 CLKIN_PCILOOPBACK B

AM51 AH51 XTAL25_IN 1 2

CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT R2309 0R2J-2-GP
AM53 AH53 1
CLKOUT_PCIE4P XTAL25_OUT TP2305TPAD14-GP
PCIE_CLKRQ4# M9 AF38 XCLK_RCOMP R2306 1 2 90D9R2F-1-GP +1.05V_VTT
PCIECLKRQ4#/GPIO26 XCLK_RCOMP

AJ50 T45 CLK_PCH_GPIO64 1 TP2304TPAD14-GP

CLKOUT_PCIE5N CLKOUTFLEX0/GPIO64
AJ52
CLKOUT_PCIE5P
PCIE_CLK_RQ5# H6 P43
Clock Flex

PCIECLKRQ5#/GPIO44 CLKOUTFLEX1/GPIO65

AK53 T42
CLKOUT_PEG_B_N CLKOUTFLEX2/GPIO66
AK51
CLKOUT_PEG_B_P
PEG_B_CLKRQ# P13 N50 CLK48_GPIO R2307 2 1 33R2J-2-GP CLK_48M_CARD 32
PEG_B_CLKRQ#/GPIO56 CLKOUTFLEX3/GPIO67

IBEXPEAK-M-GP-NF

+3.3V_ALW
A
+3.3V_RUN <Core Design> A
RN2307
8 1 PCIE_CLK_RQ0#
7 2 PEG_B_CLKRQ# 1 4 PCIE_CLK_RQ1#
6 3 PCIE_CLKRQ4# 2 3 MINI1_CLK_REQ# Wistron Corporation
5 4 PCIE_CLK_RQ5# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SRN10KJ-7GP RN2308
SRN10KJ-5-GP Title

PCH (PCI-E/SMBUS/CLOCK/CL)
Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 23 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

R2401
PCH_RTCX1 +RTC_CELL
SSID = PCH
1 2 PCH_RTCX2 RN2401
1 4
10MR2J-L-GP 2 3 INTVRMEN- Integrated SUS

2
1.1V VRM Enable

1
X2401 SRN20KJ-GP-U G2401
C2404 GAP-OPEN
High - Enable internal VRs
1 4 SC1U10V3KX-3GP

1
SC15P50V2JN-2-GP
1

1
LPC_LAD[0..3]
C2402

D U2001A 1 OF 10
LPC_LAD[0..3] 37,70 D
2 3 C2403
SC15P50V2JN-2-GP PCH_RTCX1 B13 D33 LPC_LAD0
2

2
PCH_RTCX2 RTCX1 FWH0/LAD0 LPC_LAD1
D13 RTCX2 FWH1/LAD1 B33
C32 LPC_LAD2
FWH2/LAD2 LPC_LAD3
FWH3/LAD3 A32
X-32D768KHZ-40GPU PCH_RTCRST# C14 RTCRST#
82.30001.841 SRTCRST# FWH4/LFRAME# C34 LPC_LFRAME# 37,70

SC1U10V3KX-3GP
D17 SRTCRST#
A34

RTC

LPC
LDRQ0#

1
1 2 SM_INTRUDER# A16 F34
C2401 R2406 1MR2J-1-GP INTRUDER# LDRQ1#/GPIO23
+RTC_CELL 1 2 PCH_INTVRMEN A14 AB9 INT_SERIRQ 37

2
R2404 330KR2F-L-GP INTVRMEN SERIRQ

RN2402
1 8 ACZ_BIT_CLK A30
30 PCH_AZ_CODEC_RST# HDA_BCLK
30 PCH_AZ_CODEC_BITCLK 2 7 AK7 SATA_RXN0_C 59
ACZ_SYNC_R SATA0RXN
3 6 D29 AK6
30 PCH_AZ_CODEC_SYNC
30 PCH_SDOUT_CODEC
4 5
HDA_SYNC SATA0RXP
SATA0TXN
AK11 SATA_TXN0_C C2405 1 2 SCD01U16V2KX-3GP
SATA_RXP0_C 59
SATA_TXN0 59
HDD
ACZ_SPKR P1 AK9 SATA_TXP0_C C2406 1 2 SCD01U16V2KX-3GP SATA_TXP0 59
30 ACZ_SPKR SPKR SATA0TXP
SRN33J-7-GP
ACZ_RST#_R C30 HDA_RST#
AH6 SATA_RXN1_C 59
SATA1RXN
AH5
30 PCH_SDIN_CODEC G30
HDA_SDIN0
SATA1RXP
SATA1TXN
AH9 SATA_TXN1_C C2407 1 2 SCD01U16V2KX-3GP
SATA_RXP1_C 59
SATA_TXN1 59
ODD
AH8 SATA_TXP1_C C2408 1 2 SCD01U16V2KX-3GP SATA_TXP1 59
SATA1TXP
F30
HDA_SDIN1
AF11
C SATA2RXN C
E32 AF9

IHDA
HDA_SDIN2 SATA2RXP
AF7
SATA2TXN
F32 HDA_SDIN3 SATA2TXP AF6

SATA3RXN AH3
ACZ_SDATAOUT_R B29 AH1
HDA_SDO SATA3RXP
SATA3TXN AF3
SATA3TXP AF1
H32

SATA
37 ME_UNLOCK# HDA_DOCK_EN#/GPIO33
SATA4RXN AD9
J30 HDA_DOCK_RST#/GPIO13 SATA4RXP AD8
AD6
SATA4TXN
+3.3V_RUN NO REBOOT STRAP SATA4TXP AD5

No Reboot Strap R23 TPAD14-GP TP2404 1 PCH_JTAG_TCK M3 AD3

JTAG_TCK SATA5RXN
AD1
SATA5RXP
2 ACZ_SPKR Low = Default TPAD14-GP TP2405 PCH_JTAG_TMS
1
R2410 DY 1KR2J-1-GP HDA_SPKR High = No Reboot
1 K3
JTAG_TMS SATA5TXN
AB3
AB1
TPAD14-GP TP2406 PCH_JTAG_TDI SATA5TXP
1 K1
JTAG_TDI +1.05V_VTT

JTAG
TPAD14-GP TP2407 1 PCH_JTAG_TDO J2 AF16
JTAG_TDO SATAICOMPO R2412
TPAD14-GP TP2408 1 PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2
TRST# SATAICOMPI
37D4R2F-GP +3.3V_RUN
SRN15J-2-GP
62 PCH_SPI_CLK PCH_SPI_CLK 2 3 SPI_CLK_R BA2 SPI_CLK

2
2
62 PCH_SPI_CS0# PCH_SPI_CS0# 1 4
+3.3V_RUN SPI_CS#0_R AV3 R2416 R2417
B SPI_CS0# 10KR2J-3-GP 10KR2J-3-GP B
RN2403 AY3 T3 SATA_LED# 66
SPI_CS1# SATALED#

1
1
1 2 INT_SERIRQ 62 PCH_SPI_DO PCH_SPI_DO R2415 1 2 15R2J-GP SPI_MOSI_R AY1 Y9 SATA_DET#0_R
R2411 10KR2J-3-GP SPI_MOSI SATA0GP/GPIO21

SPI
62 PCH_SPI_DI PCH_SPI_DI AV1 V1 SATA_DET#1_R
SPI_MISO SATA1GP/GPIO19

IBEXPEAK-M-GP-NF

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (SPI/RTC/LPC/SATA/IHDA)
Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 24 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

+3.3V_RUN
1
SSID = PCH
R2503
10KR2J-3-GP
U2001F 6 OF 10
2

S_GPIO Y3 AH45
S_GPIO BMBUSY#/GPIO0 CLKOUT_PCIE6N
AH46
SIO_EXT_SCI# CLKOUT_PCIE6P
37 SIO_EXT_SCI# C38 TACH1/GPIO1
PCH_GPIO6 D37 TACH2/GPIO6
D
CLKOUT_PCIE7N AF48 D

MISC
SIO_EXT_W AKE# J32 AF47
37 SIO_EXT_W AKE# TACH3/GPIO7 CLKOUT_PCIE7P
SIO_EXT_SMI# F10
37 SIO_EXT_SMI#

1
GPIO8
C2501 PCH_GPIO12
SC47P50V2JN-3GP DY K9 LAN_PHY_PWR_CTRL/GPIO12 A20GATE U2 SIO_A20GATE 37

2
HOST_ALTERT#1 T7
+3.3V_RUN GPIO15
DGPU_HOLD_RST# AA2 AM3 BCLK_CPU_N 9
SATA4GP/GPIO16 CLKOUT_BCLK0_N/CLKOUT_PCIE8N
PCH_GPIO17 F38 AM1 BCLK_CPU_P 9
TACH0/GPIO17 CLKOUT_BCLK0_P/CLKOUT_PCIE8P
PCH_GPIO22 Y7 BG10
SCLOCK/GPIO22 PECI H_PECI 9

GPIO
1
PCH_GPIO24 H10 T1 SIO_RCIN# 37
C2502 GPIO24 RCIN# +1.05V_VTT
SC47P50V2JN-3GP DY TPAD14-GP TP2507 1 PCH_GPIO27 AB12 BE10 H_PW RGD 9,42

2
GPIO27 PROCPWRGD

CPU
R2510 PCH_GPIO28 V13 BD10
GPIO28 THRMTRIP# RN2505
1 2 PCH_GPIO22
10KR2J-3-GP STP_PCI# M11 3 2
STP_PCI#/GPIO34 PCH_THERMTRIP_R 4 1 H_THERMTRIP# 9,37,42
CLK_SATA_OE# V6
SATACLKREQ#/GPIO35
2

RN2506 PCH_GPIO36 SRN56J-4-GP

AB7
SATA2GP/GPIO36 TP1
BA22 Placed Within 2" from PCH
1 4 SIO_EXT_SCI#
2 3 PCH_GPIO17 R2508 PCH_GPIO37 AB13 AW22
10KR2J-3-GP SATA3GP/GPIO37 TP2
C SRN10KJ-5-GP PCH_GPIO38 V3 BB22 C
1

SLOAD/GPIO38 TP3
PCH_GPIO39 P3 AY45
SDATAOUT0/GPIO39 TP4
PCH_GPIO45 H3 AY46
+3.3V_ALW PCIECLKRQ6#/GPIO45 TP5
DDR_RST_GATE F1 AV43
9 DDR_RST_GATE PCIECLKRQ7#/GPIO46 TP6
1

PCH_GPIO48 AB6 AV45

R2525 SDATAOUT1/GPIO48 TP7
10KR2J-3-GP 1 2 PCH_TEMP_ALERT#_C AA4 AF13
37 PCH_TEMP_ALERT# R2518 0R0402-PAD SATA5GP/GPIO49 TP8
PCH_GPIO57 F8 M18
2

GPIO57 TP9
PCH_GPIO28 N18
+3.3V_ALW TP10
A4 AJ24
VSS_NCTF_1 TP11
A49

NCTF
VSS_NCTF_2

RSVD
TPAD14-GP TP2510 1 PCH_NCTF_1 A5 AK41
VSS_NCTF_3 TP12
A50
VSS_NCTF_4
A52 AK42
PCH_GPIO57 VSS_NCTF_5 TP13
1 2 A53 VSS_NCTF_6
R2524 10KR2J-3-GP B2 M32
VSS_NCTF_7 TP14
B4 VSS_NCTF_8
HOST_ALTERT#1 1 2 B52 N32
R2513 1KR2J-1-GP VSS_NCTF_9 TP15
B53
VSS_NCTF_10
BE1 VSS_NCTF_11 TP16 M30
PCH_GPIO45 1 4 BE53
DDR_RST_GATE VSS_NCTF_12
2 3 BF1 VSS_NCTF_13 TP17 N30
B RN2509 B
BF53
SRN10KJ-5-GP VSS_NCTF_14
BH1 H12
VSS_NCTF_15 TP18
BH2
VSS_NCTF_16
BH52 AA23
PCH_GPIO24 VSS_NCTF_17 TP19
2 1 BH53
R2514 DY 100KR2J-1-GP BJ1
VSS_NCTF_18
AB45
VSS_NCTF_19 NC_1
BJ2 VSS_NCTF_20
PCH_GPIO12 1 4 BJ4 AB38
SIO_EXT_SMI# VSS_NCTF_21 NC_2
2 3 BJ49 VSS_NCTF_22
RN2501 TPAD14-GP TP2511 1 PCH_NCTF_2 BJ5 AB42
SRN10KJ-5-GP VSS_NCTF_23 NC_3
BJ50 VSS_NCTF_24
TPAD14-GP TP2512 1 PCH_NCTF_3 BJ52 AB41
VSS_NCTF_25 NC_4
BJ53 VSS_NCTF_26
D1 T39
VSS_NCTF_27 NC_5
D2
VSS_NCTF_28
D53
+3.3V_RUN VSS_NCTF_29 INIT3_3V# TP2506TPAD14-GP
E1 VSS_NCTF_30 INIT3_3V# P6 1
TPAD14-GP TP2509 1 PCH_NCTF_4 E53
RN2503 VSS_NCTF_31
C10
SIO_EXT_W AKE# TP24
4 1
PCH_GPIO6 3 2 IBEXPEAK-M-GP-NF
SRN10KJ-5-GP

RN2507
DGPU_HOLD_RST# 4 1
PCH_TEMP_ALERT#_C 3 2
SRN10KJ-5-GP

A <Core Design> A

PCH_GPIO37 1 2 +3.3V_RUN
PCH_GPIO48 R2519 1 210KR2J-3-GP
R2515 10KR2J-3-GP Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
RN2502 Taipei Hsien 221, Taiwan, R.O.C.
PCH_GPIO38 4 1 RN2504
PCH_GPIO36 3 2 STP_PCI# 4 1 Title
SRN10KJ-5-GP PCH_GPIO39
SRN100KJ-6-GP
3 2
PCH (GPIO/CPU)
Size Document Number Rev
DJ1 Calpella UMA X01
Date: Thursday, April 22, 2010 Sheet 25 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = PCH
+3.3V_RUN
+1.05V_VTT
U2001G POWER 7 OF 10
1.524A AB24 AE50 +VCCA_DAC_1_2 1 2

1
VCCCORE VCCADAC C2603 C2605 C2606 L2602 HCB1608KF-181-GP
AB26 VCCCORE

SCD01U16V2KX-3GP

SCD1U10V2KX-5GP

SC10U6D3V5MX-3GP
C2601 C2602 AB28 AE52
SC10U6D3V5KX-1GP SC1U6D3V2KX-GP VCCCORE VCCADAC +3.3V_CRT_LDO
DY AD26

2
VCCCORE

CRT
D AD28 AF53 D

2
VCCCORE VSSA_DAC
AF26 VCCCORE

VCC CORE
AF28 AF51 1 2
AF30
VCCCORE VSSA_DAC L2603 DY
HCB1608KF-181-GP
VCCCORE
AF31 VCCCORE
AH26 VCCCORE
AH28 +3VS_VCCA_LVD +3.3V_RUN
VCCCORE R2603
AH30 VCCCORE
AH31 VCCCORE VCCALVDS AH38 2 1
AJ30 C2616 0R0603-PAD-1-GP
VCCCORE
AJ31 VCCCORE VSSA_LVDS AH39 1
DY
2
+1.8V_RUN
R2611
SCD1U10V2KX-5GP
AP43 +1.8VS_VCCTX_LVDS 1 2
+1.05V_VTT VCCTX_LVDS

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP
AP45
VCCTX_LVDS

1
AT46 C2618 C2619 0R0805-PAD-2-GP 2010/04/21

LVDS
VCCTX_LVDS C2617
AK24 VCCIO VCCTX_LVDS AT45
DY SC10U6D3V5MX-3GP X01

2
TPAD14-GP TP2601 1 +1.05VS_VCCAPLL_EXP BJ24
VCCAPLLEXP +3.3V_RUN
VCC3_3 AB34

AN20
AN22
VCCIO VCC3_3 AB35 357mA

HVCMOS

1
VCCIO C2607
AN23 VCCIO VCC3_3 AD35
AN24 SCD1U10V2KX-5GP
VCCIO
AN26

2
+1.05V_VTT VCCIO
AN28
VCCIO
BJ26
C 3.208A BJ28
AT26
VCCIO
VCCIO
C

VCCIO
1

1
C2608 C2609 C2610 C2611 C2612 AT28 VCCIO
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
DY DY AU26
VCCIO
SC1U10V3KX-3GP

SC1U10V3KX-3GP +1.8V_RUN
SC10U6D3V5KX-1GP

AU28
2

2
VCCIO
AV26
AV28
AW26
VCCIO
VCCIO VCCVRM AT24 35mA
VCCIO
AW28
VCCIO +1.05V_VTT

DMI
BA26 VCCIO VCCDMI AT16
BA28 +1.05VS_VCC_DMI
BB26
BB28
VCCIO
VCCIO VCCDMI
AU16
R2601
1 2 61mA
0R0402-PAD
+3.3V_RUN

1
VCCIO C2613
BC26
VCCIO

PCI E*
BC28 SC1U10V3KX-3GP
VCCIO
BD26

2
+3.3V_RUN VCCIO
BD28
VCCIO
BE26 VCCIO VCCPNAND AM16
BE28 AK16
BG26
VCCIO VCCPNAND
AK20 156mA
1

C2614 VCCIO VCCPNAND

BG28 AK19
VCCIO VCCPNAND

1
SCD1U10V2KX-5GP BH27 AK15 C2615
VCCIO VCCPNAND SCD1U10V2KX-5GP
AK13
2

VCCPNAND
AN30 AM12

2
VCCIO VCCPNAND

NAND / SPI
AN31 AM13
VCCIO VCCPNAND
AM15
VCCPNAND
357mA AN35 VCC3_3 +3.3V_RUN
B B

1
VCCAFDI_VRM AT22
VCCVRM[1] R2605
+1.05V_VTT TPAD14-GP TP2602 1 VCCAFDIPLL BJ18
VCCFDIPLL VCCME3_3
AM8
AM9
85mA 0R0402-PAD
VCCME3_3
FDI

AM23 AP11

2
VCCIO VCCME3_3 PCH_VCCME3_3
VCCME3_3 AP9

1
C2622
SCD1U10V2KX-5GP
IBEXPEAK-M-GP-NF
3.3V CRT LDO

2
+5V_RUN +3.3V_CRT_LDO
U2601

3 4
VIN VOUT
2
1
GND DY 5
EN NC#5

1
C2620
+1.8V_RUN C2621 DY RT9198-33PBG-GP DY SC1U6D3V2KX-GP
SC1U10V2KX-1GP

2
VCCAFDI_VRM 1 2 Second 74.09091.H3F
R2606 0R0402-PAD

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (POWER1)
Size Document Number Rev
DJ1 Calpella UMA X01
Date: W ednesday, April 21, 2010 Sheet 26 of 90
5 4 3 2 1

forum.hocvienit.vn
 5 4 3 2 1

SSID = PCH
U2001J POWER 10 OF 10 +1.05V_VTT

TPAD14-GP TP2515 1VCCACLK AP51 VCCACLK VCCIO V24

V26

1
VCCIO C2706
AP53 Y24
VCCACLK VCCIO
VCCIO Y26 DY SC1U10V2KX-1GP

2
AF23 VCCLAN VCCSUS3_3 V28
U28 +3.3V_ALW
VCCSUS3_3
AF24 VCCLAN VCCSUS3_3 U26
D
VCCSUS3_3 U24 D
P28

1
DCPSUSBYP VCCSUS3_3 C2703
Y20 DCPSUSBYP VCCSUS3_3 P26

SCD1U10V2KX-5GP
N28 SCD1U10V2KX-5GP

1
VCCSUS3_3

C2707
N26

2
VCCSUS3_3
AD38 VCCME VCCSUS3_3 M28
M26

2
VCCSUS3_3
AD39 L28

USB
VCCME VCCSUS3_3
VCCSUS3_3 L26
AD41 J28
+1.05V_VTT VCCME VCCSUS3_3
VCCSUS3_3 J26
AF43 H28
1.998A AF41
VCCME VCCSUS3_3
VCCSUS3_3
H26
G28

1
VCCME VCCSUS3_3

SC1U6D3V2KX-GP
C2704 C2705 C2708 G26
SC10U6D3V5KX-1GP VCCSUS3_3
DY AF42
VCCME VCCSUS3_3
F28
F26

SC10U6D3V5MX-3GP
2

2
VCCSUS3_3 +3.3V_ALW +3.3V_ALW
V39 E28
VCCME VCCSUS3_3
E26

Clock and Miscellaneous

VCCSUS3_3
V41 C28
VCCME VCCSUS3_3
VCCSUS3_3 C26

2
V42 B27 C2709 +3.3V_RUN
VCCME VCCSUS3_3 SCD1U10V2KX-5GP D2701
VCCSUS3_3 A28
Y39 A26 CH751H-40PT-GP

2
1
VCCME VCCSUS3_3

SC1U6D3V2KX-GP
C2710
+1.05V_VTT Y41 U23 +1.05V_VTT

1
VCCME VCCSUS3_3

2
DY

2
1 2 +1.05VS_VCCA_A_DPL Y42 V23 +5V_ALW D2702
L2702 0R0805-PAD VCCME VCCIO
CH751H-40PT-GP
1

C F24 +5VALW _PCH_VCC5REFSUS 1 2 C

C2734 DY C2711 SCD1U10V2KX-5GP V5REF_SUS R2701 100R2F-L1-GP-U

1
1
SC10U6D3V5MX-3GP SC1U6D3V2KX-GP +VCCRTCEXT V9
2

DCPRTC C2712 +5V_RUN

1
+1.8V_RUN
C2713

SC1U10V2KX-1GP

2
K49 +5VS_PCH_VCC5REF 1 2
V5REF R2702 100R2F-L1-GP-U
AU24

PCI/GPIO/LPC
2

+1.05VS_VCCA_B_DPL VCCVRM
1 2

1
L2703 0R0805-PAD J38
VCC3_3
1

BB51 C2715
C2735 DY C2714 72mA +1.05VS_VCCA_A_DPL BB53
VCCADPLLA
L38 SC1U10V2KX-1GP

2
SC10U6D3V5MX-3GP VCCADPLLA VCC3_3 +3.3V_RUN
SC1U6D3V2KX-GP
2

M36
73mA +1.05VS_VCCA_B_DPL BD51
BD53
VCCADPLLB
VCC3_3
N36

1
VCCADPLLB VCC3_3 C2716
AH23 P36 SCD1U10V2KX-5GP
VCCIO VCC3_3
AJ35 C2717

2
VCCIO
AH35 U35
VCCIO VCC3_3 +3.3V_RUN
1 2
+1.05V_VTT AF34
VCCIO SCD1U10V2KX-5GP
VCC3_3 AD13
AH34
1

C2718 C2719 C2720 VCCIO

SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP AF32
VCCIO VCCSATAPLL TP2514 TPAD14-GP
AK3 1
2

VCCSATAPLL
V12 DCPSST VCCSATAPLL AK1
SCD1U10V2KX-5GP

+VCCSST
B +1.05V_VTT B
SCD1U10V2KX-5GP
1
C2723

+1.05VALW _INT_VCCSUS Y22

DCPSUS
AH22
VCCIO
1
C2724
2

1
+1.8V_RUN C2725
P18 AT20 SC1U6D3V2KX-GP
2

VCCSUS3_3 VCCVRM

2
U19
SATA

+3.3V_ALW VCCSUS3_3
SCD1U10V2KX-5GP

PCI/GPIO/LPC

AH19
163mA U20
VCCSUS3_3
VCCIO