2009-2010

PROJECT REAL TIME DSP IMPLEMENTATION IN 8-BIT

REPORT PROCESSORS―AN ALGORITHM AND
ON: COMPARATIVE ANALYSIS

By:
Subhajit Banerjee Purnapatra (9674),
&
Siddharth Kumar (9663),
VIIIth Semester,
B.Tech, Electronics Engineering.
Batch 2010. ISM Dhanbad. 1
ABSTRACT:
An attempt was made to implement a digital filter on an 8-bit RISC
architecture based processor (Atmega-16). In this course, problems particularly
regarding the time intensiveness of floating point multiplications on such processors
(lacking specialized hardware multipliers unlike DSPs) were encountered. To solve
this, we designed an algorithm which reduces each such multiplication to an addition
and a product of character variables, thereby significantly reducing calculation related
delay and hence increasing the maximum achievable sampling frequency. The filter
characteristics obtained, however, exhibited significant deviation from ideal behavior.
This report presents a discussion on the optimization algorithm used, along with a
detailed analysis drawing a comparison between the optimized and ideal filter
responses under different parameters.

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INTRODUCTION:
The concept for developing this project originated from a scrutiny of the
hardware components of the TSK 320C-6711 DSK kit. It clearly revealed that most of
the hardware used on the board is in fact superfluous with respect to the Laboratory
Assignments of the course EIC-15205. Provision for the 80 pin PCM 3003 daughter
card is an example.
In addition, the software required to operate the kit has elaborate and detailed
support for advanced implementations, again irrelevant with respect to the course. An
easier software on the other hand, can assist in a more direct approach towards
implementation, obviating the necessity for programming skills.
Put together, they present a formidable impression for the Kit and students
generally refrain from indulging into the joy of the much essential hardware
implementation of the theory of such a rich subject as DSP.
This project proposes a simple hardware based on an AVR microcontroller
(~Rs. 150) core instead of the C6711 DSP ($ 28,~Rs.1400). Using a microcontroller
instead of a microprocessor also removes the necessity of external RAM/ROM chips,
thereby minimizing hardware.

BENEFITS:

Low cost. (Rs. 1500 estimated).

Simple hardware required only for implementation of basic DSP systems. This
removes the use of superfluous hardware like special purpose chips which
often interferes with the sense of “complete understanding” of students.

Simple and user friendly software which removes the prior knowledge of even
fundamental level programming. This will help students concentrate on the
theoretical fundamentals of DSP rather than complicacy of programming.

DISADVANTAGES:

Low speed. Preliminary expectation for maximum sampling frequency =20
kHz.

Lack of actual programming support renders lesser control over hardware.

Limited to implementation of FIR and IIR filters. No provision for
implementation of advanced digital systems.

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IMPLEMENTATION:
Control signal for
enabling sampling

ADC DAC
Microcontroller Data
Data

Filter Coefficients and

sampling frequency
data, fed through SPI.

I O

Analog Analog
Input Output

As depicted above, the hardware comprises of the following basic components.

ADC: An analog to digital converter is used to sample and digitize the analog
input signal. This chip is enabled for sampling by a set of control signals from
the microcontroller thus providing it with the capability for having variable
sampling frequency.
Proposed chip: AD574A, features:
 12-bit resolution.
 35 micro second conversion time.
 Low cost, ~Rs. 450.

Microcontroller: This is the core of the hardware and does all the
mathematical work along with other controlling.
Proposed chip: Atmega 16 (AVR), features
 RISC (Reduced instruction set computing) architecture.
Yields in faster processing speed than most low budget,
commercially available microcontrollers.

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  Master clock input frequency up to 20 MHz
 8 Kb of In System Self Programmable Flash ROM.
 512 Bytes Internal SRAM.
 Cost ~ Rs. 150

DAC: Converts the digital signal back to the desired filtered analog output.
Proposed implementation is through resistor ladder since it provides the fastest
conversion.
 8-bit
 Cost ~ Rs. 80

PC Software: A customized application is to be developed which would help
the user interface the hardware.
 SPI- 3 wire “Null-Modem” configuration to be used for serial
port interface (via MAX-232 chip ~ Rs. 30).

Proposed features:
 Let user choose between FIR and IIR filter modes.
 Read the filter coefficients given as input. These coefficients can
be generated by MATLAB.
 Read the initial condition coefficients.
 Read the sampling frequency.
 Inform the user if the given sampling frequency combined with
the given order, exceeds the hardware capabilities. Otherwise,
feed the above given information to the MPU for processing via
serial port interfacing (SPI).

BRIEF DESCRIPTION OF WORKING AND ALGORITHM:

Considering any general filter, characterized by its z-transform:

H(z)= (b0+b1z-1+b2z-2+b3z-3+……+bmz-M)/( 1+a1z-1+a2z-2+a3z-3+……+anz-N)
(Ref. “Discrete Time Signal Processing”, Oppenheim-Schafer, eqn. 5.18)

Upon solving for y[n] in time domain, we easily obtain:

y[n]= b0x[n]+b1x[n-1]+b2x[n-2]+b3x[n-3]+……+bmx[n-M]-( a1y[n-1]+a2y[n-
2]+a3y[n-3]+……+any[n-N])

The following algorithm implemented on the processor shall give us the filtered
output:

1. Obtain sampling frequency from user (PC software).

2. Obtain initial conditions like x_[1],x_[2],…,x_[M] and y_[1],y_[2],…,y_[N].
(NOTE: Since negative coefficients in any array is not permissible in common
programming languages, we denote x[-1] by x_[1] etc. which provides a
convenient way to represent data.)
3. Enable ADC and read the vale to variable ‘x’.

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 4. Perform:
y=(b[0]*x + b[1]*x_[1] + b[2]*x_[2] + … + b[m]x_[M]) - (a[1]*y_[1] +
a[2]*y_[2] + … + a[n]*y_[N])
by the following code:
y=b[0]*x;
for i=1 to max(M,N)
{
if(i<M)
y= y + b[i]*x_[i];
if(i<N)
y= y - a[i]*y_[i];
}// analogous to Direct Form-II algorithm, using one loop for
both variables

5. Output ‘y’ to DAC port.

6. “Forget” the oldest value and replace with the ones just before it
for i=2 to max(M,N)
{
if(i<M)
x_[i]=x_[i-1];
if(i<N)
y_[i]=y_[i-1];
}

x_[1]=x; y_[1]=y;

7. Introduce delay until it is time again to resample, according to the given

sampling frequency.
8. Loop back to Step 3.

EXPLANATION FOR FAILURE OF ABOVE ALGORITHM IN

REAL-TIME IMPLEMENTATION:

The above algorithm was implemented on the said processor which resulted in an
extremely low sampling frequency (order of Hz). The cause was identified as follows:
1. Time consuming floating point multiplications:
While each (integer x integer) type operation required only about 3.7 µs*,
each operation of the type (float x float) required approximately 28.5 ms*.
2. Introducing each ‘if’, ‘while’ or any other branching statement produced an
unacceptably large delay of about 1 ms*.

*NOTE: Values to be reconfirmed through future hardware experimentation.

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 3. The analog smoothing filter to be designed after the DAC, to yield the final
filtered output required its cut-off frequency to closely match that of the
implemented digital filter. Such frequent variations of analog components
become highly inconvenient.

PROPOSED SOLUTIONS:
1. Implement an alternative algorithm which requires (char × char) type
multiplication and (char + char) type addition to substitute a (float × float) type
operation.

2. Avoid using arrays, which would require usage of loops for indexing purpose. The
resulting code becomes voluminous but manages to avoid branching statements.

3. We are presently experimenting with various methods to implement the smoothing

filter in order to resolve the concerned issue.

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OPTIMIZATION ALGORITHM:
Our algorithm fundamentally suggests representing each filter coefficient as an
exponent of 2.
Let
    ……. (0≤ |M|< 10; Ex
I ), be any floating point
number. This is a familiar representation for any general value that a filter coefficient
might have.
Our objective is to first represent this number in the form of :
 
 

…… (0≤ |m|< 2; ex
I). The numbers ‘m’ and ‘ex’ can then be represented as an 8-
bit value in a character variable representation.
A similar operation is performed with the input values, thus resulting in a pair
of similar values which represents the sampled value at a particular instant of time:
    (subscripts ‘b’ and ‘x’ denotes the corresponding variables they are
representing).
Now, the multiplication of two floating point values: p = b × x is reduced to
the pair of operation: p1= mb × mx and p2= exm + exx . The following example
outlines the steps involved to execute this desired conversion.

1. Let b= 2563.78 (any arbitrary value, just as an example).

2. Let b’ = log2 |b| and s = sgn(b). Therefore, b’= 11.3240 and s=1 in this case.

3. The integral part of b’ directly gives the value of exb while the fractional part of b’
raised to the power of 2 gives the absolute value of mb. Thus:
exb = [b’]* and mb= s × 2{b’}# . In this case, exb= 11 and mb= 1.248.

4. For convenience in calculation (explained in step 7 below), we further check if mb

≥ 1.0. If so, we divide it by 2 and increase the exponent by 1, thereby retaining the
overall product. Thus, mb= 0.624 and exb=12 .

5. We must consider the possibility that both exb and mb can be positive or negative.
Hence we must have provision for a sign bit when we intend to represent these
values in 8-bits. This effectively leaves us with 7-bits to perform the desired
representation.

6. Through calculations, we find that the typical values of the filter coefficients
necessary to implement a filter of 100 orders result in maximum |exb| values of
approximately 65. Hence, it can be directly represented as a signed character value
which has a range of -128≤ c < 127.
Thus, the 8-bit quantized value of exb is simply q_exb=exb .

7. In order to represent mb as an 8-bit value, we multiply it with 2(8-1) = 128 and store
the integral part of the result. Thus, q_mb= [mb × 128]* . In this case, q_mb=79.

* [x] Represents floor function.

#
{x} Represents fraction of x function.
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 Not scaling the value of mb (by 2) in step 4 above, would have resulted in q_mb=
159, which lies beyond the range of signed character variables.

8. We can now perform all necessary mathematical operations using the different
values of q_exb and q_mb (and similarly q_exx and q_mx) for the various
coefficients (and inputs).

PERFORMANCE ANALYSIS:
The above algorithm helps us to reduce calculation delay considerably. This is
due not only to the fact that 8-bit addition/multiplications are involved instead of
resource intensive 32-bit addition/multiplication; but also to the fact that the chosen
base of 2 enables the processor to perform multiplication faster (only involving bit
shifting).
The aspect to be analyzed now is the accuracy of the filter being implemented
itself. In a bid to improve the processing speed with limited architecture support, we
have made a trade-off by losing precision. This loss manifests itself as the
quantization error when we approximate the value of q_mb from mb, where the
fractional part of the coefficient is lost completely.
In order to study the effect of this loss on the nature of the implemented filter,
we use MATLAB to simulate the frequency response of a filter having its defining
coefficients as apx_b and apx_a (for approximate values of original zeroes ‘b’ and
poles ‘a’ respectively). They are defined as follows:

apx_b=(q_mb/128) × (_
) and apx_a=(q_ma/128) × (_  )

Obviously, the original filter coefficients only differ from the above,
approximated ones by the values inside the 1st bracket.
For a fixed sampling frequency, 9600 Hz, various frequency responses for a
Butterworth LPF, are plotted by altering 3 different parameters:
• Quantization bits (8, 16 and 32 corresponding to the popular architecture).
• Cutoff frequency (1.5 kHz, 2.5 kHz and 3.5 kHz).
• Order of filter (5, 15 and 25).
The graphs are presented here as follows:

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Fig.1. Bits = 8, fc = 1.5 kHz, Order = 5 Fig.2. Bits = 8, fc = 1.5 kHz, Order = 15

Fig.3. Bits = 8, fc = 1.5 kHz, Order = 25 Fig.4. Bits = 8, fc = 2.5 kHz, Order = 5

Fig.5. Bits = 8, fc = 2.5 kHz, Order = 15 Fig.6. Bits = 8, fc = 2.5 kHz, Order = 25

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 Fig.7. Bits = 8, fc = 3.5 kHz, Order = 5 Fig.8. Bits = 8, fc = 3.5 kHz, Order = 15

Fig.9. Bits = 8, fc = 3.5 kHz, Order = 25 Fig.10. Bits = 16, fc = 1.5 kHz, Order = 5

Fig.11. Bits = 16, fc = 1.5 kHz, Order = 15 Fig.12. Bits = 16, fc = 1.5 kHz, Order = 25

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Fig.13. Bits = 16, fc = 2.5 kHz, Order = 5 Fig.14. Bits = 16, fc = 2.5 kHz, Order = 15

Fig.15. Bits = 16, fc = 2.5 kHz, Order = 25 Fig.16. Bits = 16, fc = 3.5 kHz, Order = 5

Fig.17. Bits = 16, fc = 3.5 kHz, Order = 15 Fig.18. Bits = 16, fc = 3.5 kHz, Order = 25

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Fig.19. Bits = 32, fc = 1.5 kHz, Order = 5 Fig.20. Bits = 32, fc = 1.5 kHz, Order = 15

Fig.21. Bits = 32, fc = 1.5 kHz, Order = 25 Fig.22. Bits = 32, fc = 2.5 kHz, Order = 5

Fig.23. Bits = 32, fc = 2.5 kHz, Order = 15 Fig.24. Bits = 32, fc = 2.5 kHz, Order = 25

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Fig.25. Bits = 32, fc = 3.5 kHz, Order = 5 Fig.26. Bits = 32, fc = 3.5 kHz, Order = 15

Fig.27. Bits = 32, fc = 3.5 kHz, Order = 25

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CONCLUSION:
From the above graphs, we find that in some situations, our approximation
algorithm yields unacceptable level of deviation from the ideal filter behavior yet in
other situations, our algorithm works quite efficiently.
This inconsistent behavior of the approximated filter can be viewed as being
correlated with the three variable parameters mentioned before viz. quantization bits,
filter order and cutoff frequency. The relation is summarized below:

1. Effect of quantization bits:

For any given filter order and cutoff frequency, increasing the quantization bits
results in improvement of the filter characteristics as the graph more closely resembles
the ideal behavior. This observation also corresponds with our expected notion of
quantization error.

2. Effect of filter order:

It is observed that for any given value of quantization and cutoff frequency, the
characteristics deteriorates with an increase in filter order.
A study of the values of the filter coefficients reveals that higher order filters
use coefficients of greater magnitude. Consequently, our quantization error is
magnified. Such greater margin of error, especially near the zeroes, results in a larger
departure from ideal behavior.

3. Effect of cutoff frequency:

From the above graphs, it is observed that for any given value of quantization
and filter order, the best set of plots are obtained for the cutoff frequency, fc= 2500 Hz
(at sampling frequency, fs= 9600 Hz).
We are lead to believe that the cutoff frequencies for which fc / fs ≈ 0.25
produce a closer approximation to ideal behavior. This is probably due to the fact that
in this region, the average magnitude of the filter coefficients is lesser thus
extenuating the quantization error to some extent.

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