NATIONAL UNIVERSITY OF SINGAPORE

EXAMINATION FOR
(Semester II: 2009/2010)

EE4218 – EMBEDDED HARDWARE SYSTEM DESIGN

April/May 2010 - Time Allowed: 2 Hours

INSTRUCTIONS TO CANDIDATES:

1. This paper contains FOUR (4) questions and comprises SEVEN (7) printed pages.

2. Answer all FOUR (4) questions. Each question carries 20 marks.

3. This is an OPEN BOOK examination. Write your answers in the answer booklets
provided.

4. Programmable calculators are not allowed.

 EE4218 EMBEDDED HARDWARE SYSTEM DESIGN / Page 2

Q.1 Answer both parts (a) and (b).

(a)
(i) Determine the decimal value of Y after executing the following SystemC code:

sc_ufixed<12, 6> X;
sc_ufixed<8, 6, SC_RND> Y;
X = 13.796875;
Y = X;

(5 marks)

(ii) Assume the longest delays for the combinational logic networks Logic 1, Logic 2 and
Logic 3 in Figure Q1 are 4ns, 3ns and 4ns, respectively. Calculate the maximum clock
frequency for the whole circuit in Figure Q1.

(5 marks)

Logic 1 Logic 2 Logic 3

Clock

Figure Q1. The diagram of a sequential circuit.

Question 1 continues on page 3

 EE4218 EMBEDDED HARDWARE SYSTEM DESIGN / Page 3

(b) Consider the following logic expressions in a computation model:

x = ac + de
y = a + bc
w = yd + ce

(i) Decide how many 4-input LUTs at minimum would be required to implement the
logic expressions. Draw the mapped 4-input LUT netlist. Indicate the mapping
relationship between the nodes on the logic network and the 4-input LUTs, for
example, which node (nodes) is (are) mapped to which LUT. You can name each
node in your own way, for example, name v1 for a node.
(5 marks)

(ii) Write the content for the look-up table that generates the result for x, based on your
answer to Q.1(b)(i).
(5 marks)
 EE4218 EMBEDDED HARDWARE SYSTEM DESIGN / Page 4

Q.2 Answer both parts (a) and (b).

(a)
(i) Calculate the number of registers that will be generated from the VHDL code
segment as shown in Code Q2.1.
(5 marks)

Code Q2.1:
process (clk, Reset)
type StateType is (Idle, Go1);
variable State: StateType;
begin
if Reset = ‘1’ then
State := Idle;
F <= ‘0’;
G <= ‘0’;
elsif clk’event = TRUE and clk = ‘1’ then
case State is
when Idle => if Start = ‘1’ then
State := Go1;
F <= ‘1’;
end if;
when Go1 => State := Idle;
F <= ‘0’;
G <= ‘1’;
end case;
end if;
end process;

(ii) To enable Code Q2.1 to implement a safe state machine, revise the VHDL code
segment in Code Q2.1 by adding no more than 2 statements.

(5 marks)

Question 2 continues on page 5

 EE4218 EMBEDDED HARDWARE SYSTEM DESIGN / Page 5

(b) Consider an algorithm modeled by the following graph Figure Q2b.

a b c d

+ *
1 2

*3 +
4

+
5

Figure Q2b.

Assume that only two different resource types are available. One is a two-input adder, and
the other is a two-input multiplier. The adder has a delay of 20 ns. The multiplier has a
delay of 30 ns. Assume each multiplexer has a delay of 10 ns and each register has zero
setup and hold time.

(i) Determine a minimum-latency schedule if we want to achieve a cycle-time of 50ns

and we only have two adders and one multiplier. Draw the schedule with the help of
the sequencing graph.

(5 marks)

(ii) Draw the data path corresponding to the schedule determined in Q.2(b)(i). The data
path should show the resources, registers and multiplexers.
(3 marks)

(iii) Draw the state transition diagram for the controller corresponding to the schedule
determined in Q.2(b)(i). The controller is a hard-wired controller.
(2 marks)
 EE4218 EMBEDDED HARDWARE SYSTEM DESIGN / Page 6

Q.3 Answer both parts (a) and (b).

(a) The following function needs to be minimized:

f (a, b, c, d )   m(0,1,3,5,6,14)   d (7,8,10)

(i) Find all the prime implicants using the Quine-McCluskey method.
(4 marks)
(ii) Find the MSOP solutions using Petrick’s method.
(6 marks)

(b) The function f is to be mapped to a library of the following cells: {AND2 with cost 4;
OR2 with cost 5; INV with cost 1}.

(i) Draw the pattern trees for these cells using NAND2 and INV as base functions.
(3 marks)
(ii) Draw the subject graph for f using the same base functions.
(7 marks)
 EE4218 EMBEDDED HARDWARE SYSTEM DESIGN / Page 7

Q.4 Answer both parts (a) and (b).

A B2 X

S1 S2

B1 X C
10μm
S3 S4

X B3 X

10μm
Figure Q3a

(a) Figure Q3a shows a part of an FPGA chip. The blocks shown (labeled A, B, C and X)
are logic blocks, while the switches are labeled with S1 to S4. The distance between
two logic blocks (from center to center) is 10 micro meters. The function to be
implemented consists of 3 blocks to be used – A, B and C. The blocks A and C have
already been placed. The blocks labeled X and colored grey are already in use. The
position of B needs to be determined. Analytical placer is used for computing the
ideal placement. The cost function is d2 + d where d is the distance between the
centers of two logic blocks. Two connections need to be made from A to B, and one
from B to C. Where should block B be placed and why?
(6 marks)

(b) After block B is already placed, the connections need to be routed. (If you didn’t get
any answer for part (a), you may assume any location for B, except blocks labeled X,
A and C.)

(i) Draw the resource routing graph. Include only the relevant resources.
(8 marks)

(ii) Determine the routes for all the connections. Assume that the switches may be
over-used.
(6 marks)

END OF PAPER