Verilog A Users

Verilog-A
User’s Manual Draft
SILVACO International January 2004

4701 Patrick Henry Drive, Bldg. #2
Santa Clara, CA 95054
Telephone: (408) 567-1000
FAX: (408) 496-6080
Verilog-A
User’s Manual
Copyright 2004
SILVACO International
4701 Patrick Henry Drive, Building #2
Phone: (408) 567-1000

FAX: (408) 496-6080
E-Mail: support@silvaco.com
Internet: www.silvaco.com
ii SILVACO International
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SILVACO International iii

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iv SILVACO International
Preface
This manual describes SILVACO VERILOG®-A language, the analog subset of the Verilog-AMS version 2.0
language (IEEE 1364). VERILOG-A belongs to the "Analog Hardware Description Language" (AHDL)
class of computer languages. AHDLs are intended to help design analog systems in high level
behavioral forms for continuous systems.
The SMARTSPICE VERILOG-A INTERFACE provides the capability to include in a netlist one or several
modules described in VERILOG-A.
Requirements
The VERILOG-A INTERFACE is supported on the following UNIX platforms: Sun Solaris 2.7 and 2.8, Red
Hat linux 7.3 and HP 11.0. VERILOG-A is also supported on Windows NT 4.0, Windows 2000 or XP. On
the UNIX platforms, a C compiler (the gcc compiler, 2.8.1 or 2.95.3, or the SUN C compiler, SC4 or
SC6) could be be used in the VERILOG-A simulation flow for a speedup purpose. The intention of this
manual is not to explain in detail all the features of the VERILOG-A language. For further information,
the reader should consult the LANGUAGE REFERENCE MANUAL OF VERILOG-A, version 2.0 provided by
Accellera (formerly OVI).
Typographic and Syntax Conventions
Typographical conventions are used to emphasize or distinguish certain kinds of text in this manual.
The formal syntax used in this document uses the definition operator, := , to define and describe the
elements of the VERILOG-A language.
• Lowercase words represent syntactic categories. For example:
module_declaration
• Some names begin with a part that indicates how the name is used. For example:
node_identifier
represents an identifier that is used to declare or reference a node.
• Boldface words represent elements of the syntax that must be used exactly as presented. Such
items include keywords, operators, and punctuation marks. For example:
endmodule
• Vertical bars indicate alternatives. One can choose to use any one of the items separated by the
bars. For example:
attribute ::=
abstol
| access
| ddt_nature
| idt_nature
| units
| huge //Vendor compactibility specific
| blowup //Vendor compactibility specific
| identifier
• Square brackets enclose optional items. For example,
input declaration ::=
input [ range ] list_of_port_identifiers ;
• Braces enclose an item that can be repeated zero or more times. For example,
list_of_ports ::=
( port { , port } )
• Code examples are displayed in Courier font.
/* This is an example of Courier font.*/
SILVACO International v
• Within the text, the variables are in Courier italic.
This is Courier italic font.
• Within the text, the keywords, filenames, names of natures, and names of disciplines are set in
Courier font, like this:
keyword, file_name, name_of_nature, name_of_discipline.
• If a statement is too long to fit on one line, the remainder of the statement is indented on the next
line, like this:
egfet = 1.16-(7.02e-4*$temperature*$temperature)
/($temperature+1108);
vi SILVACO International
Table of Contents
Chapter 1:
Modeling Analog System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1: Modeling with the Verilog-A Language Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2: Representing a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2.1: Nets and nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.3: Verilog-A Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.4: Conservative Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.4.1: Kirchhoff’s Laws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.4.2: Reference Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4.3: Reference Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.5: Signal-Flow Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.6: Mixed Conservative and Signal-Flow Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2:
Makeup of Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2: Declaring Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3: Declaring the Module Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3.1: Module Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3.2: Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3.3: Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4: Structural Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4.1: Module Instantiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.5: Behavioral Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.5.1: Defining Analog Behavior with Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.5.2: Using Integration and Differentiation with Analog Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.6: Using Internal Nodes in Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.6.1: Using Internal Nodes in Behavioral Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.6.2: Using Internal Nodes in Higher Order Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Chapter 3:
Lexical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1: Lexical Tokens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2: White Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.3: Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.4: Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.5: Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.5.1: Integer Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.5.2: Real Constants. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.6: Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.6.1: Special Characters in Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.7: Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.7.1: Ordinary Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.7.2: Escaped Identifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
SILVACO International TOC-vii

Verilog-A User’s Manual
3.8: Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.9: System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.10: Compiler Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Chapter 4:
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1: Integer Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2: Real Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2.1: Converting Real Numbers to Integer Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.3: Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3.1: A Parameter Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3.2: Permissible Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3.3: Parameter Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3.4: Genvars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4: Natures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.4.1: Base Nature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.4.2: Derived Nature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.5: Disciplines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.5.1: Binding Natures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.5.2: Compatibility of Disciplines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.5.3: Multi-Disciplinary Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.5.4: Empty Disciplines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.5.5: Discipline of Wires and Undeclared Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.5.6: Overriding Nature Attributes From Discipline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.5.7: Deriving Natures From Disciplines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.5.8: Ground Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.6: Net Disciplines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.7: Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.8: Implicit Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Chapter 5:
Statements for the Analog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1: Analog Procedural Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.1: Block Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.2: Procedural Assignment Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2: Sequential Block Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3: Conditional Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.1: Analog Conditional Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.4: Case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.4.1: Analog Case Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.4.2: Constant Expression in Case Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.5: Looping Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.5.1: Repeat and While Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.5.2: For Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.6: Analog Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.7: Signal Access Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.8: Probes and Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.8.1: Probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.8.2: Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.8.3: The four controlled sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
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Table of Contents
5.8.4: Behavioral Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.8.5: Resistor and Conductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.8.6: RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.8.7: Simple Implicit Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.8.8: Port Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.9: Switch Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.9.1: Unassigned Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.10: Signal Access for Vector Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.10.1: Accessing Net and Branch Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.10.2: Accessing Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.11: Contribution Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.11.1: Branch Contribution Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.11.2: Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.11.3: Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.11.4: Value Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.11.5: Indirect Branch Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.11.6: Multiple Indirect Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5.11.7: Indirect Assignments and Contributions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Chapter6:
Expressions and Operators for Analog Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1: Overview of Expressions and Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2: Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2.1: Operators With Real Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.2: Real to Integer Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.3: Arithmetic Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.4: Binary Operator Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.5: Expression Evaluation Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.6: Arithmetic Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.7: Relation Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.8: Case Equality Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.9: Logical Quality Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.10: Logical Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.2.11: Bit-Wise Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.2.12: Shift Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.2.13: Ternary Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.2.14: Event OR Operator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.2.15: Concatenations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.3: Analog Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.3.1: Restrictions To Analog Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.3.2: Vector or Array Arguments To Analog Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.3.3: Analog Operators and Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.3.4: Time Derivative Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.3.5: Time Integral Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.3.6: Circular Integrator Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.3.7: Absolute Delay Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.3.8: Transition Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.3.9: Slew Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6.3.10: last_crossing function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.11: Laplace Transform Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.12: Z-Transform Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
6.3.13: Limited Exponential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
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Chapter7:
Built-In Mathematical Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1: Standard Mathematical Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2: Trigonometric and Hyperbolic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Chapter 8:
Analog Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1: Detecting and Using Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1: Event Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2: Event OR Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.3: Event Triggered Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.4: Global Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.5: Monitored Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Chapter 9:
Simulator Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1: Analysis Dependent Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.1: Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.2: AC stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.1.3: Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2: Discontinuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3: Bounding the Time Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.4: Querying the Simulation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.4.1: Obtaining Current Simulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.4.2: Obtaining the Current Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.4.3: Obtaining the Thermal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.5: Generating Random Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.6: Generating Random Numbers in Specified Distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.6.1: Uniform Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.6.2: Normal (Gaussian) Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.6.3: Exponential Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.6.4: Poisson Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.6.5: Chi-Square Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.6.6: Student’s T Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.6.7: Erlang Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9.7: Silvaco System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.7.1: $sit_get_prev . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.7.2: $sit_get_ddv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.8: Displaying Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9.9: Specifying Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.10: Working with Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.10.1: Opening a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.10.2: Special $fopen Formatting Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9.10.3: Writing to a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
9.10.4: Closing a File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9.11: User-Defined Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9.11.1: Declaring an Analog User-Defined Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9.11.2: Returning a Value from a User-Defined Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
9.11.3: Calling a User-Defined Analog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
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Table of Contents
Chapter 10:
Instantiating Modules and Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1: Instantiating Verilog-A Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1: Creating and Naming Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.2: Mapping Instance Ports to Module Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.2: Connecting the Ports of Module Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.1: Port Connection Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.2: Multilevel Hierarchal Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.3: Overriding Parameter Values in Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3.1: Overriding Parameter Values from the Instantiation Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.4: Instantiating Analog Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.1: B device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.2: C device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.3: D device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.4.4: E,F,G,H devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.4.5: I, V devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.4.6: J device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.4.7: K, L devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.4.8: M device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.4.9: O device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.4.10: Q device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.4.11: R device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.4.12: S device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.4.13: T device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.4.14: U device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.4.15: W device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.4.16: SPICE Model Card Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.4.17: SPICE Subcircuit Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.4.18: Instantiating Analog Primitives that Use Array Valued Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10.4.19: Instantiating Modules that Use Unsupported Parameter Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
Chapter 11:
Grammer Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Chapter 12:
Standard Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1: “discipline.h” content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.1: "Constants.h" file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Chapter 13:
The SmartSpice Verilog-A Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1: Choosing the SILVACO C-INTERPRETER or a third-party C compiler . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2: The SmartSpice Verilog-A interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2.1: New Verilog-A Language Features Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2.2: Attributes HUGE, BLOWUP, MAXDELTA (Cadence Compatibility) . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.2.3: The power function: $pwr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.2.4: The mathematical functions: hypot(x,y) and atan2(x,y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.2.5: Analysis Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.2.6: Usage of the .PRINT and .PLOT Smartspice commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.2.7: Usage of the command .MODIF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
SILVACO International TOC-xi

13.2.8: Usage of the command .ST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.3: The Verilog-A compiler configuration file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.4: The .verilog card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.5: Module instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.6: Model Card with Verilog-A module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.7: The Smartspice Verilog-A interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.7.1: DLL support for Windows platforms with the compiler VC++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.8: Verilog-A error and warning messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.8.1: Parsing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.8.2: Parsing warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.8.3: Simulation errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
13.8.4: Simulation Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
Chapter 14:
Device Modeling in Verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1: Device Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2: MOSFET Model Tutorial for Verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.2.1: MOSFET Model Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.3: Temperature Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
14.3.1: Temperature Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
14.3.2: DC Current Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
14.3.3: Capacitance Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
14.4: MOSFET Model LEVEL=3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.4.1: Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.4.2: MOS_LEVEL 3 Verilog-A Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.4.3: EKV MOSFET Model - using Silvaco Verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.5: EKV MOSFET Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.5.1: Geometry Device Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.5.2: Effective Channel Length and Width Calculations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.5.4: Handling of LEVEL 2/3 Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
14.5.5: Temperature Compensation Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
14.5.6: DC Current Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
14.5.7: Charge Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
14.5.8: Noise Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
14.6: Berkeley BSIM3v3 MOSFET Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
14.6.1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
14.6.3: Effective Channel Length and Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39
14.6.4: Temperature Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39
14.6.5: I-V Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
14.6.6: Capacitance Model Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-44
14.6.7: NQS Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-54
14.7: Berkeley MOSFET Model BSIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-55
14.7.1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-55
14.7.2: Instance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-55
14.7.3: Effective Channel Length and Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-66
14.7.4: Gate Dielectric Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-67
14.7.5: Temperature Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-67
14.7.6: I-V Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-69
14.7.7: Capacitance Model Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-77
14.7.8: Asymmetric MOS Junction Diode Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-79
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Table of Contents
14.7.9: Source/Drain Diffusion Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-81

14.8: BJT Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-82
14.8.1: Gummel-Poon BJT Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-82
14.9: Mextram Transistor Model (LEVEL=504) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-90
14.9.1: Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-91
14.9.2: Model constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-93
14.9.3: Temperature scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-94
14.9.4: Geometry scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-96
14.9.5: DC current Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-97
14.9.6: Description of charges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-103
14.9.7: Extended Modeling of the Reverse Current Gain EXMOD = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-106
14.9.8: Distributed High Frequency Effects In the Intrinsic Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-108
14.9.9: Heterojunction features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-109
14.9.10: Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-109
14.9.11: Self-heating feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-110
14.10: The HICUM Bipolar Transistor Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-111
14.10.1: Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-112
14.10.2: Temperature Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-119
14.10.3: DC Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-122
14.10.4: Description of Charges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-126
14.11: The VBIC Bipolar Transistor Model (LEVEL=5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 14-130
14.11.1: VBIC Model Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-130
14.11.2: DC Current Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-136
14.11.3: Charge and Capacitance Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-141
14.11.4: Excess Phase Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-144
14.11.5: Temperature Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-144
14.12: Interfacing Verilog-A Compact Model Code to the Input Deck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-148
14.13: .MODEL Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-148
14.14: Compiling Verilog-A Compact Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-149
14.15: Interfacing Verilog-A Compact Model Code to a Schematic Symbol . . . . . . . . . . . . . . . . . . . . . . . . 14-149
14.16: Declaring Verilog-A Modules Within a SmartSpice Input Deck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-150
Chapter 15:
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1: Digital circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.1: Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.2: Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.1.3: Nand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.1.4: NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.1.5: EXOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.1.6: DFF (D-type Flip Flop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
15.1.7: 4bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
15.1.8: 4bit Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.2: Analog Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
15.2.1: LPF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
15.2.2: HPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20
15.2.3: BPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
15.3: Analog Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
15.3.1: OPAMP (Operational Amplifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
15.3.2: Sample hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26
15.3.3: ADC (Pipelined ADC and user defined resolution). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28
15.3.4: ADC to DAC Example: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33
SILVACO International TOC-xiii

15.3.5: Delta-Sigma Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34

15.4: Example 1: DFF with Spice Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-36
15.5: Simulation with SmartSpice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39
15.6: Example 2: PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41
TOC-xiv SILVACO International

Chapter 1:
Modeling Analog System
1.1: Modeling with the Verilog-A Language Overview

The VERILOG-A language is a high-level Analog Hardware Description Language (AHDL) that uses
modules as the basic component to describe the structure and behavior of analog systems and their
components. With the analog statements of VERILOG-A, one can describe a wide range of conservative
systems and signal-flow systems; such as electrical, mechanical, fluid dynamic, and thermodynamic
systems. To simulate systems that contain VERILOG-A components, the user must have a VERILOG-A
license and the SMARTSPICE SIMULATOR installed on their system.
To describe a system, the user must specify both the structure of the system, and the behavior of its
components. In VERILOG-A with the SMARTSPICE CIRCUIT SIMULATOR, the user defines structures at
different levels. At the highest level, the user can define the overall system structure in a netlist. At
lower, more specific levels, the user can define the internal structure of modules by defining the
interconnections among submodules.
1.2: Representing a System

A system is a collection of interconnected components that when acted upon by a stimulus produce a
response. A hierarchical system is a system in which the components are also systems. A primitive
component (leaf component) is a component that has no subcomponents. Each primitive component
connects to zero or more nets. Each net connects to a signal which can traverse multiple levels of the
hierarchy. The behavior of each component is defined in terms of the values of the nets to which it
connects. The VERILOG-A language allows analog and mixed-signal systems to be described by a set of
components or modules.
A signal is a hierarchical collection of nets which, because port connections, are contiguous. The nets
for a signal are in the discrete domain called a digital signal. The nets that make up a signal are in the
continuous domain; the signal is an analog signal. The net that consists of signals from the continuous
and discrete domains is called a mixed signal.
The components interconnect through ports and nets to build a hierarchy, as illustrated in Figure 1-1.
1.2.1: Nets and nodes

Nets in VERILOG-A connect analog signals that are assigned values from a continuous domain. A node is
a point of physical connection between nets of continuous-time descriptions. Analog signals are also
referred to as nodes.
Nodes obey conservation-law semantics.
SILVACO International 1-1

Verilog-A User’s Manual Draft
Figure 1-1: Nets and Nodes
1.3: Verilog-A Systems

Two types of analog systems can be described with VERILOG-A: conservative and signal-flow systems. A
conservative type of system, which includes those described by conventional spice, incorporates a set of
constraints within the system that insures conservation of changes, fluxes, etc. within the system.
Signal flow systems employ a different level of formulations, which focuses only on the propagation of
signals throughout the system.
1-2 SILVACO International

Modeling Analog System
1.4: Conservative Systems

A conservative system is a system where two values are assigned to every node: a potential value and
a flow value. The potential of a node is shared by all ports and nets connected to it. The flow of a node
is such that the sum of all continuous nodes are equal to zero. For this reason, the conservation laws,
such as Kirchoff ’s Potential Law (KPL) and Kirchoff’s Flow Law (KFL), can be applied to every node.
KPL and KFL are generalizations of KVL and KCL for electrical systems which allow the conservation
laws to be applied to any conservative system.
Conservative Systems Electrical Systems
KPL KVL
KFL KCL
1.4.1: Kirchhoff’s Laws

In formulating continuous system equations, VERILOG-A uses two sets of relationships. The first are the
constitutive relationships which describe the behavior of each component. Constitutive relationships
can be kept inside the simulator as built-in primitives, or they can be provided by VERILOG-A’s module
definitions.
The second set of relationships, interconnected relationships, describe the structure of the network.
Interconnected relationships, which contain information on how the components are connected to each
other, are only a function of the system topology. They are independent of the nature of the
components.
SMARTSPICE VERILOG-A simulator uses Kirchhoff ’s Laws to define the relationships between the nodes
and the branches. Kirchhoff ’s Laws are typically associated with electrical circuits that relate voltages
and currents. However, by generalizing the concepts of voltages and currents to potentials and flows,
Kirchhoff ’s Laws can be used to formulate interconnection relationships for any type of system.
Kirchhoff ’s Laws provide the following properties relating the quantities present on nodes and
branches, as shown in Figure 1-2.
• Kirchhoff ’s Flow Law (KFL): The algebraic sum of all flows out of a node at any instant is zero (0).
• Kirchhoff ’s Potential Law (KPL): The algebraic sum of all the branch potentials around a loop at
any instant is zero (0).
These laws imply a node is infinitely small; so there is negligible difference in potential between any
two points on the node and a negligible accumulation of flow.

Figure 1-2: Kirchhoff’s Flow Law (KFL) and Potential Law (KPL)
1.4.2: Reference Nodes

The potential of a single node is defined with respect to a reference node. The reference node, called
ground in electrical systems, has a potential of zero.
1.4.3: Reference Directions

Each branch has a reference direction for the potential and flow. For example, consider the following
schematic. With the reference direction shown, the potential in this schematic is positive whenever the
potential of the terminal marked with a plus sign is larger than the potential of the terminal marked
with a minus sign. VERILOG-A uses associated reference directions. Consequently, a positive flow is
defined as one that enters the branch through the terminal marked with the plus sign, and exits
through the terminal marked with the minus sign.
1.5: Signal-Flow Systems

Signal-flow systems associate only a single value with each node. As a result, a signal-flow port must
be unidirectional. If the component has two ports, one port is the input and the other one must be the
output.
1.6: Mixed Conservative and Signal-Flow Systems

One can model systems that contain a mixture of conservative nodes and signal-flow nodes, when
practicing the top-down design cycle. It allows the flexibility for the designers to initially use signal-
flow models easily in the design cycle, and gradually convert component models to conservative forms
as the design progresses.

Chapter 2:
Makeup of Modules
2.1: Overview
This chapter introduces the concept of modules. A VERILOG-A module can be divided into 3 parts:
• The first part is an interface declaration that includes port signal declarations (the connection
points of the module) and parameter declarations (characterization of the behavior of the
component).
• The second part is the structural description that defines the connection with sub-components.
Every module can instantiate other modules, referred to as child modules. This instantiation
mechanism allows an hierarchical organization of a system through its parametric specifications
and connections.
• The third part is a behavioral description that defines relations or equations between the input
signals of the module and the output signals.
Verilog-A Module
module res(in, out);
// port declarations
inout in,out;
electrical in, out; interface declaration
// parameter declarations
parameter real R = 1;
// structural description
<module instantiation structural description
statements>
// behavioral description
analog begin
<analog behavioral statements>
behavioral description
end
endmodule // end module res
The following example defines a temperature compensated resistor to illustrate the form of a module.
The entire module is enclosed between the keywords module and endmodule.
Interface declarations:
module resistor(p, n);
inout p, n; | port signal declarations
electrical p, n; |
parameter real r=100 from (0:inf); | parameter declarations

parameter real tc=1.8 from [0:3); |

Behavioral description:
real rtc;
analog begin
@(initial_step) begin
rtc = r*(1+tc*$temperature);
end
I(p, n) <+ V(p, n)/rtc;
end
endmodule
2.2: Declaring Modules

The following syntax is used to declare a module:
module_declaration ::=
module_keyword module_identifier [ ( list_of_ports ) ] ;
[ module_items ]
endmodule
module_keyword ::=
module
| macromodule
module_items ::=
{ module_item }
| analog_block
module_item ::=
module_item_declaration
| module_instantiation
module_item_declaration ::=
parameter_declaration
| input_declaration
| output_declaration
| inout_declaration
| ground_declaration
| integer_declaration
| net_discipline_declaration
| real_declaration
module_identifier: The name of the module being declared.

list_of_ports: An ordered list of the module’s ports.
module_items: The different types of declarations and definitions.

Makeup of Modules
2.3: Declaring the Module Interface

Use the module interface declarations to define:
• Name of the module
• Ports of the module
• Parameters of the module
For example, the module interface declaration declares a module named resistor, ports named p and
n, and a parameter of type real named r.
inout p, n;
electrical p, n;
parameter real r = 50;
2.3.1: Module Name

To define the name for a module, put an identifier after the keyword module. Input and output ports
are listed in parentheses following the identifier. Multiple parts are separated by commas.
module capacitor(.., ..);
2.3.2: Ports
To declare the ports used in a module, use port declarations. To specify the type and direction of a port,
use the related declarations described in this section.
list_of_ports ::=
port { , port }
port ::=
port_expression
port_expression ::=
port_identifier
| port_identifier [ constant_expression ]
| port_identifier [ constant_range ]
constant_range ::=
msb_constant_expression : lsb_constant_expression
Example
module and(in1, in2, out); // define three ports

Port Type
To declare the type of a port, use a net discipline declaration in the body of the module. If the user does
not declare the type of a port, they can only use the port in a structural description. In other words, a
user can pass the port to module instances, but cannot access the port in a behavioral description.
Ports declared as vectors must use identical ranges for the port type and port direction declarations.
Examples
electrical out, in1, in2; // types of ports
voltage P, N; // types of ports
m1 and1(out1, ina, inb); // module instantiation (section 2.4.1)
capacitor #(1u) C1(out, ref); // module instantiation (section 2.4.1)
Port Direction
The user must declare the port direction for every port in the list of port sections of the module
declaration. To declare the direction of a port, use one of the following three syntaxes.
input_declaration ::=
input [ range ] list_of_port_identifiers ;
output_declaration ::=
output [ range ] list_of_port_identifiers ;
inout_declaration ::=
inout [ range ] list_of_port_identifiers ;
range ::=
[ constant_expression : constant_expression ]
input: Declares that the signals on the port cannot be set. Input signals can be used in expressions.
output: Declares that the signals on the port can be set. Output signals cannot be used in expressions.
inout: Declares that the port is bidirectional. The signals on the port can be both set and used in
expressions. inout is the default port direction.
Port Declaration Example

Conservative signals:
module conservative(a, b);
inout a, b; Ports a, b used on both sides (bidirectional)
electrical a, b;
analog
V(a, b) <+ I(a, b)*R;
endmodule

Makeup of Modules
Signal-flow signals:
module signal_flow(out, in);
voltage out, in;
output out; out port used for source
input in; in port used for probe
parameter real gain = 8.0;
analog
V(out) <+ gain*V(in);
endmodule
2.3.3: Parameters
With parameter declarations, the user specifies parameters that can be changed when a module is
used as an instance in a design. Using parameters allows each instance to be customized.
For each parameter the user must specify a default value, and can also specify an optional type and an
optional valid range.
Syntax
Optional type specifier Optional range specification

Parameter Parameter name =
real default value expression from or exclude
or (or[ lower bound : upper bound ]or)
integer
Examples
parameter real R0 = 1.0;
parameter real P0 = 1.0 from (0:inf);
parameter integer ip0 = 2 exclude 0;
parameter real t0 = 1.0 from (0:10];
parameter t2 = 5.0;
parameter real t3 = 4;
In all cases, the lower bound range must be numerically smaller than the upper bound range. For more
information of the parameter declarations, please see "Chapter 4:" "Data Types".

The following example illustrates how to declare parameters and variables in a module.
module diode(p, n);

Module interface inout p, n;
declarations electrical p, n;
parameter real area=4;

parameter real is=1e-14;
parameter real z=2 from (0:10);
Parameter declarations parameter real cjo=0;
parameter real m=0.5;
parameter real phi=0.7;
parameter real t_t=1p;
real vd, id, qd; //Internal variables

(local variables)
analog begin
vd = V(p, n);
id = area*is*(exp(vd/(z*$vt)) - 1);
qd = t_t*id + area*vd
Behavioral description *cjo/pow((1 - vd/phi), m);
I(p, n) <+ id + ddt(qd);
end
endmodule
Module diode has a parameter area that defaults to 4. If area is not specified for an instance, it
receives a value of 4. Similarly, the other parameters: is, n, cjo, m, phi, and t_t, have specified
default values too.
Module diode also defines three local variables: vd, id, and qd.

Makeup of Modules
2.4: Structural Descriptions

A structural description in VERILOG-A is any description in which a module instantiates another
module within its definition. A structural description of the system will connect to one or more signals
of each module through the module’s ports or connection points.
2.4.1: Module Instantiations

Instantiation allows one module to duplicate another module into itself by instantiating it. When one
module instantiates another, it can modify the values of any parameters declared within the
instantiated module, as following:
• Module instance parameter value assignment by port order, called positional association of
module parameter. Positional and order are used interchangeably in this manual.
• Module instance parameter by port name, called named association of module parameters.
The general format of module instantiation:

mod_name <#(param_assigns)> inst_name(port_assigns)
where param_assigns (or parameter name in child module) and port_assigns can be either by
positional(ordered) or name associated, and they cannot be mixed within a module
instantiation.
Positional (Ordered) Association and Assignment of Parameters

The following example will illustrate the positional (ordered) connections of module instantiation.
Example
//module interface declarations for 4 bit A/D
module a2d(d0, d1, d2, d3, in, clk);

input in, clk; //direction of ports
output d0, d1, d2, d3;
electrical in, clk; //type of ports
electrical d0, d1, d2, d3;
parameter real vrange = 1.0; //default parameter #1

parameter real tdel = 10n; //default parameter #2
parameter real trise = 10n; //default parameter #3
parameter real tfall = 10n; //default parameter #4
...
endmodule
//module interface declarations for 4 bit D/A
module d2a(d0, d1, d2, d3, in, clk);

output out; //direction of ports

input d0, d1, d2, d3, clk;
electrical out; //type of ports
electrical d0, d1, d2, d3, clk;
parameter real vthresh = 0.7; //default parameter #1

parameter real tdel = 10n; //default parameter #2
parameter real trise = 10n; //default parameter #3
parameter real tfall = 10n; //default parameter #4
...
endmodule
module sum(out, posin, negin);

inout out, posin, negin;
electrical out, posin, negin;
...
endmodule
module gain(out, in);

inout out, in;
...
endmodule
//structural instantiations of all child modules
module sub_a2d(bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, in, clock);
output bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7;
input in, clock;
electrical bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7;
electrical in, clock;
//internal signals
electrical a_out, rem_out, gain_out;
//structure instantiation for new parameter and port orders

a2d #(.vrange(5.0)) //assigned of new parameter vrange = 5.0
lsb_a2d(bit0, bit1, bit2, bit3, gain_out, clock),
msb_a2d(bit4, bit5, bit6, bit7, in, clock);
//structure instantiation for new parameter and port orders

d2a #(.vthresh (2.5)) //assigned of new parameter vrange = 2.5
convtr(aout, bit4, bit5, bit6, bit7, clock);

Makeup of Modules
//structure instantiation for port orders only

sum sum1(rem_out, aout);
gain gain1(gain_out, rem_out);
endmodule
Since vrange = 1.0 is parameter #1 and tdel = 10ns is parameter #2, respectively,
one can rewrite structure instantiation with the new assigned parameter as:
a2d #(5.0)
or can rewrite if all four parameters need to be assigned by their positional orders:
a2d #(5.0, 10n, 15n, 15n)
where port orders of child modules lsb_a2d and msb_a2d are corresponding to ports in the parent
module a2d:
a2d (d0, d1, d2, d3, in, clk);
lsb_a2d (bit0, bit1, bit2, bit3, gain_out, clock),
msb_a2d (bit4, bit5, bit6, bit7, in, clock);
Name Association
In addition to ordered or positional association, name association can also be applied.
Example
a2d #(5.0, 10n)
can be written as:

a2d #(.vrange(5.0), .tdel(10n))
lsb_a2d(.d0(bit0), .d1(bit1), .d2(bit2), .d3(bit3), .in(gain_out),
.clk(clock)),
msb_a2d(.d0(bit4), .d1(bit5), .d2(bit6), .d3(bit7), .in(in),
.clk(clock));
For more examples of module instantiation, see "Chapter 10:" "Instantiating Modules and
Primitives".

2.5: Behavioral Descriptions

The behavioral characteristics of a module are defined within an analog block.
analog_block ::=
analog statement
statement ::=
null_statement
| block statement
| branch_contribution
| Indirect_branch_assignment
| procedural_assignment
| conditional_statement
| loop_statement
| case_statement
| generate_statement
| event_controlled_statement
| discontinuity_function
| bound_step_function
| last_crossing_function
| system_task_enable
analog statement can only appear within the analog block. The syntax for a block is the following:
block_statement ::=
begin [ : block_identifier
{ block_item_declaration } ]
{ statement }
end
In the analog block, it is possible code contribution statements with the contribution operator (<+) that
define relationships among analog signals in the module.
Example
output_signal <+ f(input_signal);
V(n1, n2) <+ expression;

I(n1, n2) <+ expression;
where output_signal is a branch of potential and flow sources of V(n1,n2) and I(n1,n2),
respectively. It is possible to define f(input_signal) expression to be any combination of linear,
nonlinear, algebraic, or differential expressions involving module signals, constants, and parameters.
The modules that are written can contain at most a single analog block. When an analog block is used,
the user must place it after the interface declarations and local declarations.
The following module, which produces the sum and product of its inputs, illustrates the form of the
analog block. Here the block contains two contribution statements.

Makeup of Modules
Example
module summult(in1, in2, outsum, outmult);
input in1, in2;
output outsum, outmult;
voltage in1, in2, outsum, outmult;
analog begin
V(outsum) <+ V(in1) + V(in2);
V(outmult) <+ V(in1) * V(in2);
end
endmodule
Module dcvolts illustrates an analog block containing a single statement:

module dcvolts (outvolt);
output outvolt;
voltage outvolt;
analog
V(outvolt) <+ 5.0;
endmodule
2.5.1: Defining Analog Behavior with Control Flow

The user can also incorporate conditional control flow into a module. With control flow, it is possible to
define the behavior of a module in regions.
The following module, for example, describes a voltage deadband amplifier vdba. If the input voltage
is greater than vin_high or less than vin_low, the amplifier is active. When the amplifier is active,
the output is gain times the differential voltage between the input voltage and the edge of the
deadband. When the input is in the deadband between vin_low and vin_high, the amplifier is
quiescent and the output voltage is zero.
module vdba(in, out);

input in;
output out;
electrical in, out;
parameter real vin_low = -1.0;
parameter real vin_high = 1.0;
parameter real gain = 1 from (0:inf);
analog begin
if (V(in) >= vin_high)
V(out) <+ gain*(V(in) - vin_high);
else if (V(in) <= vin_low)
V(out) <+ gain*(V(in) - vin_low);
else
V(out) <+ 0;
end
endmodule

2.5.2: Using Integration and Differentiation with Analog Signals

The relationships defined among analog signals can include time domain differentiation and
integration. VERILOG-A provides a time derivative function, ddt, and two time integral functions, idt
and idtmod, that can be used to define such relationships. For example, a user might write a
behavioral description for an inductor as follows:
V L = Ldi ⁄ dt
∫
1
iL = ---- V ( p, n ) dt
L
0
Figure 2-1: Inductor model and reference direction
module inductor(p, n);

inout p, n;
electrical p, n;
parameter real L = 0.1u from [0:inf];
analog begin
V(p, n) <+ L * ddt(I(p, n));
I(p, n) <+ idt(V(p, n))/L;
end
endmodule
In module inductor, the voltage across the external ports of the component is defined as equal to the
L times the derivative of the current flowing between the ports, and its current is equal to the integral
of voltage divided by L.
To define a higher order derivative, the user must use an internal node or signal. For example, module
deriv_2 defines internal node n1, and sets V(n1) equal to the derivative of V(in). Then the
module sets V(out) equal to the derivative of V(n1), in effect taking the second order derivative of
V(in).
module deriv_2(in, out);

input in;
output out;
electrical in, out;
electrical n1; // Defines an internal node with electrical properties.
parameter real scale = 1e-6;
analog begin
V(n1) <+ scale*ddt(V(in));
V(out) <+ scale*ddt(V(n1));
end
endmodule

Makeup of Modules
Note: If scale is not specified, the output of the module would be in magnitude of 1e6 due to a fast varying “noise” component
of differentiating an unknown input signal.
For time domain integration, use the idt or idtmod functions, as illustrated in module
integrator.
module integrator(in, out);

input in;
output out;
electrical in, out;
parameter real scale = 1e-6;
analog begin
V(out) <+ idt(scale*V(in), 0);
end
endmodule
Module integrator sets the output voltage to the integral of the input voltage. The second term in
the idt function is the initial condition. Without initial condition, idt must be used in a
system description with feedback that forces its argument to zero; it is possible that convergence will
not likely be achieved.

2.6: Using Internal Nodes in Modules

Using VERILOG-A, the user can implement complex designs in a variety of different ways. For example,
it is possible to define behavior in modules at the leaf level, and use the netlist to define the structure
of the system. The user can also define structure within modules by defining internal nodes. With
internal nodes, you can directly define behavior in the module, or introduce internal nodes as a means
of solving higher order differential equations that define the network.
2.6.1: Using Internal Nodes in Behavioral Definitions

Consider the following RLC circuit.
Figure 2-2: RLC circuit
Module rlc uses an internal node Tmp and the ports in, ref, and out, to directly define the
behavioral characteristics of the RLC circuit. Notice how Tmp does not appear in the list of ports for
the module.
module rlc(in, out, ref);

inout in, out, ref;
electrical in, out, ref;
parameter real R=1, L=1, C=1;
electrical Tmp;
analog begin
V(in, Tmp) <+ R*I(in, Tmp);
V(Tmp, out) <+ L*ddt(I(Tmp, out));
I(out, ref) <+ C*ddt(V(out, ref));
end
endmodule
The following code shows a structural description of an RLC circuit with the new parameter
assignments. There are three module instantiations inside the module rlc. The module resistor is
instantiated with an instance named R1, the module inductor with an instance name L1, and the
module capacitor with an instance name C1.
// Verilog-A module:
‘include “discipline.h”

input in, ref;
output out;

Makeup of Modules

electrical Tmp;
resistor #(200) R1(in, Tmp);

inductor #(125m) L1(Tmp, out);
capacitor #(1u) C1(out, ref);
endmodule // rlc
in out ref
module rlc
Tmp
in out in out in out

resistor inductor capacitor
instance R1 instance L1 instance C1
Figure 2-3: RLC module hierarchy
Where the resistor, inductor and capacitor modules are:
res.va:
//Resistor

input p, n;
electrical p, n;
parameter real R=1.0 from (0:inf];
analog begin
V(p, n) <+ R*I(p, n);
end
endmodule

ind.va:
//Inductor
module inductor(p, n);

input p, n;
electrical p, n;
parameter real L=0 from (0:inf];
analog begin
V(p, n) <+ L*ddt(I(p, n));
end
endmodule
cap.va:
//Capacitor
module capacitor(p, n);

input p, n;
electrical p, n;
parameter real C=0 from (0:inf];
analog begin
I(p, n) <+ C*ddt(V(p, n);
end
endmodule
and the SMARTSPICE Netlist is:

*****VERILOG-A/AMS RLC CIRCUIT
.verilog “ind.va”
.verilog “cap.va”
.verilog “res.va”
*voltage sources
vin in 0 sin (0 5 10e06 0 0)
* Verilog-A rlc module instantiation for model card

YVLGresistor in Tmp paramsR
YVLGinductor Tmp out paramsL
YVLGcapacitor out 0 paramsC

Makeup of Modules
*Analysis
.tran 1n 800n
.options POST opts nomod probe
*output data
.print V(in) V(out)
*create a VLG model card

.model paramsR VLG MODULE = resistor
+ R=100
.model paramsC VLG MODULE = capacitor
+ C=10p
.model paramsL VLG MODULE = inductor
+ L=10uh
.end
Note: The parameter values in the model card will override the previous parameters.
Figure 2-4: RLC Waveforms

2.6.2: Using Internal Nodes in Higher Order Systems

The user can also represent the RLC circuit by its governing differential equations. The transfer
function is given by:
1 Vout
H ( s ) = -----------------------------------------
- = --------------
2
LCs + RCs + 1 Vin
In the time domain, this becomes:

2
dVout d Vout
Vout = Vin – R ⋅ C ⋅ ------------------ – L ⋅ C -------------------
-
dt dt
2
If one set:
dVout
V ( TMP ) = ------------------
dt
one can write:
dV ( TMP )
Vout = Vin – RC ⋅ V ( TMP ) – L ⋅ C ---------------------------
dt
Module rlc then becomes:

inout in, out, ref;
parameter real R=1, L=1, C=1;
electrical Tmp;
analog begin
V(Tmp, ref) <+ ddt(V(out, ref));
V(out, ref) <+ V(in) - (R*C*V(Tmp) - L*C*ddt(V(Tmp));
end
endmodule

Chapter 3:
Lexical Conventions
3.1: Lexical Tokens

A SMARTSPICE VERILOG-A source file (module_name.va) is a stream of lexical tokens. Lexical tokens
consist of one or more characters. The source file is a free format where spaces and newlines are not
syntactically significant, other than being token separators.
Lexical tokens for VERILOG-A are:
• White Space
• Comments
• Operators
• Numbers
• Strings
• Identifiers
• Keywords
• System Tasks and Functions
• Compiler Directories
3.2: White Space

White space consists of blanks, tabs, new-line characters, and form feeds. VERILOG-A ignores these
characters except in strings or when they separate other lexical tokens. For example, this code
fragment:
@(cross(V(Vctr 1p, Vctr 1n)

- Vth, 0.0, 1.0u));
is syntactically identical to:
@(cross(V(Vctr 1p, Vctr 1n) - Vth, 0.0, 1.0u));

3.3: Comments
Verilog-A has two forms to introduce comments. A one_line comment starts with the two characters //
and end with a new line. Block comments start with /* and end with */. Block comments cannot be
nested. The one_line comment token // does not have any special meaning in a block comment.
short_comment ::=
// {any_ASCII_characters_except_end_of_line} \n
// This is a one_line comment
long_comment ::=
/* {any_ASCII_character} */
/* This is a block comment or multiple line

comment */
/* This is /* an illegal */ comment */
3.4: Operators
Operators are single, double, or triple character sequences used in expressions. Unary operators are
to the left of an operand, while Binary operators are between the operands. A conditional
operator has two operator characters which separate the operands.
x = ~ y; // ~ is unary operator. y is operand.
z = x + y; // + is a binary operator. x and y are operands.
y = a ? b : c; // ?: is a ternary operator. a, b, and c are operands.
3.5: Numbers
VERILOG-A supports two basic literal data types for arithmetic operations: integer constants and
real constants. The syntax for constants is:
3.5.1: Integer Constants

The syntax for an integer constant is:
integer_constant ::=
[ sign ] unsign_num
sign ::=
+ | -
unsign_num ::=
decimal_digit { _ | decimal_digit }
decimal_digit ::=

Lexical Conventions
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
The simulator ignores the underscore character (_), so one can use it anywhere in a decimal number,
except as the first character. Using the underscore character can make long numbers more legible.
Examples of integer constants include:
277195000
277_195_000 //Same as the previous number
-634 //A negative number
0005
3.5.2: Real Constants

The syntax for a real constant is:
real_constant ::=
[ sign ] unsign_num .unsign_num
| [ sign ] unsign_num [.unsign_num] e [ sign ] unsign_num
| [ sign ] unsign_num [.unsign_num] E [ sign ] unsign_num
| [ sign ] unsign_num [.unsign_num ] scale_factor
sign ::=
+ | -
unsign_num ::=
decimal_digit { _ | decimal_digit }
decimal_digit ::=
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
scale_factor ::=
T | G | M | K | k | m | u | n | p | f | a
scale_factor represents one of the scale factors listed below. If you use scale_factor, you must
not have any white space between the number and the letter. Be certain to use the correct case for the
scale_factor:
T (tera) = 1012
G (giga) = 109
M (mega) = 106
K,k (kilo) = 103
m (milli) = 10-3
u (micro) = 10-6
n (nano) = 10-9
p (pico) = 10-12
f (femto) = 10-15
a (atto) = 10-18

Examples of real constants include:
3.5K // 3500
1e-6 // 0.000001
-8.6e9
-5e-4
0.7u
50p // 50*10e-12
1.5G // 1.5*10e9
413_556.523_642

Lexical Conventions
3.6: Strings
A string is a sequence of characters enclosed by double quotes (“ ”) and contained on a single line.
Strings are treated as a sequence of one_byte ASCII value.
“ a / b” // is a string.
“Welcome to Verilog-A” // is a string.
3.6.1: Special Characters in Strings

Certain characters can only be used in strings when preceded by an introductory character called an
escape character. Table 3-1 lists these characters in the right-hand column, with the escape sequence
that represents the character in the left-hand column.
Table 3-1:
Escape String Character produced by escape string
\n New line character.
\t Tab character.
\\ \ character.
\” ″ character
\ooo A character specified in 1-3 octal digits (0 < o < 7).

3.7: Identifiers
An identifier is used to give an object a unique name so it can be referenced. An identifier can be any
sequence of letters, digits, dollar signs ($), and the underscore character (_). The first character of an
identifier cannot be a digit or a $; it can be a letter or an underscore. Identifiers are case sensitive, and
associated with a data type (see "Chapter 4:" "Data Types"). There are two types of identifiers:
ordinary identifiers, and escaped identifiers.
3.7.1: Ordinary Identifiers

The first character of an ordinary identifier must be a letter or an underscore character (_), but the
remaining characters can be any sequence of letters, digits, dollar signs ($), and the underscore.
Examples include:
power_gain_bandwidth
MyValue
MyTime
_my$value2
3.7.2: Escaped Identifiers

Escaped identifiers start with the backslash character (\) and end with white space (space, tab,
newline, or formfeed). They provide a means of including any of the printable ASCII characters in an
identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal).
Neither the leading backslash character nor the terminating white space is considered to be part of the
identifier. Therefore, an escaped identifier \cpu3 is treated the same as a non-escaped identifier cpu3.
\base+index
\+clock
\***error-condition***
$a, b)
\a*(b+c)+d

Lexical Conventions
3.8: Keywords
Keywords are predefined non-escape identifiers which are used to define the language constructs.
Preceding a keyword with an escape character ($ causes it to be interrupted as an escaped identifier.
All keywords are defined in lowercase only. Keywords are reserved identifiers used to delimit the
language constructs.
VERILOG HDL (IEEE 1364) Keywords supported:
begin case default else

end endease endfunction endmodule
for forever function if
initial inout input module
output repeat
VERILOG-A (2.0 OVI) Keywords that are supported:
abs absdelay abstol access

acos acosh ac_stim analog
analysis asin asinh atan
atan2 atanh bound_step branch
ceil continuous connectrules cos
cosh cross ddt ddt_nature
delay discrete discipline discontinuity
domain driver_update endconnectrules enddiscipline
endnature exclude exp final_step
flicker_noise floor flow from
generate genvar ground hypot
idt idtmod idt_nature inf
initial_step integer laplace_nd laplace_np
laplace_zd laplace_zp last_crossing limexp
ln log max min
nature noise_table parameter potential
pow real sin sinh
slew sqrt strobe tan
tanh timer transition units
white_noise zi_nd zi_np zi_zd
zi_zp

VERILOG HDL (IEEE 1364) Keywords that are not supported (but are still reserved
identifiers):
always and assign buf

bufif0 bufif1 casex casez
cmos deassign defparam disable
edge endprimitive endspecify endtable
endtask event force fork
highz0 highz1 ifnone join
large macromodule medium nand
negedge nmos nor not
notif0 notif1 or pmos
posedge primitive pull0 pull1
pulldown pullup rcmos reg
release realtime rnmos rpmos
rtran rtranif0 rtranif1 scalared
small specify specparam strong0
strong1 supply0 supply1 table
task time tran tranif0
tranif1 tri tri0 tri1
triand trior trireg vectored
wait wand weak0 weak1
while wire wor xnor
xor

Lexical Conventions
3.9: System Tasks and Functions

The VERILOG-A language supports a variety of system tasks and functions, which are useful to control
the current simulator to display the results of the simulation. The $ character introduces a language
construct which enables development of user-defined tasks and functions. A name following the $ is
interpreted as a system task or a system function.
Syntax:
system_task_function ::=
$system_task_identifier | (list_of_arguments)|;
|$system_function_identifier | (list_of_arguments)|;
list_of_arguments ::=
argument {, |argument | }
argument ::=
expression
Any valid identifier, including keywords already in use in contexts other than this construct can be
used as a system task or function name.
Examples:
$display(“display a message”);
$realtime();
3.10: Compiler Directives

The character (the ASCII value 60, called open quote or accent grave) introduces a language construct
used to implement compiler directives. The compiler behavior dictated by a compiler directive takes
effect as soon as the compiler reads the directive. The directive remains in effect for the rest of the
compilation unless a different compiler directive specifies otherwise. A compiler directive in one
description file can therefore control compilation behavior in multiple description files. Any valid
identifier, including keywords already in use in contexts other than this construct can be used as a
directive name.
The following compiler directives are:

‘define
‘default_discipline
‘endif
‘ifdef
‘include
‘resetall
‘undef
Examples
‘define threshold 1.0
‘include “constant.h”

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Chapter 4:
Data Types
4.1: Integer Numbers

Use the integer declaration to declare variables of type integer.
integer_declaration ::=
integer list_of_identifiers ;
list_of_identifiers ::=
var_name { , var_name}
var_name ::=
variable_identifier
| array_identifier [ range ]
range ::=
upper_limit_const_exp : lower_limit_const_exp
In VERILOG-A, the user can declare an integer number in a range at least as great as: -231
to 231 - 1.
To declare an array, specify the upper and lower indexes of the range. Be sure that each index is a
constant expression that evaluates to an integer value.
integer A[1:128]; // Declares an array A of 128 integers

integer x, y, z[0:20]; // Declares 2 integers x, y, and an array z of 21
integers
parameter integer max_size = 20 from [1:50];

integer cur_vector[1:max_size];
/* If the max_size parameter is not overridden, the

previous two statements declare an array of 20 integers. */
4.2: Real Numbers

Use the real declaration to declare variables of type real.
real_declaration ::=
real list_of_identifiers ;
var_name { , var_name }
var_name ::=
variable_identifier
| array_identifier [ range ]
range ::=
upper_limit_const_exp : lower_limit_const_exp

In VERILOG-A, the user can declare real numbers in a range at least as great as 10-37 to 10+37. To
declare an array of real numbers, specify the upper and lower indexes of the range. Be sure that each
index is a constant expression that evaluates to an integer value.
Note: Real and integer variables have default initial values of zero.
4.2.1: Converting Real Numbers to Integer Numbers

VERILOG-A converts a real number to an integer number by rounding the real number to the nearest
integer. If the real number is equally distant from the two nearest integers, VERILOG-A converts the real
number to the integer farthest from zero. The following example illustrates what happens when real
numbers are assigned to integer numbers.
integer int_valA, int_valB, int_valC;

real real_valA, real_valB, real_valC;
real_valA = -1.8;
int_valA = real_valA; // int_valA is -2
realvalB = 1.6 ;
int_valB = real_valB; // int_valB is 2
real_valC = -1.6;
int_valC = real_valC; // int_valC is -2
If either operand in an expression is real, VERILOG-A converts the other operand to real before applying
the operator. This conversion process can result in a loss of information.
real real_var;
real_var = 9.0;
real_var = 5/8 * real_var; // real_var is 9.0, not 5.625
In this example, both 5 and 8 are integers, so 1 is the result of the division. VERILOG-A converts 1 to 1.0
before multiplying the converted number by 9.0.

Data Types
4.3: Parameters
Use the parameter declaration to specify a module’s parameters.
parameter_declaration ::=
parameter [opt_type] list_of_param_assignments ;
opt_type ::=
real
| integer
list_of_param_assignments ::=
declarator_init {, declarator_init }
declarator_init ::=
parameter_identifier = constant_exp { opt_range }
• opt_type is described in Section 4.3.1:“A Parameter Type”.

• opt_range is described in Section 4.3.2:“Permissible Values”.
• parameter_identifier is the name of a parameter being declared.
As specified in the syntax, the right-hand side of each declarator_init assignment is required to
be a constant expression. It is possible to include in the constant expression only constant numbers
and previously defined parameters.
Parameters are constants, so the value of a parameter at runtime cannot be changed. However, the
user can customize module instances by changing parameter values during compilation. See Chapter
10, “Instantiating Modules and Primitives,” for more information.
Consider the following code fragment. The parameter superior is defined by a constant expression
that includes the parameter subord.
parameter integer hold = 15;

parameter integer superior = 5*hold;
In this example, changing the value of subord also changes the value of superior because the value of
superior depends on the value of subord.
4.3.1: A Parameter Type

The user must specify a default for each parameter that is defined, but the parameter type specifier is
optional. If the parameter type specifier is omitted, VERILOG-A determines the parameter type from the
constant expression. If a type is specified, and it conflicts with the type of the constant expression, one
specified type takes precedence.
The three parameter declarations in the following examples all have the same effect. The first example
illustrates a case where the type of the expression agrees with the type specified for the parameter.
parameter integer rate = 13;

The second example omits the parameter type, so VERILOG-A derives it from the integer type of the
expression.
parameter rate = 15;
In the third example, the expression type is real, which conflicts with the specified parameter type.
The specified type, integer, takes precedence.
parameter integer rate = 15.0;
In all three cases, rate is declared as an integer parameter with the value 15.
4.3.2: Permissible Values

Use the optional range specification to designate permissible values for a parameter. If needed, the
user can specify more than one range.
opt_range ::=
from value_range_specifier
| exclude value_range_specifier
| exclude value_constant_expression
value_range_specifier ::=
start_paren expression1 : expression2 end_paren
start_paren ::=
[
| (
end_paren ::=
]
| )
expression1 ::=
constant_expression
| -inf
expression2 ::=
constant_expression
| inf
Ensure that the first expression in each range specifier is smaller than the second expression. Use a
bracket, either "[" for the lower bound or "]" for the upper, to include an end point in the range. Use a
parenthesis, either "(" for the lower bound or ")" for the upper, to exclude an end point from the range.
To indicate the value infinity in a range, use the keyword inf. To indicate negative infinity, use -inf.
For example, the following declaration gives the parameter current_value the default of -20.0. The
range specification allows current_value to acquire values in the range - ∞< cur_val < 0.
parameter real maxval = 0.0;

parameter real current_value = -20.0 from (-inf:maxval);

Data Types
The following declaration:
parameter integer positive_value = 25 from (0:50];
gives the parameter positive_value the default of 25. The range specification for positive_value
allows it to acquire values in the range 0 < positive_value <= 50. In addition to defining a range of
permissible values for a parameter, you can use the keyword exclude to define certain values as
illegal.
parameter low = 15;

parameter high = 20;
parameter integer int_value = 0 from [0:inf) exclude (low:high] exclude 2;
In this example, both a range of values, 15 < int_value <= 20, and the single value 2 are defined as
illegal for the parameter.
4.3.3: Parameter Arrays

VERILOG-A requires arrays to be initialized in their definitions and allows overriding of their values as
with other parameter types.
Parameter types have the following restrictions:
• Type of a parameter array shall be declared.
• An array assigned to an instance of a module shall be of the exact size of the array bounds of that
instance.
• Changing the array size via a parameter assignment assigns an array of the new size from the
same module as the parameter assignment that changed the parameter array size.
Example
parameter real z_array [0:4] = {1.0, 3.198, 4.56, 2.00, 1.96};
where z_array is a real array with five elements with values 1.0, 3.198, 4.56, 2.00 and 1.96.
4.3.4: Genvars
Genvars are integer valued variables used as loop indexes:
genvar_declaration :: =
genvar list_of_genvar_identifiers :
list_of_genvar_identifiers :: =
genvar_identifier {, genvar_identifier} ;
Example
genvar i;
analog begin
.....

for (i=0; i < 8; i=i+1) begin

V(out[i]) < + transition(value[i], td, tr);
end
.....
end
The genvar variable i can only be assigned within the loop control. Assignments to the genvar
variable i can consist only of expressions of static values.
4.4: Natures
The nature declaration is used to specify a collection of attributes. The attributes of a nature
characterize the analog quantities that are solved during a simulation. Attributes define the units
(such as meter, volts, and newton), access symbols and tolerances associated with an analog quantity,
and can define other characteristics as well. After defining a nature, it can be used as part of the
definition of disciplines and other natures. Access functions defined in natures are used to access the
potential and flow quantities associated to the nodes.
nature_declaration ::=
nature nature_name
[ nature_descriptions ]
endnature
nature_name ::=
nature_identifier
nature_descriptions ::=
nature_description
| nature_description nature_descriptions
nature_description ::=
attribute = constant_expression ;
attribute ::=
abstol
| access
| ddt_nature
| idt_nature
| units
| identifier
| Silvaco_supported_attribute
Silvaco_supported_attribute ::=
huge
| blowup For Vendor compatibility
| maxdelta
Each nature declaration must:

• Be defined between the keywords nature and endnature.
• Be named with a unique identifier.

Data Types
• Include all the required attributes listed in the Attribute Requirements table (see Table 4-2).
• Be declared at the top level.
The user cannot nest nature declarations inside other nature, discipline, or module declarations.
The VERILOG-A language specification allows one to define a nature in two ways. One may define the
nature directly by describing its attributes. A nature defined in this way is a base nature. The other
way one can define a nature is to derive it from another nature or a discipline. In this case, the new
nature is called a derived nature.
4.4.1: Base Nature

To declare a base nature, define the attributes of the nature. The following code declares the nature
current and voltage. The expression associated with each attribute must be a constant expression.
nature current
units = "A";
access = I;
idt_nature = charge;
abstol = 1e-12;
huge = 1e6;
endnature
nature voltage
units = "V";
access = V;
abstol = 1u;
endnature
The following table describes the predefined attributes.
Table 4-1: Predefined Atributes
Attribute Description
abstol The abstol attribute provides a tolerance measure (metric) for convergence
of potential or flow calculation. It specifies the maximum negligible for
signals associated with the nature. This attribute is required for all base
natures. It is legal for a derived nature to change abstol, but if left
unspecified it shall inherit the abstol from its parent nature. The constant
expression assigned to it shall evaluate to a real value.
access The access attribute identifies the name for the access function. When the
nature is used to bind a potential, the name is used as an access function for
the potential; when the nature is used to bind the flow, the name is used as
an access function for the flow.
This attribute is required for all base natures. It is illegal for a derived
nature to change the access attribute; the derived nature always inherits the
access attribute of its parent nature. If specified, the constant expression
assigned to it shall be an identifier (by name, not as a string).

idt_nature The idt_nature attribute provides a relationship between a nature and

the nature representing its time integral.
idt_nature can be used to reduce the need to specified tolerances on the
idt() operator. If this operator is applied directly on nets, the tolerance can
be taken from the node, which eliminates the need to give a tolerance with
the operator.
If specified, the constant expression assigned to idt_nature shall be the
name (not a string) of a nature which is defined elsewhere. It is possible for a
nature to be self-referencing with respect to its idt_nature attribute. In
other words, the value of idt_nature can be the nature that the attribute
itself is associated with.
The idt_nature attribute is optional; the default value is the nature itself.
While it is possible to override the parent’s value of idt_nature using a
derived nature, the nature thus specified shall be related (share the same
base nature) to the nature the parent uses for its idt_nature.
ddt_nature The ddt_nature attribute provides a relationship between a nature and

the nature representing its time derivative.
ddt_nature can be used to reduce the need to specified tolerances on the
ddt() operator. If this operator is applied directly on nets, the tolerance can
be taken from the node, which eliminates the need to give a tolerance with
the operator.
If specified, the constant expression assigned to ddt_nature shall be the
name (not a string) of a nature which is defined elsewhere. It is possible for a
nature to be self-referencing with respect to its ddt_nature attribute. In
other words, the value of ddt_nature can be the nature that the attribute
itself is associated with.
The ddt_nature attribute is optional; the default value is the nature itself.
While it is possible to override the parent’s value of ddt_nature using a
derived nature, the nature thus specified shall be related (share the same
base nature) to the nature the parent uses for its ddt_nature.
units The units attributed provides a binding between the value of the access
functions and the units for that value. The units field is provided so
simulators can annotate the continuous signals with their units and is also
used in the net capability rule check.
This attribute is required for all base natures. It is illegal for a derived
nature to define or change the units; the derived nature always inherits its
parent nature units. If specified, the constant expression assigned to it shall
be a string.
Other Vendor Compatibility Attributes
huge Specifies the maximum change in signal value allowed during a single
iteration. The simulator uses huge to facilitate convergence when signal
values are very large. Default is 45.036e06

Data Types
blowup Specifies the maximum allowed value for signals associated with the nature.
If the signal exceeds this value, the simulator reports an error and stops
running. Default is 1.0e09
maxdelta Specifies the maximum change allowed on a Newton-Raphson iteration.

Default is 0.3
Table 4-2: Attribute Requirements
Attribute Required or optional The constant expression must be
abstol Required A real value
access Required for all base natures An identifier
units Required for all base natures A string
blowup Optional A real value
ddt_nature Optional The name of a nature defined

elsewhere
huge Optional A real value
idt_nature Optional The name of a nature defined

elsewhere
maxdelta Optional A real value
4.4.2: Derived Nature

A nature can be derived from an already declared nature. This allows the new nature to have the same
attributes as the attributes of the existing nature. This new nature, derived nature, uses an
existing parent nature. If a nature is not derived from any other nature, it is called a base
nature.
A derived nature can declare additional attributes or override attribute values of the parent nature.
The attributes of the derived nature is are accessed in the same manner as accessing attributes of any
other nature.
Example
nature Net_current
units = “A”;
access = I;
abstol = 1u;
endnature
// An alias
nature total_Net_current : Net_current

endnature
nature New_current : Net_current // derived

abstol = 1m; // modified
max = 12.3; // new attribute
endnature
4.5: Disciplines
Use the discipline declaration to specify the characteristics of a discipline. You can then use the
discipline to declare nets.
discipline_declaration ::=
discipline discipline_identifier
[ discipline_description { discipline_description } ]
enddiscipline
discipline_description ::=
nature_binding
| domain_binding
nature_binding ::=
potential nature_identifier ;
| flow nature_identifier ;
domain_binding ::=
domain continuous ;
| domain discrete ;
Disciplines are declared at the top level. In other words, one cannot nest a discipline declaration inside
other discipline, nature, or module declarations. Discipline identifiers have global scope, so one can use
discipline identifiers to associate nets with disciplines (declare nets) inside any module. A discipline
shall be defined between the keywords discipline and enddiscipline.
4.5.1: Binding Natures

Disciplines bind a nature to potential and/or a flow. The name of the nature is specified in the
discipline. The nature binding for potential is specified using the keyword potential. The nature
binding for flow is specified using the keyword flow.
The access function defined in the nature is bound to the potential is used in the model, obeys
Kirchhoff ’s Potential Law (KPL), and is referred to as the potential access function. While the access
function defined in the nature is bound to the flow, obeys Kirchhhoff ’s Flow Law (KFL), and is referred
to as the flow access function.
The first example defines a single binding, one between potential and the nature Voltage. A
discipline with a single binding is called a signal-flow discipline.
discipline voltage
potential Voltage;//A signal-flow discipline must be bound to potential.
enddiscipline

Data Types
The next declaration, for the electrical discipline, defines two bindings. Disciplines with two
natures are called a conservative discipline.
discipline electrical
potential Voltage;
flow Current;
enddiscipline
When defining a conservative discipline, the nature bound to potential must be different from the
nature bound to flow.
Example
Nature and discipline definitions for electrical systems.
// current in amperes
nature current
units = “A”;
access = I;
abstol = 1e-12;
endnature
// potential in volts
nature voltage
units = “V”;
access = V;
abstol = 1e-6;
endnature
potential Voltage;
flow Current;
enddiscipline
4.5.2: Compatibility of Disciplines

Certain operations in VERILOG-A, such as declaring branches, are allowed only if the disciplines
involved are compatible.
• Any discipline is compatible with itself.
• Any empty discipline incompatible with all disciplines.
Consider the following declarations.
nature Voltage
access = V;
units = "V";
abstol = 1u;
endnature

nature Current
access = I;
units = "A";
abstol = 1p;
endnature
discipline emptydis
enddiscipline
potential Voltage;
flow Current;
enddiscipline
discipline sig_flow_v
potential Voltage;
enddiscipline
To determine whether the electrical and sig_flow_v disciplines are compatible:

The electrical and sig_flow_v have defined natures for potential.
In fact, electrical and sig_flow_v have the same nature for potential, but electrical has a
defined nature for flow, but sig_flow_v does not. The Disciplines are compatible.
Examine these declarations:

nature Position
access = x;
units = "m";
abstol = 1u;
endnature
nature Force
access = F;
units = "N";
abstol = 1n;
endnature
discipline mechanical
potential Position;
flow force;
enddiscipline
The electrical and mechanical disciplines are not compatible.

Both disciplines have defined natures for potential, but the Position nature is not the same as the
Voltage nature. The Disciplines not compatible end point.

Data Types
Table 4-3: Predefined disciplines in the standard definition Verilog-A file
discipline potential nature flow nature potential access flow access
electrical Voltage Current V I
magnetic Magneto_Motive Flux MMF Phi

_Force
thermal Temperature Power Temp Pwr
kinematic Position Force Pos F
rotational Angle Angular_Force Theta Tau
4.5.3: Multi-Disciplinary Example

Disciplines in VERILOG-A allow designs of multiple disciplines to be easilydefined and simulated. This
example shows how an application spanning multiple disciplines can be modeled in Verilog-A. It
models a DC-motor driven by a voltage source.
module motor_circuitt;
parameter real freq=400;
ground gnd;
electrical drive;
rotational shaft;
motor m1(drive, gnd, shaft);
vsource #(.freq(freq), .ampl(2.0)) v1(drive, gnd);
endmodule
// vp: positive terminal [V,A] vn:negative terminal [V,A]

// shaft:motor shaft [rad,Nm]
// INSTANCE parameters
// Km = motor constant [Vs/rad]Kf = flux constant [Nm/A]
// j = inertia factor [Nms^2/rad] D= drag (friction) [Nms/rad]
// Rm = motor resistance [Ohms] Lm = motor inductance [H]
// A model of a DC motor driving a shaft
module motor(vp, vn, shaft);

inout vp, vn, shaft;
electrical vp, vn;
rotational shaft;
parameter real Km = 4.5, Kf = 6.2;
parameter real j = .004, D = 0.1;
parameter real Rm = 5.0, Lm = .02;
analog begin
V(vp, vn) <+ Km*Theta(shaft) + Rm*I(vp, vn) +
ddt(Lm*I(vp, vn));
Tau(shaft) <+ Kf*I(vp, vn) - D*Theta(shaft) -
ddt(j*Theta(shaft));
end
endmodule

4.5.4: Empty Disciplines

It is possible to define a discipline with no nature bindings. These are known as empty disciplines and
they can be used in structural descriptions to let the components connected to a net determine which
natures are to be used for the net. Such disciplines may have a domain binding or they may be
domain-less, thus allowing the domain to be determined by the connectivity of the net.
Example
discipline neutral
enddiscipline
discipline interconnect
domain continuous;
enddiscipline
4.5.5: Discipline of Wires and Undeclared Nets

It is possible for a module to have nets where there are no discipline declarations. If such a net appears
bound only to ports in module instantiations, it may have no declaration at all or may be declared to
have a wire type such as wire. If it is referenced in behavioral code, then it must have a wire type. In
these cases, the net shall be treated as having an empty discipline. If the net is referenced in
behavioral code or if its net type is other than wire, then it shall be treated as having empty discipline
with a domain binding of discrete, otherwise it shall be treated as having empty discipline with no
domain binding.
This allows netlists (modules which describe connectivity only, with no behavior) which use wire as an
interconnect to be valid.
4.5.6: Overriding Nature Attributes From Discipline

A discipline can override the value of the bound nature for the pre-defined attributes as shown for the
flow ttl_curr in the example below.To do so from a discipline declaration, the bound nature and
attribute needs to be defined, as shown for the abstol value within the discipline ttl in the example
below.
The general form is shown as the attr_override terminal in Syntax 3-5: the keyword flow or potential,
then the hierarchical separator . and the attribute name, and, finally, set all of this equal to (=) the
new value (e.g., flow.abstol = 10u).
Examples
nature ttl_curr
units = "A";
access = I;
abstol = 1u;
endnature
nature ttl_volt
units = "V";
access = V;
abstol = 100u;
endnature

Data Types
discipline ttl
potential ttl_volt;
flow ttl_curr;
flow.abstol = 10u;
enddiscipline
4.5.7: Deriving Natures From Disciplines

A nature can be derived from the nature bound to the potential or flow in a discipline. This allows
the new nature to have the same attributes as the attributes for the nature bound to the potential
or the flow of the discipline. If the nature binding to the potential or the flow of a discipline
changes, the new nature shall automatically inherit the attributes for the changed nature. In order to
derive a new nature from flow or potential of a discipline, the nature declaration shall also include the
discipline name followed by the hierarchical separator (.) and the keyword flow or potential, as
shown for ttl_net_curr in the example below. A nature derived from the flow or potential of a
discipline can declare additional attributes or override values of the attributes already declared.
Examples
nature ttl_net_curr : ttl.flow
endnature // abstol = 10u as modified in ttl
nature ttl_net_volt : ttl.potential
abstol = 1m; // modified for this nature
max = 12.3; // new attribute for this nature
endnature
4.5.8: Ground Declaration

Each ground declaration is associated with an already declared net of continuous discipline. The node
associated with the net will be the global reference node in the circuit. If used in behavioral code, the
net shall be used in only the differential source and probe forms, e.g., V(gnd) is not allowed. The net
must be assigned a continuous discipline to be declared ground.
Syntax
ground_declaration ::=
ground [ range ] list_of_nets;
Example
module example_ground(in, out);
input in;
output out;
electrical in, out;
electrical gnd;
ground gnd;
parameter real V_source = 5.0;
resistor #(.r(10K)) r1(out,gnd);
analog begin
V(out) <+ V(in,gnd)*2;
end
endmodule

4.6: Net Disciplines

Net discipline declaration is used to associate nets with previously defined disciplines.
net_discipline_declaration ::=
discipline_idendifier [range] list_of_nets ;
wire [range] list_of_nets ;
range ::=
[ msb_expression : lsb_expression ]
list_of_nets ::=
net_identifier
net_identifier , list_of_nets
msb_expression ::=
constant_expression
lsb_expression ::=
constant_expression
A net declared without a range is called a scalar net. A net declared with a range is called a vector net.
electrical [1:10] nodes; //Declares a vector net

wire [3:0] connection_1, connection_2; //Declares two vector nets
Example
module multiple_inputs(multi_ports);
input [0:5] multi_ports;
electrical [0:5] multi_ports;
analog begin
generate i (0, 5)
v(multi_ports [i]) <+ 0.0;
end
endmodule
4.7: Branches
A branch is a path between two nets. If both nets are conservative, then the branch is
conservative, and it defines a branch potential and a branch flow. If one net is a
signal_flow net, then the branch is a signal_flow branch and defines either a branch
potential or a branch flow, but not both.
Each branch declaration is associated with two nets from which it derives a discipline. These nets are
referred to as the branch terminals. Only one net needs to be specified, in which case the second net
defaults to ground and the discipline for the branch is derived from the specified net. The syntax for
declaring branches is shown:
branch_declaration ::=
branch list_of_branches ;

Data Types
list_of_branches ::=
terminals list_of_branch_identifiers
terminals ::=
( net_identifier )
| ( net_identifier , net_identifier )
list_of_branch_identifiers ::=
branch_identifier
| branch_identifier , list_of_branch_identifiers
4.8: Implicit Branches

The user might find it more convenient or clearer to refer to branches by their branch terminals. The
following is an example of a named branch.
Example
module diode (p, n);
inout p, n;
electrical p, n;
parameter real area = 4;

parameter real is = ie - 14;
parameter real z = 2 from (0:10);
parameter real cjo = 0;
parameter real m = 0.5;
parameter real phi = 0.7;
parameter real t_t = ip;
branch (p, n) diode; //Declared branch

real vd, id, qd;
analog begin
vd = V (diode);
id = area* is *(exp (Vd/(z*$Vt)) -1);
qd = t_t * id + area * Vd;
I (diode) <+ id + ddt (qd);
end
endmodule


Chapter 5:
Statements for the Analog Block
5.1: Analog Procedural Block

VERILOG-A behavioral description is encapsulated within the analog procedural block. The analog
procedural block defines the behavior as a procedural sequence of statements. The conditional and
looping constructs are available for defining behaviors within the analog procedural block. The syntax
for an analog block is:
analog_block ::=
analog analog_statement ;
analog_statement ::=
analog_seq_block
|analog_seq_block
|analog_branch_contribution
|analog_indirect_branch_assignment
|analog_procedural_assignment
|analog_conditional_statement
|analog_for_statement
|analog_case_statement
|analog_event_controlled statement
|system_task_enable
|statement
statement ::=
|seq_block
|procedural_assignment
|conditional_statement
|loop_statement
|case_statement
5.1.1: Block Statements

The block statements, also referred to as sequential blocks, are a means of grouping two or more
statements together so they act syntactically like a single statement. The keywords begin and end
delimit the block statements. The procedural statements in a block statement are executed
sequentially in the given order.
Sequential Blocks
The syntax for sequential blocks is shown below:
seq_block ::=
begin [ : block_identifier { block_item_declaration }]
{ statement }
end
analog_seq_block ::=
begin [ : block_identifier { block_item_declaration }]
{ analog_statement }
end

block_item_declaration ::=
| real_declaration
An analog_seq_block is a seq_block which encapsulates one or more analog_statements.
Block Names
Name a sequential block by adding a :block_identifier after the keyword begin. The naming
of a block allows local variables to be declared for that block.
All local variables are static - that is, a unique location exists for all variables, and leaving or entering
blocks does not affect the values stored in them.
The block names give a means of uniquely identifying all variables at any simulation time.
5.1.2: Procedural Assignment Statements

Use the procedural assignment statement to modify integer and real variables:
procedural_assignment ::=
lexpr = expression ;
analog_procedural_assignments ::=
lexpr = analog_expression ;
lexpr ::=
integer_identifier
| real_identifier
| array_element
array_element ::=
integer_identifier [ constant_expression ]
| real_identifier [ constant_expression ]
The left-hand operand of the procedural assignment must be a modifiable integer or real variable, or
an element of an integer or real array. The type of the left-hand operand determines the type of the
assignment.
The right-hand operand can be any arbitrary scalar expression constituted from legal operands and
operators.
In the following code fragment, the variable phase is assigned a real value. The value must be real
because phase is defined as a real variable.
real phase;
analog begin
phase = idt( gain*V(in));
One can also use procedural assignment statements to modify array values. For example, if z is
declared as:

real z[0:3], sum;
one can make assignments such as:
z[0] = 15.7;
z[1] = 16.1;
z[2] = 17.1;
z[3] = 13.5;
sum = z[0] + z[1] + z[2] + z[3];
5.2: Sequential Block Statement

Use a sequential block when you want to group two or more statements together so that they act like a
single statement.
analog_seq_block ::=
begin [ : block_identifier { block_item_declaration } ]
{ analog_statement }
end
integer_declaration
| real_declaration
The statements included in a sequential block run sequentially.

If adding a block identifier, you can also declare local variables for use within the block. All the local
variables declared are static. In other words, a unique location exists for each local variable, and
entering or leaving the block does not affect the value of a local variable.
The following example uses two named blocks, declaring a local variable in each of them. Although the
variables have the same name, the simulator handles them separately because each variable is local to
its own block.
integer i;
...
for ( i = 0; i < 15; i = i + 1 ) begin
if ( i%2 ) begin : odd
integer i; // Declares a local variable
i = i + 1;
$display("Odd numbers counted = %d", i );
end else begin : even
integer i; // Declares a local variable
i = i + 1;
$display("Even numbers counted = %d" , i );
end
end

5.3: Conditional Statement

Use the conditional statement to run a statement under the control of specified conditions.
conditional_statement ::=
if ( expression ) true_statement_or_null
[ else false_statement_or_null ]
If expression evaluates to a nonzero number (true), the simulator executes true_statement. If

expression evaluates to zero (false), and the else statement is present, the simulator skips
true_statement and executes false_statement.
Since the numeric value of the if expression is tested for being zero (0), shortcuts are possible as
listed below.
if (expression)
if (expression ! = 0)
There can be confusion when an else is omitted from a nested if() sequence because the else part
of an if-else is optional. Always associate the else with the closest previous if(), which lacks
an else.
In the example below, the else goes with the inner if(), as shown by indentation.
if (index > 0)
if (i > j)
result = i;
else // else applies to preceding if
result = j;
If that association is not desired, a begin-end shall be used to force the proper association, as shown
below.
if (index > 0) begin

if (i > j)
result = i;
end
else result = j;
The most general way of writing a multi-way decision is through the nesting of if statements (known
as an if-else-if construct). The expressions are evaluated in order. Whenever any expression is
True, the statement associated with it shall be executed, and this action shall terminate the whole
chain. Each statement is either a single statement or a sequential block of statements.

5.3.1: Analog Conditional Statements

Analog conditional statements are syntactically equivalent to conditional statements, with the
exception of the True and/or False statements which are analog_statements. The conditional
expression shall be a genvar_expression.
analog_conditional_statement ::=
if ( genvar_expression ) true_analog_statement_or_null ;
[ else false_analog_statement_or_null ; ]
5.4: Case Statement

the case statement is a multi-way decision statement which tests if an expression matches one of a
number of other expressions, and if so, branches the expression accordingly.
Syntax
case_statement ::=
case (expression) case_item { case_item } endcase
| casex (expression) case_item { case_item } endcase
| casez (expression) case_item { case_item } endcase
case_item ::=
expression { , expression } : statement_or_null
| default [ : ] statement_or_null
The default statement is optional. Use of multiple default statements in one case statement is illegal.
The case expression and the case_item expression can be computed at runtime, but neither
expression is required to be a constant expression.
The case_item expressions are evaluated and compared in the exact order in which they are given.
During this linear search, if one of the case_item expressions matches the case expression given in
parentheses, then the statement associated with that case_item is executed. If all comparisons fail,
and the default item is given, then the default item statement is executed; otherwise none of the
case_item statements are executed.
5.4.1: Analog Case Statements

Analog case statements are syntactically equivalent to case statements, although the case item
statements can also be analog_statements, as seen below:
analog_case_statement ::=
case (genvar_expression) analog_case_item { analog_case_item } endcase
| casex (genvar_expression) analog_case_item { analog_case_item } endcase
| casez (genvar_expression) analog_case_item { analog_case_item } endcase
analog_case_item ::=
genvar_expression { , genvar_expression } : analog_statement_or_null
| default [ : ] analog_statement_or_null

5.4.2: Constant Expression in Case Statements

A constant expression can be used for a case expression. The value of the constant expression
shall be compared against case_item expressions.
Example
The following example demonstrates the usage by modeling a 3-bit priority encoder.
integer [2:0] encode;
case (1)
encode[2] : $display(“Select Line 2”);
default $strobe(“Error : One of the bits expected ON”);
endcase
The case expression here is a constant expression (1). The case_items are expressions (array
elements) and are compared against the constant expression for a match.
5.5: Looping Statement

There are several types of looping statements: repeat ( ), while ( ), and for ( ). These statements
provide a means of controlling the execution of a statement zero (0), one (1), or more times.
The for ( ) looping statements can be used to describe analog behaviors using analog operators.
Analog operators are not allowed in the repeat ( ), while ( ), and for ( ) looping statements. They are
allowed in analog_for and generate statements.
5.5.1: Repeat and While Statements

repeat( ) executes a statement a fixed number of times. Evaluation of the expression decides how
many times a statement is executed.
while( ) executes a statement until an expression becomes False. If the expression starts out False,
the statement is not executed at all.
The repeat and while expressions are evaluated once before the execution of any statement in order to
determine the number of times, if any, the statements are executed.
Syntax
repeat_statement ::=
repeat ( expression ) statement
while_statement ::=
while ( expression ) statement
5.5.2: For Statements

The for ( ) statement is a looping construct which, using an index variable, controls the execution of its
associated statement(s). If the associated statement is an analog_statement, then the control

mechanism shall consist of genvar_assignments and genvar_expressions to follow to the

restrictions associated with the use of analog operators. If the associated statements are not
analog_statements, the for ( ) statement can use procedural assignments and expressions, which
also include genvar_expressions.
The for ( ) statement controls execution of its associated statement(s) by a three step process:
1. It executes an assignment normally used to initialize an integer which controls the number of
loops executed.
2. It evaluates an expression; if the result is zero (0), the for-loop exits: otherwise the for-loop
executes its associated statement(s) and then performs Step 3.
3. It executes an assignment normally used to modify the value of the loop control variable and
repeats Step 2.
Syntax
for_statement ::=
for ( procedural_assignment ; expression ;
procedural assignment ) statement
analog_for_statement ::=
for ( genvar_assignment ; genvar_expression ;
genvar_assignment ) analog_statement
analog_for statements are syntactically equivalent to for ( ) statements, except the associated
statement is also an analog statement (which contains analog operations). The analog statement puts
the additional restriction upon the procedural assignment and conditional expressions of the for-loop
to be statically evaluated.
Example
genvar i
analog begin
.....
for (i = 0; i < 8; i = i + 1) begin
V(out[i]) <+ transition(value[i], td, tr, tf);
end
.....
end
5.6: Analog Signals

Analog signals are easily distinguished from digital signals. An analog signal has a discipline with a
continuous domain. This section describes analog branch assignments, signal access mechanisms, and
operators in VERILOG-A.
5.7: Signal Access Functions

Access functions are used to access signals on nets, ports, and branches. There are two types of access
functions: branch access functions, and port access functions. The name of the access
function for a signal is taken from the discipline of the net, port, or the branch where the signal or port

associated, and uses the ( ) operator. A port access function also takes its name from the discipline of
the port to which it is associated, but uses the port access ( <> ) operator.
If the signal or port access function is used in an expression, the access function returns the value of
the signal. If the signal access function is being used on the left side of a branch assignment, or
contribution statement, a value to the signal is assigned. A port access function cannot be used on the
left side of the branch assignment or contribution statement.
Table 5-1 shows how access functions can be applied to branches, nets, and ports. In the table: b1
refers to a branch, n1 and n2 refer to nets or ports, and p1 refers to a port. These branches, ports and
nets belong to the electrical discipline, where V is the name of the access function for the voltage
(potential) and I is the name of the access function for the current (flow).
Table 5-1: Access Function Examples
Example Comments
V(b1) Accesses the voltage across branch b1.
V(n1) Accesses the voltage of n1 (a net or a port) relative to ground.
V(n1, n2) Accesses the voltage difference between n1 and n2 (nets or ports).
I(b1) Accesses the current on branch b1.
I(n1) Accesses the current flowing from n1 (a net or port) to ground.
I(n1, n2) Accesses the current flowing between n1 and n2.
I(n1, n1) Error
I(<pl>) Accesses the current flow into the module through port p1.
A branch identifier will be the argument expression list for signal access functions, or a list of one or
two nets (or port) expressions. If two net expressions are given as arguments to a flow access function,
they will not evaluate the same signal. The net identifiers will be scalar, or resolve to a constant net of
a composite net type (array or bus) accessed by a genvar expression.
Example
I(n1, n2) creates an unnamed branch from n1 to n2 (if it does not already exist) and then accesses
the branch flow. I(n1) does the same from n1 to the global reference node (ground). Therefore:
• Accessing the flow from a net (or port) to a net (or port) defines an unnamed branch. Accessing the
potential on a single net (or port) defines an unnamed branch from that net (or port) to the global
reference node (ground).
• It is also possible to access the flow passing through a port into a module. The name of the access
function is derived from the flow nature of the discipline of the port. In this case ( <> ) is used to
delimit the port name rather than ( ).
Example
I(<p1>) is used to access the current flow into the module through the electrical port p1. (See section
5.8.8:“Port Branches” for details.)

5.8: Probes and Sources

An analog component can be represented using a network of probes and controlled sources. VERILOG-A
uses the concept of probes and sources as a means of unambiguously representing a network. The
mapping between these representations are defined in the following sections.
5.8.1: Probes
If no value is specified for either the potential or the flow, the branch is a probe. If the flow of the
branch is used in an expression anywhere in the module, the branch is a flow probe, otherwise it will
be a potential probe. Using both potential and the flow of a probe branch is illegal. The models for
probe branches are shown in Figure 5-1.
Figure 5-1: Equivalent Circuit Models for Probe Branches

The branch potential of a flow probe is zero (0). The branch flow of a potential probe is zero (0).
5.8.2: Sources
A branch (named or unnamed) is a source branch if either the potential or the flow of that branch is
assigned a value by a contribution statement anywhere in the module. If the branch potential is
specified, then it is a potential source, and if the branch flow is specified it is a flow source. A branch
cannot simultaneously be a potential and a flow source, although it can switch between them as a
switch branch.
Both the potential and the flow of a source branch are accessible in expressions anywhere in the
module. The module for potential and flow sources are shown in Figure 5-2.
Lower case f is a mode which measures the flow through the branch, and p is a mode which measures
the potential across the branch.

Figure 5-2: Equivalent Circuit Models for Source Branches

The following examples demonstrate how to formulate models, the correspondence between the
behavioral description, and the equivalent probe/source model.
5.8.3: The four controlled sources

The following example is used with each of the four behavioral statements listed below. When inserted
into this example, each statement creates a unique controlled source.
Example
module control_source(p, n, ps, ns);
electrical p, n, ps, ns;
parameter real A=1.0;
branch(ps, ns) in;
branch(p, n) out;
analog begin
// add behavioral statement here
end
endmodule
5.8.4: Behavioral Statements

The model for a voltage controlled voltage source is:
V(out) <+ A*V(in);
The model for a voltage controlled current source is:
I(out) <+ A*V(in);
The model for a current controlled voltage source is:
V(out) <+ A*I(in);
The model for a current controlled current source is:
I(out) <+ A*I(in);

5.8.5: Resistor and Conductor

Figure 5-3 shows the model for a linear conductor
Figure 5-3: Linear Conductor Model

The assignment to I(cond) makes cond a current source branch, and V(cond) accesses the
potential probe built into the current source branch.
Figure 5-4 shows the model for a linear resistor.
Figure 5-4: Linear Resistor Model

The assignment to V(res) makes res a potential source branch, and I(res) accesses the optional flow
probe built into the potential source branch.
5.8.6: RLC Circuits

A series RLC circuit is formulated by summing the voltage across its three components:
t
∫
d 1
v ( t ) = Ri ( t ) + L ------ i ( t ) + ---- i ( τ ) dτ
dt C –∞
Which can be defined as:

V(p, n) <+ R*I(p, n ) + L*ddt(I(p, n)) + idt(I(p, n))/C;
A parallel RLC circuit is formulated by summing the currents through its three components:

t
v(t)
∫
d 1
i ( t ) = ---------- + C ------ v ( t ) + ---- v ( τ ) dτ
R dt L –∞
Which can be defined as:

I(p, n) <+ V(p, n )/R + C*ddt(V(p, n)) + idt(V(p, n))/L;
5.8.7: Simple Implicit Diode

VERILOG-A allows components to be described with illicit equations.
Example
In the following example is a simple diode with a series resistor, and the module is implicit because the
diode current I(a, c) appears on both sides of the contribution operator. The current of the diode branch
is specified, making it a flow source branch. In addition, both the voltage and current of diode branch
in the behavioral description.
I(a, c) <+ is*(limexp((V(a, c) - rs*I(a, c)) /$vt) - 1);
Figure 5-5: Diode with a series resistor
5.8.8: Port Branches

The port access function accesses the flow into a port of a module. The name of the access function is
derived from the flow nature of the discipline of the port. However, (<>) is used to delimit the port
name, e. g. I(<a>) accesses the current through module port a.
Example
Writing the junction diode so that the diode current is monitored, and a message is issued if it exceeds
a given value.
module diode(a, c);

electrical a, c;
branch(a, c) i_diode, junc_cap;
parameter real is=1e-14, tf=0, cjo=0, imax=1, phi=0.7;
analog begin
I(i_diode) <+ is*(limexp(V(i_diode)/$vt) - 1);
I(junc_cap) <+
ddt(tf*I(i_diode) - 2*cjo*sqrt(phi*(phi*V(junc_cap))));

if (I(<a>) > imax)

$strobe(“warning: diode is melting!”);
end
endmodule
The expression V(<a>) is invalid for ports and nets where V is the potential access function. The port
branch I(<a>) cannot be used on the left side of a contribution operator <+.
5.9: Switch Branches

Source branches are able to switch between being potential and flow sources. To switch a branch to a
potential source, assign to its potential. To switch a branch to a flow source, assign to its flow. This type
of branch is useful when modeling ideal switches and mechanical stops. The full circuit model for a
switched branch is shown in Figure 5-6.
Figure 5-6: Circuit Model for a Switched Source Branch
Example
An ideal relay (a controlled switch) can be implemented as
module relay(p, n, ps, ns);
electrical p, n, ps, ns;
parameter vth = 0.5;
integer closed;
analog begin
closed = (V(ps, pn) > vth ? 1 : 0);

if (closed)
V(p, n) <+ 0;
else
I(p, n) <+ 0;
end
endmodule

5.9.1: Unassigned Sources

If a value is not assigned to a branch, the branch flow is set to zero (0).
Example
if (closed)
V(p, n) <+ 0;
is equivalent to
if (closed)
V(p, n) <+ 0;
else
I(p, n) <+ 0;
5.10: Signal Access for Vector Branches

VERILOG-A allows the user to arrange ports, nets, and branches as vectors. However, the access
functions can only be applied to scalars, or individual elements of a vector. The scalar element of a
vector is selected with an index. For example, V(in[1]) accesses the voltage in[1]. The index must
be a genvar expression consisting of literals and/or genvar variables, which can only be assigned to as
the iteration index for loops, and allow signal access within looping constructs.
Examples
The following is an application of access functions to elements of an analog signal vector.
// N-bit DAC example.
module dac(out, in, clk);

parameter integer width=8 from [2:24];
parameter real fullscale=1.0, vth=2.5, td=1n, tt=1n;
output out;
input [0:width - 1] in;
input clk;
electrical out;
electrical [0:width - 1] in;
electrical clk;
real aout;
genvar i;
analog begin
@(cross(V(clk) - vth, +1)) begin
aout = 0;
for (i = width - 1; i >= 0; i = i - 1) begin
if (V(in(i) > vth) begin
aout = aout + fullscale/pow(2, width - i);
end
end
end
V(out) <+ transition(aout, td, tt);

end
endmodule
// 8-bit fixed-width DAC example.
module dac8(out, in, clk);

parameter real fullscale=1.0, vth=2.5, td=1n, tt=1n;
output out;
input [0:7] in;
input clk;
electrical out;
electrical [0:7] in;
electrical clk;
real aout;
analog begin
@(cross(V(clk) - 2.5, +1)) begin
aout = 0;
aout = aout + ((V(in[7]) > vth) ? fullscale/2.0 : 0.0);
end
V(out) <+ transition(aout, td, tt);

end
endmodule
Syntax
access_function_reference ::=
bvalue
| pvalue
bvalue ::=
access_identifier (analog_signal_list)
analog_signal_list ::=
branch_indefier
| array_branch_identifier [ genvar_expression ]
| net_or_port_scalar_expression
| net_or_port_scalar_expression , net_or_port_scalar_expression
net_or_port_scalar_expression ::=

| net_or_port_identifier
| array_net_or_port_identifier [ genvar_expression ]
| vector_net_or_port_identifier [ genvar_expression ]
pvalue ::=
flow_access_identifier ( < port_scalar_expression > )
port_scalar_expression ::=
port_identifier
| array_port_identifier [ genvar_expression ]
| vector_port_identifier [ genvar_expression ]
5.10.1: Accessing Net and Branch Signals

Signals on nets and branches can be accessed by the access function of the discipline associated with
them. The name of the net and branch is specified by the argument to the access function.
Example
electrical out, in;

parameter real gm = 1;
analog
I(out) <+ gm*V(in);
electrical p, n;
branch(p, n) res;
parameter real R = 50;
analog
V(res) <+ R*I(res);
5.10.2: Accessing Attributes

The attributes of a net or branch are attached to the nature of a potential or a flow, and can be accessed
through the hierarchal referencing operator ( . ).
Example
electrical a, b, n1, n2;

branch(n1, n2) cap;
parameter real c = 1p;
analog begin
I(a, b) <+ c*ddt(V(a, b)), a.potential.abstol);
I(cap) <+ c*ddt(V(cap)), n1.potential.abstol);
end

Syntax
attribute_reference ::=
net_identifier.pot_or_flow.attribute_identifier
5.11: Contribution Statements

VERILOG-A describes analog behavior by way of the branch contribution operator <+, which is only valid
within an analog block. Branch contribution statements use the branch contribution operator in order
to describe behavior by way of a mathematical mapping of input to output signals.
5.11.1: Branch Contribution Statement

Branch contribution statements consist of two sides, a left hand and a right hand, which are separated
by a branch contribution operator. The right hand side is an expression that either evaluates to, or
promotes to a real value. The left hand side specifies the source branch signal where the right hand
side shall be assigned, and consists of a signal access function applied to a branch.
Analog behaviors can be described by the following:
V(n1, n2) <+ expression;

or
I(n1, n2) <+ expression;
(n1, n2) is an unnamed source branch, V(n1, n2) is the potential on the branch, and I(n1, n2)
is the flow on the branch. The nature of the expression can be linear, non-linear, or dynamic. The left
hand side cannot use a port access function. See the following example models a resistor and a
capacitor.
Example
electrical p, n;
analog
V(p, n) <+ r*I(p, n);
endmodule
module capacitor(p, n);

electrical p, n;
parameter real c = 0;
analog
I(p, n) <+ c*ddt(V(p, n));
endmodule

5.11.2: Relations
Source branch relations are defined by branch contribution statements. The branch is directed from
the first net of the access functions to the second net. If the second net is not specified, the global
reference node (ground) is used as the reference point.
The path of the flow between the two nets in a module is the branch relation. The potential and the
flow out of the net are the two quantities. In electrical circuits, the potential of a net is its voltage, and
the flow out is the current. Each branch also has two quantities, the potential and flow across the
branch.
Example
module amp(out, in);
input in;
output out;
voltage out, in;
parameter real Gain = 1;
analog
V(out) <+ Gain*V(in);
endmodule
5.11.3: Evaluation
For source branch contributions the statement is evaluated as following:
• The simulator evaluates the right hand side.
• The value of the right hand side is added to any previously retained value of the branch for any
later assignments to the branch. If there are no previously retained values, the right hand side is
retained.
• After the simulation, the retained value is assigned to the source branch.
Adding additional contribution statements to model the input admittance and output impedance adds
parasitics to the amplifier.
Example
module amp(out, in);
input in;
output out;
voltage out, in;
parameter real Gain=1, Rin=1, Cin=1, Rout=1, Lout=1;
analog begin
// gain of amplifier
V(out) <+ Gain*V(in);
// model input admittance

I(in) <+ V(in)/Rin;
I(in) <+ Cin*ddt(V(in));

// model output impedance

V(out) <+ Rout*I(out);
V(out) <+ Lout*ddt(I(out));
end
endmodule
5.11.4: Value Retention

If a flow is added to a branch that already has a value retained for the potential, the potential is
discarded and the branch is converted to a flow source. Alternately, if a potential is added to a branch
that already has a value retained for the flow, the flow is discarded and the branch is converted to a
potential source. This is used to model switches, but it is illegal to add to an external switch from
within an analog block.
Example
module switch(p, n, cp, cn);
electrical p, n, cp, cn;
parameter real thresh = 0.01;
analog begin
// resolve threshold crossings
@(cross(V(cp, cn) - thresh, 0));
if (V(cp, cn) > thresh)

V(p, n) <+ 0;
else
I(p, n) <+ 0;
end
endmodule
Syntax
analog_branch_contribution ::=
bvalue <+ analog_expression;
5.11.5: Indirect Branch Assignments

VERILOG-A allows descriptions that implicitly specify a branch voltage or current in a fixed point form.
Branch voltage or current is assigned a value by the expression that uses it. See section 5.8.7:“Simple
Implicit Diode” where I(a,c) appeared on both sides of the contribution operator.
Example
Consider the model for an ideal opamp. The output is driven to the voltage which results in the input
voltage being zero (0). The constitutive equation is:
V(in) == 0;

which can be formulated as:
V(out) <+ V(out) + V(in);
This statement defines the output of the opamp to be a controlled voltage source by assigning to
V(out) and defines the input to be high impedance by only probing the input voltage. The desired
behavior results because the description is formulated in such a way it reduces to V(in) = 0. This
approach does not result in the right tolerances being applied to the equation if out and in have
different disciplines.
Verilog-A includes a special syntax to use in this situation. The above branch contribution can be
rewritten using an indirect branch assignment:
V(out) : V(in) == 0;
which reads “find V(out) so that V(in) == 0”.

This indicates that out is driven with a voltage source, and the source voltage needs to satisfy the
given equation. Branches that are referenced in the equation are only probed, not driven. In particular,
V(in) acts as a voltage probe.
Example
A complete description of an ideal opamp is:
module opamp(out, pos_in, neg_in);

electrical out, pos_in, neg_in;
analog
V(out) : V(pos_in, neg_in) == 0;
endmodule
Syntax
analog_indirect_branch_assignments ::=
bvalue : nexpr == analog_expression;
nexpr ::=
bvalue
|pvalue
|ddt (bvalue | pvalue)
|idt (bvalue | pvalue)

5.11.6: Multiple Indirect Assignments

For multiple indirect assignments statements, the targets can be paired with any equation.
Examples
The following differential equation:
dx
------- = f ( x, y, z )
dt
dy
------- = g ( x, y, z )
dt
dz
------ = h ( x, y, z )
dt
can be written as:
V(x) : ddt(V(x)) == f(V(x), V(y), V(z));

V(y) : ddt(V(y)) == g(V(x), V(y), V(z));
V(z) : ddt(V(z)) == h(V(x), V(y), V(z));
or
V(y) : ddt(V(x)) == f(V(x), V(y), V(z));

V(z) : ddt(V(y)) == g(V(x), V(y), V(z));
V(x) : ddt(V(z)) == h(V(x), V(y), V(z));
or
V(z) : ddt(V(x)) == f(V(x), V(y), V(z));

V(x) : ddt(V(y)) == g(V(x), V(y), V(z));
V(y) : ddt(V(z)) == h(V(x), V(y), V(z));
without affecting the results.
5.11.7: Indirect Assignments and Contributions

Indirect assignments and contributions are incompatible. Once a value is indirectly assigned to a
branch, it cannot be contributed to using the branch contribution operator <+. It is illegal to indirectly
assign or contribute to an external branch which has an indirect branch assignment.


Chapter 6:
Expressions and Operators for Analog Blocks
6.1: Overview of Expressions and Operators

An expression is a construct that combines operands with operators to produce a result that is a
function of the values of the operands and the semantic meaning of the operators. Any legal operand is
also an expression.
A constant expression is an expression whose operands are constant numbers, and previously
defined parameters; and whose operators all come from among the unary, binary, and ternary
operators described in this chapter.
The operators listed below, with the single exception of the conditional operator, associate from left to
right. That means that when operators have the same precedence, the one farthest to the left is
evaluated first.
6.2: Operators
The symbols for the VERILOG-A operators are similar to those in the C programing language. Table 6-1
lists these operators:
Table 6-1: Operators
+ - * / Arithmetic
% Modulus
> >= < <= Relational
!== === Case equality
!= == Logical equality
! Logical negation
&& Logical and
|| Logical or
~ Bit-wise negation
& Bit-wise and
| Bit-wise inclusive or
^ Bit-wise exclusive or
^~ ~^ Bit-wise equivalence
<< Left shift
>> Right shift
?: Conditional
or Event or
{} {{}} Concatenation, replication

6.2.1: Operators With Real Operands

The operators in Table 6-2 are legal when applied to real operands. All other operators are considered
illegal when used with real operands.
Table 6-2: Legal Operators for use in Real Expressions
unary+ unary- Unary Operators
+ - * / Arithmetic
% Modulus
> >= < <= Relational
!= == Logical equality
! && || Logical
?: Conditional
or Event or
The result of using logical or relational operators on real numbers is an integer value 0 (false) or 1
(true).
Table 6-3 lists those operators which shall not be used to operate on real numbers.
Table 6-3: Operators not allowed for Real Expressions
!== === Case equality
~ & | ^ ^~ ~^ Bit-wise
<< >> Shift
{} {{}} Concatenation and

replication operator.
6.2.2: Real to Integer Conversion

Real numbers are converted to integers by rounding the real number to the nearest integer, rather
than by truncating. When a real number is assigned to an integer, the implicit conversion takes place.
The ties are rounded away from zero (0).
Examples
// The real numbers 35.6 and 35.5 both become 36 when
// converted to an integer and 35.2 becomes 35.
// Converting -1.5 to integer yields -2, converting 1.5 to

// integer yields 2.

6.2.3: Arithmetic Conversion

A common data type for each operand is determined before the operator is applied. If either operand is
real, the other is likewise converted to real. Implicit conversion takes place when an integer number is
used with a real number in an operand.
Examples
a = 3 + 5.0;
// The expression “3 + 5.0” is evaluated by “casting” the
// integer 3 to the real 3.0, and the result of the expression is 8.0.
b = 1 / 2;
// The above is integer division and the result is 0.
c = 8.0 + (1 / 2);
// (1 / 2) is treated as integer division, but the result of the
// expression is 8.0
6.2.4: Binary Operator Precedence

Table 6-4 shows the precedence order of binary operators and the conditional operator (?:).
Table 6-4: Precedence Rules for Binary Operators
+ - ! ~ (unary) Highest precedence
* / %
+ - (binary)
<< >>
< <= > >=
== != === !==
& ~&
^ ^~ ~^
| ~|
&&
||
?: (conditional operator Lowest precedence
The operators shown in Table 6-4 have the same precedence. The rows are arranged in order of
decreasing precedence for the operators.
All operators associate from left to right, except for the conditional operator which associates from
right to left. The association refers to the order in which the operators of the same precedence are
evaluated.

Example
When B is added to A and the C is extracted from the result of A + B:
A + B - C
When operators differ in precedence, the operators with higher precedence associate first.
Examples
B is divided by C (division has higher precedence than addition) and then the result is added to A:
A + B / C
Parentheses can be used to change the operator precedence:
(A + B) / C
// not the same as A + B / C
6.2.5: Expression Evaluation Order

The operators follow the associativity rules while valuating an expression as described in section
6.2.4:“Binary Operator Precedence”. However, if the final result of an expression can be determined
early, the entire expression does not need to be evaluated, as long as the remaining expression does not
contain analog expressions. This is called short circuiting and expression evaluation.
Example
integer A, B, C, result;
result = A & (B | C);
If A is known to be zero (0), the result of the expression can be determined as zero (0) without
evaluating the sub-expression B | C.
6.2.6: Arithmetic Operators

Unary Operators
The unary operators each require a single operand. The unary operators have the highest precedence
of all the operators discussed in this chapter. The unary arithmetic operators take precedence over the
binary operators. Table 6-5 shows the unary operators
Table 6-5: Unary Operators Defined
+m Unary plus m (same as m)
-m Unary minus m
! Logical Negator
~ Bitwise Unary Negator

Binary Operators
Table 6-6 shows the binary arithmetic operators. The binary operators each require two operands.
Table 6-6: Arithmetic Operators Defined
a + b a plus b
a - b a minus b
a * b a multiply by b
a / b a divide by b
a % b a modulo b
Integer division truncates any fractional part towards zero (0).

The modulus operator, for example y % z, gives the remainder when the first operand is divided by the
second, and zero (0) when z divides y exactly. The result of a modulus operation takes the sign of the
first operand.
For the case of the modulus operator where either argument is real, the operation performed is:
a % b = a - floor1(a/b)*b;
Table 6-7 gives examples of modulus operations.
Table 6-7: Examples of Modulus Operations
Modulus expression Result Comments
11 % 3 2 11/3 yields a remainder of 2.
12 % 3 0 12/3 yields no remainder.
-10 % 3 -1 The result takes the sign of the first operand
11 % -3 2 The result takes the sign of the first operand
10 % 3.75 2.5 [10 - floor (10/3.75) * 3.75 ] yields a remainder of 2.5.
1. floor(a/b)= largest integer less than or equal to (a/b).

6.2.7: Relation Operators

Table 6-8 lists and defines the relational operators.
Table 6-8: Relational Operators Defined
a<b a less than b
a>b a greater than b
a <= b a less than or equal to b
a >= b a greater than or equal to b
An expression using these relational operators yields the value zero (0) if the specified relation is false,
or the value one (1) if it is true. All the relational operators have the same precedence. Relational
operators have lower precedence than arithmetic operators. The following examples show the
implications of this precedence rule.
Examples
a < Fxx - 1 // this expression is the same as

a < (Fxx -1) // this expression, but...
Fxx - (1 < a) // this one is not the same as
Fxx - 1 < a // this expression
When Fxx - (1 < a) is evaluated, the relational expression is evaluated first, and then either zero
(0) or one (1) is subtracted from Fxx. When Fxx - 1 < a is evaluated, the value of Fxx operand is
reduced by one (1) and then compared with a.
6.2.8: Case Equality Operators

The case equality operators share the same level of precedence as the logical equality operators.
6.2.9: Logical Quality Operators

The logical equality operators rank lower in precedence than the relational operators. Table 6-9 lists
and defines the equality operators.
Table 6-9: Equality Operators Defined
a == b a equal to b
a != b a not equal to b
Both equality operators have the same precedence. These operators compare the value of the operands.
As with the relational operators, the result shall be zero (0) if comparison fails, or else one (1) if it
succeeds.

6.2.10: Logical Operators

The operators logical and (&&), and logical or (| |) are logical connectives. The result of the evaluation
of a logical comparison can be one (1, defined as true) or zero (0 defined as false). The precedence of &&
is greater than that of || and both are lower than relational and equality operators. A third logical
operator is the unary logical negation operator (!). The negation operator converts a non-zero or true
operand into zero (0), and a zero or false operand into one (1).
Examples
The following expression performs a logical and three sub-expressions without needing any
parentheses:
a < param1 && b != c && index != lastone
However, parentheses can be used to clearly show the precedence intended, as in the following rewrite
of the above example:
(a < param1) && (b != c) && (index != lastone)
6.2.11: Bit-Wise Operators

Bit-wise operators perform bit-wise manipulations on the operands. The operator combines a bit in one
operand with its corresponding bit in the other operand to calculate one bit for the result.
See Table 6-10 through Table 6-14 for details.

Table 6-10: Bit-Wise binary and operator Table 6-11: Bit-Wise exclusive or operator
& 0 1 ^ 0 1
0 0 0 0 0 1
1 0 1 1 1 0
Table 6-12: Bit-Wise binary or operator Table 6-13: Bit-Wise binary exclusive nor
Table 6-12: operator
| 0 1 ^~ 0 1
~^
0 0 1
0 1 0
1 1 1
1 0 1
Table 6-14: Bit-Wise unary negation

operator
0 1
1 0

6.2.12: Shift Operators

The shift operators (<< >>) perform left and right shifts of their left operand by the number of bit
positions given by the right operand. Both fill the vacated bit positions with zeros (0). The right
operand is treated as an unsigned number.
Example
integer start, result;
analog begin
start = 1;
result = (start << 2);
end
In this example, the register result is assigned the binary value 0100, which 0001 shifted to the left
two positions and zero-filled.
6.2.13: Ternary Operator

There is only one ternary operator, the conditional operator. The conditional operator has the lowest
precedence of all the operators listed in this chapter. A complete conditional operator expression looks
like this:
conditional_expr ? true_expr : false_expr
If conditional_expr is true, the conditional operator evaluates to true_expr, otherwise to

false_expr.
The conditional operator is right associative.
This operator performs the same function as the if-else construct. For example, the contribution
statement:
V(out) <+ V(in) > 2.5 ? 0.0 : 5.0;
is equivalent to:
If (V(in) > 2.5)

V(out) <+ 0.0;
else
V(out) <+ 5.0;
6.2.14: Event OR Operator

The event or operator performs the occurance of any one of the elements that trigger the execution of
the procedural statement following the event.
Example
analog begin
@(initial_step or cross(V(smpl) -2.5, +1)) begin

Vout = (V(in) > 2.5);

end
V(out) <+ Vout;
end
The initial step is a global event, and cross() returns a monitered event. The variable Vout
is set to zero (0) or one (1) whenever either event occurs.
6.2.15: Concatenations
A concatenation is used for joining scalar elements into compound elements (buses or arrays) for the
built-in types integer or real, or for elements declared type net_discipline. The concatenation is
expressed using the brace characters ({ }), with commas separating the expressions within.
Examples
module x;
parameter real p1[0:2] = {1.0, 2.0, 3.0};
...
endmodule
module y;
parameter real pole1=0, pole2=0, pole3=0;
x #(.p1({pole1, pole2, pole3}) x1;
...
endmodule
Module x defines a real array parameter p1. Module y instantiates x and overrides the array value of
the parameter p1 of module x via the concatenation of the scalar parameters pole1, pole2, and pole3.
Concatenation can be expressed using a replication multiplier.
Example
{c, {2{a, b}}} // equivalent to : {c, a, b, a, b}
The replication multiplier is a constant expression.

6.3: Analog Operators

Analog operators operate on an expression and return a value. They are functions that operate on
more than just the current value of their arguments, they maintain their internal state, and their
output is a function of both the input and the internal state.
Analog operators are referred to as filters. They include time derivative, time integral, and delay
operators from calculus. They also include the transition and slew filters, which remove discontinuity
from piece wise constant and continuous waveforms. They also include more traditional filters, such as
those described with laplace and Z-transform descriptions.
One special analog operator is the limexp() function, which is a version of the exp() function with
built in limits to improve convergence.
6.3.1: Restrictions To Analog Operators

Analog operators are subject to several important restrictions because they maintain their internal
state.
• Analog operators shall not be used inside conditional (if and case) or looping (for) statements
unless the conditional expression controlling the statement consists of terms which cannot change
their value during the course of an analysis, i.e, unless the conditional expression is a genvar
expression.
• Analog operators are not allowed in the repeat and while looping statements.
• Analog operators can only be used inside an analog block; they cannot be used inside an initial
or always block, or inside a user defined function.
• It is illegal to specify a null argument in the argument list of an analog operator, except as
specified elsewhere in this document.
These restrictions help prevent usage which could cause the internal state to be corrupted or become
out of date, which results in anomalous behavior.
6.3.2: Vector or Array Arguments To Analog Operators

Some analog operators require arrays or vectors to be passed as arguments: Laplace filters, Z-
transform filters, and noise_table. An array can be passed as:
• array_identifier
• const_array_expression
A const_array_expression allows the arrays to be passed within the argument list without
explicit declaration of the array object, as shown:
Syntax
const_array_expression
{const_arrayinit_element { , const_arrayinit_element}}
const_arrayinit_element ::=
constant_expression
| integer_constant_expression {constant_expression}

6.3.3: Analog Operators and Equations

Simulators formulate the mathematical description of the system in terms of first order differential
equations and solve them numerically. There is no direct way to solve a set of nonlinear differential
equations so iterative approaches are used. When using iterative approaches, some criteria
(tolerances) is needed to determine when the algorithm knows when it is close enough to the solution
and then stops the iteration. Thus, each equation, at a minimum, shall have a tolerance defined and
associated with it.
Occasionally, analog operators require new equations and new unknowns be introduced by the
simulator to convert a module description into a set of first order differential equations. In this case,
the simulator attempts to determine from context which tolerance to associate with the new equation
and new unknown. Alternatively, these operators can be used to specify tolerances.
Specifying natures also directly enforces reusability, and allows other signal attributes to be accessed
by the simulator.
6.3.4: Time Derivative Operator

The ddt operator computes the time derivative of its argument, as shown in Table 6-15.
Table 6-15: Time Derivative
Operator Comments
ddt(expr) d
Returns ------ x ( t ) , the time derivative of x, where x is expr.
dt
ddt(expr, abstol) Same as above, except absolute tolerance is specified explicitly.
ddt(expr, nature) Same as above, except nature is specified explicitly.
In DC analysis, ddt() returns zero (0). The optional parameter abstol is used as an absolute
tolerance if needed. Whether an absolute tolerance is needed depends on the context where ddt() is
used. The absolute tolerance, abstol or derived nature, applies to the output of the ddt operator
and is the largest signal level that is considered negligible.
6.3.5: Time Integral Operator

The idt operator computes the time integral of its argument, as shown in Table 6-16.
Table 6-16: Time Integral
Operator Comments
idt(expr) t
Returns ∫ x ( τ )dτ , the time integral of x from 0 to t with the initial
0
condition being computed in the DC analysis. Where x is expr.
idt(expr, ic) t
Returns ∫ x ( τ )dτ + ic , the time integral of x from 0 to t with the ini-
0
tial condition ic. In DC analysis, ic is returned. Where x is expr.

Table 6-16: Time Integral
Operator Comments
idt(expr, ic, assert) t

Returns ∫ t0
x ( τ ) dτ + ic , the time integral of x from t0 to t with the ini-
tial condition ic. idt returns ic when assert is non-zero. t0 is the

time when assert last became 0. Where x is expr.
idt(expr, ic, assert, abstol) Same as above, except absolute tolerance is specified explic-
itly.
idt(expr, ic, assert, nature) Same as above, except nature is specified explicitly.
When specified with initial conditions, idt() returns the value of the initial condition in DC and IC
analyses whenever assert is given and is non-zero. Without initial conditions, idt() multiplies its
arguments by infinity in DC analysis. Hence, without initial conditions, it can only be used in a system
with feedback which forces its argument to zero (0).
The optional parameter abstol or nature is used to derive an absolute tolerance if needed.
Whether an absolute tolerance is needed depends on the context where idt() is used. The asolute
tolerance applies to the input of the idt operator and is the largest signal level that is considered
negligible.
6.3.6: Circular Integrator Operator

The idtmod operator, also called the circular integrator, converts an expression argument into its
indefinitely integrated form similar to the idt operator, as shown it Table 6-17.
Table 6-17: Circular Integrator
Operator Comments
idtmod(expr) t
Returns ∫ x( τ )dτ , the time integral of x from 0 to t with the initial
0
condition being computed in the DC analysis. Where x is expr.
idtmod(expr, ic) t
Returns ∫ x( τ )dτ + ic , the time integral of x from 0 to t with the ini-
0
tial condition ic. In DC analysis, ic is returned. Where x is expr.
idtmod(expr, ic, modulus) Returns k, where 0 < k < modulus and k is

t
∫ x ( τ )dτ + ic = n × mo dulus + k, n = ...-3, -2, -1, 0, 1, 2, 3... . Where x is

0
expr.
idtmod(expr, ic, modu- Returns k, where 0 < k < offset + modulus and k is
lus,offset) t
∫ x( τ ) dτ + ic = n × mo dulus + k
0
. Where x is expr.

Table 6-17: Circular Integrator
Operator Comments
idtmod(expr, ic, modu- Same as above, except absolute tolerance is specified explicitly.
lus,offset, abstol)
idtmod(expr, ic, modu- Same as above, except nature is specified explicitly.

lus,offset,nature)
The initial condition is optional. If the initial condition is not specified, it defaults to zero (0).
Regardless, the initial condition shall force the DC solution to the system.
If idtmod() is used in a system with feedback configuration which forces expr to zero (0), the initial
condition can be omitted without any unexpected behavior during simulation. For example, an
operational amplifier alone needs an initial condition, but the same amplifier with the right external
feedback circuitry does not need a forced DC solution.
The output of the idtmod() function shall remain in the range:
offset <= idtmod < offset + modulus
The modulus shall be an expression which evaluates to a positive value. If the modulus is not
specified, then idtmod() will behave like idt() and not limit the output of the integrator..
The default for offset is zero (0).
The following relationships between idtmod() and idt() shall hold at all times.
Examples
if:
y = idt(expr, ic);
z = idtmod(expr, ic, modulus, offset);
then:
y = n*modulus + z; // n is an integer
where:
offset < z < modulus + offset
In this example, the circular integrator is useful in cases where the integral can get very large, such as
a VCO. In a VCO we are only interested in the output values in the range [0, 2π]:
phase = idtmod(fc + gain*V(in), 0, 1, 0);
V(OUT) <+ sin(2*‘M_PI*phase);
Here, the circular integrator returns a value in the range [0,1].
6.3.7: Absolute Delay Operator

absdelay() implements the absolute transport delay for continuous waveforms (use the transition
operator to delay discrete value waveforms). The general form is:
absdelay(input, td [, maxdelay])

input is delayed by the amount td. In all cases, td will be a positive number. If the optional
maxdelay is specified, then td can vary; but it shall be an error if it becomes larger than maxdelay.
If maxdelay is not specified, changes to td will be ignored. If maxdelay is specified, changes to td
are ignored and the initial value of maxdelay is used.
In DC and operating point analyses, absdelay() returns the value of its input. In AC and other small
signal analyses, the absdelay operator phase-shifts the input expression to the output of the delay
operator based on the following formula:
– jωtd
Output ( ω ) = Input ( ω ) ⋅ e
td is evaluated as a constant at a particular time for any small signal analysis. In time domain
analyses, absdelay() introduces a transport delay equal to the instantaneous value of td based on the
following formula:
Output ( t ) = Input ( max ( t – td, 0 ) )

The transport delay td can be either constant (typical case) or vary as a function of time (when
maxdelay is defined). A time dependent transport delay is shown in Figure 6-1 with a ramp input to
the absdelay operator for both positive and negative changes in the transport delay td and a
maxdelay of 5.
Figure 6-1: Transport Delay Example
From time 0 to 2s, the output remains at input (0). With a delay of 2s, the output then starts tracking
input(t - 2). At 3s, the transport delay changes from 2s to 4s, switching the outputback to input(0),
since input(max(t-td, 0)) returns 0. The output remains at this level until 4s when it once again starts
tracking the input from t = 0. At 5s the transport delay goes to 1s and the output correspondingly
jumps from its current value to the value defined by input(t - 1).
6.3.8: Transition Filter

transition() smooths out piecewise constant waveforms. The transition filter is used to imitate
transitions and delays on digital signals (for non-piecewise constant signals, see section 6.3.9). This
function provides controlled transitions between discrete signal levels by setting the rise time and fall
time of signal transitions, as shown in Figure 6-2.

Figure 6-2: Transition Filter
transition() stretches instantaneous changes in signals over a finite amount of time and can delay
the transitions, as shown in Figure 6-3.
Figure 6-3: Shifting The Transition Filter
Syntax
The general form is:
transition(expr [ , td [ , rise_time [ , fall_time [ , time_tol ]]]])
transition() takes the following arguments (all real-valued expressions):

• the input expression, expr
• the delay time, td (shall be non-negative)
• the rise time (shall be greater than or equal to 0)
• the fall time (shall be greater than or equal to 0)
• the time_tol (shall be positive)
The input expression is expected to evaluate over time to a piecewise constant waveform. When
applied, transition() forces all positive transitions of expr to occur over rise_time and all
negative transitions to occur in fall_time (after an initial delay of td). Thus, td models transport
delay and rise_time and fall_time model inertial delay.
transition() returns a real number which describes a piecewise linear function over time. The
transition function causes the simulator to place time-points at both corners of a transition. If time_tol
is not specified, the transition function causes the simulator to assure each transition is adequately
resolved.
td, rise_time, fall_time, and time_tol are optional. If td is not specified, it is taken to be
zero (0.0). If only a positive rise_time value is specified, the simulator uses it for both rise and fall

times. If neither rise nor fall time is specified or is equal to zero (0.0), the rise and fall time defaults
to the value defined by ‘default_transition.
If ‘default_transition is not specified, the default behavior approximates the ideal behavior of a
zero-duration transition. Forcing a zero-duration transition is undesirable because it could cause
convergence problems. Instead, a negligible, but non-zero, transition time is used. The small non-zero
transition time allows the simulator to shrink the timestep small enough so a smooth transition
occurs, and convergence problems are avoided. The simulator does not force a time point at the trailing
corner of a transition to avoid causing the simulator to take very small time steps, which would result
in poor performance.
In DC analysis, transition() passes the value of the expr directly to its output. The transition filter
is designed to smooth out piecewise constant waveforms. When applied to waveforms which vary
smoothly, the simulation results are generally unsatisfactory. In addition, applying the transition
function to a continuously varying waveform can cause the simulator to run slowly. Use transition()
for discrete signals and slew() (see section 6.3.9:“Slew Filter”) for continuous signals.
Use short transitions with caution because they can cause the simulator to slow down to meet
accuracy constraints.
The next code fragment demonstrates how the transition filter might be used.
// comparator model
analog begin
if ( V(in) > 0 ) begin
Vout = 5;
end
else begin
Vout = 0;
end
V(out) <+ transition(Vout);
end
Warning: The transition filter is designed to smooth out piecewise constant waveforms. If one apply the
transition filter to smoothly varying waveforms, the simulator might run slowly, and the results
questionable. For smoothly varying waveforms, consider using the slew filter instead.
If interrupted on a rising transition, the transition filter adjusts the slope so that at the revised end of
the transition the value is that of the new destination.

If the new destination value is below the value at the point If the new destination value is above the value at the
of interruption, the transition filter. point of interruption, the transition filter.
1. Uses the value of the original destination as the 1. Retains the original origin.
value of the new origin.
2. Adjusts the slope of the transition to the rate at 2. Adjusts the slope of the transition to the rate
which the value would decay from the value of the at which the value would increase from the
new origin to the value of the new destination in value of the origin to the value of the new
fall_time seconds. destination in rise_time seconds.
3. Causes the value of the filter output to decay at 3. Causes the value of the filter output to
the new slope, from the value at the point of increase at the new slope, from the value at the
interruption to the value at the new destination. point of interruption to the at the new
destination.
In the following example, a rising transition is interrupted when it is about three fourths complete,
and the value of the new destination is below the value at the point of interruption. The transition
filter computes the slope that would complete a transition from the new origin (not the value at the
point of interruption) in the specified fall_time. The transition filter then uses the computed slope
to transition from the current value to the new destination.
Figure 6-4: Complete Transition
An interruption in a falling transition causes the transition filter to behave in an equivalent manner.
With larger delays, it is possible for a new transition to be specified before a previously specified
transition starts. The transition filter handles this by deleting any transitions that would follow a
newly scheduled transition. A transition filter can have an arbitrary number of transitions
pending. A transition filter is used in this way to implement the transport delay of discretely
valued signals.
The following example implements a D-type flip flop. The transition filter smooths the output
waveforms.
Example
module d_ff(vin_d, vclk, vout_q, vout_qbar);

input vclk, vin_d;

output vout_q, vout_qbar;
electrical vout_q, vout_qbar, vclk, vin_d;
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans_clk = 2.5;
parameter real vtrans = 2.5;
parameter real tdel = 3u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);
integer x;
analog begin
@(cross( V(vclk) - vtrans_clk, +1 )) x = (V(vin_d) > vtrans);
V(vout_q) <+ transition(vlogic_high*x + vlogic_low*!x,tdel, trise, tfall);
V(vout_qbar) <+ transition(vlogic_high*!x + vlogic_low*x, tdel,
trise, tfall);
end
endmodule
The following example illustrates a use of the transition filter that should be avoided. The
expression is dependent on a continuous signal and, as a consequence, the filter runs slowly.
I(p, n) <+ transition(V(p, n)/out1, tdel, trise, tfall); // Do not do this.
However, the following approach can be used to implement the same behavior in a statement that runs
much faster.
I(p, n) <+ V(p, n)*transition(1/out1, tdel, trise, tfall); // Do this instead.
Examples
Example 1 - QAM modulator
In this example, the transition function is used to control the rate of change of the modulation signal in
a QAM modulator.
module qam16(out, in);
parameter freq=1.0, ampl=1.0, dly=0, ttime=1.0/freq;
input [0:4] in;
output out;
electrical [0:4] in;
electrical out;
real x, y, thresh;
integer row, col;
analog begin
row = 2*(V(in[3]) > thresh) + (V(in[2]) > thresh);
col = 2*(V(in[1]) > thresh) + (V(in[0]) > thresh);
x = transition(row - 1.5, dly, ttime);
y = transition(col - 1.5, dly, ttime);
V(out) <+ ampl*x*cos(2*‘M_PI*freq*$abstime)
+ ampl*y*sin(2*‘M_PI*freq*$abstime);
$bound_step(0.1/freq);
end

endmodule
Example 2 - A/D converter

In this example, an analog behavioral N-bit analog to digital converter, demonstrates the ability of the
transition function to handle vectors.
module adc(in, clk, out);
parameter bits = 8, fullscale = 1.0, dly = 0, ttime = 10n;
input in, clk;
output [0:bits-1] out;
electrical in, clk;
electrical [0:bits-1] out;
real sample, thresh;
integer result[0:bits-1];
genvar i;
analog begin
@(cross(V(clk)-2.5, +1)) begin
sample = V(in);
thresh = fullscale/2.0;
for (i = bits - 1; i >= 0; i = i - 1) begin
if (sample > thresh) begin
result[i] = 1.0;
sample = sample - thresh;
end else begin
result[i] = 0.0;
end
sample = 2.0*sample;
end
end
for (i = 0; i < bits; i = i + 1) begin

V(out[i]) <+ transition(result[i], dly, ttime);
end
end
endmodule
6.3.9: Slew Filter

Use the slew filter to control the rate of change of a waveform. A typical use for slew is generating
continuous signals from piecewise continuous signals. For discrete signals, consider using the
transition filter instead.
slew(expr [ , max_pos_rate [ , max_neg_rate ] ] )
expr is a dynamic expression with a real value.
max_pos_rate is a dynamic real number greater than zero, which is the maximum positive slew
rate.
max_neg_rate is a dynamic real number less than zero, which is the maximum negative slew rate.

If only one rate is specified, its absolute value is used for both rates. If no rates are given, slew passes
the signal through unchanged. If the rate of change of expr is less than the specified maximum slew
rates, slew returns the value of expr..
When applied, slew forces all transitions of expr faster than max_pos_rate to change at the
max_pos_rate rate for positive transitions, and limits negative transitions to the max_neg_rate
rate.
Figure 6-5: Slew Filter
The slew filter is particularly valuable for controlling the rate of change of sinusoidal waveforms. The
transition function distorts such signals, whereas slew preserves the general shape of the
waveform.
The following 4-bit digital-to-analog converter uses the slew function to control the rate of change of
the analog signal at its output.
Example
module dac4(d, out);
input [0:3] d;
inout out;
electrical [0:3] d;
electrical out;
parameter real slewrate = 0.1e6 from (0:inf);
real Ti;
real Vref;
real scale_fact;
analog begin
Ti = 0;
Vref = 1.0;
scale_fact = 2;
generate ii (3,0,-1) begin
Ti = Ti + ((V(d[ii]) > 2.5) ? (1.0/scale_fact) : 0);
scale_fact = scale_fact/2;
end
V(out) <+ slew( Ti*Vref, slewrate );
end
endmodule

6.3.10: last_crossing function

Related to the cross() function, the last_crossing() function returns a real value representing the
simulation time when a signal expression last crossed zero (0). The general form is:
last_crossing( expr , direction ) ;
The direction flag is interpreted in the same way as in the cross() function. The last_crossing()
function is subject to the same usage restrictions as the cross() function. The last_crossing()
function does not control the timestep to get accurate results; it uses linear interpolation to estimate
the time of the last crossing. However, it can be used with the cross function for improved accuracy.
Example
The following example measures the period of its input signal using the cross() and last_crossing()
functions.
module period(in);
input in;
voltage in;
integer crossings;
real latest, previous;
analog begin
crossings = 0;
previous = 0;
end
@(cross(V(in), +1)) begin

crossings = crossings + 1;
previous = latest;
end
latest = last_crossing(V(in), +1);
@(final_step) begin
if (crossings < 2)
$strobe("Could not measure period.");
else
$strobe("period = %g, crossings = %d",
latest-previous, crossings);
end
end
endmodule
Before the expression crosses zero (0) for the first time, the last_crossing() function returns a
negative value.
6.3.11: Laplace Transform Filters

The Laplace transform filters implement lumped linear continuous-time filters. Each filter takes an
optional parameter ε, which is a real number or a nature used for deriving an absolute tolerance (if

needed). Whether an absolute tolerance is needed depends on the context where the filter is used. The
zeros argument may be represented as a null argument. The null argument is characterized by two
adjacent commas (,,) in the argument list.
laplace_zp
laplace_zp() implements the zero-pole form of the Laplace transform filter. The general form is:
laplace_zp( expr , ζ , ρ [ , ε ] )
where ζ (zeta) is a vector of M pairs of real numbers. Each pair represents a zero, the first number in
the pair is the real part of the zero and the second is the imaginary part. Similarly, ρ (rho) is the vector
of N real pairs, one for each pole. The poles are given in the same manner as the zeros. The transfer
function is:
M–1
∏  1 – -------------------
-
s
ζ + jζ  r
k k
i
H(s ) = k=0
---------------------------------------------
N–1
-
∏  1 – --------------------
-
s
ρ + jρ  r
k
i
k
k=0
r i r i
where ζ and ζ are the real and imaginary parts of the kth zero (0), while ρ and ρ are the real
k k k k
and imaginary parts of the kth pole. If a root (a pole or zero) is real, the imaginary part shall be
specified as zero (0). If a root is complex, its conjugate shall also be present. If a root is zero, then the
term associated with it is implemented as s, rather than (1 - s/r) (where r is the root).
laplace_zd
laplace_zd() implements the zero-denominator form of the Laplace transform filter. The general form
is:
laplace_zd( expr , ζ , d [ , ε ] )
the pair is the real part of the zero and the second is the imaginary part. Similarly, d is the vector of N
real numbers containing the coefficients of the denominator. The transfer function is:
M–1
∏  1 – -------------------
-
s
ζ + jζ  r
k
i
k
H ( s ) = ---------------------------------------------
k=0
N–1
-
∑d s
k
k
k=0

r i
where ζ and ζ are the real and imaginary parts of the kth zero, while dk is the coefficient of the kth
k k
power of s in the denominator. If a zero is real, the imaginary part shall be specified as zero (0). If a
zero is complex, its conjugate shall also be present. If a zero is zero (0), then the term associated with
it is implemented as s, rather than (1 - s/ζ).
laplace_np
laplace_np() implements the numerator-pole form of the Laplace transform filter. The general form
is:
laplace_np( expr , n , ρ [ , ε ] )
where nk is a vector of M real numbers containing the coefficients of the numerator. Similarly, ρ (rho)
is a vector of N pairs of real numbers. Each pair represents a pole, the first number in the pair is the
real part of the pole and the second is the imaginary part. The transfer function is:
M–1
∑n s
k
k
H ( s ) = ---------------------------------------------
N–1
k=0
-
∏  1 – --------------------
-
s
ρ + jρ  r
k
i
k
k=0
r i
where nk is the coefficient of the kth power of s in the numerator, while ρ and ρ are the real and
k k
imaginary parts of the kth pole. If a pole is real, the imaginary part shall be specified as zero (0). If a
pole is complex, its conjugate shall also be present. If a pole is zero (0), then the term associated with it
is implemented as s, rather than (1 - s/ρ).
laplace_nd
laplace_nd() implements the numerator-denominator form of the Laplace transform filter.
The general form is:
laplace_nd( expr , n , d [ , ε ] )
where n is an vector of M real numbers containing the coefficients of the numerator, and d is a vector
of N real numbers containing the coefficients of the denominator. The transfer function is:
M
∑n s
k
k
H ( s ) = k---------------------
N
=0
-
∑d s k
k
k=0

where nk is the coefficient of the kth power of s in the numerator and dk is the coefficient of the kth
power of s in the denominator.
Examples
V(out) <+ laplace_zp(V(in), {-1,0}, {-1,-1,-1,1});
implements:
1+s
H ( s ) = ----------------------------------------------------
 1 + ----------s 
- 1 + ----------
s
 1 + j  1 – j
and
V(out) <+ laplace_nd(V(in), {0,1}, {-1,0,1});
implements:
s
H ( s ) = -------------
2
-
s –1
This example:
V(out) <+ laplace_zp(white_noise(k), , {1,0,1,0,-1,0,-1,0});
implements a band-limited white noise source as:
2 k
v out = ------------------2-
2
s –1
6.3.12: Z-Transform Filters

The Z-transform filters implement linear discrete-time filters. Each filter supports a parameter T
which specifies the sampling period of the filter. A filter with unity transfer function acts like a simple
sample-and-hold, which samples every T second and exhibits no delay. The zeros argument may be
represented as a null argument. The null argument is characterized by two adjacent commas (,,) in
the argument list.
All Z-transform filters share three common arguments: T, τ, and t0. T specifies the period of the filter,
is mandatory, and shall be positive. τ specifies the transition time, is optional, and shall be
nonnegative.
If the transition time is specified and is non-zero, the timestep is controlled to accurately resolve both
the leading and trailing corner of the transition. If it is not specified, the transition time is taken to be
one (1) unit of time (as defined by the ‘default_transition compiler directive) and the timestep is not
controlled to resolve the trailing corner of the transition. If the transition time is specified as zero (0),
then the output is abruptly discontinuous. A Z-filter with zero (0) transition time shall not be directly
assigned to a branch.
Finally t0 specifies the time of the first transition, and is also optional. If not given, the first transition
occurs at t=0.

zi_zp
zi_zp() implements the zero-pole form of the Z-transform filter. The general form is:
zi_zp( expr , ζ , ρ , T [ , τ [ , t0 ] ] )
the pair is the real part of the zero (0) and the second is the imaginary part. Similarly, ρ (rho) is the
vector of N real pairs, one for each pole. The poles are given in the same manner as the zeros. The
transfer function is:
M–1
∏1–z
–1
( ζ kr + jζ ki )
H ( z ) = -----------------------------------------------------
k=0
N–1
-
∏1 – z
–1
( ρ kr + jρ ki )
k=0
r i r i
where ζ and ζ are the real and imaginary parts of the kth zero, while ρ and ρ are the real and
k k k k
imaginary parts of the kth pole. If a root (a pole or zero) is real, the imaginary part shall be specified as
zero. If a root is complex, its conjugate shall also be present. If a root is zero (0), then the term
associated with it is implemented as z, rather than (1 - z/r) (where r is the root).
zi_zd
zi_zd() implements the zero-denominator form of the Z-transform filter.
The form is:
zi_zd( expr , ζ , d , T [ , τ [ , t0] ] )
the pair is the real part of the zero and the second is the imaginary part. Similarly, d is the vector of N
real numbers containing the coefficients of the denominator. The transfer function is:
M–1
∏1–z
–1
( ζ kr + jζ ki )
H ( z ) = -----------------------------------------------------
k=0
N–1
∑d z
–1
k
k=0
r i
where ζ and ζ are the real and imaginary parts of the kth zero, while dk is the coefficient of the
k k
kth power of s in the denominator. If a zero is real, the imaginary part shall be specified as zero (0). If
a zero is complex, its conjugate shall also be present. If a zero is zero (0), then the term associated with
it is implemented as z, rather than (1 - z/ζ).

zi_np
zi_np() implements the numerator-pole form of the Z-transform filter. The general form is:
zi_np( expr , n , ρ , T [ , τ [ , t0] ] )
where n is a vector of M real numbers containing the coefficients of the numerator. Similarly, ρ (rho) is
a vector of N pairs of real numbers. Each pair represents a pole, the first number in the pair is the real
part of the pole and the second is the imaginary part. The transfer function is:
M–1
∑n z
–k
k
H ( z ) = -----------------------------------------------------
N–1
k=0
-
∏1 – z
–1
( ρ kr + jρ ki )
k=0
r i
where nk is the coefficient of the kth power of s in the numerator, while ρ and ρ are the real and
k k
imaginary parts of the kth pole. If a pole is real, the imaginary part shall be specified as zero (0). If a
pole is complex, its conjugate shall also be present. If a pole is zero (0), then the term associated with it
is implemented as z, rather than (1 - z/ρ).
zi_nd
zi_nd() implements the numerator-denominator form of the Z-transform filter. The
general form is:
zi_nd( expr , n , d , T [ , τ [ , t0] ] )
where n is an vector of M real numbers containing the coefficients of the numerator and d is a vector of
N real numbers containing the coefficients of the denominator. The transfer function is:
M–1
∑n z
–k
k
H ( z ) = ------------------------
k=0
N–1
-
∑d z
–k
k
k=0
where nk is the coefficient of the kth power of s in the numerator and dk is the coefficient of the kth
power of s in the denominator.
6.3.13: Limited Exponential

The limexp() function is an operator whose internal state contains information about the argument
on previous iterations. It returns a real value which is the exponential of its single real argument,
however, it internally limits the change of its output from iteration to iteration in order to improve

convergence. On any iteration where the change in the output of the limexp() function is bound, the
simulator is prevented from terminating the iteration. Thus, the simulator can only converge when the
output of limexp() equals the exponential of the input. The general form is:
limexp ( expr )
The apparent behavior of limexp() is not distinguishable from exp(), except using limexp() to model
semiconductor junctions generally results in dramatically improved convergence. There are different
ways of implementing limiting algorithms for the exponential.
Table 6-18 summarizes the arguments of the analog operators defined in this section.
Table 6-18: Analog Operator Arguments
Operator Constant Expression Arguments Dynamic Expression Arguments
ddt abstol expr

idt abstol expr, ic, assert
idtmod abstol expr, ic, modulus,
offset
cross expr_tol, time_tol expr, dir
last_crossing expr, dir
delay maxdelay expr, td
transition expr, td, rise_time,
fall_time
slew expr,
max_pos_slew_rate,
max_neg_slew_rate
zi_zp zeros, poles, T, t0 expr, τ
zi_zd
zi_np
zi_nd
laplace_zp poles, abstol, zero expr

laplace_zd
laplace_np
laplace_nd
timer Time_tol start_time, period

limexp expr
If a dynamic expression is passed as an argument which expects a constant expression, the value of
the dynamic expression at the start of the analysis defaults to the constant value of the argument. Any
further change in value of that expression is ignored during the iterative analysis.

Chapter 7:
Built-In Mathematical Functions
7.1: Standard Mathematical Functions

These are the standard mathematical functions supported by VERILOG-A. The operands must be
integers or real numbers.
Table 7-1: Mathematical Functions
Function Description Domain Returned Value
ln(x) Natural logarithm x>0 Real
log(x) Decimal logarithm x>0 Real
exp(x) Exponential x < 80 Real
limexp (expr) expr is a dynamic Real

expression of type Real.
The limexp function
limits the iteration step
size to improve conver-
gence. limexp behaves
like the exp function.
sqrt(x) Square root x>0 Real
min(x,y) Minimum All x, all y Integer, if x and y

are integers;
otherwise, real
max(x,y) Maximum All x, all y Integer, if x and y

are integers;
otherwise, real
abs(x) Absolute All x Integer, if x is

integer;
otherwise, real
pow(x,y) Power of (xy) All y, if x > 0 y >= Real

0, if x = 0 y inte-
ger, if x < 0
floor(x) Largest integer less All x Integer

than or equal to x
ceil(x) Smallest integer larger All x Integer

than or equal to x

7.2: Trigonometric and Hyperbolic Functions

These are the trigonometric and hyperbolic functions supported by VERILOG-A. The operands must be
integers or real numbers. The simulator converts operands to real numbers if necessary.
The trigonometric and hyperbolic functions require operands specified in radians.
Table 7-2: Trigonometric and Hyperbolic Functions
Function Description Domain
sin(x) Sine All x
cos(x) Cosine All x
tan(x) Tangent x≠ n(π/2), n is odd

asin(x) Arc-sine -1 <= x <= 1
acos(x) Arc-cosine -1 <= x <= 1
atan(x) Arc-tangent All x
atan2(x,y) Arc-tangent of x/y All x, all y
hypot(x,y) Sqrt(x2 + y2) All x, all y
sinh(x) Hyperbolic sine All x
cosh(x) Hyperbolic cosine All x
tanh(x) Hyperbolic tangent All x
asinh(x) Arc-Hyperbolic sine All x
acosh(x) Arc-Hyperbolic cosine x >= 1

atanh(x) Arc-Hyperbolic tangent -1 <= x <= 1

Chapter 8:
Analog Events
8.1: Detecting and Using Events

Use the @ operator to run a statement under the control of particular events.
The analog behavior of a component can be controlled using events. Events have the following
characteristics:
• events have no time duration
• events can be triggered and detected in different parts of the behavioral model
• events do not block the execution of an analog block
• events can be detected using the @ operator
• events do not hold any data
• there can be both digital and analog events
There are two types of analog events, global events (see Section 8.1.4:“Global Events”) and
monitored events (see Section 8.1.5:“Monitored Events”). Null arguments are not allowed in
analog events.
8.1.1: Event Detection

Analog event detection consist of an event expression followed by a procedural statement, as shown
below:
Syntax
event_control_statement ::=
event_control statement_or_null
event_control ::=
@ event_identifier
| @ ( event_expression )
analog_event_expression ::=
global_event
| event_function
| digital_expression
| event_identifier
| posedge digital_expression
| negedge digital_expression
| event_expression or event_expression
The procedural statement following the event expression is executed whenever the event described by
the expression changes. The analog event detection is non-blocking, meaning the execution of the
procedural statement is skipped unless the analog event has occurred. The event expression consists of
one or more signal names, global events, or monitored events separated by the or operator.
The parenthesis around the event expression are required.

8.1.2: Event OR Operator

The “OR-ing” of events indicates the occurrence of any one of the events specified shall trigger the
execution of the procedural statement following the event. The keyword or is used as an event OR
operator.
Example
analog begin
@(initial_step or cross(V(smpl)-2.5,+1)) begin
vout = (V(in) > 2.5);
end
V(out) <+ vout;
end
Here, initial_step is a global event and cross() returns a monitored event. The variable vout is set
to zero (0) or one (1) whenever either event occurs.
8.1.3: Event Triggered Statements

The following two restrictions apply to statements which are evaluated as a result of an event being
triggered.
• The statement can not have expressions which use analog operators. This statement can not
maintain its internal state since it is only executed intermittently when the corresponding event is
triggered.
• The statement can not be a contribution statement because it can generate discontinuity in analog
signals.
8.1.4: Global Events

Global events are generated by a simulator at various stages of simulation. The user model can not
generate these events. These events are detected by using the name of the global event in an event
expression with the @ operator.
Global events are pre-defined in VERILOG-A. These events can not be redefined in a model.
The pre-defined global events are shown below:
Syntax
global_event ::=
initial_step [ ( analysis_list ) ]
| final_step [ ( analysis_list ) ]
analysis_list ::=
analysis_name { , analysis_name }
analysis_name ::=
" analysis_identifier "

Analog Events
initial_step and final_step generate global events on the first and the last point in an analysis
respectively. They are useful when performing actions which should only occur at the beginning or the
end of an analysis. Both global events can take an optional argument, consisting of an analysis list for
the active global event.
Example
@(initial_step(“ac”, “dc”)) // active for dc and ac only
@(initial_step(“tran”)) // active for transient only
Table 8-1 describes the return value of initial_step and final_step for standard analysis types.
Each column shows the return-on-event status. One (1) represents Yes and zero (0) represents No. A
VERILOG-A simulator can use any or all of these typical analysis types.
Table 8-1: Reaturn Values for initial_step and final_step
DC TRAN AC NOISE
Analysis
OP OP p1 pN OP p1 pN OP p1 pN
initial_step() 1 100 100 100
initial_step(“ac”) 0 000 100 000
initial_step(“noise”) 0 000 000 100
initial_step(“tran”) 0 100 000 000
initial_step(“dc”) 1 000 000 000
initial_step(unkown) 0 000 000 000
final_step() 0 001 001 001
final_step(“ac”) 0 000 001 000
final_step(“noise”) 0 000 000 001
final_step(“tran”) 0 001 000 000
final_step(“dc”) 1 000 000 000
final_step(unkown) 1 000 000 000
OP = Operating Point. pX = analysis point X where X = 1 to N.
Example
The following example measures the bit-error rate of a signal and prints the result at the end of the
simulation.
module bitErrorRate(in, ref);

input in, ref;
electrical in, ref;
parameter real period=1, thresh=0.5;
integer bits, errors;
analog begin

bits = 0;
errors = 0;
end
@(timer(0, period)) begin

if ((V(in) > thresh) != (V(ref) > thresh))
errors = errors + 1;
bits = bits + 1;
end
@(final_step)
$strobe("bit error rate = %f%%", 100.0 * errors / bits );
end
endmodule
initial_step and final_step take a list of quoted strings as optional arguments. The strings are
compared to the name of the analysis being run. If any string matches the name of the current
analysis name, the simulator generates an event on the first point and the last point of that particular
analysis, respectively.
If no analysis list is specified, the initial_step global event is active during the solution of the first
point (or initial DC analysis) of every analysis. The final_step global event, without an analysis list, is
only active during the solution of the last point of every analyses.
8.1.5: Monitored Events

Monitored events are detected using event functions with the @ operator. The triggering of a
monitored event is implicit due to change in signals, simulation time, or other runtime conditions.
Syntax
event_function ::=
cross_function
| timer_function
cross function
The cross() function is used for generating a monitored analog event to detect threshold crossings in
analog signals when the expression crosses zero (0) in the specified direction. In addition, cross()
controls the timestep to accurately resolve the crossing. The general form is:
cross ( expr [ , dir [ , time_tol [ , expr_tol ] ] ] ) ;
where expr is required, and dir, time_tol, and expr_tol are optional. All arguments are real
expressions, except dir (which is an integer expression). If the tolerances are not defined, then the
tool (e.g., the simulator) sets them. If either or both tolerances are defined, then the direction shall also
be defined.
The direction indicator can only evaluate to +1, -1, or 0. If it is set to 0 or is not specified, the event and
timestep control occur on both positive and negative crossings of the signal. If dir is +1 (or -1), the

Analog Events
event and timestep control only occur on rising edge (falling edge) transitions of the signal. For any
other transitions of the signal, the cross() function does not generate an event.
expr_tol and time_tol are defined as shown in Figure 8-1. They represent the maximum
allowable error between the estimated crossing point and the true crossing point.
Figure 8-1: Relationship between time tolerance in expression tolerance
If expr_tol is defined, time_tol shall also be defined and both tolerances shall be satisfied at the
crossing.
Example
The following description of a sample-and-hold illustrates how the cross() function can be used.
module sh(in, out, smpl);
output out;
input in, smpl;
electrical in, out, smpl;
real state;
analog begin
@(cross(V(smpl) - 2.5, +1))
state = V(in);
V(out) <+ transition(state, 0, 10n);
end
endmodule
The cross() function maintains its internal state and has the same restrictions as analog operators. In
particular, it shall not be used inside an if(), case(), casex(), or casez() statement unless the
conditional expression is a genvar expression. In addition, cross() is not allowed in the repeat() and
while() iteration statements. It is allowed in the analog_for statements.
timer function
The timer() function is used to generate analog events to detect specific points in time. The general
form is:
timer ( start_time [ , period [ , time_tol ] ] ) ;

where start_time is required; period and time_tol are optional arguments. All arguments are
real expressions.
The timer() function schedules an event which occurs at an absolute time (start_time). The analog
simulator places a time point within timetol of an event. At that time point, the event evaluates to
True.
If time_tol is not specified, the default time point is at, or just beyond, the time of the event. If the
period is specified as greater than zero (0), the timer function schedules subsequent events at
multiples of period.
Example
A pseudo-random bit stream generator is an example how the timer function can be used.
module bitStream (out);
output out;
electrical out;
parameter period = 1.0;
integer x;
analog begin
@(timer(0, period))
x = $random + 0.5;
V(out) <+ transition( x, 0.0, period/100.0 );
end
endmodule

Chapter 9:
Simulator Functions
9.1: Analysis Dependent Function

This section describes the analysis() function, which is used to determine what type of analysis is
being performed, and the small-signal source functions. The small-signal source functions only affect
the behavior of a module during small-signal analyses. The small-signal analyses provided by
SMARTSPICE include the AC and noise analyses, but others are possible. When not active, the small-
signal source functions return zero (0).
9.1.1: Analysis
The analysis() function takes one or more string arguments and returns one (1) if any argument
matches the current analysis type. Otherwise it returns zero (0). The general form is:
analysis( analysis_list )
There is no fixed set of analysis types. Each simulator can support its own set. However, simulators
shall use the types listed in Table 9-1 to represent analyses which are similar to those provided by
SMARTSPICE.
Table 9-1: Analysis Types
Name Analysis Description
“ac” .AC analysis
“dc” .OP or .DC analysis
“noise” .NOISE analysis
“tran” .TRAN analysis
“ic” The inital condition analysis which precedes a transient analysis.
“static” Any equilibrium point calculation, including a DC analysis as well as

those that precede another analysis, such as the DC analysis which
precedes an AC or noise analysis, or the IC analysis which precedes a
transient analysis.
“nodeset” The phase during an equilibrium point calculation where nodesets are
forced.
Any unsupported type names are assumed to not be a match.
Table 9-2 describes the implementation of the analysis function. Each column shows the return value
of the function. A status of one (1) represents True and zero (0) represents False.

Table 9-2: Return Values for analysis functions
Analysis Arguments Simulator Analysis

DC TRAN AC NOISE
OP TRAN OP AC OP AC
First part of “nodeset 1 1 0 1 0 1 0

“static”
Initial DC state “static” 1 1 0 1 0 1 0
Initial condition “ic” 0 1 0 0 0 0 0
DC “dc” 1 0 0 0 0 0 0
Transient “tran” 0 1 1 0 0 0 0
Small-signal “ac” 0 0 0 1 1 0 0
Noise “noise” 0 0 0 0 0 1 1
Using the analysis() function, it is possible to have a module behave differently depending on which
analysis is being run.
Example
To implement nodesets or initial conditions using the analysis function and switch branches, use the
following:
if (analysis("ic"))
V(cap) <+ initial_value;
else
I(cap) <+ ddt(C*V(cap));
9.1.2: AC stimulus
A small-signal analysis computes the steady-state response of a system which has been linearized
about its operating point and is driven by a small sinusoid. The sinusoidal stimulus is provided using
the ac_stim() function. The general form is:
ac_stim( [analysis_name [ , mag [ , phase ] ] ] )
The AC stimulus function returns zero (0) during large-signal analyses (such as DC and transient) as
well as on all small-signal analyses using names which do not match analysis_name. The name of
a small-signal analysis is implementation dependent, although the expected name (of the equivalent of
a SPICE AC analysis) is “ac”, which is the default value of analysis_name. When the name of the
small-signal analysis matches analysis_name, the source becomes active and models a source with
magnitude mag and phase phase. The default magnitude is one (1) and the default phase is zero (0).
phase is given in radians.

Simulator Functions
9.1.3: Noise
Several functions are provided to support noise modeling during small-signal analyses. To model
large-signal noise during transient analyses, use the $random() system task. The noise functions are
often referred to as noise sources. There are three noise functions, one models white noise processes,
another models 1/f or flicker noise processes, and the last interpolates a vector to model a process
where the spectral density of the noise varies as a piecewise linear function of frequency. The noise
functions are only active in smallsignal noise analyses and return zero (0) otherwise.
white_noise
White noise processes are those whose current value is completely uncorrelated with any previous or
future values. This implies their spectral density does not depend on frequency. They are modeled
using:
white_noise( pwr [ , name ] )
which generates white noise with a power of pwr.
Example
The thermal noise of a resistor could be modelled using:
I(a,b) <+ V(a,b)/R +

white_noise(4*‘P_K*$temperature/R, "thermal");
The optional name argument acts as a label for the noise source used when the simulator outputs the
individual contribution of each noise source to the total output noise. The contributions of noise
sources with the same name from the same instance of a module are combined in the noise
contribution summary.
flicker_noise
The flicker_noise() function models flicker noise. The general form is:
flicker_noise( pwr , exp [ , name ] )
which generates pink noise with a power of pwr at 1Hz which varies in proportion to 1/f exp.
noise_table
The noise_table() function interpolates a vector to model a process where the spectraldensity of the
noise varies as a piecewise linear function of frequency. The general form is:

noise_table( vector [ , name ] )
where vector contains pairs of real numbers: the first number in each pair is the frequency in Hertz
and the second is the power. Noise pairs are specified in the order of ascending frequencies.
noise_table() performs piecewise linear interpolation to compute the power spectral density
generated by the function at each frequency.
Noise model for diode

The noise of a junction diode could be modelled as shown in the following example.
I(a,c) <+ is*(exp(V(a,c) / (n * $vt)) - 1)

+ white_noise(2*‘P_Q*I(<a>))
+ flicker_noise(kf*pow(abs(I(<a>)), af), ef);
Correlated noise
Each noise function generates noise which is uncorrelated with the noise generated by other functions.
Perfectly correlated noise is generated by using the output of one noise function for more
than one noise source. Partially correlated noise is generated by combining the output of
shared and unshared noise functions.
Examples
Example 1 - Two noise voltages are perfectly correlated.
n = white_noise(pwr);
V(a,b) <+ c1*n;
V(c,d) <+ c2*n;
Example 2 - Partially correlated noise sources can also be modelled.

n1 = white_noise(1-corr);
n2 = white_noise(1-corr);
n12 = white_noise(corr);
V(a,b) <+ Kv*(n1 + n12);
I(b,c) <+ Ki*(n2 + n12);

Simulator Functions
9.2: Discontinuity
The $discontinuity function informs the simulator about a discontinuity in signal behavior.
discontinuity_function ::=
$discontinuity[ (constant_expression) ]
constant_expression, which must be zero or a positive integer, is the degree of the discontinuity.
For example, $discontinuity, which is equivalent to $discontinuity(0), indicates a
discontinuity in the equation, and $discontinuity(1) indicates a discontinuity in the slope of the
equation.
Discontinuities created by switch branches or built-in functions, such as transition and slew, do not
need to be announced.
Using the $discontinuity function does not guarantee that the simulator will be able to handle a
discontinuity successfully.
The following example shows the $discontinuity function while describing the behavior of a source
that generates a triangular wave. As the TriangularWave (see Figure 9-1) shows, the triangular wave
is continuous, but as the Triangular Wave First Derivative (see Figure 9-2) shows, the first derivative
of the wave is discontinuous.
Figure 9-1: Triangular Wave
Figure 9-2: Triangular Wave First Derivative
Example
The module triangular_source describes this triangular wave source.
module triangular_source(vout);
output vout;
voltage vout;
parameter real wavelength=10.0, amplitude=1.0;
integer slope;
real i_start;
analog begin

@(timer(0, wavelength)) begin

slope = +1;
i_start = $abstime;
$discontinuity(1); // Change from neg to pos slope
end
@(timer(wavelength/2, wavelength)) begin
slope = -1;
i_start = $abstime;
$discontinuity(1); // Change from pos to neg slope
end
V(vout) <+ amplitude * slope * (4*($abstime - i_start) / wavelength-1);
end
endmodule
The two $discontinuity functions in trisource tell the simulator about the discontinuities in
the derivative. In response, the simulator uses analysis techniques that take the discontinuities into
account.
Example
The module relay, as another example, uses the $discontinuity function while modeling a relay.
module relay(p1, p2, pos, neg);

inout p1, p2;
input pos, neg;
electrical p1, p2, pos, neg;
analog begin
@(cross(V(pos, neg)-1, 0, 0.01n, pos.potential.abstol)) $discontinuity(0);
if (V(pos, neg) >= 1)
I(p1, p2) <+ V(p1, p2) / r;
else
I(p1, p2) <+ 0;
end
endmodule
The $discontinuity function in relay tells the simulator that there is a discontinuity in the
current when the voltage crosses the value 1. For example, passing a triangular wave like that shown
in the Relay Voltage (see Figure 9-3) through module relay produces the discontinuous current
shown in the Relay Current (see Figure 9-4).

Simulator Functions
Figure 9-3: Relay Voltage
Figure 9-4: Relay Current
9.3: Bounding the Time Step

Use the $bound_step function to specify the maximum time allowed between adjacent time points
during simulation.
bound_step_function ::=
$bound_step( max_step )
max_step ::=
constant_expression
By specifying appropriate time steps, the simulator is forced to track signals as closely as one model
requires. For example, module sinwave forces the simulator to simulate at least 50 time points during
each cycle.
Example
module sinwave(out_signal);
output out_signal;
voltage out_signal;
parameter real freq=2.0, ampl=2.0;
analog begin
V(out_signal) <+ ampl * sin(2.0*’M_PI*freq*$abstime);
$bound_step(0.02 / freq); // Max time step = 1/50 period
end
endmodule

9.4: Querying the Simulation Environment

Use the simulation environment functions described in the following sections to obtain information
about the current simulation environment.
9.4.1: Obtaining Current Simulation Time

VERILOG-A provide two environment parameter functions that one can use to obtain the current
simulation time: $abstime and $realtime.
$abstime Function
Use the $abstime function to obtain the current simulation time in seconds.
abstime_function ::=
$abstime
$realtime Function
Use the $realtime function to obtain the current simulation time in seconds.
realtime_function ::=
$realtime[(time_scale)]
time_scale is a value used to scale the returned simulation time. The valid values are the integers
1, 10, and 100, followed by one of the scale factors in the following table.
Scale Factor Meaning

s Seconds
ms Milliseconds
us Microseconds
ns Nanoseconds
ps Picoseconds
fs Femtoseconds
If time_scale is not specified, the return value is scaled to the ’time_unit of the module that
invokes the function.
For example, to print out the current simulation time in seconds, code:
$strobe("Simulation time = %e", $realtime(1s));
9.4.2: Obtaining the Current Ambient Temperature

Use the $temperature function to obtain the ambient temperature of a circuit in degrees Kelvin.
temperature_function ::=
$temperature

Simulator Functions
9.4.3: Obtaining the Thermal Voltage

Use the $vt function to obtain the thermal voltage, (kT/q), of a circuit.
vt_function ::=
$vt[(temp)]
temp is the temperature, in degrees Kelvin, at which the thermal voltage is to be calculated. If temp is
not specified, the thermal voltage is calculated at the temperature returned by the $temperature
function.
9.5: Generating Random Numbers

Use the $random function to generate a signed integer, 32-bit, pseudorandom number.
$random [ ( seed ) ] ;
seed is a reg, integer, or time variable used to initialize the function. The seed provides a starting
point for the number sequence, and allows one to restart at the same point. If, as SILVACO recommends,
seed is used, you must assign a value to the variable before calling the $random function.
The $random function generates a new number every time step.
Individual $random statements with different seeds generate different sequences, and individual
$random statements with the same seed generate identical sequences.
The following code fragment uses the absolute value function and the modulus operator to generate
integers between 0 and 99.
Example
module rand_gen(outpin);
electrical outpin;
integer rand_seed, rand_num;
analog begin
rand_seed = 124; // Initialize the seed
end
rand_num = abs($random(rand_seed) % 100);
if (rand_num < 5)
V(outpin) <+ 0.0;
else
V(outpin) <+ 3.0;
end
endmodule
or
module DataStream (out);
output out;
electrical out;
parameter PERIOD = 1.0u;

parameter TR = 1p;

parameter TF = 1p;
parameter seed = 5;
real y;
integer rand_seed, x;
analog
begin
@(initial_step)
rand_seed = seed
@(timer(0, period))
x = abs($random(rand_seed) %100);
if (x >= 49)
y = 1.8;
else
y = 0.0;
V(out) <+ transition(y, 0.0, TR, TF);
end
endmodule

Simulator Functions
9.6: Generating Random Numbers in Specified Distributions

VERILOG-A provides functions that generate random numbers in the following distribution patterns:
• Uniform
• Normal (Gaussian)
• Exponential
• Poisson
• Chi-square
• Student's T
• Erlang
9.6.1: Uniform Distribution

Use the $rdist_uniform function to generate random real numbers (or the $dist_uniform
function to generate integer numbers) that are evenly distributed throughout a specified range.
$rdist_uniform ( seed , start , end ) ;
$dist_uniform ( seed , start , end ) ;
seed is a scalar integer variable used to initialize the sequence of generated numbers. seed must be
a variable because the function updates the value of seed at each iteration. To ensure generation of a
uniformdistribution, change the value of seed only when one initialize the sequence.
start is an integer expression that specifies the smallest number that the $dist_uniform
function is allowed to return. start must be smaller than end.
end is an integer expression that specifies the largest number that the $dist_uniform function is
allowed to return. end must be larger than start.
The following module returns a series of real numbers, each of which is between 20 and 80 inclusively.
Example
module uniform_check(outpin);
electrical outpin;
parameter integer start_range = 20;
integer seed, end_range;
real rand_num;
analog begin
seed = 25; // Initialize the seed
end_range = 80;
end
rand_num = $rdist_uniform(seed, start_range, end_range);
$display("Random number is %g", rand_num );
$display("Current seed is %d", seed);
V(outpin) <+ rand_num;
end
endmodule

9.6.2: Normal (Gaussian) Distribution

Use the $rdist_normal function to generate random real numbers (or the $dist_normal
function to generate integer numbers) that are normally distributed.
$rdist_normal ( seed , mean , standard_deviation ) ;
$dist_normal ( seed , mean , standard_deviation ) ;
normal distribution, change the value of seed only when one initialize the sequence.
mean is an integer expression that specifies the value to be approached by the mean value of the
generated numbers.
standard_deviation is an integer expression that determines the width of spread of the
generated values around mean. Using a larger standard_deviation spreads the generated
values over a wider range.
To generate a gaussian distribution, use a mean of 0 and a standard_deviation of 1. For
example, the following module returns a series of real numbers that together form a gaussian
distribution.
Example
module normal_check(outpin);
electrical outpin;
integer seed;
real rand_num;
analog begin
seed = 25;
end
rand_num = $rdist_normal( seed, 0, 1 );
$display("Random number is %g", rand_num);
end
endmodule
9.6.3: Exponential Distribution

Use the $rdist_exponential function to generate random real numbers (or the
$dist_exponential function to generate integer numbers) that are exponentially distributed.
$rdist_exponential ( seed , mean ) ;
$dist_exponential ( seed , mean ) ;
a variable because the function updates the value of seed at each iteration. To ensure generation of
an exponential distribution, change the value of seed only when one initialize the sequence.
mean is an integer value greater than zero. mean specifies the value to be approached by the mean
value of the generated numbers. For example, the following module returns a series of real numbers
that together form an exponential distribution.

Simulator Functions
Example
module expo_check(outpin);
electrical outpin;
integer seed, mean;
real rand_num;
analog begin
seed = 25;
mean = 6;
end
rand_num = $rdist_exponential(seed, mean);
end
endmodule
9.6.4: Poisson Distribution

Use the $rdist_poisson function to generate random real numbers (or the $dist_poisson
function to generate integer numbers) that form a Poisson distribution.
$rdist_poisson ( seed , mean ) ;
$dist_poisson ( seed , mean ) ;
Poisson distribution, change the value of seed only when one initialize the sequence.
that together form a Poisson distribution.
Example
module pois_check(outpin);
electrical outpin;
integer seed, mean;
real rand_num;
analog begin
seed = 25;
mean = 6;
end
rand_num = $rdist_poisson(seed, mean);
end
endmodule

9.6.5: Chi-Square Distribution

Use the $rdist_chi_square function to generate random real numbers (or the
$dist_chi_square function to generate integer numbers) that form a chi-square distribution.
$rdist_chi_square ( seed , degree_of_freedom ) ;
$dist_chi_square ( seed , degree_of_freedom ) ;
chi-square distribution, change the value of seed only when one initialize the sequence.
degree_of_freedom is an integer value greater than zero. degree_of_freedom determines the
width of spread of the generated values. Using a larger degree_of_freedom spreads the generated
values over a wider range. For example, the following module returns a series of real numbers that
together form a chi-square distribution.
Example
module chi_check(outpin);
electrical outpin;
integer seed, dof;
real rand_num;
analog begin
seed = 25;
dof = 6;
end
rand_num = $rdist_chi_square(seed, dof);
end
endmodule
9.6.6: Student’s T Distribution

Use the $rdist_t function to generate random real numbers (or the $dist_t function to generate
integer numbers) that form a Student’s T distribution.
$rdist_t ( seed , degree_of_freedom ) ;
$dist_t ( seed , degree_of_freedom ) ;
Student’s T distribution, change the value of seed only when one initialize the sequence.
degree_of_freedom is an integer value greater than zero. degree_of_freedom determines the
width of spread of the generated values. Using a larger degree_of_freedom spreads the generated
values over a wider range. For example, the following module returns a series of real numbers that
together form a Student’s T distribution.
Example
module student_T_check(outpin);
electrical outpin;
integer seed, dof;

Simulator Functions
real rand_num;
analog begin
seed = 25;
dof = 12;
end
rand_num = $rdist_t(seed, dof);
end
endmodule
9.6.7: Erlang Distribution

Use the $rdist_erlang function to generate random real numbers (or the $dist_erlang
function to generate integer numbers) that form an Erlang distribution.
$rdist_erlang ( seed , k , mean ) ;
$dist_erlang ( seed , k , mean ) ;
a variable because the function updates the value of seed at each iteration. To ensure generation of
an Erlang distribution, change the value of seed only when initializing the sequence.
k is an integer value greater than zero. Using a larger value for k decreases the variance of the
distribution.
that together form an Erlang distribution.
Example
module erlang_check(outpin);
electrical outpin;
integer seed, k, mean;
real rand_num;
analog begin
seed = 25;
k = 15;
mean = 10;
end
rand_num = $rdist_erlang(seed, k, mean);
$display("Random number is %g", rand_num);
end
endmodule

9.7: Silvaco System Functions

Silvaco provides system functions that are not defined in the OVI 2.0 standard. They have been added
to the VERILOG-A interface, because from experience of transistor modeling at Silvaco, it has shown that
they are very useful in helping the simulation of some models
Note: Because these tasks are not compliant with the OVI standard, they will not be recognized by Verilog-A compilers from
other vendors.
9.7.1: $sit_get_prev
Returns the value of a specified variable at a previous simulation point.
$sit_get_prev (variable, [iteration])
If the iteration argument is equal to zero (0), the value returned is the value from the previous
iteration (during the same simulation point). If the iteration argument is equal to one (1), the value
returned is the value from the previous simulation point.
If the iteration argument is omitted, the default value is zero (0).
Example
// We allow +/- 10V change between iterations
if (Vb2c1 - $sit_get_prev(Vb2c1, 1) > 10.0) begin
Vb2c1 = $sit_get_prev(Vb2c1, 1) > 5.0;
V(b2, c1) <+ Vb2c1;
end
// usage with no iteration argument
Vds_prev = $sit_get_prev(Vds);
9.7.2: $sit_get_ddv
Returns the derivative of an expression, with regard to a specific branch.
$sit_get_ddv (variable, branch_quality) ;
For each branch quantity expresions, the VERILOG-A compiler computes derivatives that are used to fill
up the spice conductance matrix. These derivative values can be accessed through the internal task
$sit_get_ddv.
Example
// $sit_get_ddv will return the value 5.0
vds = 5 * V(d,s);
Qds = $sit_get_ddv(vds, V(d,s));
// $sit_get_ddv will return the value sin(V(d,s))
vds = cos(V(d,s));
Qds = $sit_get_ddv(vds, V(d,s));

Simulator Functions
9.8: Displaying Results

VERILOG-A provides four tasks for displaying information: $strobe, $display, and $write.
$strobe
Use the $strobe task to display information on the screen. $strobe and $display use the same
arguments, and are completely interchangeable.
strobe_task ::=
$strobe [ ( { list_of_arguments } ) ]
argument
| list_of_arguments , argument
The $strobe task prints a new-line character after the final argument. A $strobe task without any
arguments prints only a new-line character.
Each argument is a quoted string or an expression that returns a value.
Each quoted string is a set of ordinary characters, special characters, or conversion specifications, all
enclosed in one set of quotation marks. Each conversion specification in the string must have a
corresponding argument following the string. One must ensure that the type of each argument is
appropriate for the corresponding conversion specification.
An argument can be specified without a corresponding conversion specification. If you do, an integer
argument is displayed using the %d format, and a real argument is displayed using the %g format.
Special Characters
Use the following sequences to include the specified characters and information in a quoted string.
Use this sequence To include

\n The new-line character
\t The tab character
\\ The backslash character, \
\” The quotation mark character, "
%% The percent character, %
%m or %M The hierarchical name of the current module, function, or named

block
Conversion Specifications
Conversion specifications have the form

% [ flag ] [ field_width ] [ . precision ] format_character
where flag, field_width, and precision can be used only with a real argument.
flag is one of the three choices shown in the table:
Flag Definition
- Left justify the output
+ Always print a sign
Blank space, or any character Print a space

other than a sign.
field_width is an integer specifying the minimum width for the field.

precision is an integer specifying the number of digits to the right of the decimal point.
format_character is one of the following characters.
Format_character Type of Argument Output Example Output

c or C Integer ASCII character format
d or D Integer Decimal format 181, 42, -267
e or E Real Real, exponential format -1.0, 5E8, 36.669E-18
f or F Real Real, fixed-point format 101.04, -3.687
g or G Real Real, exponential, or 9.5001, 6.32E-7, -25.1E6

decimal format, whichever
format results in the
shortest printed output
h or H Integer Hexadecimal format 2e, 252, a38, fff, 3E
o or O Integer Octal format 137, 777
s or S String Constant String format
Examples of $strobe Formatting

The module is defined as:
module formatting_example;
integer integer_val;
real real_val;
analog begin
integer_val = 89;
real_val = 125.456789;
$strobe("Format D gives %D" , ival);
$strobe("Format E (real) gives %E" , rval);

Simulator Functions
$strobe("Format F (real) gives %F" , rval);

$strobe("Format G (real)gives %G" , rval);
end
endmodule
When one run format_module, it displays:

Format D gives 89
Format E gives 1.254568e+02
Format F gives 125.456789
Format G gives 125.457
$display
Use the $display task to display information on the screen.
display_task ::=
$display [ ( { list_of_arguments } ) ]
argument
$display and $strobe use the same arguments and are completely interchangeable.
$write
Use the $write task to display information on the screen. This task is identical to the $strobe task,
except that $strobe automatically adds a newline character to the end of its output, whereas
$write does not.
write_task ::=
$write [ ( { list_of_arguments } ) ]
argument
The arguments one can use in list_of_arguments are the same as those used for $strobe.

9.9: Specifying Power Consumption

Use the $pwr system task to specify the power consumption of a module. The $pwr task is supported
only in analog contexts.
Note: The $pwr task is a nonstandard language extension, implemented for VERLIOG-A vendor compatiability.
pwr_task ::=
$pwr( expr )
expr is an expression that specifies the power contribution. If more than one $pwr task is specified in
a behavioral description, the result of the $pwr task is the sum of the individual contributions (See
section 13.2.3:“The power function: $pwr”).
9.10: Working with Files

VERILOG-A provides several functions for working with files. $fopen prepares a file for writing.
$fstrobe and $fdisplay write to a file. $fclose closes an open file.
9.10.1: Opening a File

Use the $fopen function to open a specified file.
fopen_function ::=
multi_channel_descriptor = $fopen ( "file_name" ) ;
multi_channel_descriptor is a 32-bit unsigned integer that is uniquely associated with
file_name. The $fopen function returns a multi_channel_descriptor value of zero if the
file cannot be opened.
One can use a multi_channel_descriptor like a set of 32 flags, where each flag represents a
single output channel. The least significant bit always refers to the standard output. The first time it
is called, $fopen opens channel 1 and returns a descriptor value of 2 (binary 10). The second time it is
called, $fopen opens channel 2 and returns a descriptor value of 4 (binary 100). Subsequent calls
cause $fopen to open channels 3, 4, 5, and so on, and to return values of 8, 16, 32, and so on, up to a
maximum of 32 open channels.
file_name is a string that can include the special commands described in "Special $fopen
Formatting Commands". If file_name contains a path indicating that the file is to be opened in a
different directory, the directory must already exist when the $fopen function runs.
The $fopen function reuses channels associated with any files that are closed.
For example, to open a file named my_file, use the code:
integer my_Chan_Descrip;
my_Chan_Descrip = $fopen( "my_file" );

Simulator Functions
9.10.2: Special $fopen Formatting Commands

The following special output formatting commands are available for use with the $fopen function.
Command Output Example

%C Design filename input.scs
%D Date (yy-mm-dd) 03-02-28
%H Host name my_computer
%S Simulator type smartspice
%P Process ID # 3781
%T Time (24hh:mm:ss) 15:41:25
%I Instance name opamp
%A Analysis name DC, TRAN, AC

The special output formatting commands can be followed by one or more modifiers, which extract
information from UNIX filenames. (To avoid opening a file that is already open, the %C command must
be followed by a modifier.) The modifiers are:
Modifier Extracted information

:r Root (base name) of the path for the file
:e Extension of the path for the file
:h Head of the path for any portion of the file before

the last /
:t Tail of the path for any portion of the file after
the last /
:: The (:) character itself
Any other character after a colon (:) signals the end of modifications. That character is copied with the
previous colon.
The modifiers are typically used with the %C command, although they can be used with any of the
commands. However, when the output of a formatting command does not contain a / and ".", the
modifiers :t and :r return the whole name, and the :e and :h modifiers return ".". As a result, be
aware that using modifiers with formatting commands other than %C might not produce the results
one expect. For example, using the command:
$fopen("%I:h.freq_dat");
opens a file named ..freq_dat.
Use a concatenated sequence of modifiers. For example, if the design file name is res.ckt, and the
statement:

$fopen("%C:r.freq_dat");
is used, then:
• %C is the design filename (res.ckt).
• :r is the root of the design filename (res).
• .freq_dat is the new filename extension.
As a result, the name of the opened file is res.freq_dat. The following table shows the various
filenames generated from a design filename (%C) of /users/maxwell/circuits/opamp.ckt by
using different formatting commands and modifiers.
Command and Modifiers Resulting Opened File

$fopen("%C"); None, because the design file cannot be overwritten.
$fopen("%C:r"); /users/maxwell/circuits/opamp
$fopen("%C:e"); ckt
$fopen("%C:h"); /users/maxwell/circuits
$fopen("%C:t"); opamp.ckt
$fopen("%C::"); /users/maxwell/circuits/opamp.ckt:
$fopen("%C:h:h"); /users/maxwell
$fopen("%C:t:r"); opamp
$fopen("%C:r:t"); opamp
$fopen("/tmp/%C:t:r.raw"); /tmp/opamp.raw
$fopen("%C:e%C:r:t"); ckt.opamp
$fopen("%C:r.%I.dat" ); /users/maxwell/circuits/opamp.opamp3.dat
9.10.3: Writing to a File

VERILOG-A provides three input/output functions for writing to a file:
$fstrobe, $fdisplay, and
$fwrite. The $fstrobe and $fdisplay functions use the same arguments and are completely
interchangeable. The $fwrite function is similar, but does not insert automatic carriage returns in
the output.
$fstrobe
Use the $fstrobe function to write information to a file.

Simulator Functions
fstrobe_function ::=
$fstrobe (multi_channel_descriptor {,list_of_arguments })
argument
The multi_channel_descriptor that is specified must have a value that is associated with one
or more currently open files. The arguments that that can be used in list_of_arguments are the
same as those used for $strobe. See "$strobe" for guidance.
For example, the following code fragment illustrates how may write simultaneously to two open files.
integer mcd1;
integer mcd2;
integer mcd;
mcd1 = $fopen("file1.dat");
mcd2 = $fopen("file2.dat");
end
...
mcd = mcd1 | mcd2; // Bitwise OR combines two channels
$fstrobe(mcd, "This is written to both files");
$fdisplay
Use the $fdisplay function to write information to a file.
fdisplay_function ::=
$fdisplay (multi_channel_descriptor {,list_of_arguments })
argument
The multi_channel_descriptor that is specified must have a value that is associated with a
currently open file. The arguments that used in list_of_arguments are the same as those used
for $strobe. See "$strobe" for guidance.
$fwrite
Use the $fwrite function to write information to a file.
fwrite_function ::=
$fwrite (multi_channel_descriptor {,list_of_arguments })
argument

The multi_channel_descriptor that is specified must have a value that is associated with a
currently open file. The arguments that one can use in list_of_arguments are the same as those
used for $strobe. See "$strobe" for guidance.
The $fwrite function does not insert automatic carriage returns in the output.
9.10.4: Closing a File

Use the $fclose function to close a specified file.
file_close_function ::=
$fclose ( multi_channel_descriptor ) ;
The multi_channel_descriptor that is specified must have a value that is associated with the
currently open file that one want to close.
9.11: User-Defined Functions

VERILOG-A supports user-defined functions. By defining and using your own functions, you can simplify
code, and enhance readability and reuse.
9.11.1: Declaring an Analog User-Defined Function

To define an analog function, use this syntax:
Syntax
analog_function_declaration ::=
analog function [ type ] function_identifier ;
function_item_declaration {function_item_declaration}
statement
endfunction
type ::=
integer
| real
function_item_declaration ::=
input_declaration
| block_item_declaration
integer_declaration
| real_declaration
type is the type of the value returned by the function. The default value is real. statement cannot
include analog operators and cannot define module behavior.
Specifically, statement cannot include:
• ddt operator

Simulator Functions
• idt operator
• idtmod operator
• Access functions
• Contribution statements
• Event control statements
• Simulator library functions, except that you can include the functions in the next list.
statement can include references to:
• $vt
• $vt(temp)
• $temperature
• $realtime
• $abstime
• analysis
• $strobe
• $display
• $write
• $fopen
• $fstrobe
• $fdisplay
• $fwrite
• $fclose
• All mathematical functions
All local variables can be declared and used in the function.

Each function that is defined must have at least one declared input. Each function must also assign a
value to the implicitly defined internal variable with the same name as the function.
Example
analog function real chopper;
input sw, in; // The function has two declared inputs.
real sw, in;
//The next line assigns a value to the implicit variable, chopper.
chopper = ((sw > 0) ? in : -in);
endfunction
The chopper function takes two variables, sw and in, and returns a real result. Use the function in
any subsequent function definition or in the module definition.
9.11.2: Returning a Value from a User-Defined Function

The user-defined function definition implicitly declares a variable, internal to the analog function,
with the same name as the analog function. This variable has the same type as the type specified in
the analog function declaration. The analog function definition initializes the return value from the
analog function by assigning the analog function result to the internal variable with the same name as

the analog function. This variable can be read and assigned within the flow; its last assigned value is
passed back on the return call.
Example
The following line illustrates from the previous example, this concept:
chopper = ((sw > 0) ? in: -in);
If the internal variable is not assigned, the function shall return zero (0).
9.11.3: Calling a User-Defined Analog Function

To call a user-defined analog function, use the following syntax.
Syntax
analog_function_call ::=
function_identifier ( expression { , expression } )
function_identifier must be the name of a defined function. Each expression is evaluated by

the simulator before the function runs. However, do not rely on having expressions evaluated in a
certain order because the simulator is allowed to evaluate them in any order.
• shall not call itself directly or indirectly, i.e., recursive functions are not permitted;
• shall only be called within an analog block; and
• can be called outside of their immediate scope.
The module phase_detector illustrates how the chopper function can be called.
module phase_detector(lo, rf, if0);
inout lo, rf, if0;
electrical lo, rf, if0;
parameter real gain = 1;
function real chopper;
input sw, in;
real sw, in;
chopper = ((sw > 0) ? in : -in);
endfunction
analog
V(if0) <+ gain * chopper(V(lo),V(rf)); //Call from within the analog block.
endmodule

Chapter 10:
Instantiating Modules and Primitives
10.1: Instantiating Verilog-A Modules

Use the following syntax to instantiate modules in other modules.
module_instantiation ::=
module_identifier [ parameter_value_assignment ] instance_list
instance_list ::=
module_instance { , module_instance} ;
module_instance ::=
name_of_instance ( [ list_of_module_connections ] )
name_of_instance ::=
module_instance_identifier
list_of_module_connections ::=
ordered_port_connection { , ordered_port_connection }
ordered_port_connection ::=
[ net_expression ]
net_expression ::=
net_identifier
| net_identifier [ constant_expression ]
| net_identifier [ constant_range ]
constant_range ::=
constant_expression : constant_expression
The instance_list expression is discussed in the following sections. The

parameter_value_assignment expression is discussed in Section 10.3: ‘Overriding Parameter
Values in Instances” .
10.1.1: Creating and Naming Instances

This section illustrates how to instantiate modules. Consider the following module, which describes a
gain block that doubles the input voltage.
module vdoubler(in, out);
input in;
output out;
electrical in, out;
analog
V(out) <+ 2.0 * V(in);
endmodule
Two of these gain blocks are connected, with the output of the first becoming the input of the second.

Figure 10-1: vquad
This higher-level component is described by module vquad, which creates two instances, named blk1
and blk2, of module vdoubler. Module vquad also defines external ports corresponding to those
shown in the schematic.
module vquad(din, dout);

input din;
output dout;
electrical din, dout;
wire blk1_blk2;
vdoubler blk1(din, blk1_blk2); //By order
vdoubler blk2(blk1_blk2, dout); //By order
endmodule
10.1.2: Mapping Instance Ports to Module Ports

When instantiating a module, it must be specified how the actual ports listed in the instance
correspond to the formal ports listed in the defining module. Module vquad, in the previous example,
demonstrates one of the two methods provided in VERILOG-A. Module vquad uses an ordered list,
where instance blk1’s first actual port name din maps to vdoubler’s first formal port name in.
Instance blk1’s second actual port name blk1_blk2 maps to vdoubler’s second formal port name,
and so on.
One can also map actual ports to the formal ports in the defining module explicitly using name pairs. If
this approach is chosen, the order of the ports does not matter. Two kinds of mapping within a single
instance cannot be mixed.
Mapping Ports with Ordered Lists

To use ordered lists to map actual ports listed in the instance to the formal ports listed in the defining
module, ensure that the instance ports are in the same order as the defining module ports. For
example, consider the following module child and the module instantiator that instantiates it.
module child(ina, inb, out);
input [0:3] ina;
input inb;
output out;

electrical [0:3] ina;

electrical inb;
electrical out;
endmodule
module instantiator(conin, conout);

input [0:6] conin;
output conout;
electrical [0:6] conin;
electrical conout;
child child1(conin[1:4], conin[6], conout);
endmodule
One can tell from the order of port names in these modules that port ina[0] in module child maps
to port conin[1] in instance child1. Similarly, port inb in child maps to port conin[6] in
instance child1. Port out in child maps to port conout in instance child1.
10.2: Connecting the Ports of Module Instances

Developing modules that describe components is an important step, and is the overall goal of
simulating a system. But an equally important step is combining those components together so that
they represent the system as a whole. This section discusses how to connect module instances, how to
use their ports, and to describe the structure and behavior of the system being modeled.
Consider again the modules vdoubler and vquad, which describe this example.
Figure 10-2: vquad

input in;
output out;
electrical in, out;
analog
V(out) <+ 2.0 * V(in);
endmodule


input din;
output dout;
electrical din, dout;
wire blk1_blk2;
vdoubler blk1(din, blk1_blk2); //By order
vdoubler blk2(blk1_blk2, dout); //By order
endmodule
This time, note how the module instantiation statements in vquad use port names to establish a
connection between output port blk1_blk2 of instance blk1 and input port blk1_blk2 of instance
blk2.
One can establish the same connections by using name pairs, as illustrated in the following two
instantiation statements:
vdoubler blk1(.out(blk1_blk2), .in(din)); //By name
vdoubler blk2(.in(blk1_blk2), .out(dout)); //By name
Module instantiation statements like:

vdoubler blk1(din, dout);
vdoubler blk2(din, dout);
establish different connections. These statements describe a system where the gain blocks are
connected in parallel, see Figure 10-3.
Figure 10-3: Parallel vdoubler
10.2.1: Port Connection Rules

It is possible to connect the ports described in the vdoubler instances because the ports are defined
with compatible disciplines, and are the same size.
• It is necessary to ensure that all ports connected to a net are compatible with each other. Ports of
any analog discipline are compatible with a reference node (ground). You can connect the ports
described in the vdoubler instances because the ports are defined with compatible disciplines
and are the same size.

• It is necesary to ensure that the sizes of connected ports and nets match. In other words, you can
connect a scalar port to a scalar net, and a vector port to a vector net or concatenated net
expression of the same width.
10.2.2: Multilevel Hierarchal Designs

One can use VERILOG-A modules inside a multilevel design hierarchy by instantiating Child
Verilog.va files inside a Parent Verilog.va module using the following procedure.
inverter.va: (Child Verilog.va)

//inverter
‘include "discipline.h"
‘include "constants.h"
module inverter(in,out);
input in;
output out;
electrical in,out;
//other parametrs that define the performance of the inverter gate

parameter real vout_high = 5,
vout_low = 0,
vth = 1.4,
tdelay = 2p from [0:inf),
trise = 1p from [0:inf),
tfall = 1p from [0:inf);
analog begin
if (V(in) > vth)
......
end
endmodule
jk_ff.va: (Child Verilog.va)

//Clocked JK FlipFlop
module jk_ff(j, k, clk, q, qbar);

inout clk, j, k, q, qbar;
electrical q, qbar, clk, j, k;
// User defined parameters

parameter real tdelay = 1n from [0:inf),
ttransit = 1n from [0:inf),
vout_high = 5,
vout_low = 0 from (-inf:vout_high),
vth = 1.4;

integer x; //Local variables
analog begin
@(initial_step) x = 0;
@(cross(V(clk) - vth, +1)) begin
if (V(j) > vth)
case (V(k) > vth)
1 : x = !x;
0 : x = 1;
endcase
.....
end
endmodule
serin_parout.va: (Parent Verilog.va)

‘include "inverter.va" “include definitions of Verilog-A modules inverter

‘include "jk_ff.va" and jk_ff”
module serin_parout(d3, d2, d1, d0, din, clk);

inout d3, d2, d1, d0, din, clk;
electrical d3, d2, d1, d0, din, clk;
//Parameters
parameter real trise = 10p from [0:inf);
parameter real tfall = 10p from [0:inf);
//Internal electrical nodes

electrical dinbar, q0, qbar0, q1, qbar1, q2, qbar2, q3, qbar3;
//Structural declarations
inverter inverter0(din, dinbar);
jk_ff jk_ff0(din, dinbar, clk, q0, qbar0); Instantiation of Verilog-A
Child modules within
Parent module
jk_ff jk_ff1(q0, qbar0, clk, q1, abar1);
analog begin
V(d0) <+ transition(V(q0),trise,tfall);
end
endmodule

10.3: Overriding Parameter Values in Instances

As noted earlier, the syntax for the module instantiation statement is:
The following sections discuss the parameter_value_assignment expression, which is further

defined as
parameter_value_assignment ::=
| #( named_param_override_list )
named_param_override_list ::=
named_param_override { , named_param_override }
named_param_override ::=
. parameter_identifier ( expression )
By default, instances of modules inherit any parameters specified in their defining module. To change
any of the default parameter values, do so on the module instantiation statement itself, or from other
modules and instances by using the defparam statement. The defparam statement is particularly
useful if to change parameters throughout modules from a single location.
10.3.1: Overriding Parameter Values from the Instantiation Statement

Using the module instantiation statement, it is possible to assign values to parameters in two ways.
You can assign values in the order the parameters are declared, or by explicitly referring to parameter
names. The new values must be constant expressions.
Overriding Parameter Values with Ordered Lists

To override parameters using an ordered list of replacement values you must ensure that the list
specifies replacement values in the same order that the parameters are defined in the defining
module. It is not required to specify replacement values for every defined parameter, but if any value is
omited you must omit every value from then on. In other words, you cannot skip over selected
parameters. If a parameter does not need a new value, however, a replacement value equal to the
default value can be specified.
Consider the two instances, weakp and plainp, instantiated within module m.
module m;
voltage clk;
electrical out_a, in_a;
mosp #(2e-6, 1e-6) weakp(out_a, in_a, clk);
mosp plainp(out_b, in_b, clk);
endmodule
The weakp module instantiation statement overrides the first two parameters given in the defining
module, mosp, giving the first parameter the new value 2e-6 and the second parameter the value 1e-6.
The plainp module instantiation statement has no parameter override expression, so the
parameters assume their default values.

Overriding Parameter Values By Name

You can also override parameter values in an instantiated module by pairing the parameter names to
be changed with the values they are to receive. A period and the parameter name come first in each
pair, followed by the new value in parentheses. The parameter name must be the name of a parameter
in the defining module of the module being instantiated. When parameter values are overridden by
name, it is not required to specify values for every parameter.
Consider this modified definition of module vdoubler. This version has three parameters, parm1,
parm2, and parm3.
Examples
input in;
output out;
electrical in, out;
parameter parm1=0.2, parm2=0.1, parm3=5.0;
analog
V(out) <+ (parm1+parm2+parm3) * V(in);
endmodule

input din;
output dout;
vdoubler #(.parm3(4.0)) blk1(din, blk1_blk2); // By name
vdoubler #(.parm1(0.3), .parm2(0.2)) blk2(blk1_blk2, dout); // By name
vdoubler #(0.3, 0.2) blk2(blk1_blk2, dout); // By order
endmodule
The module instantiation statement for instance blk1 overrides parameter parm3 by name to specify
that the value for parm3 should be changed to 4.0. The other two parameters retain the default values
0.2 and 0.1. The module instantiation statement for blk2 uses an ordered list by name to override the
first two parameters, parm1, and parm2. Parameter parm3 retains the default value 5.0.

10.4: Instantiating Analog Primitives

These sections describe how to instantiate some spice primitives in VERILOG-A code. For example, the
following VERILOG-A module instantiates two VERILOG-A primitives: a resistor and an isource.
module R_C_Filter(in out)
electrical in, out;
electrical Tmp;
analog begin
resistor #(.r (100k) R1(in, Tmp);
capacitor #(.c (20p)) C1(Tmp, out);
end
endmodule
The following table shows the device available with their name, port names and parameter names.
10.4.1: B device
Example
with L and W parameters.
Spice Syntax
B8 net18 net011 net033 Depl_TOM2 L=800e-9 W=20e-6
Verilog-A Syntax
Depl_TOM2 #(.L(800e-9), .W(20e-6)) B8(net18,net011,net033);
Note: the Verilog-A module name for a B device must have a corresponding spice model card.
In the SMARTSPICE netlist, the model card for the previous example could be:
.MODEL Depl_TOM2 NMF ( LEVEL = 5 VERSION = 2
+ BETA = 1.814862E-4 VTO = -0.3504765 ALPHA = 2.5848448
+ GAMMA = 0.0225387 DELTA = 0 LAMBDA = 0 )
10.4.2: C device
Example
with default parameter.
Spice Syntax
cf1 f2 0 500p
Verilog-A Syntax
capacitor #(500p) cf1(f2,gnd);

Example
with c,w,l,dtemp device parameters
Spice Syntax
c2 out gnd 1u l=10u w=1u dtemp=73
Verilog-A Syntax
capacitor #(.c(1u), .l(10u), .w(1u), .dtemp(73)) c2(out, gnd);
Example
with polynomial Capacitance
Spice Syntax
c3 in out POLY 2.0 0.5 0.01
Verilog-A Syntax
capacitor #(.type("POLY"), [2.0,0.5,0.01]) c3(in, out);
10.4.3: D device
Example
Spice Syntax
D1 n2 n3 DIODE IC=0.3 DTEMP=0.5
Verilog-A Syntax
diode #(.ic(0.3), .dtemp(0.5)) d1(n2, n3);
Note: the Verilog-A module name for a D device must have a corresponding spice model card.
10.4.4: E,F,G,H devices
Note: 1: Controlling nodes are specified in the port association list. ( See first example ). 2: Source types are specified by the
parameter name type and with a string argument. Several types can be specified in the same statement. Example:
..., .type(“VCR”), .type(“POLY”), ... 3: coefficient vectors specified by position are processed
following the source type. ( see next example ).
Example
VCVC with polynomial source.
Spice Syntax

f12 n4 n7 POLY(2) vcc vee 0 0 0 0 1
Verilog-A Syntax
vcvc #(.type(“POLY(2)”),[0,0,0,0,1]) F12(n4,n7,vcc,vee);
Example
Linear VCVS source.
Spice Syntax
ef f1 gnd s1 gnd 1+pp1+pp2-pp3
Verilog-A Syntax
vcvs #(.gain(1+pp1+pp2-pp3)) ef(f1,gnd,s1,gnd);
Example
Delay Source.
Spice Syntax
edelay out gnd VCVS DELAY in gnd TD=0.01
Verilog-A Syntax
vcvs #(.type("VCVS"),.type("DELAY"),.TD(0.01)) edelay1(out,gnd,in,gnd);
Example
Transformer source
Spice Syntax
ew OUT 0 TRANSFORMER IN 0 10
Verilog-A Syntax
vcvs #(.type("TRANSFORMER"), 10) Ew(out, gnd, in, gnd);
Note: “TRANS” is also accepted.
Example
Delay source with TD,TC1,TC2,NPDELAY parameters.
Spice Syntax
Etd out 0 DELAY in 0 td=1n tc1=1.1e-10 tc2=1.2e-10 npdelay=25

Verilog-A Syntax
vcvs #(.type("DELAY"),.td(1n),.tc1(1.1e-10), .tc2(1.2e-10), .npdelay(25))
edelay2(out,gnd,in,gnd);
Example
CCCS source with default parameters.
Spice Syntax
VS1 s1 0 pwl( 0 1 3n 5v 23n 5 26n 1v ) ac 1
VDS n1 0 1
FF f2 f1 VS1 pp1
F11 n3 0 vds 4
Verilog-A Syntax
vsource #(.pwl([0,1,3n,5,23n,5,26n,1]), .ac(1)) vs1(s1,gnd);
vsource #(1) vds (n1,gnd);
cccs #(.vcontrolname("vs1"), .gain(pp1)) ff(f2,f1);
cccs #("vds",4) f11(n3,n0);
Example
CCVS source with and without default parameters.
Spice Syntax
HH h2 h1 HH pp1
Verilog-A Syntax
ccvs #(.vcontrolname("hh"), .trres(pp1)) hh(h2,h1);
ccvs #("hh), pp1) hh(h2,h1);
Example
VCCS linear source with default parameter.
Spice Syntax
G1 0 ggout in in_1 10
Verilog-A Syntax
vccs #(10) g1(gnd, ggout, in, in_1);
Example
VCCS Linear source.
Spice Syntax
gh1 h2 0 h1 0 1

Verilog-A Syntax
vccs #(.gm(1)) gh1(h2,gnd,h1,gnd);
Example
VCCS source with Polynomial coefficents.
Spice Syntax
Gp 11 12 POLY(4) 5 0 6 0 7 0 8 0 0 1 1 1 1 0 0 0 0 0 0 -1
Verilog-A Syntax
vccs #(.type(“POLY(4)”),[0,1,1,1,1,0,0,0,0,0,0,-1])
Gp(n11,n12,n5,gnd,n6,gnd,n7,gnd,n8,gnd);
Example
VCCS source with VCR and NAND parameters.
Spice Syntax
gAND d d1 VCR AND(3) g1 0 g2 0 g3 0
+ delta=0.1 scale=2 m=2 tc1=1.1e-10 tc2=1.2e-10
+ 0,1G 1,1G 2,1 5,1
Verilog-A Syntax
vccs #(.type("AND(3)"), type(“VCR”),[0,1G,1,1G,2,1,5,1],.m(2),.tc1(1.1e-10),
.tc2(1.2e-10)) G1(d, d1, g1, gnd, g2, gnd, g3, gnd);
10.4.5: I, V devices
Example
currrent source with default parameter.
Spice Syntax
Iee e 0 1m
Verilog-A Syntax
isource #(1m) Iee(e, gnd);
Example
PWL current source.
Spice Syntax
i1 in1 0 1 pwl(0 0 1n 10 2n 0 4n 10 6n 0 r=2n)

Verilog-A Syntax
isource #(.dc(1), .pwl([0,1,1n,1.4,2n,2,3n,1,4n,4])) vds(in1,gnd);
Example
SFFM voltage source.
Spice Syntax
v1 out1 0 sffm( 0 1M 20K 5 1K )
Verilog-A Syntax
vsource #(.sffm([0,1M,20K, 5, 1K])) v1(out1,gnd);
Spice Syntax
AM voltage source.
v1 out1 0 am( 10 1 100 1K 1m )
Verilog-A Syntax
vsource #(.am([10, 1, 100, 1k, 1m])) v1(out1,gnd);
Spice Syntax
PWL and AC voltage source.
vin1 in 0 AC 3 0 PWL 0 0 10n 5 25m 5 25.01M 0
Verilog-A Syntax
vsource #(.ac({3,0}), .pwl({0, 0, 10n, 5, 25m, 5, 25.01M,0 })) vin1(in,
gnd);
Example
Voltage SIN source.
Spice Syntax
vin1 source1 0 SIN(0 sqrt(2)*230 50 0 0 90)
Verilog-A Syntax
vsource #(.sin([0,sqrt(2)*230, 50, 0, 0, 90])) vin1(source1, gnd);
Example
PWL source with input file.
Spice Syntax

V1 inp 0 0 PWLFILEDESC(2 0 1u 0 3.3 1n 1n) PWLFILE test3.dat
Verilog-A Syntax
vsource #(.dc(0), .pwlfiledesc([2, 0, 1u, 0, 3.3, 1n, 1n]),
.pwlfile("test3.dat")) V1(inp, gnd);
Example
PWL source with input file and delay parameter.
Spice Syntax
V1 inp 0 0 PWLFILEDESC(2 0 1u 0 3.3 1n 1n) PWLFILE DigitalEndBy1.pwl TD=3n
r=2n
Verilog-A Syntax
vsource #(0,.pwlfiledesc([2, 0, 1u, 0, 3.3, 1n, 1n]),
.pwlfile("DigitalEndBy1.pwl"), .td(3n), .r(2n)) vin1(out, gnd);
10.4.6: J device
Spice Syntax:
j1 1 2 3 0 Depl l=0.8e-6 w=20e-6
Verilog-A Syntax
Depl #(.l(0.8e-6), .w(20e-6)) j1(n1, n2, n3, gnd);
Note: the Verilog-A module name for a J device must have a corresponding spice model card.
10.4.7: K, L devices
Example
inductor with polynomial coefficients.
Spice Syntax
L99 in out POLY 4.0 0.35 0.01 R = 10
Verilog-A Syntax
inductor #(.type("POLY"), [4.0,0.35,0.01], .r(10)) L99(in,out);
Example
inductors and mutual inductors.

Spice Syntax
L_a n_0 p 6.0n
L_b p pp 8.0n
L_c pp 0 8.0n
KK_A_B l_a l_b k=0.7
Verilog-A Syntax
inductor #(.l(6.0n)) L_a(n_0,p);
inductor #(8.0n) L_b(p,pp);
inductor #(.l(8.0n)) L_c(pp,n0);
mutual #(.indnumber(2), .indnamen("l_a"), .indnamen("l_b"),
.coefficient(0.7)) KK_A_B();
10.4.8: M device
Spice Syntax
mm 2 1 0 0 modd w=5u l=5u m=10
Verilog-A Syntax
modd #(.w(5u),.l(5u),.m(10)) mm(n2, n1, gnd, gnd);
10.4.9: O device
Spice Syntax
O1 2 0 3 0 lline1 m=1
O2 2 0 3 0 lline2 length=.6095
Verilog-A Syntax
lline1 #(.m(1)) o1(n2,n0,n3,n0);
lline2 #(.length(0.6095)) o2(n2,n0,n3,n0);
Note: the Verilog-A module name for a O device must have a corresponding spice model card.
10.4.10: Q device
Spice Syntax
Q1 3 2 6 QNL IC=0.6,5.0
Q2 4 5 6 QNL OFF TEMP=50
Verilog-A Syntax
qnl #(.ic([0.6,5.0])) q1(n3,n2,n6);
qnl #(.off(),.temp(50)) q2(n4,n5,n6);

Note: the Verilog-A module name for a Q device must have a corresponding spice model card.
10.4.11: R device
Spice Syntax
r1 in1 in2 50
Verilog-A Syntax
resistor #(.r(50)) r1 (in1,in2);
10.4.12: S device
Spice Syntax
S1 np nn ncp ncn swmod M=2
Verilog-A Syntax
swmod #(.m(2)) S1(n1, n2, n3, n4);
Note: the Verilog-A module name for a S device must have a corresponding spice model card.
10.4.13: T device
Spice Syntax
T1 In1 0 Out1 0 Z0=50 TD=10ns l=0.1
Verilog-A Syntax
tline #(.z0(50),.td(10n),.l(0.1)) T1(In1,gnd,Out1);
Note: the Verilog-A module name for a T device must have a corresponding spice model card.
10.4.14: U device
Spice Syntax
u6 2 0 3 0 lline6 l=0.6095
Verilog-A Syntax
lline6 #(.l(0.6095)) U6(n2,gnd,n3,gnd);

Note: the Verilog-A module name for a U device must have a corresponding spice model card.
10.4.15: W device
Example
Spice Syntax
S_w1 25 23 21 22 24 26 0 FQMODEL=w1 TYPE=Y
Verilog-A Syntax
w1 #(.type("Y")) S_w1(n25, n23, n21, n22, n24, n26, gnd);
Note: the Verilog-A module name for a W device must have a corresponding spice model card.
10.4.16: SPICE Model Card Primitives

The new two listing show an example of how a model card can be instantiated from VERILOG-A.
Model card definition in the spice netlist file:
.model schot14v8x8 D( is=6.58e-14 n=1.008 nr=1.01
+ ISR=1e-12
+ ikf=6e-5 m=0.5 vj=0.65
+ cjo=30ff xti=3.0 eg=0.82 )
Model card instantiation in the VERILOG-A source file:

module va_schot14v8x8(p, n);
inout p,n;
electrical p,n;
schot14v8x8 diode1(p,n);
schot14v8x8 #(.area(10u)) diode2(.a(p),.c(n));
endmodule
10.4.17: SPICE Subcircuit Primitives

The new two listing show an example of how a subcircuit can be instantiated from VERILOG-A.
Subcircuit definition in the spice netlist file:
.subckt inv in out l=10u w=10u
mp out in vdd vdd pmos l=’l’ w=’w’
mn out in gnd gnd nmos l=’l’ w=’w’
.ends inv
Subcircuit instantiation in the Verilog-A source file:

module modva_inv(in, out);

inout in;
electrical out;
parameter real l=8u, w=8u;
// instantiates subcircuit ‘inv’ defined in the previous spice netlist.
inv #(l,w) s1(in,out);
endmodule // modva_inv
10.4.18: Instantiating Analog Primitives that Use Array Valued Parameters

Some analog primitives take array valued parameters. For example, one might instantiate the svcvs
primitive like this:
module fm_demodulator(vin, vout, vgnd);
input vin, vgnd;
output vout;
electrical vin, vout, vgnd;
parameter real gain = 1;
svcvs #(.gain(gain),.poles([-1M, 0, -1M, 0]))

af_filter(vout, vgnd, vin, vgnd); //port order
analog begin
...
end
endmodule
This fm_demodulator module sets the array parameter poles to a comma-separated list enclosed
by a set of square brackets.
10.4.19: Instantiating Modules that Use Unsupported Parameter Types

Some primitive modules also take parameter types that are not supported directly by the VERILOG-A
language. The following cases illustrate how to instantiate such modules. To set a string parameter in
a primitive instance, set the parameter to a string constant.
Examples
The next fragment shows how one can set the pwl descriptor file name parameter to a vsource:
vsource #(.type(“pwl”)), .pwlfiledesc(“mydata.dat”) V1(src, gnd);
To set an enumerated parameter in a primitive instance, enclose the enumerated value in quotation
marks.
The next fragment sets the parameter type to the value pulse:
vsource #(.type (“pulse”), .val1(5), .period(50u)) Vclk(clk, gnd);


Chapter 11:
Grammar Summary
source_text ::=
{description}
description ::=
module_declaration | discipline_declaration | nature_declaration
module_declaration ::=
module module_identifier [ list_of_ports ] ;
[ module_items ]
endmodule
list_of_ports ::=
( port { , port } )
port ::=
[ port_expression ]
| . port_identifier ( [ port_expression ] )
port_expression ::=
port_identifier
| port_identifier [ constant_expression ]
| port_identifier [ msb_constant_expression : lsb_constant_expression ]
module_items ::=
{ module_item }
| analog_block
module_item ::=
module_item_declaration
| parameter_override
| module_instantiation
| analog_block
module_item_declaration ::=
| input_declaration
| output_declaration
| inout_declaration
| real_declaration
| node_declaration
| branch_declaration
| genvar_declaration
| analog_function_declaration
parameter_override ::=
defparam list_of_param_assignments ;
nature_declaration ::=
nature nature_name
[ nature_descriptions ]
endnature

nature_name ::=
nature_identifier
| nature_identifier : parent_identifier
parent_identifier ::=
nature_identifier
| discipline_identifier.flow
| discipline_identifier.potential
nature_descriptions ::=
nature_description
| nature_description nature_descriptions
nature_description ::=
attribute = constant_expression ;
attribute ::=
abstol | access | ddt_nature | idt_nature | units | identifier | huge |
blowup | maxdelta
discipline_declaration ::=
discipline discipline_identifier
[ discipline_descriptions ]
enddiscipline
discipline_descriptions ::=
discipline_description
| discipline_description discipline_descriptions
discipline_description ::=
nature_binding
| attr_description
nature_binding ::=
pot_or_flow nature_identifier ;
attr_description ::=
pot_or_flow . attribute_identifier = constant_expression ;
pot_or_flow ::=
potential | flow
parameter_declaration ::=
parameter [opt_type] list_of_param_assignments ;
opt_type ::=
real | integer
list_of_param_assignments ::=
declarator_init
| list_of_param_assignments , declarator_init
declarator_init ::=
parameter_identifier = constant_expression [ { opt_range } ]
opt_range ::=

Grammar Summary
from range_specifier
| exclude range_specifier
| exclude constant_expression
range_specifier ::=
start_paren expression1 : expression2 end_paren
start_paren ::=
[ | (
end_paren ::=
] | )
expression1 ::=
constant_expression | -inf
expression2 ::=
constant_expression | inf
input_declaration ::=
input [range] list_of_port_identifiers ;
output_declaration ::=
output [range] list_of_port_identifiers ;
inout_declaration ::=
inout [range] list_of_port_identifiers ;
list_of_port_identifiers ::=
port_identifier { , port_identifier }
integer_declaration ::=
integer list_of_identifiers ;
real_declaration ::=
real list_of_identifiers ;
var_name { , var_name }
var_name ::=
variable_identifier
| array_identifier range
node_declaration ::=
discipline_identifier [range] list_of_nodes ;
list_of_nodes ::=
node_identifier
| node_identifier , list_of_nodes
branch_declaration ::=
branch list_of_branches ;
list_of_branches ::=
list_of_parallel_branches

| list_of_parallel_branches , list_of_branches
list_of_parallel_branches ::=
terminals list_of_branch_identifiers
terminals ::=
( node_identifier )
| ( node_identifier , node_identifier )
list_of_branch_identifiers ::=
branch_identifier
| branch_identifier , list_of_branch_identifiers
genvar_declaration ::=
genvar list_of_genvar_identifiers ;
list_of_genvar_identifiers ::=
genvar_identifier {, genvar_identifier }
analog_function_declaration ::=
analog function [type] function_identifier ;
function_item_declaration { function_item_declaration }
statement
endfunction
type ::=
integer
| real
function_item_declaration ::=
input_declaration
| block_item_declaration
| real_declaration
module_instantiation ::=
instance_list ::=
module_instance { , module_instance } ;
module_instance ::=
name_of_instance ( [ list_of_module_connections ] )
name_of_instance ::=
module_instance_identifier
list_of_module_connections ::=
ordered_port_connection { , ordered_port_connection } |
named_port_connection { , named_port_connection }
ordered_port_connection ::=
[ net_expression ]

Grammar Summary
named_port_connection ::=
. port_identifier ( [ net_expression ] )
parameter_value_assignment ::=
# ( ordered_param_override_list )
| # ( named_param_override_list )
ordered_param_override_list ::=
constant_expression { , constant_expression }
named_param_override_list ::=
named_param_override { , named_param_override }
named_param_override ::=
. parameter_identifier ( constant_expression )
net_expression ::=
net_identifier
| net_identifier [ expression ]
| net_identifer [ msb_constant_expression : lsb_constant_expression ]
analog_block ::=
analog statement
statement ::=
null_statement
| block_statement
| branch_contribution
| procedural_assignment
| conditional_statement
| loop_statement
| case_statement
| generate_statement
| event_controlled_statement
| last_crossing_function
| system_task_enable
null_statement ::=
;
block_statement ::=
begin [ : block_identifier
{ block_item_declaration } ]
{ statement }
end
branch_contribution ::=
bvalue <+ expression ;
bvalue ::=
access_identifier ( analog_signal_list )
analog_signal_list ::=

branch_identifier
| node_or_port_identifier
| node_or_port_identifier , node_or_port_identifier
nexpr ::=
bvalue
| ddt ( bvalue )
| idt ( bvalue )
| idtmod ( bvalue )
procedural_assignment ::=
lexpr = expression ;
lexpr ::=
integer_identifier
| real_identifier
| array_element
array_element ::=
integer_identifier [ constant_expression ]
| real_identifier [ constant_expression ]
conditional_statement ::=
if ( expression ) statement [ else statement ]
case_statement ::=
case ( expression )
case_item {case_item}
endcase
case_item ::=
expression { , expression } : statement
| default [ : ] statement
loop_statement ::=
forever statement
| repeat ( expression ) statement
| while ( expression ) statement
| for ( procedural_assignment ; expression ; procedural_assignment )
statement
generate_statement ::=
statement
start_expr ::=
constant_expression
end_expr ::=
constant_expression
incr_expr ::=
constant_expression
event_controlled_statement ::=
@ ( event_expression ) statement

Grammar Summary
event_expression ::=
simple_event [ or event_expression ]
simple_event ::=
global_event
| event_function
| identifier
global_event ::=
initial_step [ ( analysis_list ) ]
| final_step [ ( analysis_list ) ]
analysis_list ::=
analysis_name { , analysis_name }
analysis_name ::=
" analysis_identifier "
event_function ::=
cross_function
| timer_function
cross_function ::=
cross ( expression [ , opt_args ] )
opt_args ::=
direction [ , time_tol [ , expression_tol ] ]
direction ::=
+1
| -1
time_tol ::=
expression
expression_tol ::=
expression
timer_function ::=
timer ( start_time [ , period ] )
start_time ::=
expression
period ::=
expression
last_crossing_function ::=
last_crossing ( expression [ , direction ] )
system_task_enable ::=
system_task_name [ ( expression { , expression } ) ] ;
system_task_name ::= $strobe | $fstrobe | $write | $fwrite | $display |

$fdisplay | $monitor | $fmonitor | $fclose | $finish | $stop | $fopen

range ::=
[ constant_expression : constant_expression ]
constant_expression ::=
constant_primary
| string
| unary_operator constant_primary
| constant_expression binary_operator constant_expression
| constant_expression ? constant_expression : constant_expression
constant_primary ::=
number
| parameter_identifier
expression ::=
primary
| unary_operator primary
| expression binary_operator expression
| expression ? expression : expression
| function_call
| access_function ( arg_list )
| built-in_function ( arg_list )
| system_function ( arg_list )
function_call ::=
function_identifier ( expression { , expression } )
arg_list ::=
expression { , expression }
access_function ::=
bvalue
unary_operator ::=
+ | - | ! | ~
binary_operator ::=
+ | - | * | / | % | == | != | && | || | < | <= | > | >= | & | | | ^ |
^~ | ~^ | >> | <<
primary ::=
number | identifier | identifier [ expression ] | nexpr | ( expression )
number ::=
decimal_number | real_number
decimal_number ::=
[ sign ] unsigned_num
real_number ::=
[ sign ] unsigned_num . unsigned_num
| [ sign ] unsigned_num [ . unsigned_num ] e [ sign ] unsigned_num | [ sign ]
unsigned_num [ . unsigned_num ] E [ sign ] unsigned_num
| [ sign ] unsigned_num [ . unsigned_num ] unit_letter

Grammar Summary
sign ::=
+ | -
unsigned_num ::=
decimal_digit { decimal_digit }
decimal_digit ::=
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
unit_letter ::=
T | G | M | K | m | u | n | p | f | a
analog_function ::=
ddt | idt | idtmod | absdelay | transition | slew | analysis | flicker_noise
| noise_table | white_noise |laplace_zp | laplace_zd | laplace_np |
laplace_nd |
zi_zp | zi_zd | zi_np | zi_nd
built_in_function ::=
ln | log | exp | sqrt | min | max | abs | pow | sin | cos | tan | asin |
acos | atan | atan2 | sinh | cosh | tanh | asinh | acosh | atanh | hypot
|limexp | ceil | floor
system_function ::=
$realtime | $abstime | $temperature | $vt | $discontinuity | $bound_step
comment ::=
short_comment
| long_comment
short_comment ::=
// comment_text \n
long_comment ::=
/* comment_text */
comment_text ::=
{ Any_ASCII_character }
string ::=
" { Any_ASCII_character_except_newline } "
identifier ::=
simple_identifier
| escaped_identifier
simple_identifier ::=
[a-zA-Z]{a-zA-Z_$0-9}
escaped_identifier ::=
{ Any_ASCII_character_except_white_space }
white_space
white_space ::=
space | tab | newline


Chapter 12:
Standard Definitions File
The following files, discipline.h and constants.h define the type of nature and discipline,
including mathematical and physical constants. The file discipline.h declares standard natures
and disciplines useful for analog systems. One can use these definitions as they are, change them, or
override them. For further details of using these files, see Chapter 2: “Makeup of Modules” and
Chapter 2: “The SmartSpice Verilog-A Simulation Flow”.
Abstol attribute redefinition

All abstol attributes defined in this file can be overidden by defining a macro with a name composed
of the nature name and the string "_ABSTOL". To override an abstol value, the corresponding
abstol macro must be redefined before the file discipline.h is included.
Example
In the VERILOG-A source file:
// redefine the abstol attribute for the current nature

’define CURRENT_ABSTOL 2.0e-12
// include explicitly the standard file

’include "discipline.h"
module resistor(n,p);
// now every nodes declared from a discipline with the nature Current will
have the modified abstol
...
12.1: “discipline.h” content

The content of the file "discipline.h" is the following:
// Verilog-A standard definitions

//
// derived from Verilog-AMS Language Reference Manual version 2.0
//
// Natures and Disciplines
//
/*
* Default absolute tolerances may be overridden by setting the
* appropriate _ABSTOL prior to including this file
*
*/
// Electrical
// Current in amperes
nature Current
units = "A";
access = I;

idt_nature = Charge;
’ifdef CURRENT_ABSTOL
abstol = ’CURRENT_ABSTOL;
’else
abstol = 1.0e-12;
’endif
endnature
// Charge in coulombs
nature Charge
units = "coul";
access = Q;
ddt_nature = Current;
’ifdef CHARGE_ABSTOL
abstol = ’CHARGE_ABSTOL;
’else
abstol = 1e-14;
’endif
endnature
// Potential in volts
nature Voltage
units = "V";
access = V;
idt_nature = Flux;
’ifdef VOLTAGE_ABSTOL
abstol = ’VOLTAGE_ABSTOL;
’else
abstol = 1e-6;
’endif
endnature
// Flux in Webers
nature Flux
units = "Wb";
access = Phi;
ddt_nature = Voltage;
’ifdef FLUX_ABSTOL
abstol = ’FLUX_ABSTOL;
’else
abstol = 1e-9;
’endif
endnature
// Conservative
discipline

potential Voltage;
flow Current;
enddiscipline
// Signal flow
disciplines
discipline voltage
potential Voltage;
enddiscipline
discipline current
potential Current;
enddiscipline
// Magnetic
// Magneto_Motive_Force in Ampere-Turns
nature Magneto_Motive_Force
units = "A*turn";
access = MMF;
’ifdef MAGNETO_MOTIVE_FORCE_ABSTOL
abstol = ’MAGNETO_MOTIVE_FORCE_ABSTOL;
’else
abstol = 1e-12;
’endif
endnature
// Conservative discipline
discipline magnetic
potential Magneto_Motive_Force;
flow Flux;
enddiscipline
// Thermal
nature Temperature
units = "C";
access = Temp;
’ifdef TEMPERATURE_ABSTOL
abstol = ’TEMPERATURE_ABSTOL;
’else
abstol = 1e-4;
’endif
endnature
// Power in Watts
nature Power
units = "W";
access = Pwr;

’ifdef POWER_ABSTOL
abstol = ’POWER_ABSTOL;
’else
abstol = 1e-9;
’endif
endnature
// Conservative discipline
discipline thermal
potential Temperature;
flow Power;
enddiscipline
// Kinematic
// Position in
meters
nature Position
units = "m";
access = Pos;
ddt_nature = Velocity;
’ifdef POSITION_ABSTOL
abstol = ’POSITION_ABSTOL;
’else
abstol = 1e-6;
’endif
endnature
// Velocity in meters per second

nature Velocity
units = "m/s";
access = Vel;
ddt_nature = Acceleration;
idt_nature = Position;
’ifdef VELOCITY_ABSTOL
abstol = ’VELOCITY_ABSTOL;
’else
abstol = 1e-6;
’endif
endnature
// Acceleration in meters per second squared

nature Acceleration
units = "m/s^2";
access = Acc;
ddt_nature = Impulse;
idt_nature = Velocity;

’ifdef ACCELERATION_ABSTOL
abstol = ’ACCELERATION_ABSTOL;
’else
abstol = 1e-6;
’endif
endnature
// Impulse in meters per second cubed

nature Impulse
units = "m/s^3";
access = Imp;
idt_nature = Acceleration;
’ifdef IMPULSE_ABSTOL
abstol = ’IMPULSE_ABSTOL;
’else
abstol = 1e-6;
’endif
endnature
// Force in newtons
nature Force
units = "n";
access = F;
’ifdef FORCE_ABSTOL
abstol = ’FORCE_ABSTOL;
’else
abstol = 1e-6;
’endif
endnature
// Conservative disciplines
discipline kinematic
potential Position;
flow Force;
enddiscipline
discipline kinematic_v
potential Velocity;
flow Force;
enddiscipline
// Angle in radians
nature Angle
units = "rads";
access = Theta;
ddt_nature = Angular_Velocity;
’ifdef ANGLE_ABSTOL

abstol = ’ANGLE_ABSTOL;
’else
abstol = 1e-6;
endnature
// Angular velocity in radians per second

nature Angular_Velocity
units = "rads/s";
access = Omega;
ddt_nature = Angular_Acceleration;
idt_nature = Angle;
’ifdef ANGULAR_VELOCITY_ABSTOL
abstol = ’ANGULAR_VELOCITY_ABSTOL;
’else
abstol = 1e-6;
endnature
// Angular acceleration in radians per seconds squared

nature Angular_Acceleration
units = "rads/s^2";
access = Alpha;
idt_nature = Angular_Velocity;
’ifdef ANGULAR_ACCELERATION_ABSTOL
abstol = ’ANGULAR_ACCELERATION_ABSTOL;
’else
abstol = 1e-6;
’endif
endnature
// Force in newtons
nature Angular_Force
units = "n/m";
access = Tau;
’ifdef ANGULAR_FORCE_ABSTOL
abstol = ’ANGULAR_FORCE_ABSTOL;
’else
abstol = 1e-6;
’endif
endnature
// Conservative disciplines
discipline rotational
potential Angle;
flow Angular_Force;
enddiscipline
discipline rotational_omega

potential Angular_Velocity;
flow Angular_Force;
enddiscipline
12.1.1: "Constants.h" file

The constants.h file defines mathematical and physical constants commonly used in an analog
system. The constant.h file needs to be included explicitly with the following line:
‘ include "constants.h"
The content of the file is the following:
// Mathematical and physical constants
’ifdef CONSTANTS_H
’else
’define CONSTANTS_H
// M_ is a mathematical constant
’define M_E 2.7182818284590452354
’define M_LOG2E 1.4426950408889634074
’define M_LOG10E 0.43429448100325182765
’define M_LN2 0.69314718055994530942
’define M_LN10 2.30258509299404568402
’define M_PI 3.14159265358979323846
’define M_TWO_PI 6.28318530717958647652
’define M_PI_2 1.57079632679489661923
’define M_PI_4 0.78539816339744830962
’define M_1_PI 0.31830988618379067154
’define M_2_PI 0.63661977236758134308
’define M_2_SQRTPI 1.12837916709551257390
’define M_SQRT2 1.41421356237309504880
’define M_SQRT1_2 0.70710678118654752440
// P_ is a physical constants
// charge of electron in coulombs
’define P_Q 1.6021918e-19
// speed of light in vacuum in meters/sec
’define P_C 2.997924562e8
// Boltzman’s constant in joules/Kelvin
’define P_K 1.3806226e-23
// Plank’s constant in joules*sec
’define P_H 6.6260755e-34
// permittivity of vacuum in farads/meter
’define P_EPS0 8.85418792394420013968e-12
// permeability of vacuum in henrys/meter
’define P_U0 (4.0e-7 * ’M_PI)

// zero celsius in kelvin

’define P_CELSIUS0 273.15
’endif

Chapter 13:
The SmartSpice Verilog-A Simulation Flow
The main stages of the Verilog-A interface are described below:

1. A compilation phase: During the sourcing of a SMARTSPICE netlist, VERILOG-A files referred to by
the .verilog command cards are compiled by the VERILOG-A SILVACO COMPILER. As a result of
the compilation, a C file is produced for each module parsed.
2. A linkage phase: The generated C files are then automatically parsed by the SILVACO C-
INTERPRETER, and transformed into an optimized pseudo-code that will be executed during the
simulation. If the C files are compiled by a gcc or the native C compiler, a Dynamically
Linkable Library (a .so file) is produced. This library is then linked to the SMARTSPICE
executable.
3. A simulation phase: Once all VERILOG-A modules have been incorporated, the simulation in
SMARTSPICE is done as usual. The compilation, and the linkage are in fact transparent to the user.
Simulating a netlist with VERILOG-A module is still done the same way as with a traditional netlist:
first the netlist is sourced, then a simulation is run, and the results output in a text or graphical
form.
The simulator flow with example of editing VERILOG file(s) and SMARTSPICE input deck, is shown in
Figure 13-1.
Figure 13-1: Simulation Flow

13.1: Choosing the SILVACO C-INTERPRETER or a third-party C compiler

• On Windows NT 4.0, Windows 2000 and XP platforms: The SILVACO C-INTERPRETER is automatically
used, and is, for the moment, the only solution available to execute VERILOG-A modules. The user
does not need to setup anything.
• On Unix platforms: The GCC compiler is automatically used. The user needs to check that they
have access to it. This solution will provide the best results in terms of CPU usage. If the user does
not have a GCC, or a third-party C compiler installed on his platform, he can still switch to the
SILVACO C-INTERPRETER.
There are 2 ways to specify the usage of the SILVACO C-INTERPRETER:

1. by setting the environment variable SMARTSPICE_VERILOGA_SCI to 1 with the following shell
command: setenv SMARTSPICE_VERILOGA_SCI 1.
2. by setting the switch SCI to 1 in the smartspice.init_va config file.
The first way will have a global effect: everytime SMARTSPICE is run, the VERILOG-A INTERFACE will use
the SILVACO C-INTERPRETER. In contrast the second implementation of, the switch will have an effect only
on the netlists run from the same directory as the config file.
13.2: The SmartSpice Verilog-A interface

13.2.1: New Verilog-A Language Features Supported
Analog primitives
Analog primitives are SPICE devices, model cards or subcircuits that can be instantiated from a
VERILOG-A module. These SPICE analog primitives are instantiated in the same way as any other
VERILOG-A modules. The syntax of an analog primitive instantiation is the following:
Syntax
primitive_name #( parameter_override_list ) instance_name
( port_association_list );
Example
// instantiate SPICE primitives resistor, tline and capacitor.

module mva(in1,in2,out);
inout in1,in2,out;
electrical in1,in2,out;
ground grnd;
resistor #(.r(50)) r1(in1,in2);

tline #(.z0(50), .td(10n), .l(0.1)) t1(in2,grnd,out);
resistor #(.r(50)) r1out(out,grnd);
capacitor #(.c(1pf)) c1(out,grnd);
endmodule // mva

Example
vsource #(.type("sine"), .ampl(5), .freq(0.995e06)) vin1(out1,gnode);
vpwl #(.wave([0, 2, 0.03u, 3])) vin2(out2,gnode);
vsource #(.type("pulse"), .val0(5), .val1(-5), .td(10n), .rise(10n),
.fall(10n), .width(40n), .period(100n)) vin3(out3,gnode);
13.2.2: Attributes HUGE, BLOWUP, MAXDELTA (Cadence Compatibility)

The attributes Huge, Blowup and Maxdelta are now recognized by the simulator (see also Table 4-1).
The meaning of theses attributes is the following:
• huge: bounds the change in value between iteration. This helps convergence when signal values
are very large. Default: 45.036e06
• blowup: Exit the simulation with an error message when a value exceeds this attribute value.
• maxdelta: bounds the change for voltage biases allowed on a Newton-Raphson iteration. Default:
0.0
13.2.3: The power function: $pwr

The $pwr system task computes the power consumption of a module.
Note: The $pwr function is a nonstandard function.
Syntax
$pwr( expr )
where expr is an expression that specifies the power contribution.
Example
// Resistor with power contribution
module Res(pos, neg);
inout pos, neg;

electrical pos, neg;
parameter real r=5;
analog begin
V(pos,neg) <+ r * I(pos,neg);
$pwr(V(pos,neg)*I(pos,neg));
end
endmodule
Access to the power consumption from the netlist is done by using the following syntax:
@YVLGinst_name[_pwr]

Example
YVLGr1 in1 out1 Res r=1e3
YVLGr2 out1 0 Res r=1e3
.save @YVLGr1[_pwr] @YVLGr2[_pwr]
Futhermore, like any other devices, the power consumption is displayed for each instance and then
added for each model. The following listing is the output after simulating a netlist with the 2 instances
YVLGr1 and YVLGr2:
****** model type: VLG
subckt
element yvlgr2 yvlgr1
model Res Res
_pwr 1.5625e-03 1.5625e-03
Total VLG:Res power dissipation = 3.1250e-03 Watts
13.2.4: The mathematical functions: hypot(x,y) and atan2(x,y)

The function hypot(x,y) is equivalent to Sqrt(x^2 + y^2 ) and atan2(x,y) to the Arc-tangent of x/y.
13.2.5: Analysis Mode

In the current implementation, only DC, AC and transient and noise analysis are supported. Work will
be done to support the noise analysis.
13.2.6: Usage of the .PRINT and .PLOT Smartspice commands

It is possible to refer VERILOG-A objects from the netlist with the .PRINT or the .PLOT command.
Objects that are accessible from the netlist are the following:
• sources and probes of all potential or flow quantities.
• real variables.
Objects that are not yet accessible are:
• potential or flow quantities not used as a source or a probe.
• objects in a module instantiated from another VERILOG-A module.
Example
In the module I_level_shift in the following listing, I(out) and I(in) are the only quantities to be
available through the print command. The potential quantities V(out) and V(in) are not accessible.
Verilog-A module:
module I_level_shift(in,out);
input in;

output out;
electrical in,out;
parameter real iout_offset = 0;
analog
I(out) <+ I(in) + iout_offset; // I(out) and I(in) can be used in the
//.PRINT and .PLOT commands
// V(out) and V(in) are not accessible
endmodule
13.2.7: Usage of the command .MODIF

The .MODIF command card can be used to refer VERILOG-A parameters. In the following example,
the VERILOG-A parameter T is incremented by the value 1 for every new execution.
netlist:
* c sensor
.verilog "c_sensor.va"
vin 1 0 dc 0.1 PULSE (0 1 10n 10n 10n 20n 100n)
YVLGlevelShift 1 2 I_level_shift iout_offser=1
r2 2 0 1k
.op
.dc vin .1 10 1
.tran 1n 200n 1n
.print @YVLGlevelShift[I(out)]
.MODIF LOOP=2 YVLGlevelShift(iout_offset)+=1
13.2.8: Usage of the command .ST

A parameter sweep can be performed on VERILOG-A parameters with the control card .ST. In the
following example, a sweep is performed on the parameter ’r’ of the VERILOG-A resistor module.
Example
.verilog "resistor.va"
vin 1 0 1
YVLGrin 1 2 resistor
cin 2 0 1p
.TRAN 1n 10n UIC
.LET v1=v(1)
.LET v2=v(2)
.ST LIST YVLGrin(r) 1k 2k 5k
13.3: The Verilog-A compiler configuration file

A configuration file can be used to customize the execution of the VERILOG-A compiler. The name of the
configuration file is smartspice.init_va. It has to be located in the current working directory, and/or the
user home directory. Options set in the file located in the current working directory will override the
ones set in the file located in the home directory. The commands available in a configuration file are
described below.

Examples
set_c_compiler_path /main/frlocal/sparc-solaris2/bin
add_include_path ../include/
The switches available are described in the next table.
Configuration commands for The VerilogA compiler
Command name arguments Description
set_switch <switch-name> <value> set a switch
add_include_path <path-name> add an include path
set_c_compiler_path <path-name> set path for the c
compiler
Switches for the VerilogA compiler
Switch Switch Name Values Default
Verilog Preprocessor Output VPP 0 | 1 0
SmartSpice User’s Manual - Volume 2
The switch VPP (Verilog Preprocessor Output Switch) is 1, the result of the preprocessor will be stored
in a file with the same name as the input file but with the extension vpp.
The switch GCC (Gnu C Compiler switch) indicates to use gcc instead of the native C compiler. By
default, GCC is set to 1.
The switch SCI (SILVACO C-INTERPRETER) indicates to use the SILVACO C-INTERPRETER instead of a C
compiler.
Gnu C Compiler GCC 0 | 1 1

Silvaco C Interpreter SCI 0 | 1 1 on Windows
0 on Unix
Switches for the VerilogA compiler
Switch Switch Name Values Default
13.4: The .verilog card

VERILOG-A source files are compiled with the same command card .verilog. All the VERILOG-A modules
instantiated in the SMARTSPICE netlist need to have their corresponding source files compiled with the
.verilog card.
The .verilog card takes a single argument, which is the name of the VERILOG-A file. Several .verilog
cards can be used in the same netlist. The file name could have a relative or absolute path name. If
the filename has a relative path name, the directory of reference is the directory where the SMARTSPICE
netlist file is located.
Examples
.verilog “resitor.va”
.verilog “../capacitor/capacitor.va”
.verilog “/export/home/lionelk/myLib/inductor/inductor.va”
13.5: Module instantiation

VERILOG-A modules can be instantiated with a syntax similar to any other device. Also, a model card
can be created using an existing module. The syntax for a Verilog-A module instantiation is the
following:

YVLG<instance-name> <interface-node> <module-name> (<param-

name=paramvalue>)*
The following restrictions apply during a VERILOG-A module instantiation:

• <module-name> must have the same as a VERILOG-A module name or a model defined in a model
card.
• <interface-node> is the list of node instantiation. The number of nodes must match the
number of nodes declared in the VERILOG-A module. For parsing reason, the number of ports must
be fixed at instantiation time. Because of this, it is not possible to assign a value to a parameter
that defines the bounds of a vector port. The resizing of the bounds of a vector port must be done in
a model card definition.
• <param-name> must be a parameter declared in the VERILOG-A module. If a parameter has no
value assigned, the default value specified in the VERILOG-A module will be used.
Example
* instantiation of the module resistor. vss and gnd

* are the port names. The parameter resistance is
* assigned the value 1k
YVLGr1 vss gnd resistor resistance=1k
13.6: Model Card with Verilog-A module

As for other devices, it is possible to create a model card from a VERILOG-A module. The syntax is the
following:
.model <model-name> VLG MODULE= <module-name> (<param-name=param-value>)*
Example
* declares a VLG model card m_resistor that uses the Verilog-A module
* ’resistor’ and assign
.model m_resistor VLG MODULE=resistor thermal_resistance=4
and assign the value 4 to the parameter thermal_resistance
Netlist Example
The following netlist shows an RLC circuit. The VERILOG-A files containing the resistor, inductor and
capacitor modules are included with the .verilog card. The modules:
netlist:
* RLC circuit using Verilog-A modules
.verilog "resistor.va"
.verilog "inductor.va"
.verilog "capacitor.va"
VIN1 1 0 PWL 0 0 10n 5 25m 5 25.01M 0
YVLGr1 1 tmp resistor r=200

YVLGl1 tmp 2 inductor l=125m

YVLGc1 2 0 capacitor c=1u
.tran.2M 50M
.print v(1) v(2)
.end
The next netlist shows a circuit where the same VERILOG-A module is instantiated several times, but
with a different number of ports. A model card is created for each value of the parameter size. Only the
relevant parts are shown in the listing.
netlist:
.verilog "and.va"
YVLGand1 1 2 3 4 and_3
YVLGand2 4 5 6 and_2
...
...
.model and_3 VLG MODULE = V_and size=3
.model and_2 VLG MODULE = V_and size=2
In this netlist, nodes 1, 2, 3 and 4 are assigned to node in[0], in[1], in[2] and in[3] respectively. The
following listing shows the code for the Verilog-A module V_and:
module V_and(in,out);
parameter real size = 2 from [2:inf);
input [0:size-1] in;
output out;
voltage in,out;
...
...
endmodule
The modules resistor, inductor and capacitor are instantiated respectivly with the names YVLGr1,
YVLGl1, YVLGc1
13.7: The Smartspice Verilog-A interface

13.7.1: DLL support for Windows platforms with the compiler VC++
The DLL ( Dynamic Linkage Library ) mechanism allows SMARTSPICE to run VERILOG-A devices faster
than with the SILVACO C-INTERPRETER. DLLs are produced by a C/C++ compiler, and for the moment,
only the C/C++ compiler from the Microsoft Visual Studio 6.0 environment ( VC++ ), is supported. If
you wish to use another C compiler, please contact SILVACO at support@silvaco.com.
The following section describes the necessary steps to check that your system is ready to execute
VERILOG-A devices with VC++.
1. First, you will need to check that the following system variables PATH, INCLUDE and LIB are
correctly set so VC++ can run correctly. To access system variables, right click the Icon “My
Computer”, select “Properties” then check that the system variables described in the following
table are correctly set. (For the variable PATH, the value %PATH% refers to the previous value of
PATH that have to be kept)

Variables Suggested Value
PATH %PATH%;C:\Program Files\Microsoft Visual Studio\Com-

mon\Tools;C:\Program Files\Microsoft Visual Studio\Com-
mon\Msdev98\BIN;
INCLUDE C:\Program Files\Microsoft Visual Studio\VC98\INCLUDE
LIB C:\Program Files\Microsoft Visual Studio\VC98\LIB
You can also set variables in the AUTOEXEC.BAT files through the following commands:
rem we supposed that Visual Studio has been installed in the directory
rem C:\Program Files\Microsoft\Visual Studio
set MSVC_ROOT = C:\Program Files\Microsoft\Visual Studio
set PATH=%PATH%;%MSVC_ROOT%\Common\Tools;
set PATH=%PATH%;%MSVC_ROOT%\Common\MSDEV98\BIN;
set PATH=%PATH%;%MSVC_ROOT%\VC98\BIN;
set INCLUDE=%MSVC_ROOT%\VC98\INCLUDE
set LIB=%MSVC_ROOT%\VC98\LIB
2. To set the SMARTSPICE VERILOG-A interface to use DLL with VC++ instead of the SILVACO C-
INTERPRETER, the user variable SMARTSPICE_VERILOGA_VCC has to be set 1. You can set it
through the “Properties” windows or with the following command in the AUTOEXEC.bat:
set SMARTSPICE_VERILOGA_VCC=1
3. To double check now that your system is correctly configured, you can execute the following
command in a MS-DOS prompt windows:
Microsoft(R) Windows NT(TM)
(C) Copyright 1985-1996 Microsoft Corp.
C:\>echo %PATH%
C:\Program Files\Microsoft Visual Studio\Common\Tools;C:\Program
Files\Microsoft Visual
Studio\Common\Msdev98\BIN;C:\WINNT\system32;C:\WINNT;c:\Program
files\microsoft visual studio\vc98\bin;c\silvaco\bin;
C:\>cl
Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 12.00.8168 for 80x86
Copyright (C) Microsoft Corp 1984-1998. All rights reserved.
usage: cl [ option... ] filename... [ /link linkoption... ]
C:\>echo %SMARTSPICE_VERILOGA_VCC%
1

13.8: Verilog-A error and warning messages

The following section is a list of messages displayed when encountering errors. Only a subset of the
error and warning messages are listed and explained. Examples are given to clarify the warning or
error messages, but are not the only situation for which the message might occur. These messages are
listed in alphabetical order.
Two types of error messages might occur:
• Parsing Errors (or warnings): they are syntax or semantic errors related to the VERILOG-A
language. They have the following format:
<file name> at line <number>: Error:
<error message>
Example
"test1.va" at line 16: Error:
Unknown system task ’$last_cross’.
Once the error has been fixed, (here in the previous example, ‘$last_cross’ should have been
changed to ‘last_crossing’ ), re-source the netlist so SMARTSPICE will re-compile the VERILOG-A
source file.
• Simulation Errors (or warnings): run-time errors found during the SMARTSPICE simulation. Some
of these errors are domain or range checks that indicate that some VERILOG-A equations are
incomplete for some specific input values. It is the responsability of the user to create a model
where all possible input values are processed correctly. These error messages have the following
format:
Error: (VERILOGA): <error message>
Example
Error: (VERILOGA): Can not access verilog input file : ’test9.va’
13.8.1: Parsing errors

• “’analysis’ analog function requires string arguments.”
Example
if ( analysis(AC) ) // ERROR: argument must be “AC”
• “Argument <number> of the concatenation operation has an unmatched type.”
Concatenation element type does not match the other element types.
Example
reg [8*14:1] stringvar;
stringvar = {"!!!",25}; // ERROR: string type expected for argument 2.
• “Assignment statement type mismatch.”

The type of a right hand-side does not match the type of a left hand-side for a variable procedural
assignment.

Example
integer val1;
val1 = “string val”; // ERROR: integer type expected in the right hand-side.
• “Cannot assign value to genvar <name>.”
genvar variables can only be incremented in for-loops.
• “Can not evaluate size of vector <identifier> for port association.”

Expression of a vector range definition must be a constant expression ( numbers or parameters ).
• “Can not redeclare access attribute in a derived nature.”

Access attributes can only be declared in a base nature.
• “Domain error with constant argument for operator <operator name>.”

Argument is outside the domain of a mathematical operator.
• “Formal parameter <parameter name> not found in module instantiation.”

A parameter does not exist in the instantiated module.
• “Illegal type expression for parameter initialisation.”

Real or integer type are only supported for parameter.
• “Implicit node <node name> cannot be a vector.”

Implicit nodes ( nodes referenced in module instantiation statement that are not declared ) can only be
scalar.
• “Invalid access <function name> for branch <branch name>.”
Example
electrical node1;
F(node1) <+ R*I(node1); // ERROR: access function F is not valid.
• “No Branch quantity expression found.”

Internal compiler error. See previous VERILOG-A parsing errors. If not, contact support@silvaco.com.
• “No Code Generation Method for Expression <expression>.”

Internal compiler error. See previous VERILOG-A parsing errors.If not, contact support@silvaco.com.
• “Node <node name> is a vector. Index expression required.”
Access to a vector element requires a bracket operator.

• “Nodes <node name> and <node name> are not compatible.”

Two nodes referenced in a branch do not have the same discipline.
Example
electrical node1;
thermal node2;
V(n1,n2) <+ cos(ph); // ERROR: n1 and n2 have incompatible disciplines.
• “Ordered parameter assignment in analog primitive instance <instance name> not allowed.”
Example
resistor #(200)r1(in,tmp); // ERROR:parameter assignment must be by name
// ex:.p(200)
• “Parameter <name> not found in analog primitive <name> for instance <name>.
Parameter not found in an analog primitive ( spice primitive, spice subcircuit, spice model card ).
Example
$ Smartspice netlist
.SUBCKT srlc2 in out w=10u
R1 in tmp 200
L1 tmp out 125m
C1 out 0 1u
.ENDS srlc
// Verilog-A source file
srlc1 #(.c(1u)) s1(out, grnd);
"wrongSubcircuit.va" at line 12: Error:

Parameter ’c’ not found in analog primitive ’srlc1’ for instance ’s1’.
• “Port <port name> can not be declared as ground node.”
• “Preprocessor Error : Arguments mismatched for macro <macro name>

The number of actual arguments does not match the number of arguments specified during a macro
function defintion.
Example
‘define MY_MAX(x,y,z) if(x > y) then x + z else y + z
val = ‘MY_MAX(val0, val1); //ERROR: 3 arguments expected.
• “Preprocessor Error : Can not redefine <macro name>, already used as directive name.”
The macro name specified in the ‘define directive is already used. Rename macro name.
• “Preprocessor Error : Could not find file <file name>.”

The compiler could not add the file specified in the ‘include directive. Check file name.

• “Preprocessor Error : No arguments found during macro expansion.”

The number of actual arguments does not match the number of arguments specified during a macro
function defintion.
Example
‘define MY_MAX(x,y,z) if(x > y) then x + z else y + z
val = ‘MY_MAX; //ERROR: 3 arguments expected.
• “Recursivity loop found in instantiation statement for module <module name>.”

A module can not have a statment that instantiates itself.
• “Right operand of bitwise operator <operator name> should be integer.”
• “Seed argument must be an integer variable.”

The seed argument of random number generator functions must be an integer.
• “Syntax error near <character>.”
This means that the compiler is unable to determine the exact cause of the error. To find the problem,
look at the referenced line syntax. Look also at the preceding line to see if there is anything wrong
with it, such as a missing semicolon. For example, the following module is missing a semicolon in line
9.
Example
module probe_v2(vout, vin_p, vin_n);
input vin_p, vin_n;
output vout;
electrical vout, vin_p, vin_n;
analog begin
$strobe("hi") // ERROR! Missing semicolon.
$strobe("lo");
V(vout) <+ V(vin_p,vin_n);
end
endmodule
• “<task name> system task requires a string as first argument.”

Wrong type for the first argument of a task.
Example
$strobe(int_val); // ERROR: string argument expected instead of integer
• “<task name> system task requires an integer variable as first argument (channel id).”
Wrong type for the first argument of a task. Example:
$fstrobe("=== first line ==="); // ERROR: missing channel id argument

• “Range error with constant argument for operator <operator name>.
• “Redefinition of nature <nature name>.”

Nature name must be unique.
• “Unexpected character <character>.”

Lexical error. Non-valid character found.
• “Unknown discipline or type ’electrical’. To use ’electrical’ as a discipline, please include the
standard file ’discipline.h’.”
The line ‘include "discipline.h" has to be added at the beginning of the file so standard disciplines can
be referenced.
• “Wrong keyword in domain specification.”
• “Wrong number of arguments during function call.”

In an user analog function call, the actual arguments number does not match the number of formal
arguments.
Example
analog function real chopper;
input sw, in;
V(if0) <+ gain * chopper(V(rf)); // ERROR: 2 arguments expected.
13.8.2: Parsing warnings

• “Contribution statement inside analog event block. Results may be incorrect.”
To avoid convergence problems, contribution statements should to be executed at each iteration of the
SMARTSPICE simulation. For this reason, it is preferable to set only variables in event blocks or if-then
statements.
Example
if ( V(Control) > 1 )
I(a_T,b_T) <+ V(a_T,b_T)/Ron; // WARNING
• “Internal node <node name> not used. The design might not converged.”
Every internal nodes must be referenced at least once in a contribution statement. This will avoid
having a Spice singular matrix. In a hierarchical design, the condition has be true only at one
hierarchy level.
• “No instance name in hierarchical name <name>. Ignored.”

No instance name found in defparam statement.

Example
defparam top.p = 2; // WARNING: top is not an instance name.
• “’$fmonitor’ system task has no string as second argument. Ignored. “
• Unknown command line switch type <line> ignored.

Unknown command in the init file smartspice.init_va.
13.8.3: Simulation errors

• (VERILOGA): <file name> <line number>: Array index out of bound, index value is <number> for a
range definition [<number>:<number>]
This Run-time check failed because of an out-of-bound access to a vector element. Make sure the array
index is within the range definition.
• (VERILOGA): Can not access verilog input file: <file name>

A file specified in a .verilog SMARTSPICE card could not be found.
• (VERILOGA): Compilation of <file name> ... failed

The VERILOG-A compilation of a file failed. Check previous parsing error messages.
• (VERILOGA): error in absdelay for <expression>: delay amount argument has to be a positive
number (was <number>)
Delay argument in the absdelay analog function must be a positive number.
• (VERILOGA): <file name>, line <number>: Argument to <function name> function outside
domain range (<number>), returning sqrt(0.0)
Run-time domain error, make sure that arguments are within the function’s domain.
• (VERILOGA): <file name>, line <number>: division operand equals zero, returning 1.0
Run-time check for division operand.
• (VERILOGA): Failed finding model <ident name>.

See previous parsing error messages.
• (VERILOGA): in instance <name>, parameter <name> outside its validity range.
Run-time check for the parameter value inside its validity range.
Example
parameter real param1 = 5.0;
// ERROR : default value is outside validity range.

parameter real param2 = param1 exclude [-50.0:50);
• (VERILOGA): Model <ident name> from file <file name> already exits as a model card.
Duplicate model name. Look at all VERILOG-A module names declared in the used VERILOG-A files and at
all VLG model cards. Supress or rename duplicates.
• (VERILOGA): Model <ident name> initialization FAILED (see previous messages).

See previous parsing error messages.
• (VERILOGA): model <model name> of analog primitive not found.

See previous VERILOG-A parsing error messages. See previous simulation error messages.
• (VERILOGA): Not enough channel files to open file: <file name>. Limit is 31.
Too many opened files.
• (VERILOGA): when setting real parameter id <number> with value <value> for analog primitive
<name>: <error message>
• (VERILOGA): While parsing model <model name> declaration: No ’MODULE’ parameter

specified.
The keyword MODULE is missing during a VLG model card declaration.
• Error: (VERILOGA): Wrong number of ports in input deck for instance <ident name>. Model
<ident name> requires <number> port(s). <number> found(s).
The number of ports in the netlist for a YVLG device does not match the number of ports in the
corresponding VERILOG-A module definition.
Example
$ In the smartspice netlist
YVLGper
1 2 zero_div $ ERROR: Only 1 port expected.
// In the verilog-A source file

module zero_div(in);
input in;
13.8.4: Simulation Warnings

• (VERILOGA): the previous warning(s) on line <number> occured in a derivative expression
automaticaly generated by the compiler. Results might be incorrect.
Since the VERILOG-A SMARTSPICE interface uses the derivative method to fill in the Spice conductance
matrix, only mathematical expressions that contain derivate values within the function’s domain
should be used. This avoids convergence problems during simulation.

Example
p1B1 = W*cos(a1)*pow((fi_d-fi_sl),2.0)/
(pow(d_dep,2.0)*(tan(a1)+tan(a2)))*miu_sa1_var*eps_ox;
Warning: (VERILOGA): ’B2_pondere_5_temp.2.va’, line 247 : Division operand

equals zero, returning 1.0
Warning: (VERILOGA): the previous warning(s) on line ’247’ occured in a
derivative expression automaticaly generated by the compiler.Results might be
incorrect.


Chapter 14:
Device Modeling in Verilog-A
14.1: Device Modeling

This chapter will explain the development of semiconductor device models within the SMARTSPICE
VERILOG-A framework. We will cover the main aspects of semiconductor device modeling, discuss some
important modeling terminology, and give some examples for Bipolar and MOS technologies.
What are models?
Models, as implemented in SPICE simulators are a set of implemented model equations, which allow
the user to access and define the parameter values externally. The definition of the model equations
and the method for extracting the parameters is called modeling.
Many different device models, also termed Compact Models (CMs), have been developed, at
universities and through internal company research efforts, over the years for various technologies,
some of these models when parameterized match devices produced by manufacturers. It is these
models that eventually become “industry standards”.
It is these “industry standard” CMs that get implemented within the SPICE simulation program.
Two issues arise from this process. The first is no documented agreements containing the technical
specifications or other criteria used such as guidelines, definitions, and application domain. The
second issue is that the user must wait for commercial SPICE vendors to implement these compact
models within their respective codes.
VERILOG-A compact models open many areas of simulation to SPICE users that were formally closed
due to the above process.

14.2: MOSFET Model Tutorial for Verilog-A

This section describes modeling a MOS device, model parameters, and the physical basis for
mathematical formulations.
14.2.1: MOSFET Model Parameter Definitions

The MOSFET LEVEL 3 parameters are discussed below:
TOX - Oxide Thickness

TOX, one of the most important MOSFET parameters, is used to calculate gate oxide capacitance
(COX). The COX parameter may be specified instead of TOX.
RD and RS - Drain and Source Ohmic Resistance

The drain and source ohmic resistances, RD and RS, may be specified for all models. If they are not
specified, they are defaulted to zero values for both models.
LD - Lateral Diffusion Coefficient

The lateral diffusion coefficient, LD, may be specified for all MOSFET models. As discussed in the
section Metallurgical Junction Depth, LD is used to define the effective channel length. Failure to
specify either LD results in the use of the mask-defined channel length throughout the model.
VTO - Zero Bias Threshold Voltage

In addition to determining the boundary between the off region and the linear region of transistor
operation, the value of VTO is used to calculate substrate bias effects, weak inversion effects, mobility
degradation, and temperature effects.
If a value for VTO is not specified and NSUB is specified, then threshold voltage is calculated from the
equation:
2 qε si NSUB ⋅ PHI
VTO = vfb + type  ----------------------------------------------------
- + PHI
 COX 
where:
vfb = flatband voltage
type =1 for NMOS and -1 for PMOS
PHI (2φf ) is the surface potential
KP - Intrinsic Transconductance
The intrinsic transconductance, KP, may be specified. A specified value overrides any calculation or
default value in the model. If KP is not specified, but U0 and TOX (COX) are specified, then:

U 0 ⋅ ε ox
KP = U 0 ⋅ COX = -------------------
-
TOX
GAMMA - Bulk Threshold Parameter

GAMMA is the coefficient of the terms which account for substrate bias effects in the equation for
drain current. If GAMMA is not specified, it is calculated from NSUB as:
2 ⋅ q ⋅ ε si ⋅ NSUB
GAMMA = ------------------------------------------------
-
COX
PHI (2φf) - Surface Potential at Strong Inversion

The surface potential at strong inversion, PHI, may be specified. If the value is specified, it is assumed
to be equal to twice the Fermi level.
PHI = ----------- ⋅ 1 n  ------------------

2 kT NSUB
q  ni 
The value of PHI is used in threshold voltage equations.
NSUB - Effective Substrate Doping Concentration

If GAMMA is specified and NSUB is not specified, then NSUB is calculated from GAMMA. If neither
parameter is specified, then the defaults are used.
U0, UCRIT, and UEXP - Surface Mobility and Degradation Coefficient

UO is the surface mobility. If both KP and U0 are specified, KP causes U0 to be ignored. If neither KP
nor U0 are specified, default values of 600 for NMOS and 250 for PMOS are assumed.
UCRIT and UEXP account for the modeling of mobility degradation due to the vertical electric field:
UCRIT ⋅ ε si
US = U 0 ⋅  -------------------------------------------------
 COX ⋅ ( vgs – von )
If values for UCRIT and UEXP are not specified, default values of 1.0E4 V/cm and 0, respectively, are
assigned. A zero value for UEXP effectively removes all variable mobility effects from the model.
LAMBDA - Channel Length Modulation Parameter

The channel length modulation parameter, LAMBDA, may be specified.
LAMBDA is used to calculate the effective electrical channel length as the depletion region spreads
into the channel. The expression used for the effective electrical channel length is:
L electrical = L eff ⋅ ( 1 – LAMBDA ⋅ vds )
where Leff = Lmask - 2 ⋅ LD - the effective topological channel length.

XJ - Metallurgical Junction Depth

The metallurgical junction depth, XJ, may be specified. If not specified, a zero value is assigned. The
value of XJ can determine the effective channel length. The default value of the lateral diffusion
coefficient, LD, is calculated by the formula:
LD = 0.75 ⋅ XJ
Leff = Lmask – 2 ⋅ 0.75 ⋅ XJ

LD is also used to calculate short-channel effects.
IS - Bulk Junction Reverse Saturation Current

The junction reverse saturation current, IS, may be specified in either the analytical or empirical
models. The parameter represents the coefficient of the diode equation which simulates the current/
voltage characteristics of the drain to substrate and source to substrate diodes. The diode equation for
bulk-source diode is given below:
 vb - 
x
--------

ibx = IS ⋅ e
VT
– 1 where x = S or D
 
 
KT
VT ( V thermal ) = ---------
q
The substrate to source and substrate to drain diode models contain a resistance in parallel with the
current generator described above. This shunt resistance has a default value of 1.0E12 ohms.
NSS - Effective Surface State Density

The effective surface state density, NSS, should be specified only if the empirical model is to be used.
No errors result if NSS is specified in the analytical model, but NSS will not be used in any of the
calculations, and it could lead to some confusion if it is needlessly specified.
NFS - Effective Fast Surface State Density

The effective fast surface state density, NFS, may be specified for either the analytical or empirical
model. If not specified, a zero default value is assigned. The parameter is used in both models for the
weak inversion characteristics. If NFS equals zero, the weak inversion effects section of the model is
bypassed. A non-zero value of NFS produces some drain current for values of vgs < VTO.
TPG - Type of Polysilicon

The type of polysilicon, TPG, should be specified only if the empirical model is used. Specification of
silicon-type parameters in the analytical model will not result in an error, but they will not be used in
any calculations. For the analytical model, the value of VTO will not be modified further by the
specification of TPG.
PHIMS = TPG · FERMIG - FERMIS
FERMIG = Fermi level of the polysilicon gate

FERMIS = Fermi level of the substrate

where:
TPG = +1 for gate material opposite doping from NSUB
TPG = -1 for same doping as NSUB
Thus, the two Fermi levels are additive if the gate doping is of opposite polarity to the substrate, and
they are subtractive if the gate and substrate are of the same doping polarity.
If VTO is not specified then:
Vbi = VFB ( Flat Band Voltage ) + PHI

else
1⁄2
Vbi = VTO – GAMMA ⋅ PHI
where
tox
∫
Qi 1
VFB = PHIMS – ----------- – ------- ρox ( x )x dx
Cox ε ox 0
CGDO and CGSO - Drain and Source Overlap Capacitance

The gate to source and gate to drain capacitances, CGSO and CGDO, may be specified. Failure to
specify the parameter results in a zero value. If values are specified, they must be in units of F/m of
channel width.
CGBO - Gate Bulk Overlap Capacitance

The gate bulk overlap capacitance, CGBO, may be specified. Failure to specify the parameter results in
a zero value. If the value is specified, it must be in units of F/m of channel length. The quantity by the
channel length to determine total capacitance.
CBD and CBS - Zero Bias Substrate to Drain and Substrate to Source Junction
Capacitance
The zero bias substrate to drain and substrate to source capacitance may be specified or calculated:
CBX = CJ ⋅ AX where X = S or D.
If CBS or CBD is specified the CJ is overridden. The depletion capacitors are a function of the voltage
across the PN junction. The expression of this junction capacitance is divided into two regions:
VBX ( X = S or D ) ≥ FC ⋅ PB and VBX ≤ FC ⋅ PB to account for the high injection effects.
PB - Bulk Junction Potential

The bulk junction potential, PB, may be specified. If not specified, it assumes the default value of 0.8
volts. The parameter represents the PN junction contact potential for the source to substrate and
drain to substrate junctions.

FC - Forward Bias Non-Ideal Junction Capacitance Coefficient

The forward bias non-ideal junction capacitance coefficient, FC, may be specified. Along with PB, it
determines the transition between the use of the reverse bias junction capacitance equation and a
forward bias diffusion capacitance equation. The appropriate equations were previously defined. If no
value is specified, the default value of 0.5 is used. For most cases, the default gives satisfactory
performance.

14.3: Temperature Compensation

The following parameters are used for compensation of temperature-dependant parameters.
14.3.1: Temperature Model Equations

These equations model the temperature dependence of various model parameters.
Energy Gap:
The energy gap width is defined by the expression:
2
t
EG ( t ) = 1.16 – 7.02 E – 4 ⋅ --------------------
t + 1108
Saturation Current Density

The source/drain diode saturation current IS and densities JS and JSW as:
Define:
EG EG
f = -------------------------- – -------------
vt ( tnom ) vt ( t )
f
----
N
IS ( t ) = IS ⋅ e
f
----
N
JS ( t ) = JS ⋅ e
f
----
N
JSW ( t ) = JSW ⋅ e
Drain and Source Junction Potential

The temperature effects of the contact potentials of source and drain diodes:
t t  EG ( tnom ) EG ( t )
VJ ( t ) = VJ ⋅ --------------- – vt ( t ) ⋅ 3 ⋅ 1 n  --------------
- + ----------------------------- – ----------------
tnom  tnom vt ( tnom ) vt ( t )
VJ ( t )
CJ ( t ) = CJ ⋅ 1 + MJ ⋅  4 ⋅ 10 e – 4 ⋅ ∆t – --------------- + 1
 VJ 
VJSW ( t )
CJSW ( t ) = CJSW ⋅ 1 + MJSW ⋅  4 ⋅ 10 e – 4 ⋅ ∆t – ------------------------- + 1
 VJSW 
Intrinsic Carrier Concentration

3⁄2
ni ( t ) = 1.45E16 ⋅  --------------- ⋅ exp EG ⋅  --------------- – 1 ⋅  --------------------
t t 1
 tnom  tnom   2 ⋅ vt ( t )

Surface Potential
t  EG ( tnom ) EG ( t )
PHI ( t ) = PHI ⋅  --------------- – vt ( t ) ⋅ 3 ⋅ ln  --------------
t
 tnom - ⋅ ----------------------------- – ----------------
 tnom vt ( tnom ) vt ( t )
Threshold Voltage
EG ( tnom ) – EG ( t ) PH ( t ) – PHI
VTO ( t ) = VTO + ---------------------------------------------------- + type ⋅ -----------------------------------
2 2
Figure 14-1: Large Signal Model for the MOS Transistor
The capacitance of Figure 14-1 is separated into three types. The first type includes the capacitors
CBD and CBS which are associated with the back biased depletion region between the drain and
substrate, and the source and the substrate. The second type includes CGD, CGS and CGB which are
all common to the gate and are dependent upon the operating capacitor of the transistor. The third
type includes parasitic capacitors which are independent of the operating conditions.

The resistors RD and RS (Figure 14-1) represent the ohmic resistance of the drain and source
respectively. These resistors are transformed into conductances by taking their reciprocals:
drain conductance = 1.0/RD
and
source conductance = 1.0/RS
Figure 14-2: Large Signal Charge Storage Capacitors of the MOS Device
Table 14-1: Constants for Silicon
Constant Symbol Constant Description Value Units
k Boltzmann’s constant 1.381 x 10-23 J/K
ni Intrinsic carrier concentration (27°C) 1.45 x 1010 cm-3
ε0 Permittivity of free space 8.854 x 10-14 F/cm
εsi Permittivity of silicon 11.7 εo F/cm
εox Permittivity of SiO2 3.9 εo F/cm
Figure 14-2 can also represent diodes, the pn junctions between the source and substrate, and the
drain and substrate. For proper transistor operation these diodes are always reversed biased. Their
purpose in the dc model is primarily to model leakage currents. These currents are expressed as:
i BD = IS exp  -------------- – 1
VBD
 KT 

and
i BS = IS exp  ------------- – 1
VBS
 KT 
where IS is the reverse saturation current of a pn junction, K is Boltzmann’s constant and T is

temperature in Kelvin units.
The depletion capacitors are a function of the voltage across the pn junction. The expression of this
junction - depletion capacitance is divided into two regions in order to account for the high injection
effects. The first is given as:
– MJ
VBX
CBX = CJ ⋅ AX ⋅ 1 – -------------
PB
for VBX ≤ FC ⋅ PB where:

X = D for CBD and VBD, and S for CBS and VBS
AX = area of source (X = S) or drain (X = D)
CJ = zero bias (VBX = O) junction capacitance per unit area
qε si NSUB
CJ ≅ ----------------------------
-
ZDPB
where:
PB = bulk junction Potential
FC = forward bias non-ideal junction capacitance coefficient
MJ = bulk junction grading coefficient
If VBX > FC ⋅ PB then:
CJ ⋅ AX
1 – ( 1 + MJ )FC + MJ  -------------
VBX
CBX = -----------------------------------
( 1 – FC )
1 + MJ  PB 
To more closely model the depletion capacitance, break it into bottom and side wall components.
For VBX ≤ FC ⋅ PB :
CJ ⋅ AX CJSW ⋅ PX
CBX = ---------------------------------------
MJ
- + -----------------------------------------------
-
 VBX   VBX MJSW
1 – ------------- 1 – -------------
 PB   PB 
and for VBX ≥ ( FC ) ( PB ) :
CJ ⋅ AX
1 – ( 1 + MJ )FC + MJ  -------------
VBX
CBX = -----------------------------------
( 1 – FC )
1 + MJ  PB 
CJSW ⋅ PX
- 1 – ( 1 + MJSW )FC +  ------------- MJSW
VBX
------------------------------------------
( 1 – FC )
1 + MJSW  PB 

where:
AX = area of source (X = S) or drain (X = D)
PX = perimeter of source (X = S) or drain (X = D)
CJSW = zero bias bulk-source/drain sidewall capacitance
MJSW = bulk - source/drain sidewall grading coefficient
MJ = bulk junction grading coefficient
CGXO (X = S or D) is the overlap capacitance in f/m for the gate - source or gate - drain overlap. The
difference between the mask W and the actual W is due to the encroachment of the field oxide under
the silicon nitride. The expressions for gate - source/drain overlap capacitance are:
C 1 = C 2 = ( LD ) ( Weff )Cox = ( CGXO ) ⋅ Weff
where LD is the lateral diffusion component, Weff is the effective channel width, and CGXO (X = S or
D) is the overlap capacitance in F/M for the gate - source or gate - drain overlap.
A third overlap capacitance that can be significant is the overlap between the gate and the bulk. This
gate - bulk overlap capacitance is a function of the effective length of the channel. The gate - bulk
overlap capacitance is expressed by:
CGB = CGBO ⋅ Leff
The gate - channel capacitance is given as:
C 3 = Weff ( L – 2 LD ) ⋅ Cox = Weff ⋅ Leff ⋅ Cox
The term Leff is the effective channel length resulting from the mask - defined length being reduced by
the amount of lateral dopant diffusion. The channel to bulk, C 4, capacitance is a depletion capacitance
that will vary with voltage as CBS and CBD capacitances.
14.3.2: DC Current Equations

LEVEL 3 models drain current for all operating bias regions, and is computed as:
Cutoff Region
ids = 0 for vgs ≤ vth
Turn-on Region
ids = beta ⋅  vgs – vth – --------------- ⋅ vde ⋅ vde

1 + fb
for vgs > vth
 2 
where:
vde = min (vds, vdsat)
W eff W eff
beta = KP ⋅ ----------- = u eff ⋅ COX ⋅ -----------
L eff L eff
Leff = L – 2 ( LD ) Weff = W

and
GAMMA ⋅ fs
fb = fn + -----------------------------------------------
1⁄2
-
4 ⋅ ( PHI + vsb )
The narrow width effect is modeled by the parameter fn:
ε si ⋅ π ⋅ DELTA
fn = ----------------------------------------
-
2 ⋅ COX ⋅ W eff
where DELTA is the narrow width threshold adjust factor parameter.

The short channel effects are modeled by:
XJ scaled  LD scaled + wc 2 1⁄2 LD scaled 

fs = 1 – --------------------- ⋅  ------------------------------------ ⋅ 1 –  ------------------------------------ –  – ----------------------
wp
L eff  XJ scaled + wp  XJ scaled  
 XJ scaled 
1⁄2
wp = xd ⋅ ( PHI + vsb )
2 ⋅ ε si 1⁄2
xd =  --------------------------
 q ⋅ NSUB
wc = XJ scaled ⋅ 0.63135 + 0.08013929 ⋅  --------------------- – 0.0111077 ⋅  ---------------------

wp wp 2
 XJ scaled  XJ scaled
Threshold Voltage
8.14 e – 22 ⋅ ETA 1⁄2
- ⋅ vds + GAMMA ⋅ fs ⋅ ( PHI + vsb ) + fn ⋅ ( PHI + vsb )
vth = vbi – ------------------------------------------
3
COX ⋅ Leff
where vbi = vgb + PHI
1⁄2
or vbi = VTO – GAMMA ⋅ PHI
Saturation Voltage
Saturation voltage is controlled by the parameter VMAX:
vgs – vth
vsat = -------------------------
1 + fb
2 2 1⁄2
vdsat = vsat + vc – ( vsat + vc )
where
VMAX ⋅ L eff
vc = ---------------------------------
usurf
Effective Surface Mobility

U0
usurf = ------------------------------------------------------------------- for vgs > vth
1 + THETA ⋅ ( vgs – vth )

If VMAX is specified:
usurf
u eff = -------------------- for VMAX > 0
vde
1 + ----------
vc
Channel Length Modulation

The channel length reduction, ∆L , is computed as:
1⁄2
∆L = xd ⋅ [ KAPPA ⋅ ( vds – vdsat ) ] for VMAX = 0,
2 2 1⁄2
cef ⋅ xd
2
cef ⋅ xd
∆L = – ---------------------- +  ---------------------- ⋅ ( KAPPA ⋅ xd ⋅ ( vds – vdsat ) )
2
for VMAX > 0
2  2 
where cef is the critical electric field at the pinch-off point. It is computed as:
vc ⋅ ( vc + vdsat )
cef = --------------------------------------------
L eff ⋅ vdsat
The drain current ids in saturation region is computed as:
ids
ids = -------------------
∆L
1 – ---------
L eff
Subthreshold Current
In the subthreshold region of operation, the subthreshold current is dominated by the fast surface
state parameter NFS.
Define:
von = vth + fast for NFS > 0
where:
1⁄2
KT q ⋅ NFS GAMMA ⋅ fs ⋅ ( PHI + vsb ) + fn ⋅ ( PHI + vsb )
fast = --------- ⋅ 1 + --------------------- + -----------------------------------------------------------------------------------------------------------------------------------
q COX 2 ⋅ ( PHI + vsb )
The drain ids current is:
Ids = Ids at Von, Vdmin,
and
= Vsb ⋅ e (Vgs - Von)/fast for Vgs < Von

where:
vdmin = min (vds, vdsat)

14.3.3: Capacitance Calculations
Figure 14-3: Overlap Capacitances of a MOS Transistor and the imact on L and W
The five capacitance elements associated with the MOSFET model topology are described here. The
capacitances CBS and CBD are standard voltage variable junction capacitances. The remaining three
elements represent various gate capacitances, and contain both fixed and variable terms. The fixed
terms are specified as the parameters CGSO, CGDO, and CGBO in the model variable list. They
represent metallization overlap capacitances, as described in Figure 14-3. A variable portion of the
gate to channel capacitance is added to each of these fixed values, depending upon the region of
transistor operation. In the region below cutoff, the entire gate to channel capacitance is assigned to
CGB. As the device operation transitions into the saturated region, up to two-thirds of the channel
capacitance is transferred to CGS. The equation governing the transition is:
von – vgs
CGB = -------------------------- ⋅ ( COX ⋅ W ⋅ L + CGB 0 ⋅ Leff )
PHI ( T )
CGS = -------------------------- ⋅  COX ⋅ W ⋅ L + --- ⋅ CGS 0 ⋅ Weff

vgs – von 2
PHI ( T )  3 
The transition from saturated into linear operation is governed by:
CGS = Weff ⋅ CGS 0 + --- ⋅ COX ⋅ W ⋅ L ⋅  ----------------------------------------------------------------

2 1 – vgd – von
3  vgs – von + vgd – von
CGD = Weff ⋅ CGD 0 + --- ⋅ COX ⋅ W ⋅ L ⋅  ----------------------------------------------------------------

2 1 – vgd – von
3  vgs – von + vgd – von

14.4: MOSFET Model LEVEL=3

14.4.1: Model Parameters
Parameter Description Units Default
TOX Oxide thickness m 1.0E-7
NSUB Substrate doping 1/cm3 1E15
GAMMA Bulk threshold parameter V0.5 calculated
PHI Surface potential (2φf) V
VTO Zero-bias threshold voltage V 0
U0 Bulk mobility cm2/ V-s 600
VMAX Maximum drift velocity of carriers m/s 0
THETA Mobility modulation 0
ETA Static feedback 0
KAPPA Saturation field factor 0.2
DELTA Narrow width threshold adjusting factor 0
KP Transconductance parameter A/V2 2.0E-5
RD Drain ohmic resistance Ohm 0
RS Source ohmic resistance Ohm 0
IS Bulk junction saturation current A 1.0E-14
JS Bulk junction saturation current per unit area A/m2 0
JSW Sidewall junction saturation current per periphery A/m 0

length
NSS Surface state density 1/cm2 0
NFS Fast surface state density 1/cm2 0
TPG Type of gate material: 1.0

+1 opposite to substrate
-1 same as substrate
0 Al gate
XJ Metallurgical junction depth m 0
LD Lateral diffusion for length m 0

(DLAT,
LADT)
LAMDA Channel length modulation v-1 0
CGDO Gate-drain overlap capacitance F/m 0

CGSO Gate-source overlap capacitance F/m 0
CGBO Gate-bulk overlap capacitance F/m 0
CJ Zero-bias area capacitance per junction area F/m2 0
VJ Bottom junction built-in potential V 0.75
MJ Bulk junction grading coefficient 0.33
FC Forward-bias depletion junction capacitance 0.5

coefficient
CJSW Zero-bias sidewall capacitance per junction F/m 0

perimeter
MJSW Sidewall junction grading coefficient 0.33
CBD Zero-bias B-D junction capacitance F 0
CBS Zero-bias B-S junction capacitance F 0
14.4.2: MOS_LEVEL 3 Verilog-A Model

One can download Silvaco’s Verilog-A implementation of this MOS_LEVEL 3 Verilog-A Model at
www.silvaco.com.
14.4.3: EKV MOSFET Model - using Silvaco Verilog-A
Figure 14-4: Intrinsic EKV Model Elements

14.5: EKV MOSFET Model

The EKV (Enz, Krummenacher, Vittoz) MOSFET model has been developed in EPFL (“Ecole
Polytechnique Federale de lausanne” - Switzerland). The model is dedicated to the simulation of low
voltage, low current analog and mixed signal circuits using submicron CMOS technologies.
The EKV model equation is based on a single expression, which preserves continuity of first and
higher order derivatives.
The Silvaco VERILOG-A implementation is based on Version 2.6, Revision II. For more information,
please refer to the EKV Web Page at: http: //legwww.epfl.ch/ekv/.
One can download Silvaco’s Verilog-A implementation of this EKV MOSFET Model at
www.silvaco.com.
14.5.1: Geometry Device Parameters

The MOSFET geometry device parameters supported by the EKV model are:
Name Description Units Default Scaling
L Channel length m - SCALE
W Channel width m - SCALE
M Parallel multiple device factor - 1 -
NS Series multiple device factor - 1 -
AD/AS D/S diffusion junction area m2 0.0 SCALE2
PD/PS D/S diffusion junction perimeter m 0 -
NRD/NRS D/S number of squares - 0 -
GEO D/S geometry selector - 0 -
14.5.2: Effective Channel Length and Width Calculations

The basic equation set in original EPFL implementation is:
L eff = L scaled + DL scaled
W eff = W scaled + DW scaled

Geometry Model Parameters

Name Description Units Defaults Scaling
DW (DWO) Channel width correction m 0.0 SCALM
DL (DLO) Channel length correction m 0.0 SCALM
XJ Metallurgical junction depth m 0.1E-6 SCALM
LD (DLAT, Lateral diffusion into channel from D/S m 0.75 XJ SCALM

LATD, LAP)
WD (WOT) Lateral diffusion into channel from Bulk m 0.0 SCALM
LDIF Lateral diffusion beyond the gate m 0.0 SCALM
HDIF Heavily doped diffusion length m 0.0 SCALM
XL Masking and etching effects on length m 0.0 SCALM
XW Masking and etching effects on width m 0.0 SCALM
METO Fringing factor m 0.0 SCALM
GEO D/S geometry selector - 0 -
ACM Area Calculation Method selector - 2 -
SCALM Scale factor for model parameters - 1.0 -
Setup Parameters
Name Description Default
NQS Non-Quasi-Static operation switch 0
SATLIM Ratio defining the saturation limit if/ir exp (4)
SCALM Model parameter scaling factor 1
XQC Charge/Capacitance model selector 1
IIRAT Impact ionization ratio 0
Process Related Parameters
Name Description Units Default
COX Gate oxide capacitance per unit area F/m2 7.0E-4
DW Channel width correction m 0.0
DL Channel length correction m 0.0
XJ Metallurgical junction depth m 0.1E-6

Basic Parameters
VTO Long-channel threshold voltage V 0.5
GAMMA Body effect parameter V 1.0
PHI Bulk Fermi potential V 0.7
KP Transconductance parameter A/V2 50E-6
UCRIT Longitudinal critical field V/m 2E+6
EO Mobility reduction coefficient V/m 1E+12
THETA Mobility reduction coefficient (former model) 1/V 0.0
Channel Length Modulation and Charge Sharing Parameters
LAMBDA Depletion length coefficient (channel length modulation) - 0.5
WETA Narrow-channel effect coefficient - 0.25
LETA Short-channel effect coefficient - 0.1
Reverse Short-Channel Effect Parameters
QO Peak charge density A.s/m2 0.0
LK Characteristic length m 0.29E-6
Impact Ionization Related Parameters
IBA First impact ionization coefficient 1/m 0.0
IBB Second impact ionization coefficient 1/m 3E8
IBN Saturation voltage factor for impact ionization - 1.0
Intrinsic Model Temperature Parameters

TNOM (TREF, Parameter measurement temperature C 0.0

TEMPM)
TCV Threshold voltage temperature coefficient V/K 1.0E-3
BEX Mobility temperature exponent - -1.5
UCEX Longitudinal critical field temperature exponent - 0.8
IBBT Temperature coefficient for IBB 1/K 9.0E-4
Matching Parameters
AVTO Threshold voltage mismatch parameter V.m 0.0
AKP Gain mismatch parameter m 0.0
AGAMMA Body effect mismatch parameter V .m 0.0
Noise Parameters
Name Description Units Defaults
KF Flicker noise coefficient - 0.0
AF Flicker noise exponent - 0.0

LEVEL 2/3 Parameters
TOX Oxide thickness m ε ox ⁄ COX
VMAX Maximum drift velocity m/s -
UO Surface mobility cm2/(Vs) -
NSUB Substrate doping cm-3 -
VFB Flat-Band voltage V -
14.5.4: Handling of LEVEL 2/3 Parameters

If missing, some EKV parameters can be internally estimated from the value of supported LEVEL2/3
parameters using the following rules:
If TOX is given and COX is missing, the oxide capacitance is evaluated using:
COX = ε ox ⁄ TOX
If UO is given and KP is missing, the transconductance parameter is evaluated using:

KP = COX ⋅ U 0
If VMAX and U0 are given and UCRIT is missing, the longitudinal critical field is evaluated using:
UCRIT = VMAX ⁄ U 0
If NSUB is given and GAMMA is missing, the body effect parameter is evaluated using:
GAMMA = 2 qε ox NSUB ⁄ COX
If NSUB is given and PHI is missing, the bulk Fermi-potential is evaluated using:
PHI = 2 ⋅ V t ⋅ ln ( NSUB ⁄ n i )
If VFB is given and VTO is missing, the long-channel threshold voltage is evaluated using:
VTO = VFB + PHI + GAMMA ⋅ PHI
14.5.5: Temperature Compensation Equations

Define T as the device operating temperature
VTO ( T ) = VTO – TCV ⋅ ( T – TNOM )
BEX
KP ( T ) = KP ⋅  --------------------
T
 TNOM
UCEX
UCRIT ( T ) = UCRIT ⋅  --------------------
T
 TNOM
PHI ( T ) = PHI ⋅ -------------------- – 3 ⋅ V t ⋅ ln  -------------------- – E g ( TNOM ) ⋅ -------------------- + E g ( T )

T T T
TNOM  TNOM TNOM

IBB ( T ) = IBB ⋅ [ 1 + IBBT ⋅ ( T – TNOM ) ]
where E g ( T ) andE g ( TNOM )are the energy gap of silicon evaluated at T and TNOM respectively.

All intrinsic voltages are referred to the substrate and are defined by:
V G = V GB = V GS – V BS
V S = V SB = – V BS
V D = V DB = V DS – V BS
The related transconductances are obtained through derivation of the drain current:
∂I DS
g mg =
∂VG
 ∂I DS
g ms = –  
 ∂ VS 
∂I DS
g md =
∂VD
The “standard” transconductances (related to the voltages where the source is taken as reference) are
evaluated using the following relationships:
∂I DS
gm = = gmg
∂ V GS
∂I DS
g mbs = = gms – g mg – g md
∂ V BS
∂I DS
g ds = = g md
∂ V DS
Drain to Source Current

The drain current expression is a single equation, valid in all operating region and given by:
2
I DS = 2 ⋅ n ⋅ β ⋅ V t ⋅ ( i f – i′ r )
where:
k⋅T
V t = ------------
q
is the thermal voltage at the device operating temperature, n is the slope factor, β is the transconduc-
tance factor, i f is the forward normalized current and i′ r is the reverse normalized current.
Short Distance Matching

The basic idea is to take into account the influence of geometry on random mismatch between identical
transistors close to each other. This effect is described by the following relationships:

AVTO
VTO a = VTO + ---------------------------------------------------------
NP ⋅ W eff ⋅ NS ⋅ L eff
KP a = KP ⋅  1 + ---------------------------------------------------------
AKP
 NP ⋅ W eff ⋅ NS ⋅ L eff
AGAMMA
GAMMA a = GAMMA + ---------------------------------------------------------
NP ⋅ W eff ⋅ NS ⋅ L eff
Effective Gate Voltage including Reverse Short-Channel Effect

V G′ = V G – VTO a – ∆V RSCE + PHI + GAMMA a ⋅ PHI
where:
2 ⋅ Q0 1
∆V RSCE = -------------- ⋅ ------------------------------------------------------------2-
COX 
1 + --- ⋅ ( ξ + ξ + C ε )
1 2
 2 
L eff
ξ = C A ⋅  10 ⋅ --------- – 1
 LK 
–3 2
C ε = 4 ⋅ ( 22 × 10 )
C A = 0.028
Effective Substrate Factor Accounting for Charge-Sharing

o ε si LETA 3 ⋅ WETA
γ = GAMMA a – ------------- ⋅ ----------------- ⋅ ( V′ D + V′ S ) – --------------------------- ⋅ V P 0 + PHI
COX L eff W eff
where:
1 2 2
V′ S ( D ) = --- ⋅ [ V S ( D ) + PHI + ( V S ( D ) + PHI ) + ( 4 ⋅ V t ) ]
2
and
 GAMMA 2 GAMMA
 V G′ – PHI – GAMMA a ⋅  V G′ +  ---------------------------a- – ---------------------------a- ( V G′ > 0 )
VP0 =    2  2 

 – PHI ( V G′ ≤ 0 )
To prevent the effective substrate factor from becoming negative, the following equation is used:
1 o o2
γ′ = --- ⋅ ( γ + γ + 0.1 ⋅ V t )
2

Pinch-Off Voltage including Short- and Narrow-Channel

 γ′ 2 γ′
 V G′ – PHI – γ′ ⋅  V G′ +  ---- – ---- ( V G′ > 0 )
VP =  2 2

 – PHI ( V G′ ≤ 0 )
Slope Factor
GAMMA a
n = 1 + --------------------------------------------------------
-
2 ⋅ V P + PHI + 4 ⋅ V t
Large Signal Interpolation Function

The EKV MOSFET model is based on the normalized transconductance-to-current characteristic that
can be expressed by a simple and accurate analytical expression:
gms ⋅ V di ⁄ dv 1
G ( i ) = ----------------------t = ---------------- = ------------------------------------
I DS i i + 0.25 + 0.5
Integrating this equation yields the relation:
v = 2 ⋅ y + ln ( y ) with y = i + 0.25 – 0.5

which cannot be inverted analytically. Currently a simplification of this algorithm that avoids Newton-
Raphson iterations is used, leading to a continuous expression for the large signal interpolation func-
tion F(v).
 2
 -------------------------------------------------- ( v ≥ – 0.35 )
z 0 =  1.3 + v – ln ( v + 1.6 )
 1.55 + exp ( – v ) ( – 15 ≤ v < – 0.35 )

2 + z0
z 1 = ---------------------------------
-
1 + v + ln ( z 0 )
 1 + v + ln ( z )
 ---------------------------------
1
- ( v > – 15 )
 2 + z1
y = 
 -----------------------------
1
 2 + exp ( – v )- ( v ≤ – 15 )

F(v) = y ⋅ (1 + y)
Forward Normalized Current

V P – VS
i f = F  --------------------
 Vt 
Drain-to-Source Saturation Voltage for Reverse Normalized Current
1 Vt  VC
--- + ------- ⋅ i f – --- ⋅ ln ( i f ) – --- + V t ⋅ ln  ------------- – 0.6
3 1
V′ DSS = V C ⋅
4 V C
 4  2  2 ⋅ V t

where
V C = UCRIT ⋅ NS ⋅ L eff
Reverse Normalized Current
 V P – V ds – V S – V′ DSS + ∆V + ( V ds – V′ DSS ) + ∆V 
2 2 2 2
i′ r = F  --------------------------------------------------------------------------------------------------------------------------------------------------
 Vt 
where:
VD – VS
V ds = --------------------
-
2
and:
V DSS
∆V = 4 ⋅ V t ⋅ ------ + LAMBDA ⋅  i f – ------------
1
-
64  Vt 
1 Vt 1
V DSS = V C ⋅ --- + ------- ⋅ i f – ---
4 VC 2
The variable VDSS used in this formulation corresponds approximately to half the value of the actual
saturation voltage. However, the related output variable is estimated with a different expression
which gives more realistic values in weak inversion region.
Equivalent Channel Length

1 2 2
L eq = --- ⋅ ( L′ + L′ + L min )
2
where:
L min = NS ⋅ L eff ⁄ 10
and:
V ds + V ip
L′ = NS ⋅ L eff – ∆L + -----------------------
-
UCRIT
2 2 2 2
V ip = V DSS + ∆V – ( V ds – V DSS ) + ∆V
ε si
LC = ------------- ⋅ XJ
COX
V ds – V ip 
∆L = LAMBDA ⋅ L C ⋅ ln  1 + --------------------------------
-
 L C ⋅ UCRIT
Transconductance Factor
β′ 0
β = ------------------------------------------------------------------------
COX
1 + ------------------ ⋅ V t ⋅ q B + η ⋅ q I
E 0 ⋅ ε si
where:

β′ 0 = β 0 ⋅  1 + ------------------ ⋅ q B 0
COX
 E 0 ⋅ ε si 
NP ⋅ W eff
β 0 = KP a ⋅ -------------------------
L eq
q B 0 = GAMMA a ⋅ PHI
1 ⁄ 2 ( NMOS )
η = 
1 ⁄ 3 ( PMOS )
The normalized depletion and inversion charges ( q B and q I respectively) are defined in the Charge
Equations section above.
For compatibility with EKV model versions prior to v2.6, the former mobility reduction model which
uses the parameter THETA is also available as an option. When THETA is given and E0 is not given,
the simpler expression is used:
β0
β = ---------------------------------------------
-
1 + THETA ⋅ V′ P
where:
1 2 2
V′ P = --- ⋅ ( V P + V P + 2 ⋅ V t )
2
Impact Ionization Current

This effect was not taken into account in versions prior to 2.3. The impact ionization current flows
from Drain (or Source is Vds < 0.0) to the Bulk for a N-type MOS transistor and is expressed by:
V ib = V D – V S – IBN ⋅ 2 ⋅ V DSS
 – IBB ⋅ L C
- ⋅ V ib ⋅ exp  --------------------------
IBA
 I DS ⋅ ----------
IBB  V ib 
( V ib > 0 )
I DB = 
 0 ( V ib ≤ 0 )

IIRAT model parameter leads to direct a portion of the substrate current from the drain to the source.
14.5.7: Charge Equations

Both a charge conservative model and a simpler capacitance model are available. The selected model
depends on the value of the parameter XQC. Note that a simplified formulation is used for the reverse
normalized current instead of the expression given in the DC Current Equations section.
Define:
VP – V D
i r = F  ---------------------
 Vt 
1
xf = --- + i f
4
1
xr = --- + i r
4

and:
GAMMA a
n q = 1 + -----------------------------------------------------
-
–6
2 ⋅ V P + PHI + 10
Intrinsic Node Charges (XQC=0)

The expression for the total charge of the Drain, Source, Gate, and Bulk nodes can be expressed by:
Q ( D, S, G, B ) = C ox ⋅ V t ⋅ q ( D, S, G, B )
where:
C ox = COX ⋅ NP ⋅ W eff ⋅ NS ⋅ L eff
and q ( D, S, G, B ) are the normalized intrinsic node charges defined as follows.
 4 3 ⋅ x r + 6 ⋅ xr ⋅ x f + 4 ⋅ x r ⋅ x f + 2 ⋅ x f 1
3 2 2 3
q D = – n q ⋅  ------ ⋅ -------------------------------------------------------------------------------------------------
- – ---
 15 2
2
( xf + xr )
3 2 2 3
 4 3 ⋅ x f + 6 ⋅ x f ⋅ xr + 4 ⋅ x f ⋅ x r + 2 ⋅ xr 1
q S = – n q ⋅  ------ ⋅ -------------------------------------------------------------------------------------------------
- – ---
 15 2
2
( xf + xr )
  GAMMA ⋅ V + PHI + 10 –6 n q – 1

P
- –  --------------
 –  -------------------------------------------------------------------------------
a
- ⋅q ( V′ G > 0 )
  Vt   nq  I
qB = 
 V′ G
 –  --------- ( V′ G ≤ 0 )
 Vt
q G = – qI – q B
The normalized inversion charge is given by the equation:
 4 x f + x f ⋅ x r + xr 
2 2
q I = q S + q D = – n q ⋅  --- ⋅ ------------------------------------------ – 1
3 x f + xr 
Intrinsic Capacitances (XQC=1)

A simplified capacitance model is obtained by neglecting the slight bias dependence of the slope factor
n, resulting in the following expressions for the 5 total intrinsic capacitances:
C ( gs, gd, gb, sb, db ) = C ox ⋅ c ( gs, gd, gb, sb, db )
where
2  x r + x r + x f ⁄ 2
2
c gs = --- ⋅  1 – ------------------------------------
-
3  (x + x )
2

f r
2  x f + x f + x r ⁄ 2
2
c gd = --- ⋅  1 – ------------------------------------
-
3  (x + x ) 
2
f r

nq – 1
c gb = --------------- ⋅ ( 1 – c gs – c gd )
nq
c sb = ( n q – 1 ) ⋅ c gs
c db = ( n q – 1 ) ⋅ c gd
9
This model is suitable for High Frequency analysis ( f > 10 GHz).
14.5.8: Noise Model Equations

Thermal Noise
A new expression has been implemented which is valid in all regions of operation, including for small
Vds:
S thermal = 4 kT ⋅ β ⋅ q I
Flicker Noise
The expression is similar to the standard NLEV=2 flicker noise model:
2
KF ⋅ g m
S flicker = -----------------------------------------------------------------------------------
AF
-
NP ⋅ W eff ⋅ NS ⋅ L eff ⋅ COX ⋅ f

14.6: Berkeley BSIM3v3 MOSFET Model

14.6.1: Introduction
BSIM3v3 is the industry-standard, physics-based, deep-submicron MOSFET model for digital and
analog circuit designs from the Device Group at the University of California at Berkeley.

The foundation of the BSIM3 model is a coherent pseudo 2-D approach. Major short-channel effects
and high-field effects such as threshold voltage reduction, effects due to non-uniform doping in direc-
tions perpendicular or parallel to the surface, mobility reduction due to vertical field, carrier velocity
saturation, channel length modulation, drain induced barrier lowering (DIBL), substrate current
induced body effects (SCBE), subthreshold conduction, parasitic resistance effects, and LDD effects
are included.
Care has been taken to retain the physical functional forms while improving model accuracy and com-
putational efficiency. Model equations have been formed to simplify parameter extraction. The param-
eter set is small. Every parameter has physical meaning, and the effects of the parameters are
predictable. This feature makes it feasible to perform a statistical study of the impact of fabrication
processes on device characteristics. Drain current and its first derivative in all operating regions, and
the boundaries between regions are continuous, and convergence in circuit simulation is easy to
obtain.
Control Parameters
Parameter Description Default
MOBMOD Mobility model selector 1
CAPMOD Flag for the short channel capacitance model
NQSMOD Flag for NQS model
BINUNIT Bin unit selector 1
All binnable model parameters are internally calculated using the same expression:
PL PW PP
P = P 0 + -------- - + --------------------------
- + ---------- -
L eff W eff L eff × W eff
As an example, for the parameter K1: P0=K1, PL=LK1, PW=WK1, Pp=PK1.

If BINUNIT=1, the values of Leff and Weff used in the binning equation above are in microns.
Otherwise, they are in meters. For a device with Leff=0.5µm and Weff=10 µm : if BINUNIT=1, the
parameter values for VSAT, LVSAT, WVSAT and PVSAT are lE5, lE4, 2E4 and 3E4, respectively.
Therefore, the effective value of VSAT for this device is:
Vsat = lE5 + lE4/0.5 + 2E4/10 + 3E4/(0.5 * 10) = 1.28E5
To get the same effective value of VSAT for BINUNIT=0, the values of VSAT, LVSAT, WVSAT and
PVSAT would be lE5, lE-2, 2E-2 and 3E-8, respectively. Thus,
Vsat = lE5 + lE-2/0.5E6 + 2E-2/10e-6 + 3E-8/(0.5E-6 * 10E-6) = 1.28E5
The parameters used in dW and dL equations cannot be binned.
If the model parameter BINFLAG is specified with a value greater than 0.9 and LREF, WREF are set
to non-zero values, parameter values are then interpolated as:

P = P 0 + P L ⋅  --------- – ----------------------- + P W ⋅  ----------- – ------------------------- + P P ⋅  --------- – ----------------------- ⋅  ----------- – -------------------------

1 1 1 1 1 1 1 1
 L eff LREF eff  W eff WREF eff  L eff LREF eff  W eff WREF eff
The effective values of LREF and WREF are computed in a manner consistent with the effective
channel width and length (XW and XL are replaced by XWREF and XLREF, respectively).
DC Parameters
VTH0 Threshold voltage @Vbs=0 for large L V 0.7 (NMOS)

-0.7 (PMOS)
VFB Flat-band voltage V
DELVTO Zero-bias threshold voltage shift V 0.0
K1 First-order body effect coefficient 1⁄2 0.53

V
K2 Second-order body effect coefficient - -0.0186
K3 Narrow width coefficient - 80.0
K3B Body effect coefficient of K3 V

–1 0.0
W0 Narrow width parameter m 2.5E-6
NLX Lateral non-uniform doping coefficient m 1.74E-7
DVT0W First coefficient of narrow width effect on Vth at - 0

small L
DVT1W Second coefficient of narrow width effect on Vth m

–1 5.3E6
at small L
DVT2W Body-bias coefficient of narrow width effect on V

–1 -0.032
Vth at small L
DVT0 First coefficient of short-channel effect on Vth - 2.2
DVT1 Second coefficient of short-channel effect on Vth - 0.53
DVT2 Body-bias coefficient of short-channel effect on V

–1 -0.032
Vth
VBM Maximum applied body bias in Vth calculation V
U0 Mobility at nominal temperature cm ⋅ V

2 –1
⋅s
–1 670 (NMOS)
250 (PMOS)
UA First-order mobility degradation coefficient m⋅V

–1 2.25E-9
UB Second-order mobility degradation coefficient m ⋅V

2 –2 5.87E-19

UC Body-effect of mobility degradation coefficient m⋅V

–2 -4.65E-11
MOBMOD=1,2
–1 -0.0465
V
MOBMOD=3
VSAT Saturation velocity at nominal temperature m⋅s

–1 8.0E4
A0 Bulk charge effect coefficient for channel length - 1.0
AGS Gate bias coefficient of the Abulk V

–1 0.0
B0 Bulk charge effect coefficient for channel width m 0.0
B1 Bulk charge effect width offset m 0.0
KETA Body-bias coefficient of the bulk charge effect V

–1 -0.047
A1 First non-saturation factor V

–1 0.0
A2 Second non-saturation factor - 1.0
RDSW Width coefficient of parasitic resistance Ω ⋅ µm

WR 0.0
PRWG Gate bias coefficient of RDSW V

–1 0.0
PRWB Body effect coefficient of RDSW –1 ⁄ 2 0.0

V
WR Width offset from Weff for Rds calculation - 1.0
WINT Width offset fitting parameter from I-V without m 0.0

bias
LINT Length offset fitting parameter from I-V without m 0.0

bias
DWG Coefficient of Weff’s gate dependence m⋅V

–1 0.0
DWB Coefficient of Weff’s substrate body bias depen- –1 ⁄ 2 0.0

m⋅V
dence
VOFF Offset voltage in the subthreshold region at V -0.08

large W and L
NFACTOR Subthreshold swing factor - 1.0
ETA0 DIBL coefficient in subthreshold region - 0.08
ETAB Body-bias coefficient for the subthreshold DIBL V

–1 -0.07
effect
DSUB DIBL coefficient exponent in subthreshold - DROUT

region
CIT Interface trap capacitance F⋅m

–2 0.0

CDSC Drain/Source to channel coupling capacitance F⋅m

–2 2.4E-4
CDSCD Drain-bias sensitivity of CDSC –1 –2 0.0

F⋅V ⋅m
CDSCB Body-bias sensitivity of CDSC –1 –2 0.0

F⋅V ⋅m
PCLM Channel length modulation parameter - 1.3
PDIBLC1 First output resistance DIBL effect correction - 0.39

parameter
PDIBLC2 Second output resistance DIBL effect correction - 0.0086

parameter
PDIBLCB Body effect coefficient of DIBL correction param- V

–1 0.0
eters
DROUT L dependence coefficient of the DIBL correction - 0.56

parameter in ROUT
PSCBE1 First substrate current body-effect parameter V⋅m

–1 4.24E8
PSCBE2 Second substrate current body-effect parameter m⋅V

–1 1.0E-5
PVAG Gate dependence of Early voltage - 0.0
DELTA Effective Vds parameter V 0.01
ALPHA0 First impact ionization current parameter m⋅V

–1 0.0
ALPHA1 Impact ionization current parameter for length V

–1 0.0
scaling (introduced in version 3.2 but supported
in all versions in SmartSpice)
BETA0 Second impact ionization current parameter V 30
NGATE Poly gate doping concentration (a zero value cm

–3 0.0
means infinity)
(Note 5)
AC and Capacitance Parameters

The following parameters: CIT, CDSC, CDSCD, CDSCB, PCLM, PDIBLC1, PDIBLC2, PDIBLCB,
DROUT, PSCBE1 and PBSCE2 are common to DC and AC equations. They are described in the pre-
ceding table.
Only model parameters specific to AC equations are listed below. These model parameters are used in
Intrinsic and Extrinsic Capacitance Models.

XPART Charge partitioning rate flag - 0
CGSO Non-LDD region source-gate overlap capacitance F⋅m

–1
per unit channel length
CGD0 Non-LDD region drain-gate overlap capacitance F⋅m

–1
per unit channel length
CGB0 Gate bulk overlap capacitance per unit channel F⋅m

–1
length
CGSL Light doped source-gate region overlap capaci- F⋅m

–1 0.0
tance
CGDL Light doped drain-gate region overlap capacitance F⋅m

–1 0.0
CKAPPA Coefficient for lightly doped region overlap capaci- F⋅m

–1 0.6
tance
CF Fringing field capacitance F⋅m

–1
CLC Constant term for the short channel model m 0.1E-6
CLE Exponential term for the short channel model - 0.6
DLC Length offset fitting parameter from C-V m LINT
DWC Width offset fitting parameter from C-V m WINT
VFBCV Flat-band voltage parameter V -1
NOFF CV parameter in Vgsteff, CV for weak to strong - 1.0

inversion
VOFFCV CV parameter in Vgsteff, CV for week to strong V 0.0

inversion
ACDE Exponential coefficient for charge thickness in m⋅V

–1 1.0
CAPMOD=3 for accumulation and depletion
regions
MOIN Coefficient for the gate-bias dependent surface V 15.0

potential

MOS Diode and Access Resistance Model Parameters
RSH Source/Drain sheet resistance in ohms per square Ω ⋅ sq

–1 0.0
JS Bottom junction saturation current per unit area A⋅m

–2 1.E-4
JSW Side wall junction saturation current density per unit A⋅m
–1 0.0
length
IJTH Diode limiting current A 0.1
NJ Emission coefficient of junction - 1.0
CJ Bottom junction capacitance per unit area at zero-bias F⋅m

–2 5.0E-4
MJ Bottom junction capacitance grading coefficient - 0.5
PB Bottom junction built-in potential V 1.0
CJSW Sidewall junction capacitance per unit length at zero- F⋅m

–1 5.0E-10
bias
MJSW Sidewall junction capacitance grading coefficient - 0.33
PBSW Sidewall junction built-in potential V 1.0
CJSWG Gate sidewall junction capacitance per unit length at F⋅m

–1 CJSW
zero-bias
MJSWG Gate sidewall junction capacitance grading coefficient - MJSW
PBSWG Gate sidewall junction built-in potential V PBSW
METO Fringing factor m 0
RD Drain ohmic resistance Ω 0
RS Source ohmic resistance Ω 0
RDC Drain contact resistance Ω 0
RSC Source contact resistance Ω 0
IS Bulk junction saturation current A 1e-14
N Bulk diode emission coefficient - 1
NDS Reverse bias slope factor‘- 1 1.0
VNDS Reverse slope transition voltage V -1.0
LD Lateral diffusion for length m
WD Lateral diffusion for width m 0

LDIF Lateral diffusion beyond the gate m 0
HDIF Heavily doped diffusion length m 0
X Masking and etching effects on L m 0
XW Masking and etching effects on W m 0
LMLT Length multiplier - 1.0
WMLT Width multiplier - 1.0
SCALM Model parameter scaling factor - 1.0
FC Coefficient for the forward-bias depletion junction capac- - 0.5

itance formula
CJGATE Gate edge capacitance F⋅m

–1 CJSW
CBD Total zero bias B-D junction capacitance F 0
CBS Total zero bias B-S junction capacitance F 0
BULK Substrate node name String “0”
NQS Model Parameters
ELM Elmore constant of the channel - 5
Temperature Effect Parameters
TNOM Temperature at which parameters are extracted o

C 27
PRT Temperature coefficient for RDSW Ω ⋅ µm 0
UTE Mobility temperature exponent - -1.5
KT1 Temperature coefficient for threshold voltage V -0.11
KT1L Channel length sensitivity of temperature coeffi- V⋅m 0.0

cient for threshold voltage
KT2 Body-bias coefficient of the Vth temperature effect - 0.022
UA1 Temperature coefficient for UA m⋅V

–1 4.31E-9
UB1 Temperature coefficient for UB m ⋅V

2 –2 -7.61E-18

UC1 Temperature coefficient for UC m⋅V

–2 Mobmod=1,2:
-5.6E-11
–1
Mobmod=3:
V -0.056
AT Temperature coefficient for saturation velocity m⋅s

–1 3.3E4
XTI Junction current temperature exponent coefficient - 3.0
TPB Temperature coefficient of PB V⋅K

–1 0.0
TPBSW Temperature coefficient of PBSW V⋅K

–1 0.0
TPBSWG Temperature coefficient of PBSWG K

–1 0.0
TCJSW Temperature coefficient of CJSW K

–1 0.0
TCJSWG Temperature coefficient of CJSWG K

–1 0.0
TCJ Bottom junction capacitance temperature coeffi- K

–1 0.0
cient
TVJ Bottom junction potential temperature coefficient V⋅K

–1 0.0
TMJ1 Linear MJ temperature coefficient K

–1 0.0
TMJ2 Parabolic MJ temperature coefficient K

–2 0.0
TCJSW Sidewall junction capacitance temperature coeffi- K

–1 0.0
cient
TVJSW Sidewall junction potential temperature coefficient V⋅K

–1 0.0
TMJSW1 Linear MJSW temperature coefficient K

–1 0.0
TMJSW2 Parabolic MJSW temperature coefficient K

–2 0.0
TTT1 Linear TT temperature coefficient K

–1 0.0
TTT2 Parabolic TT temperature coefficient K

–2 0.0
TRD1 Linear temperature coefficient for drain resistance K

–1 0.0
TRD2 Parabolic temperature coefficient for drain resis- K

–2 0.0
tance
TRS1 Linear temperature coefficient for source resistance K

–1 0.0
TRS2 Parabolic temperature coefficient for source resis- K

–2 0.0
tance

EG Energy gap at 300 K eV 1.16
GAP1 First bandgap correction factor eV ⋅ K

–1 7.02e-4
GAP2 Second bandgap correction factor K 1108
W and L Parameters
WL Coefficient of length dependence for width offset m

WLN 0.0
WLN Power of length dependence of width offset - 1.0
WW Coefficient of width dependence for width offset m

WWN 0.0
WWN Power of width dependence of width offset - 1.0
WWL Coefficient of length and width cross term for width m

WWN + WLN 0.0
offset
LL Coefficient of length dependence for length offset m

LLN 0.0
LLN Power of length dependence for length offset - 1.0
LW Coefficient of width dependence for length offset m

LWN 0.0
LWN Power of width dependence for length offset - 1.0
LWL Coefficient of length and width cross term for m

LWN + LLN 0.0
length offset
LLC Coefficient of length dependence for CV channel m

LLN LL
length offset (version 3.2)
LWC Coefficient of width dependence for CV channel m

LWN LW
length offset (version 3.2)
LWLC Coefficient of length and width dependence for CV m

LWN + LLN LWL
channel length offset (version 3.2)
WLC Coefficient of length dependence for CV channel m

WLN WL
width offset (version 3.2)
WWC Coefficient of width dependence for CV channel m

WWN WW
width offset (version 3.2)
WWLC Coefficient of length and width dependence for CV m

WWN + WLN WWL
channel width offset (version 3.2)
WREF Reference channel width m 0.0

LREF Reference channel length m 0.0
XWREF Difference between physical and drawn reference m 0.0

width
XLREF Difference between physical and drawn reference m 0.0

length
Bound Parameters
LMIN Minimum channel length m 0.0
LMAX Maximum channel length m 1.0
WMIN Minimum channel width m 0.0
WMAX Maximum channel width m 1.0
TMIN Minimum temperature °C -273.15
TMAX Maximum temperature °C -273.15
Process Parameters
COX Gate oxide capacitance F⋅m

–2
TOX Gate oxide thickness m 1.5E-8
TOXM Gate oxide thickness at which parameters are m TOX

extracted
XJ Junction depth m 1.5E-7
GAMMA1 Body-effect coefficient near the surface 1⁄2

V
GAMMA2 Body-effect coefficient in the bulk 1⁄2

V
NCH Channel doping concentration cm

–3 1.7E17
NSUB Substrate doping concentration cm

–3 6.0E16
VBX Vbs at which the depletion width equals XT V
XT Doping depth m 1.55E-7

14.6.3: Effective Channel Length and Width

Define
L scaled = L ⋅ SCALE + XL ⋅ SCALM
W scaled = W ⋅ SCALE + XW ⋅ SCALM
A
W eff = W ⋅ SCALE ⋅ WMLT + XW ⋅ SCALM (for ACM equations)
IV Model
Bias-Independent Quantities:
L eff = L ⋅ SCALE ⋅ LMLT + XL ⋅ SCALM – 2 ⋅ dL
A
W′ eff = W eff – 2 ⋅ dW′
where
WL WW WWL
dW′ = WINT + -----------------
WLN
+ ------------------
WWN
- + -----------------------------------------
WWN
-
WLN
L scaled W scaled L scaled ⋅ W scaled
LL LW LWL
dL = LINT + ----------------
LLN LWN
- + -----------------------------------------
- + ------------------ LLN LWN
-
Bias-Dependent Effective Channel Width (for Vdsat, Vasat, Vdseff, and Idso equations):
W eff = W′ eff – 2 ⋅ ( DWG ⋅ Vgsteff + DWB ⋅ ( φ s – V bseff – φ s ) )
CV Model
L active = L ⋅ SCALE ⋅ LMLT + XL ⋅ SCALM – 2 ⋅ δL eff
A
W active = W eff – 2 ⋅ δW eff
where
WL WW WWL
δW eff = DWC + ----------------
WLN
- + ------------------
WWN
- + -----------------------------------------
WWN
-
WLN
LL LW LWL
δL eff = DLC + ----------------
LLN
- + ------------------
LWN
- + -----------------------------------------
LLN LWN
-
14.6.4: Temperature Equations

Define
T
T ratio = --------------------
TNOM
where T is the instance temperature and TNOM is a model parameter corresponding to the
temperature at which model parameters have been extracted,
kB ⋅ T k B ⋅ TNOM
V t = --------------
- and V tnom = ------------------------------
-
q q

as the thermal voltage at device and nominal temperature, respectively.
Model parameter temperature scaling

In order to account for temperature effects, several model parameters are temperature-scaled:
VTH 0 ( T ) = VTH 0 ⋅  KT 1 + KT 1 L ⋅ --------- + KT 2 ⋅ V bseff ⋅ ( T ratio – 1 )

L
 L eff 
UTE
U 0 ( T ) = U 0 ⋅ ( T ratio )
VSAT ( T ) = VSAT – AT ⋅ ( T ratio – 1 )
RDSW ( T ) = RDSW + PRT ⋅ ( T ratio – 1 )
UA ( T ) = UA + UA 1 ⋅ ( T ratio – 1 )
UB ( T ) = UB + UB 1 ⋅ ( T ratio – 1 )
UC ( T ) = UC + UC 1 ⋅ ( T ratio – 1 )
14.6.5: I-V Model Equations

Threshold Voltage
V th = VTH 0 – K 1 ⋅ Φ s + K 1 ox ⋅ φ s – V bseff – K 2 ox ⋅ V bseff
+ K 1 ox ⋅  1 + ------------- – 1 ⋅ φ s + ( K 3 + K 3 b ⋅ V bseff ) ⋅ ---------------------------- ⋅ φ s

NLX TOX
 L eff  W′ eff + W 0
L eff L eff
– DVT 0 ⋅  exp  – D VT 1 ⋅ --------- + 2 ⋅ exp  – D VT 1 ⋅ ---------  ⋅ ( V bi – φ s )
  2 lt   lt  
L eff L eff
–  exp  – DSUB ⋅ --------- + 2 ⋅ exp  – DSUB ⋅ ---------  ⋅ ( ETA 0 + ETAB ⋅ V bseff ) ⋅ V ds
  2 l t 0  lt 0  
L ⋅ W L eff ⋅ W eff
– DVT 0 W ⋅  exp  – D VT 1 W ⋅ ------------------------- + 2 ⋅ exp  – D VT 1 W ⋅ -------------------------  ⋅ ( V bi – φ s )
eff eff
  2 l tw   l tw 
where
ε si ⋅ X dep
lt = ---------------------- ⋅ ( 1 + DVT 2 ⋅ V bseff )
COX
ε si ⋅ X dep
l tw = ---------------------- ⋅ ( 1 + DVT 2 W ⋅ V bseff )
COX
2 ⋅ ε si ⋅ ( φ s – V bseff )
X dep = -------------------------------------------------
q ⋅ NCH
ε si ⋅ X dep 0
lt0 = ------------------------
-
COX
2 ⋅ ε si ⋅ φ s
X dep 0 = -----------------------
q ⋅ NCH
2
V bseff = V bc + 0.5 ⋅ [ V bs – V bc – δ 1 + ( V bs – V bc – δ 1 ) – ( 4 ⋅ δ 1 ⋅ V bc ) ]

δ 1 = 0.001
In version 3.0, V bc is computed as follows:
 K1 
2
V bc = 0.9 ⋅  φ s – -----------------2 if K2 > 0, otherwise V bc = – 10
 4 ⋅ K2 
In version 3.1 and 3.2, it is computed as follows:
 K1 
2
V bc = 0.9 ⋅  φ s – -----------------2 if K2 < 0, otherwise V bc = – 30
 4 ⋅ K2 
In version 3.2, the following intermediate variables are computed to account for TOXM:
TOX TOX
K 1 ox = K 1 ⋅ ------------------- and K 2 ox = K 2 ⋅ -------------------
TOXM TOXM
The expressions of V bi and φ s are given in the paragraph related to temperature dependence.
Effective Vgs - Vth

V gs – V th
2 ⋅ n ⋅ V t ⋅ ln 1 + exp  ------------------------
 2 ⋅ n ⋅ Vt 
V gsteff = ----------------------------------------------------------------------------------------------------------------------------------------------------------------
2 ⋅ φs V gs – V th – 2 ⋅ VOFF
1 + 2 ⋅ n ⋅ COX ⋅ -------------------------------- - ⋅ exp  – ------------------------------------------------------ -
q ⋅ ε si ⋅ NCH  2 ⋅ n ⋅ Vt 
Cd
n = 1 + NFACTOR ⋅ -------------
COX
L eff L eff
( CDSC + CDSCD ⋅ V ds + CDSCB ⋅ V bseff ) ⋅  exp  – D VT 1 ⋅ ----------- + 2 exp  – DVT 1 ⋅ --------- 
  2 ⋅ lt   lt  
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
COX
CIT
+ -------------
COX
ε si
C d = -----------
-
X dep
Mobility
MOBMOD = 1
U0
µ eff = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
V gsteff + 2 ⋅ V th V gsteff + 2 ⋅ V th
1 + ( UA + UC ⋅ V bseff ) ⋅  --------------------------------------- + UB ⋅  ---------------------------------------
 TOX   TOX 
MOBMOD = 2
U0
µ eff = -----------------------------------------------------------------------------------------------------------------------------------2
V gsteff V gsteff
1 + ( UA + UC ⋅ V bseff ) ⋅  ---------------- + UB ⋅  ----------------

MOBMOD = 3
U0
µ eff = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
 V gsteff + 2 V th  V gsteff + 2 V th 2
1 + UA ⋅ ----------------------------------- + UB ⋅ ----------------------------------- ⋅ ( 1 + UC ⋅ V bseff )
Drain Saturation Voltage

For Rds > 0 or λ ≠ 1
2
–b – b – 4 ⋅ a ⋅ c
V dsat = ----------------------------------------------
2⋅a
a = A bulk ⋅ W eff ⋅ VSAT ⋅ C OX ⋅ R ds +  --- – 1 ⋅ A bulk

2 1
λ 
b = –  ( V gsteff + 2 ⋅ V t ) ⋅  --- – 1 + A bulk ⋅ E sat ⋅ L eff

2
 λ 
+ 3 ⋅ A bulk ⋅ ( V gsteff + 2 ⋅ V t ) ⋅ W eff ⋅ VSAT ⋅ COX ⋅ Rds


2
c = ( V gsteff + 2 ⋅ V t ) ⋅ E sat ⋅ L eff + 2 ⋅ ( V gsteff + 2 ⋅ V t ) ⋅ W eff ⋅ VSAT ⋅ COX ⋅ R ds
λ = A 1 ⋅ V gsteff + A 2
For Rds = 0, λ = 1
E sat ⋅ L eff ⋅ ( V gsteff + 2 ⋅ V t )

V dsat = -------------------------------------------------------------------------------------------
-
A bulk ⋅ E sat ⋅ L eff + ( V gsteff + 2 ⋅ V t )
 K1  A 0 ⋅ L eff
A bulk =  1 + -------------------------------------- ⋅  ----------------------------------------------------
 2 ⋅ φ s – V bseff  L eff + 2 ⋅ XJ ⋅ X dep
  
2
L eff B0 1
⋅ 1 – AGS ⋅ V gsteff ⋅  ---------------------------------------------------- + -------------------------  ⋅ -----------------------------------------------
 L eff + 2 ⋅ XJ ⋅ X dep W eff + B 1  1 + KETA ⋅ V bseff
2 ⋅ VSAT
E sat = -------------------------
µ eff
Effective Vds
1 2
V dseff = V dsat – --- ⋅ ( V dsat – V ds – DELTA + ( V dsat – V ds – DELTA ) + 4 ⋅ DELTA ⋅ V dsat )
2
Drain Current
I dso V ds – V dseff  V ds – V dseff
I ds = --------------------------------- ⋅  1 + -----------------------------
- ⋅  1 + -----------------------------
-
R ds ⋅ I dso VA V ASCBE 
1 + -----------------------
V dseff
V dseff
W eff ⋅ µ eff ⋅ COX ⋅ V gsteff ⋅  1 – A bulk ⋅ ------------------------------------------------- ⋅ V dseff
 2 ⋅ ( V gsteff + 2 ⋅ V t )
I dso = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L eff ⋅ [ 1 + V dseff ⁄ ( E sat ⋅ L eff ) ]

PVAG ⋅ V gsteff  1 –1
V A = V Asat +  1 + --------------------------------------- ⋅ ------------------ + -----------------------
1
 E sat ⋅ L eff   V ACLM V ADIBLC
A bulk ⋅ E sat ⋅ L eff + V gsteff

V ACLM = -------------------------------------------------------------------- ⋅ ( V ds – V dseff )
PCLM ⋅ Ab bulk ⋅ E sat ⋅ l itl
( V gsteff + 2 ⋅ V t ) A bulk ⋅ V dsat

V ADIBLC = --------------------------------------------------------------------------------- ⋅  1 – ---------------------------------------------------------------------------
-
θ rout ⋅ ( 1 + PDIBLCB ⋅ Vbseff )  A bulk ⋅ V dsat + V gsteff + 2 ⋅ V t
L eff L eff
θ rout = PDIBLC 1 ⋅ exp  – DROUT ⋅ ------------- + 2 ⋅ exp  – DROUT ⋅ --------- + PDIBLC 2
 2 ⋅ l t 0  lt 0 
– PSCBE 1 ⋅ l itl
-------------------- = ------------------------- ⋅ exp  ----------------------------------------
1 PSCBE 2
V ASCBE L eff  V ds – V dseff 
A bulk ⋅ V dsat
E sat ⋅ L eff + V dsat + 2 ⋅ R ds ⋅ VSAT ⋅ C OX ⋅ W eff ⋅ V gsteff ⋅ 1 – ------------------------------------------------ -
2 ⋅ ( V gsteff + 2 ⋅ V t )
V Asat = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
2 ⁄ λ – 1 + R ds ⋅ VSAT ⋅ C OX ⋅ W eff ⋅ A bulk
ε si ⋅ TOX ⋅ XJ
l itl = -------------------------------------
ε ox
Substrate Current
I dso V ds – V dseff
I sub =  -------------------------- + ALPHA 1 ⋅ ( V ds – V dseff ) ⋅ exp  – ------------------------------ ⋅ --------------------------------- ⋅  1 + -----------------------------
ALPHA 0 BETA 0
-
 L eff   V ds – V dseff R ds ⋅ I dso  VA 
1 + -----------------------
V dseff
Polysilicon Depletion Effect

1 q ⋅ N GATE ⋅ X poly 2
V poly = --- ⋅ X poly ⋅ E poly = -------------------------------------------------
2 2 ⋅ ε si
ε ox ⋅ E ox = ε si ⋅ E poly = 2 ⋅ q ⋅ ε si ⋅ N GATE ⋅ V poly
V gs – V FB – φ s = V poly + V ox
ε ox
2
2
- ⋅ ( V gs – V FB – φ s – V poly ) – V poly = 0
---------------------------------------------------------------------
2 ⋅ q ⋅ ε si ⋅ N GATE ⋅ TOX 2
q ⋅ ε si ⋅ N GATE ⋅ TOX 2  2 ⋅ ε ox 2 ⋅ (V
gs – V FB – φ s ) 
V gseff = V FB + φ s + -------------------------------------------------------------- ⋅  1 + -------------------------------------------------------------- – 1
ε ox
2
 q ⋅ ε si ⋅ N GATE ⋅ TOX 2

Drain/Source Resistance
RDSW ⋅ [ 1 + PRWG ⋅ V gsteff + PRWB ⋅ ( φ s – V bseff – φ s ) ]
Rds = ----------------------------------------------------------------------------------------------------------------------------------------------------------------
WR
-
6
( 10 ⋅ W′ eff )

14.6.6: Capacitance Model Equations

Overlap Capacitances
The following expressions corespond to a NMOS device.
• Source Overlap Charge
CAPMOD=0
Q overlap, s
------------------------- = ( CGSO + CF ) ⋅ V gs
W active
CAPMOD=1
if (Vgs < 0)
Q overlap, s CKAPPA ⋅ CGSL 4 ⋅ V gs

------------------------- = ( CGSO + CF ) ⋅ V gs – ------------------------------------------------- ⋅  1 – --------------------------
- – 1
W active 2  CKAPPA 
else
Q overlap, s
------------------------- = ( CGSO + CF + CKAPPA ⋅ CGSL ) ⋅ V gs
W active
CAPMOD=2
1  2 
V gs, overlap = --- ⋅  ( V gs + δ ) – ( V gs + δ ) + 4 ⋅ δ  where δ = 0.02
2  
Q overlap, s  4 ⋅ V gs, overlap 

------------------------- = ( CGSO + CF ) ⋅ V gs + CGSL ⋅  V gs – V gs, overlap – --------------------------- ⋅  1 – ----------------------------------
- – 1 
CKAPPA
W active 2  CKAPPA 
 
• Drain Overlap Charge
Q overlap, d
The expresssion of ------------------------- can be easily obtained from the preceding equations by replacing Vgs,
W active
CGSO and CGSL, by Vgd, CGDO and CGDL, respectively.
• Gate Overlap Charge
Q overlap, g = – ( Q overlap, s + Q overlap, d )
Instrinsic Charges
CAPMOD=0
• Accumulation region (Vgs < VFBCV + Vbs)
Q g = W active ⋅ L active ⋅ COX ⋅ ( V gs – V bs – VFBCV )
Q sub = – Q g
Q inv = 0
• Subthreshold region (Vgs < Vth)

K1  4 ⋅ ( V gs – V bs – VFBCV )
2
Q b = – W active ⋅ L active ⋅ COX ⋅ ---------- ⋅  – 1 + 1 + ----------------------------------------------------------------
-
2  K1
2

Qg = –Qb
Q inv = 0
• Strong inversion region (Vgs > Vth)
V gs – V th
V dsat, cv = -----------------------
-
A′ bulk
CLC CLE
A′ bulk = A bulk 0 ⋅  1 +  -------------
  L eff  
 K1  A 0 ⋅ L eff B0  1
A bulk 0 =  1 + -------------------------------------- ⋅  ---------------------------------------------------
- + ---------------------------  ⋅ -----------------------------------------
 2 ⋅ φ s – V bseff  L eff + 2 ⋅ XJ ⋅ X dep W′ eff + B 1  1 + KETA ⋅ V bs
V th = VFBCV + φ s + K 1 ⋅ φ s – V bseff
(i) 50/50 Charge partition

if Vds < Vdsat
2
V ds A′ bulk ⋅ V ds
Q g = W active ⋅ L active ⋅ C OX ⋅ V gs – VFBCV – φ s – --------
- + ---------------------------------------------------------------------------
-
2
 A′ bulk ⋅ V ds
12 ⋅ V gs – V th – -----------------------------
 2 
2
A′ bulk ⋅ V ds A′ bulk ⋅ V ds
2
Q inv = – W active ⋅ L active ⋅ C OX ⋅ V gs – V th – ----------------------------- + ---------------------------------------------------------------------------
-
2  A′ bulk 
12 ⋅ V gs – V th – ---------------
- ⋅V
 2 ds
2
( 1 – A′ bulk ) ⋅ V ds ( 1 – A′ bulk ) ⋅ A′ bulk ⋅ V ds
Q b = W active ⋅ L active ⋅ C OX ⋅ VFBCV – V th + φ s + ------------------------------------------
- + ---------------------------------------------------------------------------
-
2 A′ bulk

12 ⋅ V gs – V th – ---------------- ⋅ V ds 
 2 
Q s = Q d = 0.5 ⋅ Q inv
2
2
= – W active ⋅ L active ⋅ C OX ⋅ V gs – V th – ----------------------------- + ---------------------------------------------------------------------------
-
2  A′ bulk 
12 ⋅ V gs – V th – ---------------- ⋅ V ds
 2 
Otherwise,
V dsat
Q g = W active ⋅ L active ⋅ C OX ⋅  V gs – VFBCV – φ s – -------------
 3 

1
Q s = Q d = – --- ⋅ W active ⋅ L active ⋅ C OX ⋅ ( V gs – V th )
3
( 1 – A′ bulk ) ⋅ V dsat
Q b = – W active ⋅ L active ⋅ COX ⋅  VFBCV + φ s – V th + -----------------------------------------------
-
 3 
(ii) 40/60 channel-charge Partition

if (Vds < Vdsat)
2
- + ---------------------------------------------------------------------------
-
2 A′ bulk ⋅ V ds
12 ⋅  V gs – V th – -----------------------------
 2 
2
2
Q inv = – W active ⋅ L active ⋅ C OX ⋅ V gs – V th – ----------------------------- + ---------------------------------------------------------------------------
-
2 A′ bulk

12 ⋅ V gs – V th – ---------------- ⋅ V ds 
 2 
2
- – ---------------------------------------------------------------------------
-
2 A′ bulk

12 ⋅ V gs – V th – ---------------- ⋅ V ds 
 2 
Q d = – W active ⋅ L active ⋅ C OX
( V gs – V th ) A′ bulk ⋅ V ds ⋅ ( V gs – V th ) ( A′ bulk ⋅ V ds )
2 2
V gs – V th A′ bulk A′ bulk ⋅ V ds ⋅ ------------------------------ - – --------------------------------------------------------------- + -------------------------------------

6 8 40
⋅ ------------------------ – ---------------- ⋅ V ds + ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
2 2 A′ 2
 V – V – --------------- bulk
- ⋅ V ds 
 gs th
2 
Qs = –( Qg + Qb + Qd )
otherwise,
V dsat
 3 
4
Q d = – ------ ⋅ W active ⋅ L active ⋅ C OX ⋅ ( Vgs – V th )
15
Q b = – W active ⋅ L active ⋅ C OX ⋅  VFBCV + φ s – V th + -----------------------------------------------
-
 3 
Qs = –( Qg + Qb + Qd )
(iii) 0/100 Channel-charge Partition

if Vds < Vdsat

2
- + ---------------------------------------------------------------------------
-
2
 A′ bulk ⋅ V ds
12 ⋅ V gs – V th – -----------------------------
 2 
2
2
Q inv = – W active ⋅ L active ⋅ C OX ⋅ V gs – V th – ----------------------------- + ----------------------------------------------------------------------------
2 A′ bulk
12 ⋅  V gs – V th – ---------------- ⋅ V ds
 2 
2
- – ---------------------------------------------------------------------------
-
2 A′ bulk

12 ⋅ V gs – V th – ---------------- ⋅ V ds 
 2 
2
V gs – V th A′ bulk ( A′ bulk ⋅ V ds )
Q d = – W active ⋅ L active ⋅ C OX ⋅ -----------------------
- + ---------------- ⋅ V ds – ---------------------------------------------------------------------------
-
2 4 A′ bulk

24 ⋅ V gs – V th – ---------------- ⋅ V ds 
 2 
Qs = –( Qg + Qb + Qd )
otherwise
V dsat
 3 
Q b = – W active ⋅ L active ⋅ C OX ⋅  VFBCV + φ s – V th + -----------------------------------------------
-
 3 
Qd = 0
Qs = –( Qg + Qb )
CAPMOD=1
Define
V fb = V th – φ s – K 1 ⋅ φ s – V bseff in version 3.0 and 3.1,
and
V fb = V th 0 – φ s – K 1 ox ⋅ φ s – V bseff in version 3.2,
where Vth0 corresponds to the bias-independent threshold voltage.

if Vgs < (Vfb + Vbs + Vgsteffcv)
Q g 1 = – W active ⋅ L active ⋅ C OX ⋅ ( V gs – V fb – V bs – V gsteffcv )
else
K1 
2 4 ⋅ ( V gs – V fb – V gsteffcv – V bs )
Q g 1 = W active ⋅ L active ⋅ C OX ⋅ ---------- ⋅  – 1 + 1 + ------------------------------------------------------------------------------
2  K1
2

Qb 1 = –Qg 1

V gsteffcv
V dsat, cv = --------------------
-
A′ bulk
CLC CLE
A′ bulk = A bulk 0 ⋅  1 +  -------------
  L eff  
 K1  A 0 ⋅ L eff B0  1
A bulk 0 =  1 + ---------------------------- ⋅  ---------------------------------------------------
- + -------------------------  ⋅ -----------------------------------------
 2 φ s – V bs  L eff + 2 ⋅ XJ ⋅ X dep W eff + B 1  1 + KETA ⋅ V bs
In version 3.0 and 3.1,

V gs – V th
V gsteffcv = n ⋅ V t ⋅ ln 1 + exp  ------------------------
 n ⋅ Vt 
In version 3.2, the model parameters NOFF and VOFFCV are supported:
V gs – V th – VOFFCV
V gsteffcv = NOFF ⋅ n ⋅ V t ⋅ ln 1 + exp  ---------------------------------------------------------
 NOFF ⋅ n ⋅ V t 
if Vds <= Vdsat
 2 
 V ds A′ bulk ⋅ V ds 
Q g = Q g 1 + W active ⋅ L active ⋅ C OX ⋅  V gsteffcv – --------- + -------------------------------------------------------------------------
 2 A′ bulk 
 12 ⋅  V gsteffcv – ---------------- ⋅ V ds 
 2 
 2 
 1 – A′ bulk ( 1 – A′ bulk ) ⋅ A′ bulk ⋅ V ds 
Q b = Q b 1 + W active ⋅ L active ⋅ C OX ⋅  ------------------------- ⋅ V – -------------------------------------------------------------------------
 2 A′ bulk 
12 ⋅  V gsteffcv – ---------------- ⋅ V ds 
ds
  2 
(i) 50/50 Channel-charge Partition
 2 
W active ⋅ L active ⋅ C OX  A′ bulk A′ bulk ⋅ V ds 
Q s = Q d = – ----------------------------------------------------------- ⋅  V gsteffcv – ---------------- ⋅ V ds + -------------------------------------------------------------------------
2  2 A′ 
12 ⋅  V gsteffcv – ---------------- ⋅ V ds 
bulk
  2 
(ii) 40/60 channel-charge Partition

W active ⋅ L active ⋅ C OX
Q s = – ------------------------------------------------------------------------2-
A′ bulk
2 ⋅  V gsteffcv – ---------------- ⋅ V ds
 2 
V 3 4
– --- ⋅ V gsteffcv ⋅ A′ bulk ⋅ V ds + --- ⋅ V gsteffcv ⋅ ( A′ bulk ⋅ V ds ) – ------ ⋅ ( A′ bulk ⋅ V ds ) 
2 2 2 2 3
 gsteffcv 3 3 15 
Qd = –( Qg + Qb + Qs )
 
W active ⋅ L active ⋅ C OX 
2
A′ bulk ( A′ bulk ⋅ V ds ) 
Q s = – ----------------------------------------------------------- ⋅  V gsteffcv + ---------------- ⋅ V ds – -------------------------------------------------------------------------
2  2 A′ bulk 
 12 ⋅  V gsteffcv – ---------------- ⋅ V ds 
 2 

Qd = –( Qg + Qb + Qs )
if Vds > Vdsat
V dsat
Q g = Q g 1 + W active ⋅ L active ⋅ C OX ⋅  V gsteffcv – -------------
 3 
( V gsteffcv – V dsat )
Q b = Q b 1 – W active ⋅ L active ⋅ C OX ⋅ ----------------------------------------------
3
Q s = Q d = – ----------------------------------------------------------- ⋅ V gsteffcv
3
(ii) 40/60 Channel-charge Partition
2 ⋅ W active ⋅ L active ⋅ C OX
Q s = – ------------------------------------------------------------------- ⋅ V gsteffcv
5
Qd = –( Qg + Qb + Qs )

2 ⋅ W active ⋅ L active ⋅ C OX
Q s = – ------------------------------------------------------------------- ⋅ V gsteffcv
3
Qd = –( Qg + Qb + Qs )
capmod=2
The definition of Vfb is the same as in CAPMOD=1.
Q g = – ( Q inv + Q acc + Q sub 0 + δQ sub )
Q b = Q acc + Qsub 0 + δQ sub
Q inv = Q s + Q d
 2 
V FBeff = V fb – 0.5 ⋅  V 3 + V 3 + 4 ⋅ δ 3 ⋅ V fb  where V 3 = V fb – V gb – δ 3 and δ 3 = 0.02
 
Q acc = – W active ⋅ L active ⋅ C OX ⋅ ( V FBeff – V fb )
K1  4 ⋅ ( V gs – V FBeff – V gsteffcv – V bseff )

2
Q sub 0 = – W active ⋅ L active ⋅ C OX ⋅ ---------- ⋅  – 1 + 1 + -------------------------------------------------------------------------------------------
-
2  K1
2

V gsteff, cv
V dsat, cv = ----------------------
-
A′ bulk
CLE
A′ bulk = A bulk 0 ⋅  1 +  ----------------- 
CLC
  L active 
 K1  A 0 ⋅ L eff B0  1
A bulk 0 =  1 + -------------------------------------- ⋅  ---------------------------------------------------
- + ---------------------------  ⋅ -----------------------------------------------
 2 ⋅ φ s – V bseff  L eff + 2 ⋅ XJ ⋅ X dep W′ eff + B 1  1 + KETA ⋅ V bseff

V gs – V th – VOFFCV
V gsteffcv = NOFF ⋅ n ⋅ V t ⋅ ln 1 + exp  ---------------------------------------------------------
 NOFF ⋅ n ⋅ V t 
 2 
V cveff = V dsat, cv – 0.5 ⋅  V 4 + V 4 + 4 ⋅ δ 4 ⋅ V dsat, cv  where V 4 = V dsat, cv – V ds – δ 4 and δ 4 = 0.02
 
 2 
 
2
A′ bulk A′ ⋅ V
Q inv = – W active ⋅ L active ⋅ C OX ⋅  V gsteffcv – ---------------- ⋅ V cveff + -------------------------------------------------------------------------------
bulk cveff
  2  A′ 
12 ⋅  V gsteffcv – ---------------- ⋅ V cveff 
bulk
  2 
 2 
 1 – A ′ bulk ( 1 – A′ bulk ) ⋅ A′ bulk ⋅ V cveff 
δQ sub = W active ⋅ L active ⋅ C OX ⋅  ---------------------- ⋅ V cveff + -------------------------------------------------------------------------------
 2 A′ bulk 
 12 ⋅  V gsteffcv – ---------------- ⋅ V cveff 
 2 
Q s = Q d = 0.5 ⋅ Q inv =
 2 
W active ⋅ L active ⋅ C OX  A′ bulk
2
A′ bulk ⋅ V cveff 
– ----------------------------------------------------------- ⋅  V gsteffcv – ---------------- ⋅ V cveff + -------------------------------------------------------------------------------
2  2 A′ bulk 
 2 
(ii) 40/60 Channel-charge Partition

Q s = – -------------------------------------------------------------------------2-
A′ bulk
2 ⋅  V gsteffcv – ---------------- V cveff
 2 
V 3 4 2
– --- ⋅ V gsteffcv ⋅ A′ bulk ⋅ V cveff + --- ⋅ V
2
⋅ ( A′ bulk ⋅ V cveff ) – ------ ⋅ ( A′ bulk ⋅ V cveff ) 
2 2 3
 gsteffcv 3 3 gsteff 15 
Q d = – -------------------------------------------------------------------------2-
A′ bulk
2 ⋅  V gsteffcv – ---------------- V cveff
 2 
V 3 5
– --- ⋅ V gsteffcv ⋅ A′ bulk ⋅ V cveff + V gsteff ⋅ ( A′ bulk ⋅ V cveff ) – --- ⋅ ( A′ bulk ⋅ V cveff ) 
2 2 1 3
 gsteffcv 3 5 
 2 
 V gsteffcv A′ bulk ⋅ V ds ( A′ bulk ⋅ V ds ) 
Q s = – W active ⋅ L active ⋅ C OX ⋅  --------------------- + ----------------------------- – -------------------------------------------------------------------------------
 2 4 A′ bulk 
 2 

 
 V gsteffcv 3 ⋅ A′ bulk ⋅ V cveff 
2
( A′ bulk ⋅ V cveff )
Q d = – W active ⋅ L active ⋅ C OX ⋅  --------------------- + ------------------------------------------ – ----------------------------------------------------------------------------
 2 4 A′ bulk 
 2 
CAPMOD=3 (available in version 3.2 only)

CAPMOD=3 only supports zero biased Vfb, i.e., Vfb is calculated from bias independent Vth regardless
of the version number. This is different from CAPMOD=1 and 2.
V fb = V th 0 – φ s – K 1 ox φ s – V bseff
Q acc = W active ⋅ L active ⋅ C OX eff ⋅ V gbacc
1 2
V gbacc = --- ⋅ [ V 0 + V 0 + 4 ⋅ δ 3 ⋅ V fb ]
2
V 0 = V fb + V bseff – V gs – δ 3
 2 
V FBeff = V fb – 0.5 ⋅  V 3 + V 3 + 4 ⋅ δ 3 ⋅ V fb  where V 3 = V fb – V gb – δ 3 and δ 3 = 0.02
 
COX ⋅ C cen
COX eff = -------------------------------
-
COX + C cen
C cen = ε si ⁄ X DC
 V gsteff, cv ⋅ ( V gsteff, cv + 2 ⋅ K lox ⋅ 2 Φ B )

Φ δ = V t ⋅ ln  ----------------------------------------------------------------------------------------------------
-
 
2
moin ⋅ K lox ⋅ V t
2
K lox 4 ⋅ ( V gs – V FBeff – V bseffs – V gsteff, cv )
Q sub 0 = – W active ⋅ L active ⋅ C OX eff ⋅ ------------- ⋅ – 1 + 1 + ------------------------------------------------------------------------------------------------
2
2 K lox
1 2
V cveff = V dsat – --- ⋅ ( V 1 + V 1 + 4 ⋅ δ 3 ⋅ V dsat )
2
V 1 = V dsat – V ds – δ 3
V gsteff, cv – ϕ δ
V dsat = ----------------------------------
-
A′ bulk
Q inv = – W active ⋅ L active ⋅ C OX eff ⋅
2
1 
2
A′ bulk ⋅ V cveff
V gsteff, cv – ϕ δ –  --- ⋅ A bulk ′ ⋅ V cveff + --------------------------------------------------------------------------------------------------
-
 2 12 ⋅ ( V gsteff, cv – ϕ δ – A′ bulk ⋅ V cveff
⁄ 2 ) 
2
1 – A′ bulk ( 1 – A′ bulk ) ⋅ A ′ bulk ⋅ V cveff
δQ sub = – W active ⋅ L active ⋅ C OX eff ⋅ ------------------------- ⋅ V cveff – --------------------------------------------------------------------------------------------------
-
2 12 ⋅ ( V gsteff, cv – ϕ δ – A′ bulk ⋅ V cveff ⁄ 2 )
(i) 50/50 Charge Partition

1 W active ⋅ L active ⋅ C OX eff

Q S = Q D = --- ⋅ Q -⋅
= – ----------------------------------------------------------------
2 inv 2
2 2
1 A′ bulk ⋅ V cveff
V gsteff, cv – ϕ δ – --- ⋅ A′ bulk ⋅ V cveff + --------------------------------------------------------------------------------------------------
-
2 12 ⋅ ( V gsteff, cv – ϕ δ – A′ bulk ⋅ V cveff ⁄ 2 )
(ii) 40/60 Charge Partition

W active ⋅ L active ⋅ C OX eff 3 4 2
Q s = – -----------------------------------------------------------------------------------------2- ( V gsteff, cv – ϕ δ ) – --- ( V gsteff, cv – ϕ δ ) A′ bulk V cveff +
2 ( V gsteff, cv – ϕ δ – A′ bulk V cveff ⁄ 2 ) 3
2 2 2 3
--- ( V gsteff, cv – ϕ δ ) ( A′ bulk V cveff ) – ------ ( A′ bulk V cveff ) ]
3 15
W active ⋅ L active ⋅ C OX eff 3 5 2

Q D = – -----------------------------------------------------------------------------------------2- ( V gsteff, cv – ϕ δ ) – --- ( V gsteff, cv – ϕ δ ) A′ bulk V cveff +
2 ( V gsteff, cv – ϕ δ – A′ bulk V cveff ⁄ 2 ) 3
2 1 3
( V gsteff, cv – ϕ δ ) ( A′ bulk V cveff ) – --- ( A′ bulk V cveff ) ]
5
(iii) 0/100 Charge Partition
W active ⋅ L active ⋅ C OX eff 1 A′ bulk V cveff

2 2
Q S = – ----------------------------------------------------------------- ⋅ V gsteff, cv – ϕ δ + --- A′ bulk V cveff – -----------------------------------------------------------------------------------------------
2 2 12 ⋅ ( V gsteff, cv – ϕ δ – A′ bulk V cveff ⁄ 2 )
W active ⋅ L active ⋅ C OX eff 3 A′ bulk V cveff

2 2
- ⋅ V gsteff, cv – ϕ δ – --- A′ bulk V cveff + ----------------------------------------------------------------------------------------------
Q D = – ---------------------------------------------------------------- -
2 2 12 ⋅ ( V gsteff, cv – ϕ δ – A′ bulk V cveff ⁄ 2 )
Intrinsic Capacitances (with Body bias and DIBL)

∂Q s, d, g, b ∂V gsteffcv
C ( s, d, g, b ) ,g = ------------------------ ⋅ ------------------------
∂V gsteffcv ∂V gt
∂Q s, d, g, b ∂Q s, d, g, b ∂V gsteffcv  ∂V th ∂V th
- + ------------------------ ⋅ ------------------------ ⋅ ------------ + ------------
C ( s, d, g, b ) ,s = ----------------------
∂V ds ∂V gsteffcv ∂V gt  ∂V ds ∂V bs
∂Q s, d, g, b ∂Qs, d, g, b ∂V gsteffcv ∂V th
- + ------------------------ ⋅ ------------------------ ⋅ ------------
C ( s, d, g, b ) ,d = ----------------------
∂V ds ∂V gsteffcv ∂V gt ∂V ds
∂Q s, d, g, b ∂Q s, d, g, b ∂V gsteffcv ∂V th
- + ------------------------ ⋅ ------------------------ ⋅ ------------
C ( s, d, g, b ) ,b = ----------------------
∂V bs ∂V gsteffcv ∂V gt ∂V bs
Capacitance Model Implementation

The charge conservative capacitance model is evaluated in three steps:
• The variable gate, bulk and drain charges, qg, qb and qd respectively, are calculated as functions of
the gate, drain, source and bulk voltages. The charge contribution of the overlap, bulk-drain and
bulk-source capacitances are not added to qg and qb at this step. The partitioning ratio of qd to qs
is determined using the XPART model parameter. Nine basic “capacitances” (partial derivatives of
the qg, qd and qb charges with respect to Vgb, Vdb and Vsb) are calculated as follows;
cggb = ∂q g ⁄ ∂V gb cdgb = ∂q d ⁄ ∂V gb cbgb = ∂q b ⁄ ∂V gb

cgdb = ∂q g ⁄ ∂V db cddb = ∂q d ⁄ ∂V db cbdb = ∂q b ⁄ ∂V db
cgsb = ∂q g ⁄ ∂V sb cdsb = ∂q d ⁄ ∂V sb cbsb = ∂q b ⁄ ∂V sb
• The total gate, drain and bulk charges (Qg, Qd and Qb respectively) are calculated. These charges
contain the variable gate (qg), drain (qd) and bulk (qb) charges as well as the charge contribution of
the overlap, bulk-drain and bulk-source capacitances.
• Sixteen derivatives of the terminal charges with respect to the terminal voltages are computed as
follows:
∂Qn
-------------
∂Vm
where n and m are gate, source, drain or bulk. These derivatives are used as transcapacitances for
small signal AC analysis.
The following BSIM3v3 device parameters can be stored, printed and/or measured using the .save,
.probe, .print and .measure statements (see the table listing all output variables)
• The variable intrinsic transcapacitances:
cggb cdgb cbgb
cgdb cddb cbdb
cgsb cdsb cbsb
• The variable bulk-drain and bulk-source capacitances: capbd and capbs
• The total gate, drain and bulk charges Qg, Qd and Qb
capgdo, gate-drain overlap capacitance
capgso, gate-source overlap capacitance
capgbo, gate-bulk overlap capacitance
capgg, total gate capacitance (cggb + capgdo + capgso + capgbo)
Capacitances listed in the above table are used in .AC analysis. The capacitance matrix used in all
types of simulation in the frequency domain is shown in following table.
Node Gate Drain Source Bulk
+cggb +cgdb +cgsb -(cggb+cgdb+cgsb)

+capgdo -capgdo -capgso -capgbo
Gate
+capgso
+capgbo
+cdgb +cddb +cdsb -(cdgb+cddb+cdsb)

Drain -capgdo +capgdo -capbd
+capbd
-(cggb+cdgb+cbgb) -(cgdb+cddb+cbdb) -(cgsb+cdsb+cbsb) +(cggb+cgdb+cgsb)

-capgso +capgso +(cdgb+cddb+cdsb)
Source
+capbs +(cbgb+cbdb+cbsb)
-capbs
+cbgb +cbdb +cbsb -(cbgb+cbdb+cbsb)

-capgbo -capbd -capbs +capgbo
Bulk
+capbd
+capbs

14.6.7: NQS Model Equations

The charge-deficit NQS model can be turned on by setting NQSMOD=1 (default 0 =OFF). An enhanced
version of Berkeley NQS model can also be invoked by setting NQSMOD=5.
Quasi-static equilibrium channel charge:
Q eq = – ( Q g + Q b )
Actual channel charge and Qdef obtained from subcircuit:

Q ch = Q eq – Q def
1 1 1
g τ = --- = ------------ + ----------
τ τ drift τ diff
with
2
q ⋅ L eff
τ diff = --------------------------------
-
16 ⋅ µ eff ⋅ KT
and
3
COX ⋅ W eff ⋅ L eff ζ
τ drift = ----------------------------------------------------------- ≈ ------------
µ eff ⋅ ε ⋅ Q eq – α ⋅ Q def Q eq
where,
ε ≡ Elmore Constant (default=5)
0.0 ≤ α ≤ 1.0 (default = 0.5)

3
COX ⋅ W eff ⋅ L eff
ζ = ---------------------------------------------
-
µ eff ⋅ ε

14.7: Berkeley MOSFET Model BSIM4

14.7.1: Introduction
BSIM4 model is developed to explicitely address many issues in modeling sub-0.13 microns CMOS
technology and RF high-speed CMOS circuit simulation
The Silvaco Verilog-A implementation is based on the most recent Berkeley release of May, 09 2003,
namely BSIM4 version 3.0.
14.7.2: Instance Parameters

Besides standard instance parameters L, W, ... supported by all MOSFET devices, the following
BSIM4-specific parameters can be specified on the device statement:
NF Number of device fingers - 1
SA Distance between OD edge to poly of one side m 0
SB Distance between OD edge to poly of the other side m 0
SD Distance between neighbour fingers m 0
MIN Minimize either D or S in area/perimeter equations - 0
RBPB Resistance connected between BP and B nodes Ω
RBPD Resistance connected between BP and DB nodes Ω
RBPS Resistance connected between BP and SB nodes Ω
RBDB Resistance connected between DB and B nodes Ω
RBSB Resistance connected between SB and B nodes Ω
ACNQSMOD AC NQS model selector -
RBODYMOD Substrate resistance network model selector -
RGATEMOD Gate resistance network model selector -
GEOMOD Geometry dependent parasitics model selector -
RGEOMOD S/D resistance and contact model selector - 0
Control Parameters
MOBMOD Mobility model selector 0
RDSMOD Bias-dependent S/D resistance model selector 0
IGCMOD Global model selector for Igs, Igd, Igcs and Igcd 0

IGBMOD Global model selector for Igb 0
RGATEMOD Gate-resistance model selector 0
RBODYMOD Model selector for distributed substrate resistance network 0
DIOMOD Junction Diode IV model selector 1
CAPMOD Capacitance model selector 2
GEOMOD Geometry dependent parasitics model selector 0
PERMOD Source/Drain perimeter model selector 0
TEMPMOD Temperature model selector 0
Threshold Voltage Parameters
VTH0 Long-channel threshold voltage at Vbs=0 V 0.7 (NMOS)

-0.7 (PMOS)
VFB Flat-band voltage (see note below) V -1.0
PHIN Non-uniform vertical doping effect V 0.0
K1 First body bias coefficient V 0.5
K2 Second body bias coefficient - 0.0
K3 Narrow width coefficient - 80.0
K3B Body effect coefficient of K3 V

–1 0.0
W0 Narrow width parameter m 2.5E-6
LPE0 Non-uniform lateral doping parameter at Vbs=0 m 1.74E-7
LPEB Non-uniform lateral doping effect on K1 m 0.0
VBM Maximum applied body bias in Vth calculation V -3.0
DVT0 First coefficient of short channel effect on Vth - 1.0
DVT1 Second coefficient of short channel effect on Vth - 1.0
DVT2 Body-bias coefficient of short channel effect on Vth V

–1 -0.032
DVT0W First coefficient of narrow width effect on Vth for m

–1 0.0
small channel length
DVT1W Second coefficient of narrow width effect on Vth for m

–1 5.3E6
small channel length

DVT2W Body-bias coefficient of narrow width effect on Vth V

–1 -0.032
for small channel length
DVTP0 First coefficient of pocket implant effect on Vth for m 0.0

long channel effect
DVTP1 Second coefficient of pocket implant effect on Vth for V

–1 0.0
long channel effect
Moderate Inversion Parameters
VOFF Offset voltage in moderate inversion region for large V -0.08

width and length
VOFFL Coefficient for gate length dependence of VOFF m 0.0
MINV Coefficient of moderate inversion - 0.0
Mobility Parameters
U0 Low field mobility 2

m ⁄ Vs 0.067 (NMOS)
0.025 (PMOS)
UA Coefficient of first-order mobility degra- m⁄V 1.0E9

dation due to vertical field (MODMOD=0,1)
1.0E-15
(MODMOB=2)
UB Coefficient of second-order mobility deg- m ⁄V

2 2 1.0E-19
radation due to vertical field
UC Coefficient of mobility degradation due to V

–1 -0.0465
body-bias effect (MODMOD=1)
(MODMOD=1)
2
-0.0465E-9
m ⁄V (MODMOB=0,2)
(MODMOB=0,2)
EU Exponent for mobility degradation of - 1.67 (NMOS)

MODMOB=2 1.0 (PMOS)

Unified Current Saturation Parameters
LAMBDA Velocity overshoot coefficient 3

m ⁄ Vs 0.0
VTL Thermal velocity m⁄s 2.0E5
LC Velocity back scattering coefficient m 0.0
XN Velocity back scattering coefficient - 3.0
Output Resistance Parameters
PCLM Channel length modulation parameter - 1.0
PDIBLC1 First output resistance DIBL effect correction param- - 0.39

eter
PDIBLC2 Second output resistance DIBL effect correction - 0.0001

parameter
PDIBLCB Body effect coefficient of DIBL correction parameters V

–1 0.0
DROUT L dependence coefficient of the DIBL correction - 1.0

parameter in Rout
PSCBE1 First substrate current body-effect parameter V⁄m 4.24E8
PSCBE2 Second substrate current body-effect parameter m⁄V 1.0E-5
PVAG Gate dependence of Early voltage - 0.0
DELTA Effective Vds parameter V 0.01
FPROUT Pocket degradation parameter in Rout V⁄ m 0.0
PDITS Magnitude of DITS on Rout V

–1 0.0
PDITSL L dependence of DITS on Rout m

–1 0.0
PDITSD Vds dependence of DITS on Rout V

–1 0.0

Asymmetric and Bias-Dependent Rds Parameters
RDSW Zero-bias LDD resistance per unit width (RDS- Ω ⋅ µm

WR 200.0
MOD=0)
RDSWMIN LDD resistance per unit width at high Vgs and Ω ⋅ µm

WR 0.0
zero Vbs (RDSMOD=0)
RDW Zero bias lightly-doped drain resistance Rd(V) Ω ⋅ µm

WR 100.0
per unit width (RDSMOD=1)
RDWMIN Lightly-doped drain resistance per unit width Ω ⋅ µm

WR 0.0
at high Vgs and zero Vbs (RDSMOD=1)
RSW Zero bias lightly-doped source resistance Rs(V) Ω ⋅ µm

WR 100.0
per unit width (RDSMOD=1)
RSWMIN Lightly-doped source resistance per unit width Ω ⋅ µm

WR 0.0
at high Vgs and zero Vbs (RDSMOD=1)
PRWG Gate bias dependence of LDD resistance V

–1 1.0
PRWB Body bias dependence of LDD resistance V

– 0.5 0.0
WR Width dependence parameter of LDD resis- - 1.0

tance
Quantum-Mechanical Inversion-Layer Thickness and High-k Gate Dielectrics Parameters
EPSROX Gate dielectric constant relative to the vacuum - 3.9 (SiO2)
TOXE Electrical gate equivalent oxide thickness m 4.0E-9
TOXP Physical gate equivalent oxide thickness m TOXE
TOXM TOXE at which BSIM4 parameters are extracted m TOXE
DTOX Defined as TOXE-TOXP m 0.0

Gate-Induced Drain Leakage (GIDL) Current Parameters
AGIDL Pre-exponential coefficient for GIDL Ω

–1 0.0
BGIDL Exponential coefficient for GIDL V⁄m 2.3E9
CGIDL Parameter for the body bias effect on GIDL V

3 0.5
EGIDL Fitting parameter for band bending V 0.8
Gate Tunneling Current Parameters
AIGBACC Parameter for Igb in accumulation 2 –1 0.43

F⋅s ⁄g⋅m
BIGBACC Parameter for Igb in accumulation 2 –1 –1 0.054

F⋅s ⁄g⋅m ⋅V
CIGBACC Parameter for Igb in accumulation V

–1 0.075
NIGBACC Parameter for Igb in accumulation - 1.0

(Note 1)
AIGBINV Parameter for Igb in inversion 2 –1 0.35

F⋅s ⁄g⋅m
BIGBINV Parameter for Igb in inversion 2 –1 –1 0.03

F⋅s ⁄g⋅m ⋅V
CIGBINV Parameter for Igb in inversion V

–1 0.006
EIGBINV Parameter for Igb in inversion V 1.1
NIGBINV Parameter for Igb in inversion - 3.0

(Note 1)
AIGC Parameter for Igs, Igd, Igcs and Igcd 2 –1 0.43 (NMOS)
F⋅s ⁄g⋅m 0.31 (PMOS)
BIGC Parameter for Igcs and Igcd 2 –1 –1 0.054 (NMOS)

F⋅s ⁄g⋅m ⋅V 0.024 (PMOS)
CIGC Parameter for Igcs and Igcd V

–1 0.075 (NMOS)
0.03 (PMOS)
AIGSD Parameter for Igs and Igd 2 –1 0.43 (NMOS)

F⋅s ⁄g⋅m 0.31 (PMOS)
BIGSD Parameter for Igs and Igd 2 –1 –1 0.054 (NMOS)

F⋅s ⁄g⋅m ⋅V 0.024 (PMOS)

CIGSD Parameter for Igs and Igd V

–1 0.075 (NMOS)
0.03 (PMOS)
DLCIG S/D overlap length for Igs/Igd m LINT
NIGC Parameter for Igs, Igd, Igcs and Igcd - 1.0

(Note 1)
POXEDGE Factor for the gate oxide thickness in - 1.0

the S/D overlap regions (Note 1)
PIGCD Vds dependence of Igcs and Igcd - (Note 2)

(Note 1)
NTOX Exponent for the tox ratio - 1.0
TOXREF Nominal gate oxide thickness A 30.0

(Note 1)
Electrode Gate, Intrinsic-Input Resistance and NQS Model Parameters
RSHG Gate-electrode sheet resistance Ω /square 0.1
XGW Distance from the gate contact to the channel edge m 0.0
XGL Difference between Ldrawn and physical gate lenght m 0.0
XRCRG1 Parameter for distributed channel-resistance effect - 12.0
XRCRG2 Parameter to account for the excess channel diffusion - 1.0

conductance
Substrate Resistance Network Parameters
GBMIN Minimum conductance for the substrate resistance model Ω

–1 1.0E-12
RBPB Resistance connected between BP and B nodes Ω 50.0
RBPD Resistance connected between BP and DB nodes Ω 50.0
RBPS Resistance connected between BP and SB nodes Ω 50.0
RBDB Resistance connected between DB and B nodes Ω 50.0
RBSB Resistance connected between SB and B nodes Ω 50.0

Stress Effect Parameters
SAREF Reference distance between OD edge to poly of m 0.0

one side
SBREF Flicker noise frequency exponent m 0.0
WLOD Width parameter m 0.0
KU0 Mobility degradation/enhancement coefficient m 0.0
KVSAT Saturation velocity degradation/enhancement m 0.0

parameter
TKU0 Temperature coefficient of KU0 - 0.0
LKU0 Length dependence of KU0 m

llodku0 0.0
WKU0 Width dependence of KU0 m

w lodku0 0.0
PKU0 Cross-term dependence of KU0 m

w lodku0+llodu0 0.0
LLODKU0 Length parameter for U0 stress effect - 0.0
WLODKU0 Width parameter for U0 stress effect - 0.0
KVTH0 Threshold shift parameter V⋅m 0.0
LKVTH0 Length dependence of KVTH0 V⋅m

llodku0 0.0
WKVTH0 Width dependence of KVTH0 V⋅m

w lodku0 0.0
PKVTH0 Cross-term dependence of KVTH0 V⋅m

w lodku0+llodu0 0.0
LLODVTH Length parameter for Vth stress effect - 0.0
WLODVTH Width parameter for Vth stress effect - 0.0
STK2 K2 shift factor related to Vth0 change m 0.0
LODK2 K2 shift modification factor - 1.0
STETA0 ETA0 shift factor related to Vth0 change m 0.0
LODETA0 ETA0 shift modification factor - 1.0

Asymmetric Source/Drain Junction Diode Parameters
NJS Junction emission coefficient (Source side) - 1.0
NJD Junction emission coefficient (Drain side) - NJS
XITS Junction current temperature exponent (Source side) - 3.0
XITD Junction current temperature exponent (Drain side) - XITD
IJTHSREV Limiting current in reverse bias region (Source side) A 0.1
IJTHDREV Limiting current in forward bias region (Drain side) A IJTHSREV
IJTHSFWD Limiting current in forward bias region (Source side) A 0.1
IJTHDFWD Limiting current in reverse bias region (Drain side) A IJTHSFWD
XJBVS Fitting parameter for diode breakdown (Source side) - 1.0
XJBVD Fitting parameter for diode breakdown (Drain side) - XJBVS
BVS Breakdown voltage (Source side) V 10.0
BVD Breakdown voltage (Drain side) V BVS
JSS Bottom junction reverse saturation current density A⁄m

2 1.0E-4
(Source side)
JSD Bottom junction reverse saturation current density A⁄m

2 JSS
(Drain side)
JSWS Isolation-edge sidewall reverse saturation current den- A⁄m 0.0

sity (Source side)
JSWD Isolation-edge sidewall reverse saturation current den- A⁄m JSWS

sity (Drain side)
JSWGS Gate-edge sidewall reverse saturation current density A⁄m 0.0

(Source side)
JSWGD Gate-edge sidewall reverse saturation current density A⁄m JSWGS

(Drain side)
CJS Bottom junction capacitance per unit area (Source F⁄m

2 5.0E-4
side)
CJD Bottom junction capacitance per unit area (Drain side) F⁄m
2 CJS
PBS Bottom junction built-in potential (Source side) V 1.0
PBD Bottom junction built-in potential (Drain side) V PBS
MJS Bottom junction grading coefficient (Source side) - 0.5
MJD Bottom junction grading coefficient (Drain side) - MJS

CJSWS Isolation-edge sidewall junction capacitance per unit F⁄m 5.0E-10

lenght (Source side)
CJSWD Isolation-edge sidewall junction capacitance per unit F⁄m CJSWS

length (Drain side)
PBSWS Isolation-edge sidewall junction built-in potential V 1.0

(Source side)
PBSWD Isolation-edge sidewall junction built-in potential V PBSWS

(Drain side)
MJSWS Isolation-edge sidewall junction grading coefficient - 0.33

(Source side)
MJSWD Isolation-edge sidewall junction grading coefficient - MJSWS

(Drain side)
CJSWGS Gate-edge sidewall junction capacitance per unit F⁄m CJSWS

lenght (Source side)
CJSWGD Gate-edge sidewall junction capacitance per unit F⁄m CJSWS

length (Drain side)
PBSWGS Gate-edge sidewall junction built-in potential (Source V PBSWS

side)
PBSWGD Gate-edge sidewall junction built-in potential (Drain V PBSWS

side)
MJSWGS Gate-edge sidewall junction grading coefficient (Source - MJSWS

side)
MJSWGD Gate-edge sidewall junction grading coefficient (Drain - MJSWS

side)
Series/Parallel Devices Modeling Parameters
DMCG Distance from the contact center to the gate edge m 0.0
DMCI Distance in the channel length direction from the contact m DMCG
center to the isolation edge
DMDG Same as DMCG but for merged devices only m 0.0
DMCGT DMCG in test structures m 0.0
DWJ Offset of the S/D junction width due to variations m DWC
XGW Distance from the gate contact to the channel edge m 0.0
XGL Offset of the gate length due to variations in patterning m 0.0
NGCON Number of gate contacts (1 or 2 only) - 1

Charge-Voltage (CV) Parameters

Three capacitance models are available in BSIM4 and come from BSIM3v3.2.2. The BSIM3v3.2.2
capacitance model parameters are used without any change in BSIM4, with one exception: CKAPPA is
separated into CKAPPAS and CKAPPAD for the source side and the drain side diodes, respectively.
CKAPPAS* Coefficient for Source/Gate overlap capacitance F/m 0.6
CKAPPAD* Coefficient for Drain/Gate overlap capacitance F/m CKAPPAS
W and L Parameters
WINT Channel width offset parameter m 0.0
LINT Channel length offset parameter m 0.0
WL Coefficient of length dependence for width offset m

WLN 0.0
WLN Power of length dependence of width offset - 1.0
WW Coefficient of width dependence for width offset m

WWN 0.0
WWN Power of width dependence of width offset - 1.0
WWL Coefficient of length and width cross term for width m

WWN + WLN 0.0
offset
LL Coefficient of length dependence for length offset m

LLN 0.0
LLN Power of length dependence for length offset - 1.0
LW Coefficient of width dependence for length offset m

LWN 0.0
LWN Power of width dependence for length offset - 1.0
LWL Coefficient of length and width cross term for m

LWN + LLN 0.0
length offset
LLC Coefficient of length dependence for CV channel m

LLN LL
length offset
LWC Coefficient of width dependence for CV channel m

LWN LW
length offset
LWLC Coefficient of length and width dependence for CV m

LWN + LLN LWL
channel length offset
WLC Coefficient of length dependence for CV channel m

WLN WL
width offset

WWC Coefficient of width dependence for CV channel m

WWN WW
width offset
WWLC Coefficient of length and width dependence for CV m

WWN + WLN WWL
channel width offset
DLC Length offset fitting parameter for C-V model m LINT
DWC Width offset fitting parameter for C-V model m WINT
DWG Coefficient of Weff gate bias dependence m⋅V

–1 0.0
DWB Coefficient of Weff body bias dependence –1 ⁄ 2 0.0

m⋅V
XW Offset for channel width due to mask/etch effect m 0.0

(Note 1)
XL Offset for channel length due to mask/etch effect m 0.0

(Note 1)
14.7.3: Effective Channel Length and Width

Define
L scaled = L ⋅ SCALE + XL
W ⋅ SCALE
W scaled = -------------------------------- + XW
NF
IV model
Bias-Independent Quantities:
L eff = L scaled – 2 ⋅  LINT + ----------------- -

LL LW LWL
+ ------------------
- + -----------------------------------------
 L scaled W scaled L scaled ⋅ W scaled
LLN LWN LLN LWN
 WL WW WWL 
W′ eff = W scaled – 2 ⋅  WINT + -----------------
WLN
+ ------------------
WWN
-
- + -----------------------------------------
WWN
 L scaled W scaled L scaled ⋅ W scaled WLN
Bias-Dependent Effective Channel Width:
W eff = W′ eff – 2 ⋅ ( DWG ⋅ Vgsteff + DWB ⋅ ( φ s – V bseff – φ s ) )
Weff is used in Vdsat, Vasat, Vdseff, and Idso equations.

BSIM4 uses the effective source/drain diffusion width W effcj for modeling parasitics, such as source/
drain resistance, gate electrode resistance and gate-induced drain leakage (GIDL) current.
W effcj = W scaled – 2 ⋅  DWJ + ---------------- -

WLC WWC WWLC
- + ------------------
- + -----------------------------------------
 WLN WWN
WLN WWN 

CV model
L active = L scaled – 2 ⋅  DLC + ----------------- -

LLC LWC LWLC
+ ------------------
- + -----------------------------------------
 LLN LWN
LLN LWN 
W active = W scaled – 2 ⋅  DWC + ---------------- -

WLC WWC WWLC
- + ------------------
- + -----------------------------------------
 L scaled W scaled L scaled ⋅ W scaled
WLN WWN WLN WWN
14.7.4: Gate Dielectric Model

BSIM4 accounts for the finite charge-layer thickness effect in both IV and CV models. For this pur-
pose, BSIM4 accepts the electrical gate oxide thickness TOXE and/or the physical gate oxide thickness
TOXP, or their difference DTOX = TOXE - TOXP, as model parameters.
BSIM4 also allows to specify a gate dielectric constant (EPSROX) different from 3.9 (SiO2) for high-k
dielectrics modeling. This is an alternative to the “equivalent oxide” approach.
EPSROX ⋅ ε
C oxe = -----------------------------------0-
TOXE
EPSROX ⋅ ε
C oxp = -----------------------------------0-
TOXP
14.7.5: Temperature Equations

Define
T
T ratio = --------------------
TNOM
where T is the instance temperature and TNOM is a model parameter corresponding to the tempera-
ture at which model parameters have been extracted,
kB ⋅ T k B ⋅ TNOM
V t = --------------
- and V tnom = ------------------------------
-
q q
as the thermal voltage at device and nominal temperature, respectively.
Model parameter temperature scaling

In order to account for temperature effects, several model parameters are temperature-scaled:
KT1 ( T ) = KT1 ⋅ ( T ratio – 1 )
KT1L ( T ) = KT1L ⋅ ( T ratio – 1 )
KT2 ( T ) = KT2 ⋅ ( T ratio – 1 )
UTE
U 0 ( T ) = U 0 ⋅ ( T ratio )
UA ( T ) = UA + UA 1 ⋅ ( T ratio – 1 )
UB ( T ) = UB + UB 1 ⋅ ( T ratio – 1 )
UC ( T ) = UC + UC 1 ⋅ ( T ratio – 1 )
VSAT ( T ) = VSAT – AT ⋅ ( T ratio – 1 )

RdsMod=0 (internal source/drain LDD resistance)

RDSW ( T ) = RDSW + PRT ⋅ ( T ratio – 1 )
RDSWMIN ( T ) = RDSWMIN + PRT ⋅ ( T ratio – 1 )
RdsMod=1 (external source/drain LDD resistance)

RDW ( T ) = RDW + PRT ⋅ ( T ratio – 1 )
RDWMIN ( T ) = RDWMIN + PRT ⋅ ( T ratio – 1 )
RSW ( T ) = RSW + PRT ⋅ ( T ratio – 1 )
RSWMIN ( T ) = RSWMIN + PRT ⋅ ( Tratio – 1 )
Junction Diode IV and CV parameters

In the following equations, x stands for S or D, depending if the parameter is related to the source side
or the drain side, respectively.
E g ( TNOM ) E g ( T )
 -------------------------------
- – ---------------- + XTIx ⋅ ln ( T ratio )
 V tnom Vt 
J sx ( T ) = JSx ⋅ exp  ---------------------------------------------------------------------------------------------------------
 NJx 
 
 -------------------------------
- – ---------------- + XTIx ⋅ ln ( T ratio )
 V tnom Vt 
J sswx ( T ) = JSSWx ⋅ exp  ---------------------------------------------------------------------------------------------------------
 NJx 
 
 -------------------------------
- – ---------------- + XTIx ⋅ ln ( T ratio )
 V tnom Vt 
J sswgx ( T ) = JSSWGx ⋅ exp  ---------------------------------------------------------------------------------------------------------
 NJx 
 
CJx ( T ) = CJx ⋅ [ 1 + TCJ ⋅ ( T – TNOM ) ]
CJSWx ( T ) = CJSWx ⋅ [ 1 + TCJSW ⋅ ( T – TNOM ) ]
CJSWGx ( T ) = CJSWGx ⋅ [ 1 + TCJSWG ⋅ ( T – TNOM ) ]
PBx ( T ) = PBx – TPB ⋅ ( T – TNOM )
PBSWx ( T ) = PBSWx – TPBSW ⋅ ( T – TNOM )
PBSWGx ( T ) = PBSWGx – TPBSWG ⋅ ( T – TNOM )
Energy gap calculation

The energy gap width at device and nominal temperature is defined by the expressions, respectively:
2
–4 T
E g ( T ) = 1.16 – 7.02 ⋅ 10 ⋅ --------------------------
T + 1108.0
2
–4 TNOM
E g ( TNOM ) = 1.16 – 7.02 ⋅ 10 ⋅ -------------------------------------------
TNOM + 1108.0

Intrinsic carrier concentration, surface potential and built-in potential calculation

TNOM 1.5 E g ( TNOM )
n i = 1.45 ⋅ 10 ⋅  -------------------- ⋅ exp  21.5565981 – -------------------------------
10
-
 300.15   2 ⋅ V tnom 
φ s = 0.4 + PHIN + V tnom ⋅ ln  ------------------

NDEP
 ni 
NDEP ⋅ NSD
V bi = V tnom ⋅ ln  ------------------------------------
-
 ni
2 
Flat-Band Voltage (for Tunneling Current Equations)

if NGATE > 0.0
V fbsd = V tnom ⋅ log  -----------------------

NGATE
 NSD 
otherwise
V fbsd = 0
14.7.6: I-V Model Equations

Threshold Voltage
In addition to all the features of the BSIM3v3 model, the BSIM4 threshold voltage model can more
accurately model devices with non-uniform doping profile in both vertical and lateral directions. It also
removes a phantom second V th roll-up when L < L min in BSIM3v3. A new long channel DIBL model
for pocket devices is also implemented.
The complete V th equation implemented in BSIM4 is
L
V th = VTH 0 + KT 1 + KT 1 L ⋅ --------- + KT 2 ⋅ V bseff
L eff
LPEB
+ ( K 1 ox ⋅ φ s – V bseff – K 1 ⋅ φ s ) ⋅ 1 + ----------------- – K 2 ox ⋅ V bseff
L eff
+ K 1 ox ⋅  1 + ---------------- – 1 ⋅ φ s + ( K 3 + K 3 B ⋅ V bseff ) ⋅ φ s ⋅ ----------------------------

LPE 0 TOXE
L eff W′ eff + W 0
DVT 0 W DVT 0
– 0.5 ⋅ ---------------------------------------------------------------------------------- + ---------------------------------------------------------- ⋅ ( V bi – φ s )
L ⋅ W′ L eff
cosh  DVT 1 W ⋅ --------------------------- – 1 cosh  DVT 1 ⋅ --------- – 1
eff eff
 l tw   lt 
0.5
– ----------------------------------------------------------- ⋅ ( ETA 0 + ETAB ⋅ V bseff ) ⋅ V ds
L eff
cosh  DSUB ⋅ --------- – 1
 lt0 

where
TOXE TOXE
K 1 ox = K 1 ⋅ ------------------- and K 2 ox = K 2 ⋅ -------------------
TOXM TOXM
2
V bseff = V bc + 0.5 ⋅ [ V bs – V bc – δ 1 + ( V bs – V bc – δ 1 ) – ( 4 ⋅ δ 1 ⋅ V bc ) ]
In version 3.0 and later, a smoothing function is added to set an upper bound for the body bias:
2
V′ bseff = 0.95 ⋅ φ s – 0.5 ⋅ ( 0.95 ⋅ φ s – V bseff – δ 1 + ( 0.95 ⋅ φ s – V bseff – δ 1 ) + 4 ⋅ δ 1 ⋅ 0.95 ⋅ φ s )
and all equations are evaluated with V′ bseff instead of V bseff .
δ 1 = 0.001 V
 K1 
2
V bc = 0.9 ⋅  φ s – -----------------2 if K2 < 0, otherwise V bc = – 30
 4 ⋅ K2 
ε si ⋅ TOXE ⋅ X dep
l tw = --------------------------------------------- ⋅ ( 1 + DVT 2 W ⋅ V bseff )
EPSROX
ε si ⋅ TOXE ⋅ X dep
lt = - ⋅ ( 1 + DVT 2 ⋅ V bseff )
--------------------------------------------
EPSROX
2 ⋅ ε si ⋅ ( φ s – V bseff )
X dep = -------------------------------------------------
q ⋅ NDEP
ε si ⋅ TOXE ⋅ X dep 0
lt0 = ------------------------------------------------
EPSROX
2 ⋅ ε si ⋅ φ s
X dep 0 = -------------------------
-
q ⋅ NDEP
The expressions of the built-in voltage of the source/drain junctions V bi and the surface potential φ s
are given in the paragraph related to temperature dependence.
Poly-Silicon Gate Depletion Effect

2
q ⋅ ε si ⋅ N GATE ⋅ TOXE  2 ⋅ EPSROX ⋅ ( V gs – VFB – φ s ) 
2
V gseff = VFB + φ s + ------------------------------------------------------------------
- ⋅  1 + -------------------------------------------------------------------------------------
- – 1
 
2 2
EPSROX q ⋅ ε si ⋅ N GATE ⋅ TOXE
Improved Effective (Vgs-Vth)

In BSIM3v3, there is no parameter dedicated to the moderate inversion region. In BSIM4, two model
parameters, VOFFL and MINV, are introduced to improve the model accuracy in this region.
For non-uniform channel doping profiles, VOFF has the following length dependence:
VOFFL
V′ off = VOFF + ----------------------
L eff
2
gm gm
MINV is incorporated to improve the accuracy of g m , ------- and ------- in the moderate inversion region via:
Id Id

* atan ( MINV )
m = 0.5 + ----------------------------------
π
to improve parameter optimization process.
The expression of the effective (Vgs-Vth) reads:
* V gseff – V th
n ⋅ V t ⋅ ln 1 + exp  m ⋅ ------------------------------
 n ⋅ Vt 
V gsteff = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
 
*
* 2 ⋅ φ ( 1 – m ) ⋅ ( V – V ) – V′
m + n ⋅ Coxe ⋅ ------------------------------------ s
- ⋅ exp  – ------------------------------------------------------------------------------
gseff th off

q ⋅ ε si ⋅ NDEP  n ⋅ V t 
where the sub-threshold swing n is written as

C dep C dsc + CIT
n = 1 + NFACTOR ⋅ ------------ + ----------------------------
-
C oxe C oxe
( CDSC + CDSCD ⋅ V ds + CDSCB ⋅ V bseff ) ⋅ 0.5

C dsc = ------------------------------------------------------------------------------------------------------------------------------
-
 L eff
cosh DVT 1 ⋅ --------- –1
 lt 
ε si
C dep = -----------
-
X dep
Mobility
Mobmod = 0
U0
µ eff = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
V gsteff + 2 ⋅ V th V gsteff + 2 ⋅ V th
1 + ( UA + UC ⋅ V bseff ) ⋅  --------------------------------------- + UB ⋅  ---------------------------------------
 TOXE   TOXE 
Mobmod = 1
U0
µ eff = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
 V gsteff + 2 V th  V gsteff + 2 V th 2
1 + UA ⋅ ----------------------------------- + UB ⋅ ----------------------------------- ⋅ ( 1 + UC ⋅ V bseff )
 TOXE   TOXE 
Mobmod = 2
U0
µ eff = -------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
V gsteff + C 0 ⋅ ( VTH 0 – VFB – φ s ) EU
1 + ( UA + UC ⋅ V bseff ) ⋅  ---------------------------------------------------------------------------------------
 TOXE 
where C 0 = 2 for NMOS and C 0 = 2.5 for PMOS.
Bulk Charge Effect

  A 0 ⋅ L eff
A bulk =  1 + F doping ⋅  ----------------------------------------------------
  L eff + 2 ⋅ XJ ⋅ X dep
  
2
L eff B0 1
⋅ 1 – AGS ⋅ V gsteff ⋅  ---------------------------------------------------- + ---------------------------  ⋅ -----------------------------------------------
 L eff + 2 ⋅ XJ ⋅ X dep W′ eff + B 1  1 + KETA ⋅ V bseff

where
LPEB
1 + ----------------- ⋅ K 1 ox
L eff TOXE
F doping - + K 2 ox – K 3 B ⋅ ----------------------------- ⋅ φ s
= ------------------------------------------------
2 ⋅ φ s – V bseff W′ eff + W 0
Asymmetric and Bias-Dependent Drain/Source Resistances

Rdsmod = 0 (internal Rds(V))
1
RDSWMIN + R DSW ⋅ PRWB ⋅ ( φ s – V bseff – φ s ) + --------------------------------------------------
1 + PRWG ⋅ Vgsteff
R ds = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
WR
-
6
( 10 ⋅ W effcj )
Rdsmod = 1 (external Rd(V) and Rs(V))
1
RDWMIN + R DW ⋅ – P RWB ⋅ V bd + -------------------------------------------------------------------
1 + PRWG ⋅ ( V gd – V fbsd )
R d = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
WR
-
6
( 10 ⋅ W effcj ) ⋅ NF
1
RSWMIN + RSW ⋅ – P RWB ⋅ V bs + -------------------------------------------------------------------
1 + PRWG ⋅ ( V gs – V fbsd )
R s = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------
WR
-
6
( 10 ⋅ W effcj ) ⋅ NF
where V fbsd is the flat-band voltage between gate and source/drain calculated in the “Tunneling Cur-
rents” section.
Drain Saturation Voltage

Define
λ = A 1 ⋅ V gsteff + A 2
For Rds > 0 or λ ≠ 1 (extrinsic case)
2
–b – b – 4 ⋅ a ⋅ c
V dsat = ----------------------------------------------
2⋅a
a = A bulk ⋅ W eff ⋅ VSAT ⋅ C oxe ⋅ R ds +  --- – 1 ⋅ A bulk

2 1
λ 

b = –  ( V gsteff + 2 ⋅ V t ) ⋅  --- – 1 + A bulk ⋅ E sat ⋅ L eff

2
 λ 
+ 3 ⋅ A bulk ⋅ ( V gsteff + 2 ⋅ V t ) ⋅ W eff ⋅ VSAT ⋅ Coxe ⋅ R ds


2
c = ( V gsteff + 2 ⋅ V t ) ⋅ E sat ⋅ L eff + 2 ⋅ ( V gsteff + 2 ⋅ V t ) ⋅ W eff ⋅ VSAT ⋅ C oxe ⋅ R ds
For Rds = 0 and λ = 1 (intrinsic case)
E sat ⋅ L eff ⋅ ( V gsteff + 2 ⋅ V t )

V dsat = -------------------------------------------------------------------------------------------
-
A bulk ⋅ E sat ⋅ L eff + ( V gsteff + 2 ⋅ V t )
where
2 ⋅ VSAT
E sat = -------------------------
µ eff
corresponds to the critical electrical field at which the carrier velocity becomes saturated.
To account for velocity overshoot:
 1 + V ds – V dseff
2 
 
-----------------------------
E ⋅ l
- – 1

= E sat ⋅  1 + -------------------------- ⋅ --------------------------------------------------------
-
LAMBDA sat itl
E′ sat
 L eff ⋅ µ eff  V ds – V dseff 2 
 1 + ------------------------------ + 1
  E sat ⋅ l itl  
where l itl and V dseff are defined in following paragraphs.
As GAMMA defaults to 0 and so ensures backward compatibility, this equation is supported by all ver-
sions of BSIM4.
Effective Vds
An effective Vds is used to ensure a smooth transition near Vdsat from electrode to saturation regions:
1 2
V dseff = V dsat – --- ⋅ ( V dsat – V ds – DELTA + ( V dsat – V ds – DELTA ) + 4 ⋅ DELTA ⋅ V dsat )
2
Drain Current
The current equation for both linear and saturation regions is expressed by
I ds 0 ⋅ NF VA V ds – V dseff  V ds – V dseff  V ds – V dseff
I ds = --------------------------------- ⋅ 1 + ------------ ⋅ ln  -------------- ⋅  1 + -----------------------------
1
- ⋅ 1 + -----------------------------
- ⋅ 1 + -----------------------------
-
R ds ⋅ I ds 0 C clm  V Asat   V ADIBL   V ADITS   V ASCBE 
1 + -----------------------
V dseff
where
V dseff
W eff ⋅ µ eff ⋅ C oxeff ⋅ V gsteff ⋅  1 – A bulk ⋅ ------------------------------------------------- ⋅ V dseff
 2 ⋅ ( V gsteff + 2 ⋅ V t )
I dso = -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L eff ⋅ [ 1 + V dseff ⁄ ( E sat ⋅ L eff ) ]
V A = V Asat + C clm ⋅ ( V ds – V dseff )
R ds ⋅ I ds 0  V dsat 1
C clm = ------------------- ⋅ F ⋅ F PVAG ⋅  1 + ----------------------
1
- ⋅ L + ------------- ⋅ -------
PCLM  V dseff   eff E sat  l itl

1
F = ------------------------------------------------------------------------------
L eff
1 + FPROUT ⋅ -------------------------------------
V gsteff + 2 ⋅ V t
V gsteff
F PVAG =  1 + PVAG ⋅ -------------------------
 E sat ⋅ L eff
( V gsteff + 2 ⋅ V t ) A bulk ⋅ V dsat

V ADIBL = --------------------------------------------------------------------------------- ⋅  1 – ---------------------------------------------------------------------------
- ⋅ F PVAG
θ rout ⋅ ( 1 + PDIBLCB ⋅ V bseff )  A bulk ⋅ V dsat + V gsteff + 2 ⋅ V t
PDIBLC 1
θ rout = ----------------------------------------------------------------------------- + PDIBLC 2
L eff
2 ⋅  cosh  DROUT ⋅ --------- – 1
  lt0  
– PSCBE 1 ⋅ l itl
-------------------- = ------------------------- ⋅ exp  ----------------------------------------
1 PSCBE 2
V ASCBE L eff  V ds – V dseff 
A bulk ⋅ V dsat
E sat ⋅ L eff + V dsat + 2 ⋅ R ds ⋅ VSAT ⋅ Coxe ⋅ W eff ⋅ V gsteff ⋅ 1 – ------------------------------------------------ -
2 ⋅ ( V gsteff + 2 ⋅ V t )
V Asat = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2 ⁄ λ – 1 + R ds ⋅ VSAT ⋅ C oxe ⋅ W eff ⋅ A bulk
ε si ⋅ TOXE ⋅ XJ
l itl = -----------------------------------------
EPSROX
1
V ADITS = -------------------- ⋅ F ⋅ [ 1 + ( 1 + PDITSL ⋅ L eff ) ⋅ exp ( PDITSD ⋅ V ds ) ]
PDITS
C oxe ⋅ C cen
C oxeff = ----------------------------
-
C oxe + C cen
ε si
C cen = ----------
-
X DC
–9
1.9 × 10
X DC = -------------------------------------------------------------------------------------------------------
-
 V gsteff + 4 ⋅ ( VTH 0 – VFB – φ s ) 0.7
1 + -----------------------------------------------------------------------------------
 2 ⋅ TOXP 
A source end velocity limit model is introduced to account for the current saturation mechanism due to
the high electric field and strong velocity overshoot in nanoscale MOSFETs. It is supported in all ver-
sions of BSIM4 and is turned on if the model parameter VTL is set to a positive value. VTL defaults to
0:
I ds
I′ ds = --------------------------------------------------------------------
-
ν 2 ⋅ MM 1 ⁄ ( 2 ⋅ MM )
1 +  ------------
sHD
 ν sBT 
where
I ds
ν sHD = ---------------------------------------------------
-
V gsteff ⋅ C oxeff ⋅ W eff
1–r L eff
ν sBT = ------------ ⋅ VTL and r = --------------------------------------
1+r XN ⋅ L eff + LC

MM = 2 is a constant value.
Substrate Currents
Impact Ionization Current
I sub =  -------------------------- + ALPHA 1 ⋅ ( V ds – V dseff ) ⋅ exp  – ------------------------------ ⋅ I dsNoSCBE

ALPHA 0 BETA 0
 L eff   V ds – V dseff
I ds 0 ⋅ NF VA V ds – V dseff  V ds – V dseff
I dsNoSCBE = --------------------------------- ⋅ 1 + ------------ ⋅ ln  -------------- ⋅  1 + -----------------------------
1
- ⋅ 1 + -----------------------------
-
R ds ⋅ I ds 0 C clm  V Asat   V ADIBL   V ADITS 
1 + -----------------------
V dseff
Gate-Induced Drain Leakage (GIDL) Current

3
V ds – V gseff – EGIDL 3 ⋅ TOXE ⋅ BGIDL V db
I GIDL = AGIDL ⋅ W effcj ⋅ NF ⋅ --------------------------------------------------------- ⋅ exp  – --------------------------------------------------------- ⋅ ------------------------------------
-
3 ⋅ TOXE V ds – V gseff – EGIDL CGIDL + V 3
db
The equivalent expression for the Gate-Induced Source Leakage (GISL) current has been added to
make the gate induced leakage component of the substrate current symmetric:
3
– V ds – V gdeff – EGIDL 3 ⋅ TOXE ⋅ BGIDL V sb
I GISL = AGIDL ⋅ W effcj ⋅ NF ⋅ ------------------------------------------------------------- ⋅ exp  – -------------------------------------------------------------- ⋅ ------------------------------------
-
3 ⋅ TOXE  – V ds – V gdeff – EGIDL CGIDL + V3
sb
Gate Direct Tunneling Currents (optional)
Two global selectors are provided to turn on/off the tunneling components. Igcmod=1 turns on Igcs,
Igcd, Igs and Igd. Igbmod=1 turns on Igb.
Voltage Across Oxide

V ox = V oxacc + V oxdepinv
V oxacc = V fbzb + V FBeff
V oxdepinv = K 1 ox ⋅ Φ s + V gsteff
where
1 2
V FBeff = V fbzb – --- ⋅ ( V fbzb – V gb – δ + ( V fbzb – V gb – δ ) + 4 ⋅ δ ⋅ V fbzb ) ( δ = 0.02 )
2

V fbzb = V th 0 – Φ s – K 1 ⋅ Φ s ( V th 0 is the threshold voltage at Vbs=0 and Vds=0)
K 1 ox 4
Φ s = ------------ ⋅ 1 + ------------
2
⋅ ( V gseff – V gsteff – V FBeff – V bseff ) – 1
2 K 1 ox
Gate-to-Substrate Current
I gb = I gbacc + I gbinv
where
I gbacc = W eff ⋅ L eff ⋅ A ⋅ T oxRatio ⋅ V gb ⋅ V aux

⋅ exp [ – B ⋅ TOXE ⋅ ( AIGBACC – BIGBACC ⋅ V oxacc ) ⋅ ( 1 + CIGBACC ⋅ Voxacc ) ]
–2 2 0.5
A=4.97232e-7 A ⋅ V and B=7.45669e11 ( g ⁄ ( Fs ) )
NTOX
T oxRatio =  ---------------------------
TOXREF 1
⋅ -------------------2-
 TOXE  TOXE
V gb – V fbzb  
V aux = NIGBACC ⋅ V t ⋅ log  1 + exp  – -----------------------------------------
-
  NIGBACC ⋅ V t 
and
I gbinv = W eff ⋅ L eff ⋅ A ⋅ T oxRatio ⋅ V gb ⋅ V aux
⋅ exp [ – B ⋅ TOXE ⋅ ( AIGBINV – BIGBINV ⋅ V oxdepinv ) ⋅ ( 1 + CIGBINV ⋅ V oxdepinv ) ]
–2 2 0.5
A=3.75956e-7 A ⋅ V and B=9.82222e11 ( g ⁄ ( Fs ) )
V oxdepinv – EIGBINV
V aux = NIGBINV ⋅ V t ⋅ log  1 + exp  ----------------------------------------------------------- 
  EIGBINV ⋅ V t 
Gate-to-Channel Currents
–4
PIGCD ⋅ V ds + exp ( – PIGCD ⋅ Vds ) – 1 + 10
I gcs = I gc ⋅ -----------------------------------------------------------------------------------------------------------------------
2 –4
-
( PIGCD ⋅ V ds ) + 2.0 × 10
–4
1 – ( PIGCD ⋅ Vds + 1 ) ⋅ exp ( – PIGCD ⋅ V ds ) + 10
I gcd = I gc ⋅ ------------------------------------------------------------------------------------------------------------------------------------
2 –4
-
( PIGCD ⋅ V ds ) + 2.0 × 10
where
I gc = W eff ⋅ L eff ⋅ A ⋅ T oxRatio ⋅ V gseff ⋅ V aux
⋅ exp [ – B ⋅ TOXE ⋅ ( AIGC – BIGC ⋅ V oxdepinv ) ⋅ ( 1 + CIGC ⋅ V oxdepinv ) ]
–2 –2
A=4.97232e-7 A ⋅ V for NMOS and A=3.42537e-7 A ⋅ V for PMOS
2 0.5 2 0.5
B=7.45669e11 ( g ⁄ ( Fs ) ) for NMOS and B=1.16645e12 ( g ⁄ ( Fs ) ) for PMOS
V gseff – VTH 0
V aux = NIGC ⋅ V t ⋅ log  1 + exp  -------------------------------------- 
  NIGC ⋅ V t  
The model parameter PIGCD is not specified, it is calculated by:

B ⋅ TOXE  V dseff 
- ⋅ 1 – -----------------------
PIGCD = -------------------------- -
V gsteff
2  2 ⋅ V gsteff
The Gate-to-Channel currents are expressed as functions of V dseff instead of V ds to account for the
saturation effect observed at high Vds:
–4
PIGCD ⋅ V dseff + exp ( – PIGCD ⋅ V dseff ) – 1 + 10
I gcs = I gc ⋅ -----------------------------------------------------------------------------------------------------------------------------------
2 –4
-
( PIGCD ⋅ Vdseff ) + 2.0 × 10
–4
1 – ( PIGCD ⋅ Vdseff + 1 ) ⋅ exp ( – PIGCD ⋅ V dseff ) + 10
I gcd = I gc ⋅ -----------------------------------------------------------------------------------------------------------------------------------------------
2 –4
-
( PIGCD ⋅ V dseff ) + 2.0 × 10
Gate-to-S/D Currents
I gs = W eff ⋅ DLCIG ⋅ A ⋅ T oxRatioEdge ⋅ V gs ⋅ V′ gs
⋅ exp [ – B ⋅ TOXE ⋅ POXEDGE ⋅ ( AIGSD – BIGSD ⋅ V′ gs ) ⋅ ( 1 + CIGSD ⋅ V′ gs ) ]
and
I gd = W eff ⋅ DLCIG ⋅ A ⋅ T oxRatioEdge ⋅ V gd ⋅ V′ gd
⋅ exp [ – B ⋅ TOXE ⋅ POXEDGE ⋅ ( AIGSD – BIGSD ⋅ V′ gd ) ⋅ ( 1 + CIGSD ⋅ V′ gd ) ]
where
–2 –2
A=4.97232e-7 A ⋅ V for NMOS and A=3.42537e-7 A ⋅ V for PMOS
2 0.5 2 0.5
B=7.45669e11 ( g ⁄ ( Fs ) ) for NMOS and B=1.16645e12 ( g ⁄ ( Fs ) ) for PMOS
NTOX
T oxRatioEdge =  -------------------------------------------------------
TOXREF 1
⋅ --------------------------------------------------------------2-
 TOXE ⋅ POXEDGE ( TOXE ⋅ POXEDGE )
2 –4
V′ gd = ( V gd – V fbzd ) + 10
2 –4
V′ gs = ( V gs – V fbzd ) + 10
the expression of V fbsd is given in the “Temperature Equations” section.
14.7.7: Capacitance Model Equations

BSIM4 provides three options for selecting intrinsic and overlap/fringing capacitance models. Those
three capacitance models come from BSIM3v3.2.2.
The following table maps the BSIM4 CV models to those implemented in BSIM3v3.2.2:
Matched Intrinsic CAPMOD in Matched Overlap/fringing CAPMOD in

CAPMOD in BSIM4
BSIM3v3.2.2 BSIM3v3.2.2
0 0 0
1 2 2
2 (default) 3 2

Gate Electrode and Intrinsic-Input Resistance

In BSIM4, four options are available:
RgateMod = 0 (zero-resistance)
In this case, no gate resistance is generated.
RgateMod = 1 (constant-resistance)
W effcj 
RSHG ⋅  XGW + ------------------------------- -
 3 ⋅ NGCON
Rgeltd = -------------------------------------------------------------------------------------
NGCON ⋅ ( L drawn – XGL ) ⋅ NF
RgateMod = 2 (IIR model with variable resistance)
I ds W eff ⋅ µ eff ⋅ C oxeff ⋅ V t

------- = XRCRG 1 ⋅  --------------
- + XRCRG 2 ⋅ -------------------------------------------------------
1
R ii  V dseff L eff 
RgateMod = 3 (IIR model with two nodes)

For these two latter cases, NQS models should be deactivated (TrnqsMod=0 and AcnqsMod=0).
Substrate Resistance Network

The model selector RbodyMod can be used to turn on/off the resistance network.
RbodyMod = 0 (Off)
No substrate resistance network is generated.
RbodyMod = 0 (On)
All five resistances in the substrate network are present simultaneously:
14.7.8: Asymmetric MOS Junction Diode Models

In this section, x stands for S or D because expressions are similar for the source and drain sides.
Effective Junction Area and Perimeter

If Ax is given
Ax eff = Ax
otherwise
Ax eff is computed from NF, DWJ, GeoMod, DMCG, DMCI, DMDG, DMCGT and MIN.

If Px is given
if (PerMod = 0) Px eff = Px else Px eff = Px – NF ⋅ W effcj
otherwise
Px eff is computed from NF, DWJ, GeoMod, DMCG, DMCI, DMDG, DMCGT and MIN.
Junction Diode IV Model

Saturation Current
I sbx = J sx ( T ) ⋅ Ax eff + J sswx ( T ) ⋅ Px eff + J sswgx ( T ) ⋅ NF ⋅ W effcj
DioMod=0 (resistance-free)
V bx
I bx = I sbx ⋅ exp  -------------------------------
- – 1 ⋅ f breakdown + V bx ⋅ GMIN
 NJx ⋅ V tnom
where
BVx + V bx 
f breakdown = 1 + XJBVx ⋅ exp  – -------------------------------
-
DioMod=1 (breakdown-free)
IJTHxFWD > 0 (Current limiting feature)
Define
V jxm = NJx ⋅ V tnom ⋅ ln  1 + -----------------------------------

IJTHxFWD
 I sbx 
If V bx < V jxm
V bx
I bx = I sbx ⋅ exp  -------------------------------
- – 1 + V bx ⋅ GMIN
otherwise
IJTHxFWD + I sbx
I bx = IJTHxFWD + --------------------------------------------------- ⋅ ( V bx – V jxm )
NJx ⋅ Vtnom
IJTHxFWD ≤ 0 (resistance- and breakdown-free model)
V bx
I bx = I sbx ⋅ exp  -------------------------------
- – 1 + V bx ⋅ GMIN
DioMod=2 (resistance and breakdown)

In this case, the expressions corresponding to noimod=0 are used along with the exponential term lin-
earization in the forward-bias mode (IJTHxFWD) and in the reverse-bias mode (IJTHxREV), as
described in the preceding paragraph.

Junction Diode CV Model

C bx = C jbx ⋅ Ax eff + C jbxsw ⋅ Px eff + C jbxswg ⋅ N F ⋅ W effcj
If V bx < 0
V bx  – MJx
C jbx = CJx ( T ) ⋅  1 – --------------------
-
 PBx ( T )
V bx – MJSWx
C jbxsw = CJSWx ( T ) ⋅  1 – -------------------------------
 PBSWx ( T ) 
V bx – MJSWGx
C jbxswg = CJSWGx ( T ) ⋅  1 – ------------------------------------ 
 PBSWGx ( T )
otherwise
V bx
C jbx = CJx ( T ) ⋅  1 + MJx ⋅ ---------------------
 PBx ( T )
V bx
C jbxsw = CJSWx ( T ) ⋅  1 + MJSWx ⋅ -------------------------------
 PBSWx ( T )
V bx
C jbxswg = CJSWGx ( T ) ⋅  1 + MJSWGx ⋅ ------------------------------------
 PBSWGx ( T )
14.7.9: Source/Drain Diffusion Resistance

If RgeoMod=0, the source diffusion resistance is not generated.
If NRS is given,
R sdiff = NRS ⋅ RSH
otherwise
R sdiff is computed from NF, DWJ, GeoMod, DMCG, DMCI, DMDG, DMCGT, RSH and MIN.
If RgeoMod=0, the drain diffusion resistance is not generated.

If NRD is given,
R ddiff = NRD ⋅ RSH
otherwise
R ddiff is computed from NF, DWJ, GeoMod, DMCG, DMCI, DMDG, DMCGT, RSH and MIN.

14.8: BJT Modeling

14.8.1: Gummel-Poon BJT Model Equations
DC Current Equations
The “eff” suffix on a parameter indicates that the parameter is temperature and geometry scaled. See
the temperature effects equations below.
The DC characteristics of the BJT transistor are determined by 20 model parameters.
Define:
Forward diffusion current:
vbe
IS eff  --------------------
ibf = ------------ ⋅ e NF ⋅ vt – 1
BF  
The current equations for the collector current (ic) and the base current (ib) are:
ib = ibf
Base Charge Equations

The parameters VAF and VAR represent the forward and reverse Early voltages. The parameters IKF
and IKR determine the high current BF roll-off. ISE, NI, ISC, and NC determine the low current BF
roll-off.
Base charge factor qb is determined as follows:
1
q 1 = ------------------------------------------------
 1 – ------------
vbc
- – -------------
vbe
 VAF VAR
Substrate Current Equations

The substrate current flows from the substrate to the collector for vertical transistors and substrate to
base for lateral transistors.
For vertical transistors:
vbs
 ------------------
- 
⋅ vt
ibs = ISS eff ⋅  e – 1
NS
when vbs > -10 · NS · vt
 
 
and:
ibs = – I SS eff when vbs ≤ -10 · NS · vt

Variable Base Resistance Equations

SMARTSPICE incorporates the well known variable base resistance model. There are three parameters in
the model: RB, IRB, and RBM. RB is base resistance for low currents (low injection level). RBM is base
resistance for high base currents (high injection level). IRB is the base current at which the base
resistance equals (RB + RBM)/2.
If IRB is not specified:
rbb = RBMeff +  ----------------------------------------------

RBeff – RBMeff
 qb 
otherwise
tan ( z ) – z
rbb = RBMeff + 3 ⋅ RBeff – RBMeff ⋅ -------------------------------------------
z ⋅ tan ( z ) ⋅ tan ( z )
where:
1⁄2
ib
– 1 + 1 + 144 ⋅ ----------------------------- -
π 2 ⋅ IRBeff
z = -----------------------------------------------------------------------------
1⁄2
-
24  ib 
-----2- ⋅ ------------------------
n  ( IRBeff )
Capacitance Equations
The total junction capacitance is computed as a sum of the depletion and diffusion capacitances. The
depletion capacitance dominates low current behavior. The diffusion capacitance dominates high
current behavior.
In the following equations, for depletion capacitance:
fc = FC
Base Emitter Capacitance Equations

The base-emitter capacitance is computed as a sum of diffusion and depletion capacitance.
cbe = cbediff + cbedep
Base-Emitter Diffusion Capacitance

Model parameters TF, XTF, ITF, and VTF can be used to modify the diffusion capacitance:
∂
cbediff = -------------  TF ⋅ --------
ibe
for ibe ≤ 0
∂vbe  qb 
∂ ibe
cbediff = ------------- TF ⋅ ( TF + 1 arg tf ) ⋅ -------- for ibe > 0
∂vbe qb
where:

vbc
----------------------------
2 1.44 ⋅ VTF
arg tf = XTF ⋅  -------------------------- ⋅ e
ibe
 ibe + ITF
Internal base-emitter current is determined by:

vbe
--------------------
 NE ⋅ vt 
ibe = ISeff ⋅ e –1
 
Base-Emitter Depletion Capacitance

The following equations model the base-emitter depletion capacitance.
vbe – MJE
cbedep = CJEeff ⋅  1 – ------------ for vbe < fc · VJE
 VJE
vbe
1 – fc ⋅ ( 1 + MJE ) + MJE ⋅ ------------
VJE for vbe ≥ fc · VJE
cbedep = CJEeff ⋅ -----------------------------------------------------------------------------------
( 1 + MJE )
-
( 1 – fc )
Base-Collector Capacitance Equations

The base-collector capacitance is computed as a sum of the depletion and diffusion capacitances.
cbc = cbcdiff + cbcdep
Base-Collector Diffusion Capacitance

The diffusion capacitance is modeled by model parameter TR:
∂
cbcdiff = ------------- ( TR ⋅ ibc )
∂vbc
where:
vbc
--------------------
 NR ⋅ vt 
ibc = ISeff ⋅ e –1
 
Base-Collector Depletion Capacitance

The following equations model the base-collector depletion capacitance.
vbc –MJC
cbcdep = XCJC ⋅ CJCeff ⋅  1 – ------------ for vbc < fc · VJC
 VJC
vbc
1 – fc ⋅ 1 + MJC + MJC ⋅ ------------
VJC
cbcdep = XCJC ⋅ CJCeff ⋅ ------------------------------------------------------------------------------- for vbc ≥ fc · VJC
( 1 – fc ) ( 1 + MJC )

External Base-Internal Collector Junction Capacitance

Parameter XCJC is used to model the base-collector capacitance as a distributed capacitance. When
XCJC is set to one, the entire base-collector capacitance is connected to the internal base node.
vbcx –MJC
cbcx = CJCeff ⋅ ( 1 – XCJC ) ⋅  1 – ------------- for vbcx < fc · VJC
 VJC 
vbcx
1 – fc ⋅ ( 1 + MJC ) + MJC ⋅ -------------
VJC
cbcx = CJCeff ⋅ ( 1 – XCJC ) ⋅ ------------------------------------------------------------------------------------
- for vbcx ≥ fc · VJC
( 1 – fc ) ( 1 + MJC )
Substrate Capacitance
– MJS
cs = CJSeff ⋅  1 – ------------
vs
for vs < fc · VJS
 VJS
vs
1 – fc ⋅ 1 + MJS + MJS ⋅ ------------
VJS
cs = CJSCeff ⋅ -----------------------------------------------------------------------------
( 1 + MJS )
- for vs ≥ fc · VJS
( 1 – fc )
where:
ccs = cs
vs = vsc
Temperature Effects Equations

SMARTSPICE contains a number of temperature equations. These equations model the temperature
dependence of various model parameters. Temperature model selection parameters TEMPLEV and
TEMPLEVC can be used to select different temperature models.
For energy gap width:
2
t
EG ( t ) = EG ( 0 ) – gap 1 ⋅ ---------------------------
( t + gap 2 )
where:
EG(0) = 1.16, gap1 = 7.02E-4, gap2 =1108.0
Define:
f = -------------------------- – ------------- + XTI ⋅ 1 n  ---------------

EG EG t
vt ( tnom ) vt ( t )  tnom
Saturation Currents and Current Gain

XTB
BF ( t ) = BF ⋅  ---------------
t
 tnom

XTB
BR ( t ) = BR ⋅  ---------------
t
 tnom
f
---------
ISE NE
ISE ( t ) = ------------------------------
XTB
⋅ e
 --------------
t 
-
 tnom
f
ISC ---------
ISC ( t ) = -----------------------------
- ⋅ e NC
XTB
 ---------------
t
 tnom
f
ISS ---------
ISS ( t ) = ------------------------------
XTB
⋅ e NS
 --------------
t 
-
 tnom
IS ( t ) = IS ⋅ e f
f
---------
IBE ( t ) = IBE ⋅ e NF
f
---------
IBC ( t ) = IBC ⋅ e NR
IKF ( t ) = IKF ⋅ ( 1 + TIKF 1 ⋅ ∆t + TIKF 2 ⋅ ∆t 2 )
IKR ( t ) = IKR ⋅ ( 1 + TIKR 1 ⋅ ∆t + TIKR 2 ⋅ ∆t 2 )
IRB ( t ) = IRB ⋅ ( 1 + TIRB 1 ⋅ ∆t + TIRB 2 ⋅ ∆t 2 )
IKF ( t ) = IKF ⋅ ( 1 + TIKF 1 ⋅ ∆t + TIKF 2 ⋅ ∆t 2 )
IKR ( t ) = IKR ⋅ ( 1 + TIKR 1 ⋅ ∆t + TIKR 2 ⋅ ∆t 2 )
IRB ( t ) = IRB ⋅ ( 1 + TIRB 1 ⋅ ∆t + TIRB 2 ⋅ ∆t 2 )
Capacitance Temperature Equations

SMARTSPICE uses different sets of equations to model the temperature effects of the contact potential.
In the following equations, “X” stands for E, C, or S (emitter, collector, or substrate).
t t EG ( tnom ) EG ( t )
VJX ( t ) = VJX ⋅ --------------- – vt ( t ) ⋅ 3 ⋅ 1 n --------------- + ----------------------------- – ----------------
tnom tnom vt ( tnom ) vt ( t )
VJX ( t )
CJX ( t ) = CJXO ⋅ 1 + MJX ⋅  4 ⋅ 10 e – 4 ⋅ ∆t – -------------------- + 1
 VJX 
VJSW ( t )
CJSW ( t ) = CJSW ⋅ 1 + MJSW ⋅  4 ⋅ 10 e – 4 ⋅ ∆t – ------------------------- + 1
 VHSW 

Basic DC Model Parameters
Parameter Description Units Default Area
(TYPE) +1 for NPN

-1 for NPN
IS Saturation current A 1.0E-16 *
BF Maximum forward current gain 100
NF Forward current emission coeffi- 1.0

cient
BR Maximum reverse current gain 1.0
NR Reverse current emission coefficient 1.0
Low Current Beta Degradation Parameters
ISE B-E leakage saturation current A 0 *
NE B-E leakage emission coefficient 1.5
ISC B-C leakage saturation current A 0 *
NC B-C leakage emission coefficient 1.5

Base Width Modulation Parameters (Early Effect)
VAF Forward early voltage V infinite
VAR Reverse early voltage V infinite
High Current Beta Degradation Effect Parameters
IKF Forward knee current A infinite *
IKR Reverse knee current A infinite *
NK (NKF) Knee current roll-off coefficient 0.5
Parasitic Resistor Parameters
Parameters Description Units Default Area
RB Low bias base resistance Ohm 0 *
RBM High bias base resistance Ohm RB *
IRB Current where base resistance A infinite *

equals (RB + RBM)/2
RE Emitter resistance Ohm 0 *
RC Collector resistance Ohm 0 *
Junction Capacitor Parameters
CJE B-E zero-bias depletion capacitance F 0 *
VJE B-E built-in potential V 0.75
MJE B-E junction exponential factor 0.33
FC Coefficient for forward-bias depletion 0.5

capacitance formula
CJC B-C zero-bias depletion capacitance F 0 *
VJC B-C built-in potential V 0.75
MJC B-C junction exponential factor 0.33

XCJC Fraction of B-C depletion capacitance 1

connected to internal base node
CJS (CJB) Zero-bias substrate junction capacitance F 0 *
VJS (VJB) Substrate junction built-in potential V 0.75
MJS(MJB) Substrate junction exponential factor 0.5
Substrate Current Parameters
Parameters Description Units Default Area
ISS Substrate saturation current A 0 *
NS Substrate current emission factor 1.0
Transit Time Parameters
TF Forward transit time sec 0
XTF Fitting coefficient for TF 0
ITF Coefficient for TF current dependence A 0 *
VTF Coefficient for TF voltage dependence V infinite
TR Reverse transit time sec 0
Xtb Forward and Reverse Temperature 0

exponent
Eg Energy Gap eV 1.16
XTi Temperature component of IS 3
TNOM Nominal Temperature K 300 Ti
One can download Silvaco’s Verilog-A implementation of the Gummel-Poon BJT Model at
www.silvaco.com.

14.9: Mextram Transistor Model (LEVEL=504)

Mextram level 504 is implemented to be compliant to the Philips Nat. lab unclassified report, “The
Mextram Bipolar Transistor Model LEVEL 504”, issued in December 2002.
Details and news on Mextram are available on Philips Semiconductors web site (http://
www.semiconductors.philips.com/Philips_Models/).
The large signal equivalent circuit is shown below (please note the addition of overlap capacitances
QBCO and QBEO):
RE E1 In C2 Ic1c2 C1 RCC
E C
Ib1+Ib2 Iavl
Qte+Qbe+Qn Qtc+Qbc+Qepi
B2
Qb1b2 RBV
Ib1b2
ISb1 Iex+Isub+Ib3 Isub+XIsub-Isf
B1 S
SQte Qtex+Qex
Qts
RBC XIex+XIsub
XQtex+XQex
Qbeo Qbco
Figure 14-5: Equivalent Circuit for Large Signal Analysis


.
MULT Multiplication factor - 1
TREF Reference temperature °C 27
DTA Difference of the device temp. to ambient temperature °C 0
EXMOD Flag for extended modelling of the reverse current gain - 1
EXPHI Flag for the distributed high frequency effects in transient - 1
EXAVL Flag for extended modelling of avalanche currents - 0
IS Collector-emitter saturation current A 22E-18
IK Collector-emitter high injection knee current A 0.10
VER Reverse Early voltage V 2.50
VEF Forward Early voltage V 44.00
BF Ideal forward current gain - 215.00
IBF Saturation current of the non-ideal forward base current A 2.7E-15
MLF Non-ideality factor of the non-ideal forward base current - 2.00
XIBI Part of ideal base current taht belongs to the sidewall - 0.00
BRI Ideal reverse current gain - 7.00
IBR Saturation current of the non-ideal reverse base current A 1.0E-15
VLR Cross-over voltage of the non-ideal reverse base current V 0.20
XEXT Part of IEX, QEX, QTEX and ISUB that depends on the base- - 0.63
collector voltage VBC1 instead of VB1C1
WAVL Epilayer thickness used in weak-avalanche model m 1.1E-6
VAVL Voltage determining curvature of avalanche model V 3.00
SFH Current spreading factor of avalanche model (Used if - 0.30

EXAVL=1)
RE Emitter resistance Ω 5.00
RBC Constant part of the base resistance Ω 23.00
RBV Variable part of the base resistance at zero bias Ω 18.00
RCC Constant part of the collector resistance Ω 12.00
RCV Resistance of the unmodulated epilayer Ω 150.00

SCRCV Space charge resistance of the epilayer Ω 1250.0
IHC Critical current for velocity saturation in the epilayer A 4.0E-3
AXI Smoothness parameter for the onset of quasi-saturation - 0.30
CJE Zero bias emitter-base depletion capacitance F 73E-15
VDE Emitter-base diffusion voltage V 0.95
PE Emitter-base grading coefficient - 0.40
XCJE Fraction of the emitter-base depletion capacitance that - 0.40

belongs to the sidewall
CJC Zero bias collector-base depletion capacitance F 78E-15
VDC Collector-base diffusion voltage V 0.68
PC Collector-base grading coefficient - 0.5
XP Constant part of CJC - 0.35
MC Collector current modulation coefficient - 0.5
XCJC Fraction of the collector-base depletion capacitance under - 32.0E-3

the emitter area
MTAU Non-ideality factor of the emitter stored charge - 1.00
TAUE Minimum transit time of stored emitter charge s 2.0E-12
TAUB Transit time of stored base charge s 4.2E-12
TEPI Transit time of stored epilayer charge s 41E-12
TAUR Transit time of reverse extrinsic stored base charge s 520E-12
DEG Bandgap difference over the base eV 0.0
XREC Pre-factor of the recombination part of IB1 - 0.0
AQB0 Temperature coefficient of the zero bias base charge - 0.30
AE Temperature coefficient of the resistivity of the emitter - 0.0
AB Temperature coefficient of the resistivity of the base - 1.00
AEPI Temperature coefficient of the resistivity of the epilayer - 2.50
AEX Temperature coefficient of the resistivity of the extrinsic - 0.62

base
AC Temperature coefficient of the resistivity of the buried layer - 2.00
DVGBF Bandgap voltage difference of forward current gain V 50.0E-3
DVGBR Bandgap voltage difference of reverse current gain V 45.0E-3
VGB Bandgap voltage of the base V 1.17

VGC Bandgap voltage of the collector V 1.18
VGJ Bandgap voltage recombination emitter-base junction V 1.15
DVGTE Bandgap voltage difference of emitter stored charge V 0.05
AF Flickernoise exponent - 2.00
KF Flickernoise coefficient ideal base current - 20E-12
KFN Flickernoise coefficient non-ideal base current - 20E-12
ISS Base-substrate saturation current A 48E-18
IKS Base-substrate high injection knee current A 250E-6
CJS Zero bias collector-substrate depletion capacitance F 315E-15
VDS Collector-substrate diffusion voltage V 0.62
PS Collector-substrate grading coefficient - 0.34
VGS Bandgap voltage of the substrate V 1.20
AS For a closed buried layer : AS = AC - 1.58

For an open buried layer : AS = AEPI
RTH Thermal resistance °C /W 300.00
CTH Thermal capacitance J/ °C 3.00E-9
CBEO Emitter-base overlap capacitance F 0.0
CBCO Collector-base overlap capacitance F 0.0
14.9.2: Model constants

MC_AJE = 3.0
MC_AJC = 2.0
MC_AJS = 2.0
Constants A and B for impact ionization depend on transistor type:
For NPN:
MC_An = 7.03 · 105 cm-1
MC_Bn = 1.23 · 106 V · cm-1
For PNP:
MC_An = 1.58 · 106 cm-1
MC_Bn = 2.04 · 106 V · cm-1

14.9.3: Temperature scaling

The reference temperature is TREF (in °C ). The simulation temperature is computed from TEMP
and DTEMP (instance parameters), and from the model parameter DTA (all values specified in °C ).
Temperature conversions
TK = TEMP + DTA + 273.15 + VdT
(VdT is the voltage of the thermal node, if used)

TRK = TREF + 273.15
TK
T N = -------------
TRK
k
V T = --- ⋅ T K (Thermal voltage)
q
k
V TR = --- ⋅ T RK
q
1 1 1
---------- = ------- – ----------
V ∆T V T V TR
Resistances
–A
The various parameters A describe the mobility of the corresponding regions : µ ∼ t N . The
AQB 0
temperature dependence of the zero-bias charge goes as Q B 0 T ⁄ Q B 0 = t N.
RBCT = RBC · TNAEX
RBVT = RBV · TNAB
RCCT = RCC · TNAC
RCVT = RCV · TNAEPI
Depletion Capacitances
The junction diffusion voltage VDX with respect to temperature is:
VDX T = – 3 ⋅  --- ⋅ T K ⋅ ln ( T N ) + VDX ⋅ T N + ( 1 – T N ) ⋅ V GAP

k
 q
where:
 V GAP = VGB
for the base-emitter junction: 
 X = E

 V GAP = VGC
for the base-collector junction: 
 X = C
 V GAP = VGS
for the collector-substrate junction: 
 X = S
The temperature scaling rule is the same for depletion capacitances CJE and CJS:
PX
CJX T = CJX ⋅  ----------------
VDX
 VDX T
where PX is the grading coefficient.
The collector depletion capacitance is divided up in a variable and constant part. The constant part is
temperature independent.
 VDC PC 
CJC T = CJC ⋅  ( 1 – XP ) ⋅  ----------------- + XP 
 VDC T
 
CJC
XP T = XP ⋅ ---------------
CJC T
Current Gain
 DVGBF 
BF T = BF ⋅ T N ( AE – AB – AQB 0 ) ⋅ exp  – ----------------------- 
 V ∆T 
 DVGBR 
BRIT = BRI ⋅ exp  – ----------------------- 
 V ∆T 
Currents and Voltages
( 4 – AB – AQB 0 )
IS T = IS ⋅ T N ⋅ exp { – V GB ⁄ V ∆T }
( 1 – AB )
IK T = IK ⋅ T N
( 6 – 2 ⋅ MLF )
IBF T = IBF ⋅ T N ⋅ exp { ( – VGJ ) ⁄ ( MLF ⋅ V ∆T ) }
IBR T = IBR ⋅ T N 2 ⋅ exp { ( – VGC ) ⁄ ( 2 ⋅ V ∆T ) }
·
( AQB 0 ) VDC PC –1
VEF T = VEF ⋅ T N ( 1 – XP ) ⋅  ----------------- + XP
 VDC T

( AQB 0 )  VDE  – PE
VER T = VER ⋅ T N -----------------
 VDE T
VLR and VLF are assumed temperature independant.

( 4 – AS )
ISS T = ISS ⋅ T N ⋅ exp { ( – V GS ) ⁄ V ∆T }
( 1 – AS ) IS T ISS
IKS T = IKS ⋅ T N ⋅ --------- ⋅ -------------
IS ISS T
( 1 – AS )
When either IS = 0 or ISST = 0 then IKS T = IKS ⋅ T N .
Transit Times
( AB – 2 )
TAUE T = TAUE ⋅ T N ⋅ exp { ( – DVGTE ) ⁄ V ∆T }
( AQB 0 + AB – 1 )
TAUB T = TAUB ⋅ T N
( AEPI – 1 )
TEPI T = TEPI ⋅ T N
TAUBT + TEPI T
TAUR T = TAUR ⋅ ----------------------------------------------
TAUB + TEPI
Avalanche constant
Note that this temperature rule is independent of TREF since we take MC_BN as a material constant.
–4 –6 2
Bn T = MC_BN [ 1 + 7.2 ⋅ 10 ( T K – 300 ) – 1.6 ⋅ 10 ( T K – 300 ) ]
Heterojunction features
( AQB 0 )
DEG T = DEG ⋅ T N
14.9.4: Geometry scaling

The parameter MULT can be used to put transistors in parallel. The following parameters are affected
by the value of MULT :
IS, IK, IBF, IBR, IHC, ISS, IKS, CJE, CJC, CJS, CTH, CBEO, CBCO are multiplied by MULT
RE, RBC, RBV, RCC, RCV, SCRCV, RTH are divided by MULT
and the flicker-noise coefficients are scaled as :
( 1 – AF )
KF → KF ⋅ MULT
1 – [ 2 ( MLF – 1 ) + AF ( 2 – MLF ) ]
KFN → KFN ⋅ MULT

14.9.5: DC current Equations

Ideal forward and reverse current
V B2E1
I F = IS T ⋅ exp  --------------
 VT 
V∗ B 2 C 2
I R = IS T ⋅ exp  ------------------
 VT 
Model parameter: IS
The value of V∗ B 2 C 2 is not always the same as the node voltage VB2C2. The expression for
exp ( V∗ B 2 C 2 ⁄ V T ) will be given in variable collector resistance section.
Main Current IN
The Moll-Ross or integral charge-control relation is used to take into account high injection in the
base. To avoid dividing by zero at punch-through, the depletion charge term q0 is modified.
I VTE VTC
q 0 = 1 + ---------------- + ----------------
VER T VEF T
I I
I q 0 + ( q 0 ) 2 + 0.01
q 1 = -------------------------------------------------
2
= q 1 ⋅  1 + --- n 0 + --- n B
I I 1 1
q B
 2 2 
IF – IR
I N = ----------------
I
-
qB
Forward Base Currents

The total ideal base current is separated into a bulk and sidewall component. The bulk component
depends on voltage VB2E1 and the sidewall component on voltage VB1E1. The separation is given by
parameter XIBI.
Bulk component:
IS T  VB 2E 1 
I B 1 = ( 1 – XIBI ) ⋅ ----------- ⋅  exp  --------------- – 1 
BF T  VT 
Sidewall component:
IS T  VB1E1 
I B 1 = XIBI ⋅ ----------- ⋅  exp  --------------- – 1 
S
BF T   VT 

The non-ideal base current is given by:

 V B2E1 
I B 2 = IBF T ⋅  exp  -------------------------- – 1  + G MIN ⋅ V B 2 E 1
 MLF ⋅ V T
 
Model parameters: IS, BF, XIBI, IBF and MLF.
Reverse Base Currents
 VB 1C 1 
 exp  --------------- – 1 
  VT  
IB3 = IBR T ⋅  ---------------------------------------------------------------------  + G MIN ⋅ V B 1 C 1
V
 exp  --------------- + exp  ---------------- 
B 1 C 1 VLR T
  2 ⋅ VT   2 ⋅ VT  
 
The substrate current (holes injected from base to substrate), including high injection is given by:
 VB 1 C 1 
2 ⋅ ISS T ⋅  exp  --------------- – 1 
 VT 
 
I SUB = ---------------------------------------------------------------------------------------
IS T  VB1C1 
1 + 1 + 4 ⋅ -------------- ⋅  exp  --------------- 
IKS T   VT 

The current with substrate bias in forward is only included as a signal to the designer :
 V SC 1 
I SF = ISST ⋅  exp  ------------ – 1 
 VT 
 
The extrinsic base current (electrons injected from collector to extrinsic base, similar to IB1) is given
by:
VB 1 C 1
4 ⋅ IS T ⋅ exp  ---------------
 VT 
g 1 = ----------------------------------------------------
IK T
g1
n BEX = --------------------------------
-
( 1 + 1 + g1 )
n BEX derivatives are computed from an approximated equation : n Bex ≈ 1 + g 1 + 1
1 1 
I EX = -------------- ⋅  --- ⋅ IK T ⋅ n BEX – IS T 
BRI T  2 
Model parameters: IBR, VLR, ISS, IKS, BRI, IS, IK
Weak Avalanche Current

In reverse mode IC1C2 < 0 or hard saturation V B 2 C 1 ≥ VDC T the avalanche current is zero.
IAVL = 0

In forward mode we have the following gradient of the electric field for zero bias :
2 VAVL
dEdx 0 = ---------------------2
WAVL
The depletion layer thickness becomes :
2 VDC T – V B 2 C 1
XD = ----------------- ⋅ --------------------------------------
dEdx0 1 – I CAP ⁄ IHC
The current ICAP will be given in Intrisic collector depletion charge section.
The generation of avalanche current increases at high current levels. This is only taken into account
when flag EXAVL = 1.
When EXAVL = 0, then the effective thickness of the epilayer is :

WEff = WAVL
When EXAVL = 1, then :
Xi  2
W eff = WAVL ⋅  1 – --------------------
-
 2 ⋅ W EPI
For either value of EXAVL the thickness over which the electric field is important is :
x D ⋅ W eff
W D = --------------------------------
-
2 2
x D + W eff
The average electric field and the field at the base-collector junction are :
VDC T – V B 2 C 1
E AV = --------------------------------------
WD
I CAP
E 0 = E AV + --- ⋅ W D ⋅ dEdx0 ⋅  1 – -----------
1
-
2 IHC
When EXAVL = 0, then the maximum of the electric field is :

E M = E0
When EXAVL = 1, then
2⋅X
SH W = 1 + 2 ⋅ SFH ⋅  1 + --------------i 
 W EPI
1 + SFH
E fi = ------------------------------
1 + 2 ⋅ SFH
IC1 C2 
E W = E AV – --- ⋅ W D ⋅ dEdx 0 ⋅  E fi – -----------------------------
1
-
2  IHC ⋅ SHW
1 2 2
E M = --- ⋅ ( E W + E 0 + ( E W – E 0 ) + 0.1 ⋅ E AV ⋅ I CAP ⁄ IHC )
2
The injection thickness Xi / WEPI is given in Variable collector resistance section.

For either value of EXAVL the intersection point λ D and the generation factor GEM are :
EM ⋅ WD
λ D = ------------------------------------
-
2 ⋅ ( E M – E AV )
An  – B nT – B nT W eff 
G EM = ---------- ⋅ E M ⋅ λD ⋅  exp  ------------- – exp ------------- ⋅  1 + ----------
λ D  
-
B nT  EM  E 
 M
When E M ≈ E AV the expression for λ D will diverge. Hence for (1-EAV/EM) < 10-7 we need to take the
appropriate analytical limit and get :
– B nT
G EM = A n ⋅ W eff ⋅ exp  -------------
 EM 
The generation factor may not exceed 1 and may not exceed
I
VT qB RET
G MAX = ---------------------------------------------------------
- + ----------
- + ----------------------------------
-
I C 1 C 2 ⋅ ( RBC T + RB 2 ) BF T RBC T + RB 2
The variable base resistance RB2 at the end of section Variable base resistance. The base base charge
I
term q B was given in section Main current IN. The avalanche current then is :
G EM ⋅ G MAX
I AVL = I C 1 C 2 ⋅ --------------------------------------------------------------------
G EM ⋅ ( 1 + G MAX ) + G MAX
Series resistances:
emitter: RET = constant
base : RBCT = constant
collector: RCCT = constant
Variable Base Resistance

The variable part of the base resistance is modulated by the base charges and takes into account the
base current crowding:
Q V TE V TC
q 0 = 1 + ---------------
- + ---------------
-
VER T VEF T
Q Q 2
Q q 0 + ( q 0 ) + 0.01
q 1 = ----------------------------------------------------
-
2
3 ⋅ RBV T
RB 2 = -----------------------
Q
-
q B
2 ⋅ VT  VB 1B 2  VB 1B 2
I B 1 B 2 = -------------- ⋅  exp  --------------- – 1  + --------------
-
RB 2   VT 
 RB 2
Model parameters : RBV, VER, VEF.

Variable Collector Resistance

This model of the epilayer resistance takes into account:
• The decrease in resistance due to carriers injected from the base if only the internal base-collector
junction is forward biased (quasi-saturation) and if both the internal and external base-collector
junctions are forward biased (hard saturation and reverse mode of operation).
• Ohmic current flow at low current densities.
• Space charge limited current flow at high current densities (Kirk effect, only in forward mode).
The current through the epilayer is given by :
K0 = 1 + 4 ⋅ exp [ ( V B 2 C 2 – VDC T ) ⁄ V T ]
KW = 1 + 4 ⋅ exp [ ( V B 2 C 1 – VDC T ) ⁄ V T ]
2 ⋅ exp [ ( V B 2 C 1 – VDC T ) ⁄ V T ]
p W = ----------------------------------------------------------------------------
-
1 + KW
For numerical reasons, when pW < e-40 then p W → 0 .
1
In version 1, p W derivatives are computed from an approximated equation : p W ≈ --- ⋅ ( K W – 1 )
2
K0 + 1
E C = V T ⋅ K 0 – K W – ln  ------------------
 K W + 1
E C + VC 1 C 2
I C 1 C 2 = ----------------------------
-
RCV T
In reverse mode the node voltage difference VB2C2 is the quantity that we use in further calculations.
In forward mode the relation between the voltage difference VB2C2 and the current IC1C2 is not smooth
enough. We will instead calculate V∗ B 2 C 2 that is to be used in subsequent calculations. It has
smoother properties than VB2C2 itself. In forward mode the node voltage VC2 is only used for K0 and
IC1C2. For the rest of the quantities in the epilayer model a distinction must be made between forward
and reverse mode.
Forward mode (IC1C2 > 0)

The voltage and current at which quasi-saturation or Kirk effect start are :
I C 1 C 2 ⋅ RCV T
= VDC T + 2 ⋅ V T ⋅ ln  ----------------------------------
- + 1 – V B 2 C 1
th
V qs
 2 ⋅ VT 
1  th th 2 2
V qs = ---  V qs + ( V qs ) + 4 ⋅ ( 0.1 ⋅ VDC T ) 
2 
V qs V qs + IHC ⋅ SCRCV
I qs = ---------------------- ⋅ -------------------------------------------------------
SCRCV V qs + IHC ⋅ RCV

1 + AXI ⋅ ln { 1 + exp [ ( I C 1 C 2 ⁄ I qs – 1 ) ⁄ AXI ] }

α = -------------------------------------------------------------------------------------------------------------------
-
1 + AXI ⋅ ln { 1 + exp [ – 1 ⁄ AXI ] }
We need to solve :
V qs V qs + SCRCV ⋅ IHC ⋅ y i
α ⋅ I qs = ---------------------------------
- ⋅ ---------------------------------------------------------------
-
SCRCV ⋅ y i
2 V qs + RCV ⋅ IHC
which leads to
V qs
v = --------------------------------------
-
IHC ⋅ SCRCV
1 + 1 + 4 ⋅ α ⋅ v ⋅ (1 + v)
y i = ---------------------------------------------------------------
2 ⋅ α ⋅ (1 + v )
The injection thickness is given by :
xi yi
- = 1 – -------------------------
------------- -
W EPI 1 + pW ⋅ yi
The hole density p∗ 0 at the base-collector junction is
I C 1 C 2 ⋅ RCV xi
g = -------------------------------- ⋅ --------------
2 ⋅ VT W EPI
g–1 2
p∗ 0 = ------------ +  ------------ + 2 g + p W ⋅ ( p W + g + 1 )
g–1
2  2 
For numerical reasons, when p∗ 0 < e then p∗ 0 → 0

– 40
V∗ B 2C2 ⁄ V T
e = p∗ 0 ⋅ ( p∗ 0 + 1 ) ⋅ exp ( VDC T ⁄ V T )
Reverse mode (IC1C2 < 0)

The hole density at the base-collector junction is :
2 ⋅ exp { ( V B 2 C 2 – VDC T ) ⁄ V T }
p∗ 0 = ------------------------------------------------------------------------------
1 + K0
1
In version 1, p∗ 0 derivatives are computed from an approximated equation : p 0∗ ≈ --- ⋅ ( K 0 – 1 )
2
exp ( V∗ B 2 C 2 ⁄ V T ) = exp ( V B 2 C 2 ⁄ V T )
The injection thickness is :
xi EC
- = --------------------------------------------------
------------- -
W EPI EC + VB 2C 2 – V B 2 C 1

–5 – 40
Numerical problems might arise for I C 1 C 2 ≈ 0 . When V C 1 C 2 < 10 ⋅ V T or E C < e ⋅ VT ⋅ ( K0 + KW )
approximate
p∗ 0 + p W
p av = ----------------------
2
xi p av
- = -----------------
-------------
W EPI p av + 1
14.9.6: Description of charges

Emitter depletion charges
The total base-emitter depletion capacitance is separated into a bulk and sidewall component. The
bulk component is located between node E1 and node B2 and the sidewall component between nodes
B1 and E1 (see Fig. 2-19).
The bulk component is :

– 1 ⁄ PE
V FE = VDE T ⋅ ( 1 – a jE )
V jE = V B2E1 – 0.1 VDE T ⋅ ln { 1 + exp [ ( V B2E1 – V FE ) ⁄ 0.1 VDE T ] }
VDE T 1 – PE
V TE = ----------------- ⋅ [ 1 – ( 1 – V jE ⁄ VDE T ) ] + a jE ⋅ ( V B2E1 – V jE )
1 – PE
Q TE = ( 1 – XCJE ) ⋅ CJET ⋅ V TE
The sidewall component is :

S
V jE = V B1E1 – 0.1 VDE T ⋅ ln { 1 + exp [ ( V B1E1 – V FE ) ⁄ 0.1 VDE T ] }
VDE T
= XCJE ⋅ CJE T ⋅  ----------------- ⋅ [ 1 – ( 1 – V jE ⁄ VDE T ) ] + a jE ⋅ ( V B1E1 – V jE )
S S 1 – PE S
Q TE
 1 – PE 
Intrinsic collector depletion charge

In forward mode (IC1C2 > 0) then
1
B 1 = --- SCRCV ⋅ ( I C 1 C 2 – IHC )
2
B 2 = SCRCV ⋅ RCV T ⋅ IHC ⋅ I C 1 C 2
2
V xi = 0 = B 1 + B 1 + B2
In reverse mode (IC1C2 < 0) then

Vxi=0 = VC1C2
The junction voltage for the capacitance is given by

V junc = V B 2 C 1 + V xi = 0
0.1 VDC T IC 1C 2 ≤ 0

V ch =   IC 1 C2 
 VDC T ⋅  0.1 + 2 ⋅ --------------------------
I C 1 C 2 + I qs
- IC1 C2 > 0

a jc – XP T
b jc = -----------------------
-
1 – XP T
– 1 ⁄ PC
V FC = VDC T ⋅ ( 1 – bjc )
V jc = V junc – V ch ⋅ ln { 1 + exp [ ( V junc – V FC ) ⁄ V ch ] }
 IHC ⋅ I C 1 C 2
 -------------------------------- IC 1 C2 > 0
I CAP =  IHC + I C 1 C 2
I IC1 C2 ≤ 0
 C1C2
I CAP MC
f I =  1 – -----------
-
 IHC
VDC T 1 – PC
V CV = ----------------- ⋅ [ 1 – f I ⋅ ( 1 – V jc ⁄ VDC T ) ] + f I ⋅ b jc ⋅ ( V junc – V jc )
1 – PC
V TC = ( 1 – XP T ) ⋅ V CV + XP T ⋅ V B 2 C 1
Q TC = XCJC ⋅ CJC T ⋅ V TC
Extrinsic collector depletion charges

The extrinsic collector depletion charge is partitioned between nodes B1 and C1 and nodes B and C1
respectively, independent of flag EXMOD.
V jCE X = V B 1 C 1 – 0.1 VDC T ⋅ ln { 1 + exp [ ( V B 1 C 1 – V FC ) ⁄ 0.1 VDC T ] }
VDC T 1 – PC
VTEX V = ----------------- ⋅ [ 1 – ( 1 – V jCEX ⁄ VDC T ) ] + b jc ⋅ ( V B 1 C 1 – V jCEX )
1 – PC
Q TEX = CJC T ⋅ [ ( 1 – XP T ) ⋅ VTEX V + XP T ⋅ V B 1 C 1 ] ⋅ ( 1 – XCJC ) ⋅ ( 1 – XEXT )
XV jCEX = V BC 1 – 0.1 VDC T ⋅ ln { 1 + exp [ ( V BC 1 – V FC ) ⁄ 0.1 VDC T ] }
VDC T 1 – PC
XVTEX V = ----------------- ⋅ [ 1 – ( 1 – XV jCEX ⁄ VDC T ) ] + b jc ⋅ ( V BC 1 – XV jC EX )
1 – PC
XQ TEX = CJC T ⋅ [ ( 1 – XP T ) ⋅ XVTEX V + XP T ⋅ V BC 1 ] ⋅ ( 1 – XCJC ) ⋅ XEXT

Depletion charge
– 1 ⁄ PS
V FS = VDS T ⋅ ( 1 – ajs )
V jS = V SC 1 – 0.1 VDS T ⋅ ln { 1 + exp [ ( V SC 1 – V FS ) ⁄ 0.1 VDS T ] }
 VDS T 1 – PS 
Q TS = CJS T ⋅  ----------------- ⋅ [ 1 – ( 1 – V jS ⁄ VDC T ) ] + a js ⋅ ( V SC 1 – V jS ) 
 1 – PS 
Stored emitter charge

IS T 1 ⁄ MTAU
Q E 0 = TAUE T ⋅ IK T ⋅  ----------
 IK T
V B2E1 ⁄ MTAU ⋅ V T
QE = QE0 ⋅ ( e – 1)
Stored base charges

Q B 0 = TAUB T ⋅ IK T
4 ⋅ IS T V B2E1
f1 = ----------------- ⋅ exp  --------------
IK T  VT 
f1
n 0 = --------------------------
-
1 + 1 + f1
In version 1, n 0 derivatives are computed from an approximated equation : n 0 ≈ 1 + f 1 + 1
1 Q
Q BE = --- ⋅ QB 0 ⋅ n 0 ⋅ q 1
2
4 ⋅ IS T V∗ B2C2
f2 = ----------------- ⋅ exp  -----------------
IK T  VT 
f2
n B = --------------------------
-
1 + 1 + f2
In version 1, n B derivatives are computed from an approximated equation : n B ≈ 1 + f 2 + 1
1 Q
Q BC = --- ⋅ QB 0 ⋅ n B ⋅ q 1
2

V∗ B 2 C 2
The expression for exp  ------------------ was given in section Variable collector resistance.
 VT 
Stored epilayer charge

4 ⋅ TEPI T ⋅ V T
Q EPI 0 = -------------------------------------
-
RCV T
1 xi
Q EPI = --- ⋅ Q EPI 0 ⋅ -------------- ⋅ ( p∗ 0 + p W + 2 )
2 W EPI
Stored extrinsic charges

V B 2 C 1 – VDC T
g 2 = 4 ⋅ exp  --------------------------------------
 VT 
g2
p WEX = ---------------------------
-
1 + 1 + g2
In version 1, p WEX derivatives are computed from an approximated equation : p Wex ≈ 1 + g 2 + 1
TAUR T
Q EX = ---------------------------------------------- ⋅  --- ⋅ Q B 0 ⋅ n BEX + --- ⋅ Q EPI 0 ⋅ p WEX
1 1
TAUB T + TEPI T  2 2 
The electron density nBEX was given in section Reverse base currentsExtended Modeling of the Reverse
Current Gain EXMOD = 1.
14.9.7: Extended Modeling of the Reverse Current Gain EXMOD = 1

Currents
The base currents IEX and ISUB are redefined:
I EX = ( 1 – XEXT ) ⋅ I EX
I SUB = ( 1 – XEXT ) ⋅ I EX
A part XEXT of the base current of the extrinsic transistor is connected to the base terminal:
 V BC 1 
2 ⋅ ISS T ⋅  exp  ------------- – 1 
 VT 
 
XIM SUB = XEXT ⋅ -----------------------------------------------------------------------------
IS T  V BC 1 
1 + 1 + 4 --------------  exp  ------------- 
IKS T   VT 


V BC 1
4 ⋅ IS T ⋅ exp  -------------
 VT 
Xg 1 = --------------------------------------------------
IK T
Xg 1
Xn BEX = -------------------------------------
( 1 + 1 + Xg 1 )
In version 1, XnBEX derivatives are computed from an approximated equation : Xn Bex ≈ 1 + Xg1 + 1
XIM EX = ----------------- ⋅  --- ⋅ IK T ⋅ Xn BEX – IS T

XEXT 1
BRI T  2 
To improve convergency behavior the conductivity of branch B-C1 is limited by a resistance of value
RCCT :
  
  VT 
V EX = V T  2 + ln  ---------------------------------------------------------------------------------- 
 XEXT ⋅  -------------- IS T

  ⋅ ISS T ⋅ RCC T 
 BRI T 
( V BC 1 – V EX ) + ( V BC 1 – V EX ) 2 + 0.0121
VB EX = ---------------------------------------------------------------------------------------------------------
-
2
VB EX
F EX = ------------------------------------------------------------------------------------------------
-
RCC T ⋅ ( XIM EX + XIM SUB ) + VB EX
In version 1, the expression for F EX is different :
VB EX
F EX = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
IS
XEXT ⋅  -------------- T
+ ISS T ⋅ RCC T + ( XIM EX + XIM SUB ) ⋅ RCC T + VB EX
 BRI T 
XI SUB = F EX ⋅ XIM SUB
XI EX = F EX ⋅ XIM EX
Charges
The charge QEX is redefined:
Q EX = ( 1 – XEXT ) ⋅ Q EX
 V BC 1 – VDC T 
Xg 2 = 4 ⋅ exp   ------------------------------------ 
 VT 
 
Xg 2
Xp WEX = --------------------------------
-
1 + 1 + Xg 2

In version 1, XpWEX derivatives are computed from an approximated equation : Xp Wex ≈ 1 + Xg2 + 1
TAUR T
XQ EX = F EX ⋅ XEXT ⋅ ---------------------------------------------- ⋅  --- ⋅ Q B 0 ⋅ Xn BEX + --- ⋅ Q EPI 0 ⋅ Xp WEX
1 1
TAUB T + TEPI T  2 2 
Model parameters : XEXT, TAUR, TAUB, TEPI
14.9.8: Distributed High Frequency Effects In the Intrinsic Base

Distributed high frequency effects are modeled, in first order approximation, both in lateral direction
(current crowding) and in vertical direction (excess phase-shift). The distributed effects are an optional
part of the Mextram model and can be switched on and off by flag EXPHI (on: EXPHI = 1 and off:
EXPHI = 0). The high frequency current crowding is modeled by:
1  ∂Q TE ∂Q BE ∂Q E 
C B = --- ⋅  ----------------------- + ---------------------- -
- + ----------------------
5  ∂Q
B 2 E 1 ∂V B 2 E 1 ∂V B 2 E 1
In version 1, the expression for C B is different :
1  ∂Q TE 1 Q ∂n 0 ∂Q E 
C B = --- ⋅  ----------------------- + --- ⋅ Q B 0 ⋅ q 1 ⋅ -
+ ----------------------
5  ∂Q B 2 E 1 2 ∂ V B 2 E 1 ∂V B 2 E 1
∂Q B1B2
Moreover, version 1 accounts for all derivatives of Q B 1 B 2 . In version 0, only ----------------------- was computed.
∂V B 2 E 1
QB 1B 2 = C B ⋅ VB 1 B 2
For reasons of simplification, only the forward depletion and diffusion charges are taken into account.
The partial derivative of QB1B2 with respect to VB2E1 has to be neglected in the AC analysis. In
transient analysis the convergency behavior may be improved by approximating this derivative with:
∂Q B 1 B 2 ∂Q BE ∂Q E   V B 1 B 2
------------------- =  ------------------ - ⋅ ----------------
- + ------------------
∂V B 2 E 1  ∂V B 2 E 1 ∂V B 2 E 1  5 ⋅ VT
In vertical direction (excess phase-shift) base-charge-partioning is used. For reasons of simplification it

is only implemented for the forward base charge (QBE) and for low level injection. Now QBE and QBC
are redefined according to:
QBE = ( 1 – q C ) ⋅ QBE
QBC = q C ⋅ QBE + QBC
with
1
q C = ---
3

14.9.9: Heterojunction features

The most important difference between SiGe and pure Si transistors is the functional difference
between hole charges and Gummel number. When the Ge concentration has a non-zero slope dE g ≠ 0
I Q
we redefine the q 0 describing the Early effect for the currents (the q 0 remains unchanged).
V TE DEGT – V TC DEGT
exp  --------------- - + 1 ⋅ ----------------- – exp  ---------------- ⋅ -----------------
I
 VER T VT   VEF T VT 
q 0 → ---------------------------------------------------------------------------------------------------------------------------------
DEGT
exp  ----------------- – 1
 VT 
Another feature that might be needed for SiGe transistors is recombination in the base. This changes
the forward ideal base current (when XREC ≠ 0 ).
IS T  V B2E1 
I B 1 → ----------- ⋅ ( 1 – XIBI ) ⋅ ( 1 – XREC ) ⋅  exp  -------------- – 1  +
BF T  VT 
 
 V B2E1  V∗ B 2 C 2  V TC 
XREC ⋅  exp  -------------- +  exp  ------------------ – 2  ⋅  1 + ---------------
- ⋅ ( 1 + nB n0 )
  VT   VT   VEF T
 
The last term also describes Auger recombination in high injection.
14.9.10: Noise Model

For noise analysis noise current sources are added to the small signal equivalent circuit.
Thermal noise:
2 = 4 ⋅ k ⋅ TK
iN - ⋅ ∆f
----------------------
RE RE T
2 = 4 ⋅ k ⋅ TK
iN - ⋅ ∆f
----------------------
RBC RBC T
2 = 4 ⋅ k ⋅ TK
iN - ⋅ ∆f
----------------------
RCC RCC T
For the variable part of the base resistance a different formula is used, taking into account the effect of
current crowding on noise behavior.
VB 1B 2
4 exp  --------------- + 5
4 ⋅ k ⋅ TK VT
iN 2 = ----------------------- ⋅ ------------------------------------------- ⋅ ∆f
RBV RB 2 3
For the variable part of the collector resistance we take base-widening into account :
4⋅k⋅T K  EPI  Q
iN - ⋅ 1 + --------------
2 = ---------------------- - ⋅ ∆f
RCV RCV T  Q EPI 0
Collector current shot noise:

If + Ir
iN 2 = 2 ⋅ q ⋅ --------------
I
⋅ ∆f
C qB
Forward base current shot noise and 1/f noise:

 IB 1 AF
iN 2 =  2 q ⋅ [ I B 1 + I B 2 ] + --------- ⋅ ( 1 – XIBI ) ⋅  ----------------------- +
KF
f  1 – XIBI
B 
KFN 2 ⋅ ( MLF – 1 ) + AF ⋅ ( 2 – MLF ) 
-------------- ⋅ I B 2  ⋅ ∆f
f 
Emitter-base sidewall current shot noise and 1/f noise :
 S AF

--------- ⋅ XIBI ⋅  -------------
2 =  2 ⋅ q ⋅ I S B 1 + KF I B1 
iN
f 
-
XIBI  ⋅ ∆f
BS  
Reverse base current shot noise and 1/f noise:
2  KF AF 
iN B 3 =  2 ⋅ q ⋅ I B 3 + --------- ⋅ ( I B 3 )  ⋅ ∆f
 f 
Extrinsic current shot noise and 1/f noise:

When EXMOD = 0 we have :
2  KF AF 
iN IEX =  2 ⋅ q ⋅ I EX + --------- ⋅ ( I EX )  ⋅ ∆f
 f 
If EXMOD = 1 we have :
 I EX AF

iNIEX =  2 ⋅ q ⋅ I EX + --------- ⋅ ( 1 – XEXT ) ⋅  --------------------------  ⋅ ∆f
2 KF
f  1 – XEXT 
 
 XI EX AF 
iN XIEX =  2 ⋅ q ⋅ XI EX + --------- ⋅ XEXT ⋅  -----------------  ⋅ ∆f
2 KF
f  XEXT
 
Substrate current shot noise (between nodes B1 and S, respectively B and S) :
2
iN ISUB = 2 ⋅ q ⋅ I SUB ⋅ ∆f
2
iN XISUB = 2 ⋅ q ⋅ XI SUB ⋅ ∆f
14.9.11: Self-heating feature

To enable self-heating capability, set instance parameter SELFT to 1.
Power dissipation is given by :
P diss = I N ⋅ ( V B2E1 – V∗ B 2 C 2 ) + I C 1 C 2 ⋅ ( V∗ B 2 C 2 – V B 2 C 1 ) – I avl ⋅ V∗ B 2 C 2
2 2 2
+V EE 1 ⁄ RE T + V CC 1 ⁄ RCC T + V BB 1 ⁄ RBC T
S
+ I B 1 B 2 ⋅ V B 1 B 2 + ( I B 1 + I B 2 ) ⋅ V B2E1 + I B1 ⋅ V B1E1
+ ( I EX + I B 3 + I SUB ) ⋅ V B 1 C 1 + ( XIEX + XISUB ) ⋅ V BC 1
+ ( XI SUB + I SUB – I SF ) ⋅ V C 1 S
One can download Silvaco’s Verilog-A implementation of the Mextram Model at www.silvaco.com.

14.10: The HICUM Bipolar Transistor Model

The HIgh CUrrent Model (HICUM) is an advanced transistor model for bipolar transistors with main
emphasis on circuit design for high-speed applications. This model has been developed and
continuously improved for about 15 years. Work started about 1982 at Ruhr-University Bochum,
Germany, with major emphasis on high-speed ECL-type circuits for fibre-optic applications.
The model has been extended to high-speed small-signal applications since 1989, as well as to SiGe
HBTs since 1993. HICUM development resulted from the experience that the SPICE Gummel-Poon
model (SGPM) is not accurate enough for high-speed large-signal transient applications and the
required high collector current densities. Other major disadvantages of the SGPM are lack of sufficient
physical background, poor description of base resistance and (quasi-)saturation effects.
Silvaco Verilog-A implementation of HICUM complies with version 2.1 of the model.

Equivalent Circuit
Figure 2-6: Equivalent circuit for DC and transient analysis.
Figure 2-7: Equivalent circuit for AC and noise analysis.
General Parameters
BULK Name of the global node used to connect the substrate - “0”
when the terminal ns of the device is unspecified. (gnd)

Transfer Current Parameters
C10 ICCR constant A.C 3.76e-32
MCF Ideality factor - 1.0
IS Collector saturation current A
QP0 Zero bias hole charge C 2.78e-14
ICH High-current correction term for 2D/3D-ICCR A 2.09e-2
HJEI Base-Emitter depletion charge weighting factor (HBTs) - 1.0
HJCI Base-Collector depletion charge weighting factor (HBTs) - 1.0
HFE Emitter minority charge weighting factor (HBTs) - 1.0
HFC Collector minority charge weighting factor (HBTs) - 1.0
Internal Junction Capacitances Parameters
CJEI0 B-E zero-bias depletion capacitance F 8.11e-15
VDEI B-E built-in voltage V 0.95
ZEI B-E exponent coefficient - 0.5
ALJEI B-E ratio of maximum to zero-bias value - 1.8
CJCI0 B-C zero-bias depletion capacitance F 1.16e-15
VDCI B-C built-in voltage V 0.8
ZCI B-C exponent coefficient - 0.333
VPTCI B-C punch-through voltage (a zero value means infinity) V 0.0
ZCIR B-C exponent coefficient under punch-through condi- - (*)

tions
Transit Time and Minority Charge Parameters
T0 Low-current forward transit time at Vbci=0 s 4.75e-12
DT0H Time constant for base and BC SCR width modulation s 2.1e-12
TBVL Time constant for modeling carrier jam at low Vcei s 4.0e-12

Transit Time and Minority Charge Parameters
TEF0 Storage time in neutral emitter s 1.8e-12
GTFE Exponent coefficient for current dependence of TEF0 - 1.4
THCS Saturation time constant at high current densities s 3.0e-11
ALHC Smoothing factor for normalized injection width - 0.75
FTHC Partitioning factor between Base and Collector - 0.6
TR Reverse transit time s 0.0
Critical Current Parameters
RCI0 Internal collector resistance at low electric fields Ω 1.278e+2
VLIM Voltage defining the limit between high and low electric V 0.7
fields in the collector
VPT Epilayer punch-through voltage of B-C SCR V 5.0
VCES Internal C-E saturation voltage V 0.1
Excess Phase Parameters
ALIT Transfer current additional delay time factor - 0.45
ALQF Minority charge additional delay time factor - 0.225
Lateral Scaling Parameters
LATB Scaling factor for QfC in bE direction - 3.765
LATL Scaling factor for QfC in lE direction - 0.342

Base Current Components Parameters
IBEIS Bottom B-E saturation current A 1.16e-20
MBEI Bottom B-E non-ideality factor - 1.015
IREIS Bottom B-E recombination saturation current A 1.16e-16
MREI Bottom B-E recombination non-ideality factor - 2.0
IBEPS Peripheral B-E saturation current A 3.72e-21
MBEP Peripheral B-E non-ideality factor - 1.015
IREPS Peripheral B-E recombination saturation current A 1.0e-30
MREP Peripheral B-E recombination non-ideality factor - 2.0
IBCIS Internal B-C saturation current A 4.39e-20
MBCI Internal B-C non-ideality factor - 1.03
IBCXS External B-C saturation current A 1.16e-20
MBCX External B-C non-ideality factor - 1.015
Peripheral/External Capacitances Parameters
CJEP0 Peripheral B-E zero-bias depletion capacitance F 2.07e-15
VDEP Peripheral B-E built-in voltage V 1.05
ZEP Peripheral B-E exponent coefficient - 0.4
ALJEP Peripheral B-E ratio of maximum to zero-bias value - 2.4
CJCX0 External B-C zero-bias depletion capacitance F 5.39e-15
VDCX External B-C built-in voltage V 0.7
ZCX External B-C exponent coefficient - 0.333
ZCXR External B-C exponent coefficient under punch-through - (*)

conditions
VPTCX External B-C punch-through voltage (a zero value means V 100

infinity)

Peripheral/External Capacitances Parameters
CEOX B-E overlap capacitance F 1.13e-15
CCOX B-C overlap capacitance F 2.97e-15
FBC B-C external capacitance partitioning factor - 0.1526
Internal Base Resistance Parameters
RBI0 Zero-bias internal base resistance Ω 71.76
FGEO Geometry factor for long emitter stripe - 0.73
FDQR0 Correction factor for modulation by SCRs - 0.0
FQI Ratio of internal to total minority charge - 0.9055
FCRBI Ratio of HF shunt to total internal capacitance - 0.0
External Series Resistances Parameters
RCX External collector resistance Ω 9.165
RBX External base resistance Ω 8.83
Substrate Networks Parameters
RSU Parasitic substrate series resistance Ω 100.0
CSU Parasitic substrate capacitance F 1.0e-15

Substrate Transistor Parameters
ITSS Transfer saturation current A 7.44e-21
MSF Forward non-ideality coefficient - 1.05
MSR Reverse emission coefficient - 1.01
TSF Forward minority charge transit time s 0.0
ISCS S-C diode saturation current A 8.62e-20
MSC S-C diode non-ideality factor - 1.1
Substrate-Collector Capacitance Parameters
CJS0 S-C zero-bias depletion capacitance F 3.64e-14
VDS S-C built-in voltage V 0.6
ZS S-C exponent coefficient - 0.447
VPTS S-C punch-through voltage (a zero value means infinity) V 0.0
Base-Collector Avalanche Parameters
FAVL Avalanche multiplication factor - 1.186
QAVL Avalanche exponent coefficient C 11.1e-15
Base-Emitter Breakdown Parameters
IBETS B-E tunneling saturation current A 1.0e-2
ABET B-E tunneling exponent coefficient - 40

Temperature Dependence Parameters
TNOM Reference temperature at which parameter measure- °C 27

ment has been done
VGB Equivalent band-gap voltage V 1.17
GAP1 First bandgap correction factor. eV/K 7.02E-4

Recommended values:
7.02E-4 or 4.43E-4 - Silicon
4.56E-4 - Germanium
5.41E-4 - Gallium Arsenide
GAP2 First bandgap correction factor. K 1108

Recommended values:
1108 or 636 - Silicon
210 - Germanium
204 - Gallium Arsenide
ALB Relative temperature coefficient of current gain –1 6.3e-3

K
ALT0 First temperature coefficient of low-bias transit time –1 0.0

K
KT0 Second temperature coefficient of low-bias transit time –2 0.0

K
ALVS Relative temperature coefficient of VLIM –1 1.0e-3

K
ALCES Relative temperature coefficient of VCES –1 0.4e-3

K
ZETARCI Temperature exponent coefficient of RCI - 1.6
ZETARBI Temperature exponent coefficient of RBI - 0.588
ZETARCX Temperature exponent coefficient of RCX - 0.223
ZETARBX Temperature exponent coefficient of RBX - 0.206
ZETARE Temperature exponent coefficient of RE - 0.0
ALFAV Relative temperature coefficient of FAVL –1 8.25e-5

K
ALQAV Relative temperature coefficient of QAVL –1 1.96e-4

K

Thermal Network and Self-Heating Parameters
SELFT Turn on self-heating effect, 0 means OFF, other val- 0

ues means ON (overrides the value of the option
SHMOD).
RTH Thermal resistance K/W 0.0
CTH Thermal capacitance K/J 0.0
XRT Exponent for RTH temperature dependence - 0.0
DTMAX Maximum temperature rise above heatsink K 1000
14.10.2: Temperature Scaling

The reference temperature at which the parameters are determined is TNOM (TREF) (in ° C). The
actual device operating temperature depends on instance parameters TEMP and DTEMP (in ° C).
Intermmediate variables
All temperatures are internally converted to Kelvin:
T = TEMP + 273.15
T 0 = TNOM + 273.15
Define the thermal voltage by:
V T =  --- ⋅ T
k
 q
V T 0 =  --- ⋅ T 0
k
 q
and
T
T r = ------
T0
∆T = T – T 0
Transfer Current
C 10 ( T ) = C 10 ⋅ T N ⋅ exp  -------------- ⋅ ( T r – 1 )
3 VGB
 VT 
ZEI  VDEI ( T ) 
QP 0 ( T ) = QP 0 ⋅ 1 + ----------- ⋅  1 – -------------------------- 
2  VDEI 

The expression of the built-in voltage VDEI(T) is defined below.
Saturation Currents
Define the correction term: α T = ALB ⋅ ∆T
VGB
and the factor R T = -------------- ⋅ ( T r – 1 )
VT
saturation currents can be defined by the following expressions:
MCF ⋅ R
⋅ exp  -------------------------T- – α T
3 ⁄ MBEI
IBEIS ( T ) = IBEIS ⋅ T r
 MBEI 
MCF ⋅ R
⋅ exp  -------------------------T- – α T
3 ⁄ MBEP
IBEPS ( T ) = IBEPS ⋅ T r
 MBEP 
MCF ⋅ R T
⋅ exp  --------------------------
3 ⁄ MREI
IREIS ( T ) = IREIS ⋅ T r
 MREI 
MCF ⋅ R T
⋅ exp  --------------------------
3 ⁄ MREP
IREPS ( T ) = IREPS ⋅ T r
 MREP 
MCF ⋅ R T
⋅ exp  --------------------------
3 ⁄ MBCI
IBCIS ( T ) = IBCIS ⋅ T r
 MBCI 
MCF ⋅ R T
⋅ exp  --------------------------
3 ⁄ MBCX
IBCXS ( T ) = IBCXS ⋅ T r
 MBCX 
Saturation currents have been made temperature-dependent in version 2.1. This results in the
division of the parameter ITSS (saturation current for the parasitic PNP device) into forward and
reverse components :
RT
⋅ exp  --------------
3 ⁄ MSF
ITSFS ( T ) = ITSS ⋅ Tr
 MSF
RT
⋅ exp  --------------
3 ⁄ MSR
ITSRS ( T ) = ITSS ⋅ T r
 MSR
RT
⋅ exp  --------------
3 ⁄ MSC
ISCS ( T ) = ISCS ⋅ T r
 MSC
Series Resistances
ZETARCI
RCI 0 ( T ) = RCI 0 ⋅ T r
ZETARBI
RBI 0 ( T ) = RBI 0 ⋅ T r
ZETARBX
RBX ( T ) = RBX ⋅ T r

ZETARCX
RCX ( T ) = RCX ⋅ T r
ZETARE
RE ( T ) = RE ⋅ T r
Transit Time and Minority Charge

ZETARCI
VLIM ( T ) unsmoothed = VLIM ⋅ ( 1 – ALVS ⋅ ∆T ) ⋅ T r
A smoothing function has been introduced in order to prevent VLIM(T) to become negative at very
high temperature:
 VLIM ( T ) unsmoothed 
VLIM ( T ) = V T ⋅  1.0 + ln 1.0 + exp  ----------------------------------------------------
- – 1.0 
 VT 
 
VCES ( T ) = VCES ⋅ ( 1 + ALCES ⋅ ∆T )

2
T 0 ( T ) = T 0 ⋅ ( 1 + ALT 0 ⋅ ∆T + KT 0 ⋅ ∆T )
( ZETARCI – 1 )
THCS ( T ) = THCS ⋅ T r
Tr
TEF 0 ( T ) = TEF 0 ⋅ -----------------------------------
1 + ALB ⋅ ∆T
Depletion Capacitances
The junction diffusion voltage is defined by the classical expression:
EG ( T 0 ) EG ( T )
VDx ( T ) = VDx ⋅ T r – V T ⋅ 3 ⋅ ln ( T r ) + -------------------- – ------------------
VT 0 VT
with the bandgap voltage at device and nominal temperatures given by:
2
T
EG ( T ) = VGB – GAP 1 ⋅ --------------------------------
( T + GAP 2 )
and
2
T0
EG ( T 0 ) = VGB – GAP 1 ⋅ ----------------------------------
( T 0 + GAP 2 )
If the model parameter GAP1 is set to zero, the expression reduces to the original formulation:
VDx ( T ) = VDx ⋅ T r – VGB ⋅ ( T r – 1 ) – 3 ⋅ V T ⋅ ln ( T r )
Moreover, a smoothing function has been introduced in order to prevent VDx(T) to become negative at
very high temperature:
VDx ( T ) unsmoothed – VD α
VDx ( T ) = VD α + V T ⋅ ln 1.0 + exp  -------------------------------------------------------------------
 VT 
with
VDx
VD α = 1.001 ⋅ ---------------
ALJx
If ALJx is not available as a model parameter, an internal built-in value (set to 2.4) is used.

The temperature scaling rule for depletion capacitances is:
VDx Zx
CJx ( T ) = CJx 0 ⋅  ----------------------
 VDx ( T )
with: x = EI, CI, EP, CX or S depending on the junction.
The control parameters used to limit the capacitance value at high forward bias are defined by:
VDEI ( T )
ALJEI ( T ) = ALJEI ⋅ --------------------------
VDEI
VDEP ( T )
ALJEP ( T ) = ALJEP ⋅ ---------------------------
VDEP
Avalanche
FAVL ( T ) = FAVL ⋅ exp ( ALFAV ⋅ ∆T )
QAVL ( T ) = QAVL ⋅ exp ( ALQAV ⋅ ∆T )
Tunneling
VDEP ( T ) CJEP 0 ( T )
2
IBETS ( T ) = IBETS ⋅  --------------------------- ⋅ -----------------------------
 VDEP  CJEP 0
VDEP ( T )
ABET ( T ) = ABET ⋅ ---------------------------
VDEP
All other parameters are assumed to be temperature independent.
14.10.3: DC Equations
Internal Voltages
Define:
Vbei = V ( B′ ) – V ( E′ )
Vbci = V ( B′ ) – V ( C′ )
Vbep = V ( B * ) – V ( E′ )
Vbcp = V ( B * ) – V ( C′ )
Vsci = V ( S′ ) – V ( C′ )
Quasi-Static Transfer Current

I T = I Tf – I Tr

The main current can be mathematically split into a forward component:
I Tf 1 
I Tf = I Tf 1 ⋅  1 + ----------- I Tf 1 = ---------- ⋅ exp  --------------------------
C 10 Vbei
- with:
ICH Q pT MCF ⋅ V T
and an inverse component:
I Tr = ---------- ⋅ exp  -------------

C 10 Vbci
Q pT  VT 
Model parameters: ICH, C10 and MCF.

The base charge is given by:
Q pT = QP 0 + HJEI ⋅ Q jEI + HJCI ⋅ Q jCI + Q fT + Q rT
Q jEI and Q jCI are the depletion charges stored at the BE and BC junction,
Q fT and Q rT are weighted minority charges stored in the transistor.
In general, the minority charges Q fT and Q rT are non-linearly dependent on I Tf and I Tr . For this
case, the implicit equation involving the common variable Q pT is solved internally by using a simple
iteration process.
Model parameters: QP0, HJEI and HJCI.
Critical Current for Onset of High Current Effects
V ceff 2 –3
1 x + x + 10
I CK = ------------------------ ⋅ ------------------------------------------------ ⋅ 1 + ------------------------------------
RCI 0 ( T ) V ceff 2 2
1 +  --------------------------
 VLIM ( T )
with:
V ceff – VLIM ( T )
x = --------------------------------------------
-
VPT
and the smoothed effective collector voltage:
V
V ceff = V T ⋅ 1 + ln  1 + exp  ------c- – 1 
  VT  
with:
V c = Vbei – Vbci – VCES ( T )
Model parameters: RCI0, VLIM and VPT.
Base-Emitter Voltage Controlled Minority Charge

Q fT = Q f 0 + HFE ⋅ ∆Q fE + ∆Q fB + HFC ⋅ Q fCT
Q f 0 corresponds to the low-current component and the other components correspond to the emitter,
base and collector contributions at high collector current densities. It is important to notice that Q fCT
is not the actual collector minority charge because it includes a bias-dependent weighting function due
to the lateral current spreading.

Model parameters: HFE and HFC.
Low Current Density Component

Q f 0 = τ f 0 ⋅ I Tf
with the current-independent transit time given by:
CJCI 0 ( T ) C jCI
τ f 0 = T 0 + DT 0 H ⋅  ---------------------------- – 1 + TBVL ⋅  ---------------------------
- – 1
 C jCI   CJCI 0 ( T ) 
with C jCI as the internal Base-Collector depletion capacitance (evaluated without punch-through
effect to cover all regions).
Model parameters: T0, DT0H and TBVL.
High Current Density Base Component

2
∆QfB = ( 1 – FTHC ) ⋅ THCS ( T ) ⋅ w ⋅ I Tf
with the normalized injection width:
2
i + i + ALHC I CK
w = ----------------------------------------- and i = 1 – --------
-
1 + 1 + ALHC I Tf
Model parameters: THCS, FTHC and ALHC.
High Current Density Emitter Component

I Tf GTFE I Tf
∆Q fE = TEF 0 ( T ) ⋅  --------- ⋅ ---------------------------
 I CK 1 + GTFE
Model parameters: TEF0 and GTFE.
High Current Density Collector Component

Q fCT = FTHC ⋅ THCS ( T ) ⋅ I Tf ⋅ fCT
Define the normalized current:
2
i + i + ALHC I CK
i ck = 1 – ----------------------------------------- with i = 1 – --------
-
1 + 1 + ALHC I Tf
Two cases have to be considered:
• LATB > LATL
2 ln ( 1 + LATL ⋅ w ) ln ( 1 + LATB ⋅ w )
fCT = ----------------------------------------- ⋅ ---------------------------------------------- – ----------------------------------------------
LATB – LATL LATL LATB

κ–1
w = ------------------------------------------------
LATB – κ ⋅ LATL

and the intermediate variable:
1 + LATL ick – 1
κ =  ---------------------------
 1 + LATB
• LATB = LATL
2
- ⋅ [ z ⋅ ln ( z ) – LATB ⋅ w ]
f CT = --------------------------
2
LATB ⋅ z
with z = ( 1 + LATB ⋅ w )
and the normalized injection width:
1 – i ck
w = -------------------------------------
-
1 + LATB ⋅ i ck
Model parameters: FTHC, THCS, ALHC, LATB and LATL.
Base-Collector Voltage Controlled Minority Charge
Q r = TR ⋅ I Tr
Model parameters: TR.
Static Base Current Components
I jBEI = IBEIS ( T ) ⋅ exp  ----------------------------- – 1 + IREIS ( T ) ⋅ exp  ----------------------------- – 1

Vbei Vbei
 MBEI ⋅ V T  MREI ⋅ V T
I jBEP = IBEPS ( T ) ⋅ exp  ------------------------------- – 1 + IREPS ( T ) ⋅ exp  ------------------------------- – 1

Vbep Vbep
 MBEP ⋅ V T  MREP ⋅ V T
I jBCI = IBCIS ( T ) ⋅ exp  ----------------------------- – 1

Vbci
 MBCI ⋅ V T
I jBCX = IBCXS ( T ) ⋅ exp  ------------------------------- – 1

Vbcp
 MBCX ⋅ V T
Internal Base Resistance

The DC internal resistance is modeled by:
ln ( 1 + η )
r BI = r i ⋅ -----------------------
η
with the current crowding factor
r i ⋅ I jBEI
η = FGEO ⋅ --------------------- ( I jBEI is the base current component previously calculated).
VT
and the conductivity modulated internal resistance,

Q0
r i = RBI 0 ( T ) ⋅ ------------------------ ⋅ f p
Q 0 + ∆Q p

with:
Q0 = QP 0 ( T ) ⋅ ( 1 + FDQR 0 )
∆Q p = Q jEI + Q jCI + Q f
and the periphery correction factor.

QjEI + Q f ⋅ FQI
f p = ---------------------------------------
-
Q jEI + Q f
The depletion charges, Q jEI , Q jCI and the actual minority charge, Q f are described in the charge
section below.
Model parameters: RBI0, FGEO, FDQR0, FCRBI, FQI and QR0.
Collector-Base Breakdown: Avalanche Current
QAVL ( T )
I AVL = I Tf ⋅ FAVL ( T ) ⋅ V CBeff ⋅ exp  – --------------------------------
 C jCI ⋅ V CBeff
with:
V CBeff = VDCI ( T ) – Vbci
Emitter-Base Breakdown: Tunneling Current

1 – ZEP ZEP – 1
I BET = IBETS ( T ) ⋅ ( – V e ) ⋅ ( 1 – V e ) ⋅ exp ( – ABET ( T ) ⋅ ( 1 – V e ) )
Parasitic Substrate Transistor
I TS = ITSS ⋅ exp  -------------------------- – exp  --------------------------

Vbcp Vsci
 MSF ⋅ V T  MSR ⋅ V T
I SC = ISCS ⋅ exp  -------------------------- – 1

Vsci
 MSC ⋅ V T
14.10.4: Description of Charges

Actual Base-Emitter Voltage Controlled Minority Charge
Q f = Q f 0 + ∆Q fE + ∆Q fB + Q fC
The terms Q f 0 , ∆Q fE and ∆Q fB have been already defined in DC equations.
The collector component is defined by:

Q fC = FTHC ⋅ THCS ( T ) ⋅ I Tf ⋅ f C
Define the normalized current:
2
i + i + ALHC I CK
i ck = 1 – ----------------------------------------- with i = 1 – --------
-
1 + 1 + ALHC I Tf
and the intermediate variable:

1 + LATB ick – 1
κ =  --------------------------- as in DC equations.
 1 + LATL
Two cases have to be considered:
• LATB > LATL
f C = ----------------------------------------- ⋅ f Ci ⋅ ln  --------------------------- – f Cb + fCl

2 1 + LATB
LATB – LATL  1 + LATL
with:
LATL + LATB 2 LATL ⋅ LATB 3
fCi = w + ----------------------------------------- ⋅ w + --------------------------------------- ⋅ w
2 3
2 3
z ⋅ { 2 ⋅ ln ( z ) – 1 } + 1 z ⋅ { 3 ⋅ ln ( z ) – 1 } + 1
f Cb =  1 – ----------------- ⋅ ------------------------------------------------------- +  ----------------- ⋅ -------------------------------------------------------
LATL LATL
 LATB  4 ⋅ LATB  LATB  9 ⋅ LATB
with: z = 1 + LATB ⋅ w ,
f Cl has the same form as f Cb but with LATB and LATL interchanged.
and the normalized injection width:

1–κ
w = ------------------------------------------------
LATB – κ ⋅ LATL
• LATB = LATL
2 1 + LATB ⋅ w ⁄ 3
f C = w ⋅ -------------------------------------------
1 + LATB ⋅ w
1 – i ck
w = -------------------------------------
-
1 + LATB ⋅ i ck
Model parameters: FTHC, THCS, ALHC, LATB and LATL.
Emitter-base depletion charges and capacitances

Define the (forward) voltage at which the classical expression intercepts the maximum constant value.
1
– -----------
ZEI
V f = VDEI ( T ) ⋅ 1 – ALJEI ( T )
and the auxiliary voltage:

V f – Vbei
ν j = V f – V T ⋅ ln ( 1 + e ) with e = exp  -------------------------
 VT 
the internal Base-Emitter capacitance is defined by:

CJEI 0 ( T ) e 1
- ⋅ ------------ + ALJEI ( T ) ⋅ CJEI 0 ( T ) ⋅ ------------
C jEI = -------------------------------------------------------
ZEI e + 1
( 1 – ν j ⁄ VDEI ( T ) ) e + 1
and the corresponding charge reads:

CJEI 0 ( T ) ⋅ VDEI ( T ) νj ( 1 – ZEI )

Q jEI = ---------------------------------------------------------- ⋅ 1 –  1 – -------------------------
- + ALJEI ( T ) ⋅ CJEI 0 ( T ) ⋅ ( Vbei – ν j )
1 – ZEI  VDEI ( T )
Model parameters: CJEI0, VDEI, ZEI and ALJEI.
The expressions of the peripheral Base-Emitter capacitance C jEP and corresponding charge Q jEP are
obtained by inserting the related model parameters as well as the voltage Vbep in the previous
equations.
Model parameters: CJEP0, VDEP, ZEP and ALJEP.
Base Collector Depletion Charges and Capacitances

The model is similar to that used for Base Emitter junction modeling. However, a punch-through effect
at large reverse bias is accounted for.
Define the (forward) voltage at which the classical expression intercepts the maximum constant value
1
– -----------
ZCI
V fCI = VDCI ( T ) ⋅ 1 – 2.4
the auxiliary voltages:

V fCI – Vbci
ν jr = V fCI – V T ⋅ ln ( 1 + e r ) with e r = exp  ------------------------------
VT
and
ν jm = – ( VPTCI – VDCI ( T ) ) + V r ⋅ ln ( 1 + e m )
with:
VPTCI – VDCI ( T ) + ν jr
e m = exp  -----------------------------------------------------------------
 Vr 
and the voltage at which the transition from medium to large reverse bias starts.
V r = 0.1 ⋅ ( VPTCI – VDCI ( T ) ) + 4 ⋅ V T
The capacitance consists of three components:
C jCI = C jCIcl + C jCIpt + C jCIfb
with the term corresponding to the classical equation at medium bias and
CJCI 0 ( T ) em er
- ⋅ ---------------
C jCIcl = -----------------------------------------------------------
ZCI e + 1 e + 1
- ⋅ -------------
-
( 1 – ν jm ⁄ VDCI ( T ) ) m r
the term corresponding to the maximum value at large forward bias,

1
C jCIfb = 2.4 ⋅ CJCI 0 ( T ) ⋅ --------------
er + 1
and the term corresponding to the large reverse bias region beyond punch-through;
CjCI 0 r 1
- ⋅ ----------------
C jCIpt = -------------------------------------------------------------
ZCIR e + 1
( 1 – ν jr ⁄ VDCI ( T ) ) m
with:

VDCI ( T ) ( ZCI – ZCIR )

CjCI 0 r = CJCI 0 ( T ) ⋅  --------------------------
 VPTCI 
The corresponding charge is obtained by integration of the capacitance.
Q jCI = Q jCIm + Q jCIr + Q jCIf – Q jCIc
with the component at medium bias:
CJCI 0 ( T ) ⋅ VDCI ( T ) ν jm  ( 1 – ZCI )

Q jCIm = ---------------------------------------------------------- ⋅ 1 –  1 – -------------------------
-
1 – ZCI  VDCI ( T )
the component at large reverse bias
ν jr ( 1 – ZCIR )
Q jCIr = ------------------------ ⋅ 1 –  1 – -------------------------
-
CjCI 0 r
1 – ZCIR VDCI ( T )
the component at large forward bias:

Q jCf = 2.4 ⋅ CJCI 0 ( T ) ⋅ ( Vbci – ν jr )
and a correction component resulting from the integration process:
CjCI 0 r ⋅ VDCI ( T ) ν jm  ( 1 – ZCIR )

Q jCIc = -------------------------------------------------- ⋅ 1 –  1 – -------------------------
-
1 – ZCIR  VDCI ( T )
Model parameters: CJCI0, VDCI, VPTCI, ZCI and ZCIR.
Substrate-Collector Depletion Charge and Capacitance

The expressions of the Substrate-Base capacitance C jS and corresponding charge Q jS are obtained by
inserting the related model parameters as well as the voltage Vsci in the equations used for the Base-
Collector junction.
Model parameters: CJS0, VDS, ZS and VPTS0.
New temperature mappings

The temperature dependence of junction diffusion voltages VDx (x = EI, CI, EP, CX or S) is now
expressed by the classical expression:
EG ( T 0 ) EG ( T )
VDx ( T ) = VDx ⋅ T r – V T ⋅ 3 ⋅ ln ( T r ) + -------------------- – ------------------
VT 0 VT
with the bandgap voltage at device and nominal temperatures given by:
2
T
EG ( T ) = VGB – GAP 1 ⋅ --------------------------------
( T + GAP 2 )
and
2
T0
EG ( T 0 ) = VGB – GAP 1 ⋅ ----------------------------------
( T 0 + GAP 2 )
EG is now defined as an alias for VGB.

14.11: The VBIC Bipolar Transistor Model (LEVEL=5)

The Vertical Bipolar Inter-Company (VBIC) model was defined by a group of IC and CAD industry
representatives, to provide a public domain, standard BJT model.
The model is based upon Kull’s enhancements to the Spice Gummel-Poon (SGP) bipolar model, with
extensions to incorporate the physical effects characteristic of modern bipolar transistors.
Equivalent circuit
s CBCO c
RS RCX
si
Ibcp Qbcp
RBIP/qbp cx
bp
Itfp−Itrp
Ibep Qbep
RCI
ci
Qbcx Qbc
Ibc−Igc
RBX RBI/qb
b bx bi
Qbex Qbe Itxf−Itzr

Ibex Ibe
ei
RE
CBEO
dt xf1 Flxf xf2
CTH Qcxf
Ith RTH Itzf 1Ω
tl
thermal network excess phase network
Figure 2-8: Equivalent Circuit of the VBIC Bipolar Model (large signal)
14.11.1: VBIC Model Parameters

For parameters noted with an asterisk (*), a zero value means infinity.
General Parameters
LEVEL Model selector (must be set to 5 for VBIC) - 1
VERSION Version parameter. Only 1.1 (if REV=5) and 1.2 (if REV= - 1.2
0) are permitted, otherwise 1.2 is assumed.
REVISION Revision parameter. Only 0 (if VERS=1.2) and 5 (if - 0

VERS=1.1) are permitted, otherwise 0 is assumed.

General Parameters
BULK Name of the global node used to connect the substrate - “0”
when the terminal ns of the device is unspecified. (gnd)
QBM Selector for SGP qb formulation (v1.2) - 0.0
SELFT Self-heating effect switch, 0 means OFF, other values - 0

mean ON (the value of SHMOD option is overridden).
Saturation Current Parameters
IS Transport saturation current A 1e-16
ISRR Reverse saturation current factor for HBTs - 1.0

(v1.2)
IBEI Ideal B-E saturation current A 1e-18
IBEN Non-ideal B-E saturation current A 0.0
IBCI Ideal B-C saturation current A 1e-16
IBCN Non-ideal B-C saturation current A 0.0
ISP Transport saturation current of the para- A 0.0

sitic device
IBEIP Ideal B-E saturation current of the parasitic A 0.0

device
IBENP Non-ideal B-E saturation current of the par- A 0.0

asitic device
IBCIP Ideal B-C saturation current of the parasitic A 0.0

device
IBCNP Non-ideal B-C saturation current of the par- A 0.0

asitic device
Emission Coefficient Parameters
NF Forward emission coefficient - 1.0
NR Reverse emission coefficient - 1.0
NEI Ideal B-E emission coefficient - 1.0
NEN Non-ideal B-E emission coefficient - 2.0
NCI Ideal B-C emission coefficient - 1.0

Emission Coefficient Parameters
NCN Non-ideal B-C emission coefficient - 2.0
NFP Forward emission coefficient of the parasitic - 1.0

device
NCIP Ideal B-C emission coefficient of the parasitic - 1.0

device
NCNP Non-ideal B-C emission coefficient of the para- - 2.0

sitic device
Partioning Parameters
WBE Portion of IBEI from Vbei, 1-WBE from - 1.0

Vbex
WSP Portion of ICCP from Vbep, 1-WSP from - 1.0

Vbci
High Current Beta Degradation Effect Parameters
IKF Forward knee current A 0.0
IKR Reverse knee current A 0.0
NKF High current roll-off coefficient (v1.2) - 0.5
IKP Parasitic knee current A 0.0
Early Voltage Parameters
VEF Forward Early voltage V 0.0
VER Reverse Early voltage V 0.0

Weak Avalanche Parameters
AVC1 B-C weak avalanche parameter 1 - 0.0
AVC2 B-C weak avalanche parameter 2 - 0.0
Resistance Parameters
RCX Extrinsic collector resistance Ω 0.0
RCI Intrinsic collector resistance Ω 0.0
RBX Extrinsic base resistance Ω 0.0
RBI Intrinsic base resistance Ω 0.0
RS Substrate resistance Ω 0.0
RBP Parasitic base resistance Ω 0.0
RTH Thermal resistance of device. K/W 0
XRT Exponent for RTH temperature - 0

dependence.
Overlap Capacitance Parameters
CBEO Extrinsic B-E overlap capacitance F 0.0
CBCO Extrinsic B-C overlap capacitance F 0.0
CCSO Fixed C-S capacitance (v1.2) F 0.0
Junction Capacitance Parameters
FC Forward bias depletion capacitance limit - 0.9
CJE B-E zero bias capacitance F 0.0
PE B-E built-in potential V 0.75

Junction Capacitance Parameters
ME B-E grading coefficient - 0.33
AJE B-E capacitance smoothing factor - -0.5
CJC B-C intrinsic zero bias capacitance F 0.0
CJEP B-C extrinsic zero bias capacitance F 0.0
PC B-C built-in potential V 0.75
MC B-C grading coefficient - 0.33
AJC B-C capacitance smoothing factor - -0.5
VRT B-C capacitance limiting voltage (v1.2) V 0.0
ART B-C capacitance limiting smoothing fac- V 0.1

tor (v1.2)
CJCP S-C zero bias capacitance F 0.0
PS S-C built-in potential V 0.75
MS S-C grading coefficient - 0.33
AJS S-C capacitance smoothing factor - -0.5
CTH Thermal capacitance of device. K/J 0
Epilayer Parameters
VO Epi drift saturation voltage V 0.0
GAMM Epi doping parameter - 0.0
HRCF High current RC factor - 1.0
QCO Epi charge parameter - 0.0
Transit Time and Excess Phase Parameters
TF Forward transit time s 0.0
QTF Variation of TF with base-width modulation - 0.0
XTF Coefficient of TF bias dependence - 0.0

Transit Time and Excess Phase Parameters
VTF Coefficient of TF dependence on Vbc - 0.0
ITF Coefficient of TF dependence on Ic - 0.0
TR Reverse transit time s 0.0
TD Forward excess-phase delay time s 0.0
TNOM Nominal temperature (model parameter mea- °C 27

surement temperature)
DTMAX Maximum temperature rise above heatsink. K 1000
XRE Temperature exponent of RE - 0.0
XRB Temperature exponent of RBI and RBX (v1.1.5) - 0.0

Temperature exponent of RBI (v1.2)
XRBX Temperature exponent of RBX (v1.2) - 0.0
XRC Temperature exponent of RCI and RCX (v1.1.5) - 0.0

Temperature exponent of RCI (v1.2)
XRCX Temperature exponent of RCX (v1.2) - 0.0
XRBP Temperature exponent of RBP (v1.2) - 0.0
XRS Temperature exponent of RS - 0.0
XVO Temperature exponent of VO - 0.0
EA Activation energy for IS V 1.12
DEAR Activation energy shift for ISRR (v1.2) V 0.0
EAP Activation energy for ISP (v1.2) V 1.12
EAIE Activation energy for IBEI V 1.12
EAIC Activation energy for IBCI/IBEIP V 1.12
EAIS Activation energy for IBCIP V 1.12
EANE Activation energy for IBEN V 1.12
EANC Activation energy for IBCN/IBENP V 1.12
EANS Activation energy for IBCNP V 1.12
XIS Temperature exponent of IS - 3.0

XIKF Temperature exponent of IKF (v1.2) - 0.0
XISR Temperature exponent of ISRR (v1.2) - 0.0
XII Temperature exponent of IBEI/IBCI/IBEIP/ - 3.0

IBCIP
XIN Temperature exponent of IBEN/IBCN/IBENP/ - 3.0

IBCNP
TNF Temperature coefficient of NF - 0.0
TAVC Temperature coefficient of AVC2 - 0.0
TVBBE1 First temperature coefficient of VBBE (v1.2) –1 0.0

V⋅K
TVBBE2 Second temperature coefficient of VBBE (v1.2) –2 0.0

V⋅K
TNBBE Temperature coefficient of NBBE (v1.2) –1 0.0

K
Noise Parameters
KFN B-E flicker noise constant - 0.0
AFN B-E flicker noise exponent - 1.0
BFN B-E flicker noise 1/f dependence - 1.0
Base-Emitter Tunneling Parameters
IBBE B-E breakdown current (v1.2) A 1.0e-6
NBBE B-E breakdown emission coefficient (v1.2) - 1.0
VBBE B-E breakdown voltage (v1.2) V 0.0

The VBIC expressions of base and collector currents are similar to SGP equations. The base current is
divided into base-emitter and base-collector components.
It is assumed that geometry and/or temperature scaled values of model parameters are used in the
following expressions.

Define the branch voltages used in equations below:

Vbei = v(bi) - v(ei)
Vbex = v(bx) - v(ei)
Vbci = v(bi) - v(ci)
Vbcx = v(bi) - v(cx)
Vrci = v(cx) - v(ci)
Vrbi = v(bx) - v(bi)
Vbep = v(bx) - v(bp)
Vbcp = v(si) - v(bp)
Vrbp = v(cx) - v(bp)
Collector Current Contributions

The VBIC (zero excess phase) forward and reverse transport currents are:
Itfi Itri
Itzf = --------- and Itzr = ----------
qb qb
where:
Itfi and Itri are forward and reverse ideal currents and qb is the normalized base charge calculated
as a function of applied bias.
Ideal Forward and Reverse Currents
Itfi = IS ⋅  exp  ------------------------ – 1.0

Vbei
  NF ⋅ Vtd 
The expression of ideal reverse current has been modified to account for a separate saturation current
IS in reverse operation (HBTs).
Itri = IS ⋅  exp  ------------------------ – 1.0 (v1.1.5)

Vbci
  NR ⋅ Vtd 
or
Itri = IS ⋅ ISSR ⋅  exp  ------------------------ – 1.0 (v1.2)

Vbci
  NR ⋅ Vtd 
Parameters: IS, ISSR (v1.2), NF, NR.
Base Charge
2
q1 q1 + 4 ⋅ q2
qb = ------ + --------------------------------- (v1.1.5)
2 2
with:

qdbe qdbc
q 1 = 1.0 + -------------- + ------------- (a zero value means infinity for VER and VEF)
VER VEF
Itfi Itri
q 2 = ------------ + ----------- (a zero value means infinity for IKR and IKF)
IKR IKF
qdbe and qdbc are the normalized depletion charges.
if: (QBM < 0.5)
1.0 NKF
 -------------
NKF
- 
q1 + 4 ⋅ q 2
q1  
qb = ------ + -----------------------------------------------------
2 2
else,
q1 NKF
qb = ------ ⋅ [ 1.0 + ( 1.0 + 4.0 ⋅ q 2 ) ] (SGP)
2
Transport Current and Base Charge of the Parasitic Device

Itfp – Itrp
Iccp = -----------------------------
qbp
where:
Itfp = ISP ⋅  WSP ⋅ exp  ---------------------------- + ( 1.0 – WSP ) ⋅ exp  ---------------------------- – 1.0
Vbep Vbci
  NFP ⋅ Vtd  NFP ⋅ Vtd 
Itrp = ISP ⋅  exp  ---------------------------- – 1.0

Vbcp
  NFP ⋅ Vtd 
1 1 + 4 ⋅ q2p
qbp = --- + -------------------------------
2 2
Itfp
q 2 p = ----------- (a zero value means infinity for IKP)
IKP
Parameters: ISP, WSP, NFP, IKP.
Currents in Modulated Resistors

The following currents are computed only if corresponding model parameters RBI, RCI and RBP have
non-zero values (negative values are considered as zero). Otherwise, internal related nodes simply
collapse.
Define:

1.0 + GAMM ⋅ exp  -------------
Vbci
RCI > 0.0
Kbci =   Vtd 

 0.0 RCI ≤ 0.0


1.0 + GAMM ⋅ exp  --------------
Vbcx
RCI > 0.0
Kbcx =   Vtd 

 0.0 RCI ≤ 0.0
Parameters: RCI, GAMM.
The intrinsic collector current is modeled with the enhanced Kull quasi-saturation model:
Iohm
Irci = --------------------------------
2
1.0 + derf
where:
Vrci + Vtd ⋅ ( Kbci – Kbcx – log ( rKp 1 ) ) Kbci + 1.0

Iohm = ----------------------------------------------------------------------------------------------------------- with rKp 1 = ----------------------------
RCI Kbcx + 1.0
RCI ⋅ Iohm
derf = ----------------------------------------------------
2
Vrci + 0.01
VO + ------------------------------------
2.0 ⋅ HRCF
VO and HRCF are model parameters for which a zero value means infinity.
A simple qb modulation model is used and leads to:
Vrbi ⋅ qb
Irbi = ------------------------
RBI
Parameter: RBI
A similar expression is used to model the qbp modulation in parasitic device:
Vrbp ⋅ qbp
Irbp = ------------------------------
RBP
Parameter: RBP
Intrinsic and Extrinsic Base-Emitter Current

The base-emitter current is partitioned between intrinsic and extrinsic contributions to account for the
distributed nature of the base.
Ibe = WBE ⋅ IBEI ⋅  exp  --------------------------- – 1.0 + IBEN ⋅  exp  ------------------------------ – 1.0
Vbei Vbei
NEI ⋅ Vtd NEN ⋅ Vtd
Ibex = ( 1.0 – WBE ) ⋅ IBEI ⋅  exp  --------------------------- – 1.0 + IBEN ⋅  exp  ------------------------------ – 1.0
Vbex Vbex
  NEI ⋅ Vtd    NEN ⋅ Vtd 
Parameters: WBE, IBEI, NEI, IBEN, NEN.
Base-Emitter Breakdown Current

In v1.2, a simple exponential model has been introduced to account for the base-emitter tunneling
effect. New contributions, noted Ibebk and Ibexbk, are added to the intrinsic and extrinsic base-
emitter currents Ibe and Ibex, respectively.
If: VBBE > 0.0

Ibebk = – WBE ⋅ IBBE ⋅  exp  ------------------------------------------ – EBBE (v1.2 only)

– VBBE – Vbei
  NBBE ⋅ Vtd  
Ibexbk = –( 1.0 – WBE ) ⋅ IBBE ⋅  exp  ------------------------------------------- – EBBE (v1.2 only)

– VBBE – Vbex
  NBBE ⋅ Vtd  
else,
Ibebk = 0.0 (v1.2 only)
Ibexbk = 0.0 (v1.2 only)

Parameters: WBE, IBBE (v1.2), NBBE (v1.2), VBBE (v1.2) and EBBE (v1.2).
Intrinsic Base-Collector Current
Ibc = IBCI ⋅  exp  --------------------------- – 1.0 + IBCN ⋅  exp  ------------------------------ – 1.0

Vbci Vbci
  NCI ⋅ Vtd    NCN ⋅ Vtd 
Parameters: IBCI, NCI, IBCN, NCN.
Base-Collector Weak Avalanche Current

If AVC 1 > 0 , a weak avalanche contribution is calculated and added to the base-collector current.
Igc = ( Itzf – Itzr – Ibc ) ⋅ avalm

where:
MC – 1.0
avalm = AVC 1 ⋅ vl ⋅ exp ( –AVC 2 ⋅ vl )
2
( PC – Vbci ) + 0.01 + PC – Vbci
vl = ------------------------------------------------------------------------------------------
2
Parameters: PC, MC, AVC1, AVC2.
Base-Emitter Current of the Parasitic Device
Ibep = IBEIP ⋅  exp  --------------------------- – 1.0 + IBENP ⋅  exp  ------------------------------ – 1.0

Vbep Vbep
  NCI ⋅ Vtd    NCN ⋅ Vtd 
Parameters: IBEIP, NCI, IBENP, NCN.
Base-Collector Current of the Parasitic Device
Ibcp = IBCIP ⋅  exp  -------------------------------- – 1.0 + IBCNP ⋅  exp  ---------------------------------- – 1.0

Vbcp Vbcp
  NCIP ⋅ Vtd    NCNP ⋅ Vtd 
Parameters: IBCIP, NCIP, IBCNP, NCNP.

14.11.3: Charge and Capacitance Equations

Normalized Junction Depletion Charge
VBIC has two depletion charge models: the standard Gummel-Poon model and a single-piece model for
which the capacitance is smoothly limited to a constant value for a forward biased junction.
In v1.2, new equations (and model parameters) have been added to account for reach-through limiting
effect in the base-collector junction. These equations are used to evaluate normalized base-collector
depletion charges qdbc and qdbep if the value of VRT is greater than zero. This effect is not
accounted for in the calculation of qdbe and qdbex.
It is important to notice that the expressions of vl and vl0 are different in v1.2. The smoothing factor is
4*AJ*AJ, where AJ is expressed in volts.
Standard Gummel-Poon model

If the smoothing coefficient AJx (x=C,E or S) is less than or equal to zero, the regional depletion
capacitance model is used to compute depletion charges.
Define dvh = V – FC ⋅ Px
where:
V is the junction applied voltage,
Px (x=C,E or S) is the junction built-in potential and
FC is the forward bias depletion capacitance limit.
If: dvh > 0.0
dvh ⋅ Mx
1.0 – Mx 1.0 – FC + ------------------------
1.0 – ( 1.0 – FC ) 2.0 ⋅ Px
qj = Px ⋅ -------------------------------------------------------- + dvh ⋅ ----------------------------------------------------
-
1.0 – Mx ( 1.0 – FC )
1.0 + Mx
else, if VRT > 0.0 and V < – VRT (reach-through limiting)
VRT 1.0 – Mx  ( 1.0 – Mx ) ⋅ ( V + VRT )

qj = ---------------------- ⋅ 1.0 –  1.0 + ------------- ⋅ 1.0 – ------------------------------------------------------------- (v1.2 only)
Px
1.0 – Mx  Px   Px + VRT 
else,
V 1.0 – Mx
1.0 –  1.0 – -------
 Px
qj = Px ⋅ --------------------------------------------------------
1.0 – Mx
where:
Mx (x=C,E or S) is the junction grading coefficient.
Single piece model
If the smoothing coefficient AJx (x=C,E or S) is positive, the single piece depletion capacitance model is
used to compute depletion charges.
If VRT > 0.0 and ART > 0.0 (reach-through limiting)
Define: dv 0 = – FC ⋅ Px

VRT + dv 0
vn 0 = ------------------------------ (v1.2 only)
VRT – dv 0
2 ⋅ vn 0
vnl 0 = ---------------------------------------------------------------------------------------------------------------------------------------------- (v1.2 only)
( vn 0 – 1.0 ) + 4 ⋅ AJx + ( vn 0 + 1.0 ) + 4 ⋅ ART 2
2 2 2
vl 0 = 0.5 ⋅ ( vnl 0 ⋅ ( VRT – dv 0 ) – VRT – dv 0 ) (v1.2 only)
2.0 ⋅ V + VRT + dv 0
vn = ---------------------------------------------------- (v1.2 only)
VRT – dv 0
2 ⋅ vn
vnl = ---------------------------------------------------------------------------------------------------------------------------------------- (v1.2 only)
( vn – 1.0 ) + 4 ⋅ AJx + ( vn + 1.0 ) + 4 ⋅ ART 2
2 2 2
vl 0 = 0.5 ⋅ ( vnl ⋅ ( VRT – dv 0 ) – VRT – dv 0 ) (v1.2 only)
sel = 0.5 ⋅ ( vnl + 1.0 ) (v1.2 only)
VRT –Mx
crt =  1.0 + ----------- (v1.2 only)
 Px 
cmx = ( 1.0 – FC )
– Mx
(v1.2 only)
cl = ( 1.0 – sel ) ⋅ crt + sel ⋅ cmx (v1.2 only)
 1.0 – ------ vl  1.0 – Mx  1.0 – ------- vl 0 1.0 – Mx

- -
 Px   Px 
qj = Px ⋅ ------------------------------------------- – Px ⋅ -------------------------------------------- + ( V – vl + vl 0 ) ⋅ cl (v1.2 only)
1.0 – Mx 1.0 – Mx
else,
Define:
2
vl = 0.5 ⋅ ( V – FC ⋅ Px – ( V – FC ⋅ Px ) + AJx ) + FC ⋅ Px (v1.1.5)
or:
2 2
vl = 0.5 ⋅ ( V – FC ⋅ Px – ( V – FC ⋅ Px ) + 4 ⋅ AJx ) + FC ⋅ Px (v1.2)
and:
2
vl 0 = 0.5 ⋅ ( – FC ⋅ Px – ( – FC ⋅ Px ) + AJx ) + FC ⋅ Px (v1.1.5)
or:
2 2
vl 0 = 0.5 ⋅ ( – FC ⋅ Px – ( – FC ⋅ Px ) + 4 ⋅ AJx ) + FC ⋅ Px (v1.2)
the depletion charge can be expressed by:
 1.0 – ------ vl  1.0 – Mx  1.0 – vl 0 1.0 – Mx

- --------
 Px V – vl + vl 0  Px 
qj = – Px ⋅ ------------------------------------------- + --------------------------------- + Px ⋅ --------------------------------------------
1.0 – Mx ( 1.0 – FC )
Mx 1.0 – Mx
Parameters: AJx, Px, Mx (x=C,E or S), FC, VRT (v1.2), ART (v1.2).

Base-Emitter Charge
The base-emitter charge is partitioned between Qbe and Qbex.
Qbe contains also a diffusion charge component.
Qbe = CJE ⋅ qdbe ⋅ WBE + tff ⋅ Itzf

qdbe is the normalized depletion charge calculated using the algorithm described above:
qdbe = qj ( Vbei, PE, ME, FC, AJE )

tff is the forward transit time modeled as:
2
tff = TF ⋅ ( 1.0 + QTF ⋅ q 1 ) ⋅  1.0 + XTF ⋅ exp  ---------------------------- ⋅  --------------------------- 
Vbci Itfi
  1.44 ⋅ VTF  Itfi + ITF 
that reduces to:
tff = TF ⋅ ( 1.0 + QTF ⋅ q 1 ) if Itfi ≤ 0.0

Parameters: CJE, WBE, PE, ME, FC, AJE, TF, QTF, XTF, ITF (a zero value for ITF means infinity).
Qbex = CJE ⋅ qdbex ⋅ ( 1.0 – WBE )

qdbex is the normalized depletion charge calculated using the algorithm described above:
qdbex = qj ( Vbex, PE, ME, FC, AJE )

Parameters: CJE, WBE, PE, ME, FC, AJE.
Base-Collector Charge
The intrinsic base-collector charge Qbc contains contributions of depletion and diffusion charges. As
the extrinsic charge Qbcx, it also includes a term corresponding to the charge associated with the base
pushout into the collector.
The intrinsic base-collector charge is
Qbc = CJC ⋅ qdbc + TR ⋅ Itri + QC 0 ⋅ Kbci
qdbc is the normalized depletion charge calculated using the algorithm described above:
qdbc = qj ( Vbci, PC, MC, FC, AJC )
Parameters: CJC, TR, QC0, PC, MC, FC, AJC.
The extrinsic base-collector charge is
Qbcx = QC 0 ⋅ Kbcx
Parameter: QC0.
Base-Emitter Charge of the Parasitic Device

Qbep = CJEP ⋅ qdbep + TR ⋅ Itfp
qdbep is the normalized depletion charge calculated using the algorithm described above:
qdbep = qj ( Vbep, PC, MC, FC, AJC )

Parameters: CJEP, TR, PC, MC, FC and AJC.
Base-Collector Charge of the Parasitic Device

Qbcp = CJCP ⋅ qdbcp
or:
Qbcp = CJCP ⋅ qdbcp + CCSO ⋅ Vbcp
The contribution of the fixed capacitance CCSO is added to the total base-collector charge.
qdbcp is the normalized depletion charge calculated using the algorithm described above:
qdbcp = qj ( Vbcp, PS, MS, FC, AJS )
Temperature dependence of thermal resistance

XRT
RTH ( T ) = RTH ⋅  --------------------
T
 TNOM
TNOM is the temperature at which the model parameters have been extracted. T corresponds to the
dynamic temperature Td if self-heating is turned on. Otherwise, T corresponds to the operating
temperature. The capacitance Cth is assumed to be temperature indepdendent.
14.11.4: Excess Phase Network

If the excess phase delay TD is set to a positive value then an internal network is created (nodes xf1
and xf2). The capacitance and inductance values are set to TD and TD/3 respectively and the value of
the current source is set to Itzf. Finally, the collector current is calculated using the resulting current
Itxf induced in the inductor.
Icc = Itxf – Itzr
14.11.5: Temperature Scaling

Temperature effects are presented using the device temperature T d dynamically calculated during
iterations. If the self-heating calculation is not turned on T d is not taken into account in temperature
scaling and the device operating temperature T op is used instead.
The following abbreviations are defined for convenience:
k k Td
V td = --- ⋅ T d V tnom = --- ⋅ T nom and r td = ------------
-
q q T nom
Parasitic Resistors
XRC
RCX ( T d ) = RCX ⋅ ( r td )
XRC
RCI ( T d ) = RCI ⋅ ( r td )

XRB
RBX ( T d ) = RBX ⋅ ( r td )
XRB
RBI ( T d ) = RBI ⋅ ( r td )
XRE
RE ( T d ) = RE ⋅ ( r td )
XRS
RS ( T d ) = RS ⋅ ( r td )
XRC
RBP ( T d ) = RBP ⋅ ( rtd ) (v1.1.5)
Saturation Currents
XIS
-----------
EA 1.0 – r td
⋅ exp  – --------- ⋅ --------------------
NF
IS ( T d ) = IS ⋅ ( r td )
 NF V td 
XIS
-------------
EA 1.0 – r td
⋅ exp  – ------------- ⋅ --------------------
NFP
ISP ( T d ) = ISP ⋅ ( r td )
 NFP V td 
XIKF
IKF ( T d ) = IKF ⋅ ( r td ) (v1.2 only)
XISR
----------------
DEAR 1.0 – r td
⋅ exp  – ------------------ ⋅ --------------------
NR
ISRR ( T d ) = ISRR ⋅ ( r td )
 NR V td 
XII
------------
EAIE 1.0 – r td
⋅ exp  – ---------------- ⋅ --------------------
NEI
IBEI ( T d ) = IBEI ⋅ ( r td )
 NEI V td 
XIN
---------------
EANE 1.0 – r td
⋅ exp  – ------------------ ⋅ --------------------
NEN
IBEN ( T d ) = IBEN ⋅ ( r td )
 NEN V td 
XII
------------
EAIC 1.0 – r td
⋅ exp  – ---------------- ⋅ --------------------
NCI
IBCI ( T d ) = IBCI ⋅ ( r td )
 NCI V td 
XIN
---------------
EANC 1.0 – r td
⋅ exp  – ------------------ ⋅ --------------------
NCN
IBCN ( T d ) = IBCN ⋅ ( r td )
 NCN V td 
XII
------------
EAIC 1.0 – r td
⋅ exp  – ---------------- ⋅ --------------------
NCI
IBEIP ( T d ) = IBEIP ⋅ ( r td )
NCI V td
XIN
---------------
EANC 1.0 – r td
⋅ exp  – ------------------ ⋅ --------------------
NCN
IBENP ( T d ) = IBENP ⋅ ( r td )
 NCN V td 
XII
-----------------
EAIS 1.0 – r td
⋅ exp  – ---------------- ⋅ --------------------
NCIP
IBCIP ( T d ) = IBCIP ⋅ ( r td )
 NCIP V td 
XIN
-------------------
EANS 1.0 – r td
⋅ exp  – ------------------- ⋅ --------------------
NCNP
IBCNP ( T d ) = IBCNP ⋅ ( r td )
 NCNP V td 
2
VBBE ( T d ) = VBBE ⋅ ( 1.0 + TVBBE 1 ⋅ ( T d – T nom ) + TVBBE 2 ⋅ ( T d – T nom ) )

NBBE ( T d ) = NBBE ⋅ ( 1.0 + TNBBE ⋅ ( T d – T nom ) )
VBBE ( T d ) 
EBBE ( T d ) = exp  – -------------------------------------------
-
 NBBE ( T d ) ⋅ V td
Non-Ideality Factors and Weak Avalanche Model Parameters

NF ( T d ) = NF ⋅ ( 1.0 + TNF ⋅ ( T d – T nom ) )
NR ( T d ) = NR ⋅ ( 1.0 + TNF ⋅ ( T d – T nom ) )
AVC 2 ( T d ) = AVC 2 ⋅ ( 1.0 + TAVC ⋅ ( T d – T nom ) )
Built-in Potentials
PE, PC and PS are scaled using the corresponding parameters EAIE, EAIC, EAIS, and the following
algorithm (Px means PE, PC, or PS and EAIx means EAIE, EAIC, or EAIS).
 1.0 + 1.0 + 4.0 ⋅ exp  – psiin --------------- 

  V td  
Px ( T d ) = psiin + 2.0 ⋅ V td ⋅ log  -----------------------------------------------------------------------------
 2.0 
 
where:
psiin = psiio ⋅ r td – 3.0 ⋅ V td ⋅ log ( r td ) – EAIx ⋅ ( rtd – 1.0 )
In v1.2, the expression psiio has been updated and reads now:
psiio = 2.0 ⋅ V tnom ⋅ log  exp  --------------------------- – exp  – --------------------------- 

Px Px
  2.0 ⋅ V tnom  2.0 ⋅ V tnom 
However the original expression is maintained when invoking:
psiio = 2.0 ⋅ V td ⋅ log  exp  -------------------- – exp  – -------------------- 

Px Px
  2.0 ⋅ V td  2.0 ⋅ V td 
Zero-Bias Capacitances
ME
CJE ( T d ) = CJE ⋅  --------------------
PE
 PE ( T d )
MC
CJC ( T d ) = CJC ⋅  --------------------
PC
 PC ( T d )
MC
CJEP ( T d ) = CJEP ⋅  --------------------
PC
 PC ( T d )
MS
CJCP ( T d ) = CJCP ⋅  -------------------
PS
 PS ( T d )

Epilayer Parameters
1.0 – r td
⋅ exp  – EA ⋅ --------------------
XIS
GAMM ( T d ) = GAMM ⋅ ( r td )
 V td 
XVO
VO ( T d ) = VO ⋅ ( r td )
One can download Silvaco’s Verilog-A implementation of the VBIC Model at www.silvaco.com.

14.12: Interfacing Verilog-A Compact Model Code to the Input Deck

VERILOG-A models are identified by the YVLG prefix followed by the device name (e.g.,
YVLGmodel_name). The model_name.va file must also be referenced within the SPICE deck.
Syntax
.VERILOG "model_name.va"
YVLGmodel_name < ports> params
14.13: .MODEL Card

.Model cards are required in all spice decks containing YVLG modules, and supports external
parameter settings.
Syntax
YVLGmodel_name < ports> params
* Define the model card for the model_name module

.MODEL params VLG MODULE = model_name
+ L = 10E-6, W = 20E-6
*** Process Related Model Parameters
+ COX = 3.45E-3
+ XJ = 0.15E-6
*** Intrinsic Model Parameters
+ VTO = 0.6
+ GAMMA = 0.71
+ PHI = 0.97
+ KP = 150E-6
+ E0 = 88.0E6
+ UCRIT = 4.5E6
+ DL = -0.05E-6
+ DW = -0.02E-6
+ LAMBDA = 0.23
+ LETA = 0.28
+ WETA = 0.05
+ Q0 = 280E-6
+ LK = 0.5E-6
*** Substrate Current Parameters
+ IBN = 1.0
+ IBA = 200E6
+ IBB = 350E6
*** Intrinsic Model Temperature Parameters
+ TNOM = 25.0
+ TCV = 1.5E-3
+ BEX = -1.5
+ UCEX = 1.7
+ IBBT = 0.0
*** 1/f Noise Model Parameters
+ KF = 1E-27
+ AF = 1
+ TYPE=1

The complete SPICE deck for a DC analysis of a VERILOG-A implemented EKV model with extrinsic
capacitance is shown below.
14.14: Compiling Verilog-A Compact Models

The Silvaco VERILOG-A gives one the ability to compile the custom models developed by using VERILOG-A
with the native host C compiler. Since the VERILOG-A code accepted by the Interpreter is ANSI C, it can
be compiled by using any C compiler. Compiled VERILOG-A models using the host C compiler will
provide the fastest execution speed once a model has been fully developed within SMARTSPICE VERILOG-A
framework. Once this is performed, the provided models.c file should be modified (as described
below) and the library libsmart.so should be built by using the provided Makefile.
Finally, the environment variable, LD_LIBRARY_PATH, should be set to reference the location of the
file (libsmart).
14.15: Interfacing Verilog-A Compact Model Code to a Schematic Symbol

Create a symbol as specified within the SCHOLAR USER’S MANUAL. Using the SYMBOL EDITOR, press
the SMARTSPICE button to access the SMART SPICE STRING EDITOR. Within this window, type the following
string:
YVLGmodel_name @Path %P1 %P2 %P3…..%Pn <ParamsID> param1=@param1

param2=@param2 paramn=@paramn
Where %Pn represents pin names and paramn=@paramn allows values for paramn to be entered
from the schematic.
The SPICE deck must contain the following:
and the
.MODEL ParamsID VLG MODULE = model_name

*** Process Related Model Parameters
+ COX = 3.45E-3
+ XJ = 0.15E-6
.
.
.
.
.

14.16: Declaring Verilog-A Modules Within a SmartSpice Input Deck

VERILOG-A modules can be used inside the input deck as following:
.verilog “file.va” name of the file that contains the Verilog-A module(s)
that will be used within this input deck.
YVLGpart_name <port pins> module_name <parameter values> that is contained

within file.va.
or
YVLGpart_name <port pins> model_card_ID_name
.MODEL model_card_ID_name VLG MODULE = module_name

+ <parameter values
Examples
*Spice deck no VLG Model Card
.verilog “resistor.va”
.verilog “inductor.va”
.verilog “capacitor.va”
*voltage source
vin in 0 sin (0 5 10e06 0 0)
*SmartSpice Verilog-A module instantiantion

YVLGres in 2 resistor r=200
YVLGind 2 out inductor l=10u
YVLGcap out 0 capacitor c=10p
.tran 1n 800n
.print v(in) v(out)
.end
or
*Spice deck with VLG Model Card
.verilog “resistor.va”
.verilog “inductor.va”
.verilog “capacitor.va”
*voltage source
vin in 0 sin (0 5 10e06 0 0)
*SmartSpice Verilog-A module instantiantion

YVLGres in 2 paramsR
YVLGind 2 out paramsL
YVLGcap out 0 paramsC
*VLG model card

.model paramsR VLG MODULE = resistor
+ r = 200 $ optional, but it will override the first parameter.
.model paramsL VLG MODULE = inductor
+ L = 10uh $ optional, but it will override the first parameter.
.model paramsC VLG MODULE = capacitor
+ C = 10p $ optional, but it will override the first parameter.
.tran in 800n
.print v(in) v(out)
.end


Chapter 15:
Verilog-A Examples
This chapter provides VERILOG-A examples from simple digital gates to complex behavioral models of a
Phase Lock loop.
15.1: Digital circuits

This section shows the following digital components, including primitive digital circuit components.
• Inverter
• Buffer
• Nand
• Nor
• Exor
• DFF
• Shift_registor
• Counter
15.1.1: Inverter
Figure 15-1 shows the Inverter circuit symbol.
in out
Figure 15-1: Inverter

Inverter behavior shows the following.
Logic Table
IN OUT
1
0
We can write VERILOG-A for inverter as such (inv.in):
‘Include "discipline.h"
module inv(in, out);
input in;
output out;

electrical in,out;
parameter real vout_high = 5;

parameter real vout_low = 0;
parameter real vth = 2.5;
parameter real tdelay = 5n; //propagation delay
parameter real trise = 8.5n; //rise time
parameter real tfall = 10n; //fall time
real Val;
analog begin
@( initial_step ) begin // initial condition
if ( V(in) > vth ) val = vout_low;
else val = vout_high;
end
@( cross( V(in) - vth, +1) ) val = vout_low; // Vin>vth => vout_low
@( cross( V(in) - vth, -1) ) val = vout_high; // Vin<vth => vout_high
V(out) <+ transition( val,tdelay,trise,tfall );

end
endmodule
Figure 15-2: Inverter Simulation Result

A Spice inputdeck can be described as the following (inv.va):
*----LOGIC ( inverter ) Circuit-----*

*
.verilog "inv.va"
.options post probe iplot_one numdgt=10
+ accurate
v01 vcc 0 dc 5
v02 in 0 pulse(0 5 1u 1n 1n 1u 2u)
*
YVLG_NOT in out inv
.tran 1n 10u
.iplot v(in)
+ ’v(out)+10’
.probe all
.end

Verilog-A Examples
15.1.2: Buffer
Figure 15-3 is the Buffer circuit symbol.
Figure 15-3: Buffer

Buffer behavior shows the following.
Logic Table
IN OUT
0 0
1 1
We can write VERILOG-A for buffer as such (buff.va):
module inv(in,out);
input in;
output out;
electrical in,out;
parameter real vout_high = 5;

parameter real vout_low = 0;
parameter real vth = 2.5;
parameter real tdelay = 5; // propagation delay time
parameter real trise = 8.5n; // rise time
parameter real tfall = 11n; // fall time
real val;
analog begin
@( initial_step ) begin // initial condition
if ( V(in) > vth ) val = vout_low;
else val = vout_high;
end
@( cross( V(in) - vth, +1) ) val = vout_low; // Vin>vth => vout_low
@( cross( V(in) - vth, -1) ) val = vout_high; // Vin<vth => vout_high
V(out) <+ transition( val,tdelay,trise,tfall );

end
endmodule

Figure 15-4: Buffer Simulation Result

The Spice inputdeck describes the following (buf.in):
*----LOGIC ( Buffer ) Circuit-----*

*
.verilog "buffer.va"
.options post probe iplot_one numdgt=10
+ accurate
v01 vcc 0 dc 5
v02 in 0 pulse(0 5 1u 1n 1n 1u 2u)
*
YVLG_buf in out buffer
.tran 1n 10u
.iplot v(in)
+ ’v(out)+10’
.probe all
.end
15.1.3: Nand
Figure 15-5 is a well known Nand circuit symbol.
in1
out
in2
Figure 15-5: Input Nand Circuit

2-input Nand behavior shows the following.

Verilog-A Examples
Logic Table
IN1 IN2 Out
0 0 1
0 1 1
1 0 1
1 1 0
We can describe this as the following (nand.va)
module dnand(in,out);
parameter real size = 2 from [2:inf),

vout_high = 5,
vth = 2.5,
tdelay = 5n from [0:inf),
trise = 10n from [0:inf),
tfall =12n from [0:inf);

output out;
voltage in,out;
integer in_state[0:size-1],i;
integer out_state;
real vout;
analog
begin
@(initial_step)
for(i=0;i<size;i=i+1) in_state[i]=0;
generate i (0,size-1)
begin
@(cross(V(in[i]) - vth))
begin
in_state[i] = V(in[i]) > vth;
out_state = 1;
for (i=0;i<size;i=i+1)
if (!(out_state && in_state[i])) out_state = 0;
if (out_state) vout = vout_low; // inversion of output
else vout = vout_high;
end
end
V(out) <+ transition(vout,tdelay,trise,tfall);

end
endmodule

Figure 15-6: 2 - Input Nand Simulation Result

Spice inputdeck show the following(nand.in).
*----LOGIC ( NAND ) Circuit-----*

*
.verilog "nand.va"
.options iplot_one
v01 in1 0 pulse(0 5 0u 1n 1n 1u 2u)

v02 in2 0 pulse(0 5 1u 1n 1n 2u 4u)
YVLG_nand in1 in2 out nand
.tran 1n 40u
.iplot v(in1)
+ ’v(in2)+10’
+ ’v(out)+20’
.probe all
.end
The number of input is limited by size, so if you want more input, you had better set "size = number" as
is needed.
Example
If you want 4 input nand,
module dnand(in,out); you don’t need change
parameter real size = 4 from [4:inf), you must change from 2 to 4
The Spice inputdeck is described: (4nand.in)
*----LOGIC ( 4 input NAND ) Circuit-----*

*
.verilog "nand.va"

Verilog-A Examples
.options iplot_one
v01 in1 0 pulse(0 5 0u 1n 1n 1u 2u)

v02 in2 0 pulse(0 5 1u 1n 1n 2u 4u)
v03 in3 0 pulse(0 5 0u 1n 1n 4u 8u)
v04 in4 0 pulse(0 5 1u 1n 1n 8u 16u)
YVLG_nand in4 in3 in2 in1 out nand size=4

.tran 1n 40u
.iplot v(in1)
+ ’v(in2)+10’
+ ’v(in3)+20’
+ ’v(in4)+30’
+ ’v(out)+40’
.probe all
.end
Figure 15-7: 4 - Input Nand Simulation result
15.1.4: NOR
Figure 15-8 is a well known 2 input NOR circuit.
In1
out
in2
Figure 15-8: 2-Input NOR

2-input NOR circuit behavior shows the following LOGIC Table.

Logic Table
IN1 IN2 Out
0 0 1
0 1 0
1 0 0
1 1 0
This circuit is described as the following (nor.va):
module dnor(in,out);
parameter real size = 2 from [2:inf),

vout_high = 5,
vth = 2.5,
tdelay = 5n from [0:inf),
trise = 10n from [0:inf),
tfall = 10n from [0:inf);

output out;
voltage in,out;
integer in_state[0:size-1],i;
integer out_state;
real vout;
analog
begin
@(initial_step)
for(i=0;i<size;i=i+1) in_state[i]=0;
generate i (0,size-1)
begin
begin
in_state[i] = V(in[i]) > vth;
out_state = 0;
for (i=0;i<size;i=i+1)
if (in_state[i]) out_state = 1;
if (out_state) vout = vout_low;
else vout = vout_high;
end
end

end
endmodule

Verilog-A Examples
Figure 15-9: 2- Input NOR Simulation Result

Spice inputdeck(nor.in):
*----LOGIC ( 2-Input NOR ) Circuit-----*

.verilog "nor.va"
.option post probe iplot_one
v01 vcc 0 dc 5
v02 in1 0 pulse(0 5 1u 1n 1n 1u 2u)
v03 in2 0 pulse(0 5 2u 1n 1n 2u 4u)
*
YVLG_OR in1 in2 out dnor
.tran 1n 20u
.iplot v(in1)
+’v(in2)+10’
+’v(out)+20’
.probe all
.end
This example can also expand the number of input. If you want more (ex. the number is 3), change the
VERILOG-A source and Spice inputdeck as follows.
Verilog-A source file (nor.va):
module dnor(in,out); you don’t need to change

parameter real size = 3 from [3:inf), you must change from 2 to 3
Spice inputdeck (3nor.in):
*----LOGIC ( 3-Input NOR ) Circuit-----*

.verilog "nor.va"

v01 in1 0 pulse(0 5 1u 1n 1n 1u 2u)

v02 in2 0 pulse(0 5 2u 1n 1n 2u 4u)
v03 in3 0 pulse(0 5 2u 1n 1n 4u 8u)
*
YVLG_OR in1 in2 in3 out nor size=3
.tran 1n 20u
.iplot v(in1)
+ ’v(in2)+10’
+ ’v(in3)+20’
+ ’v(out)+30’
.probe all
.end
Figure 15-10: 3-Input NOR Simulation Result
15.1.5: EXOR
Figure 15-11 is a well-known 2 input XOR circuit.
in1
out
in2
Figure 15-11: 2-Input XOR

2-input XOR circuit behavior show the following LOGIC Table.

Verilog-A Examples
Logic Table
IN1 IN2 Out
0 0 0
0 1 1
1 0 1
1 1 0
This circuit is described as follows (xor.va).
Verilog-A Source file(xor.va):
module dxor(in,out);
parameter real vh=5,
vl=0,
vth=1.5,
tdelay=10n,
trise=5n,
tfall=5n;
input [0:1] in;
output out;
voltage in,out;
real vout;
analog
begin
if ( V(in[0])==V(in[1]) ) vout=vl;
else vout=vh;
generate i (0,1)
begin
begin
if ( V(in[0])==V(in[1]) ) vout=vl;
else vout=vh;
end
end

end
endmodule

Figure 15-12: XOR Simulation Result
Spice inputdeck show the following(xor.in):
*----LOGIC ( 2-Input XOR ) Circuit-----*

*
.verilog "xor.va"
.option post probe iplot_one method=gear
v01 vcc 0 dc 5
v02 in1 0 pulse(0 5 1u 1n 1n 1u 2u)
v03 in2 0 pulse(0 5 2u 1n 1n 2u 4u)
*
YVLG_OR in1 in2 out dxor
.tran 10n 40u
.iplotv(in1)
+’v(in2)+10’
+’v(out)+20’
.probe all
.end
15.1.6: DFF (D-type Flip Flop)

Figure 15-13 is D type Flip Flop (RTL symbol)
D Q
CLK Q
Figure 15-13: D-Type Flip Flop

Verilog-A Examples
Its behavior is shown in the following table.
Logic Table
CLK D Q Q_bar
0 0 0 1
0 1 0 1
1 1 1 0 (CLK:L - >H)
1 0 0 1 (CLK:L - >H)
VERILOG-A source file for DFF is described as follows:
Verilog-A source file(dff.va):
module vdff(q, qbar, clk, d);

input clk,d;
output q,qbar;
voltage q, qbar, clk, d;
parameter real tdelay = 5n from [0:inf),

ttransit = 5n from [0:inf),
vout_high = 5,
vth= 2.5;
integer x;
analog
begin
@(initial_step) x = 0;
@(cross(V(clk) - vth, +1 )) x = (V(d) > vth);
V(q) <+ transition( vout_high*x + vout_low*!x, tdelay, ttransit );

V(qbar) <+ transition( vout_high*!x + vout_low*x, tdelay, ttransit );
end
endmodule

Figure 15-14: DFF Simulation Result
Spice inputdeck shows the following(dff.in):
*----LOGIC ( 4bit Shift Register ) Circuit-----*

*
.verilog "dff.va"
v02 d1 0 pwl(0 0 0.999u 0 1u 5 1.999u 5 2u 0 20u 0 R 0n)

v03 clk 0 pulse(0 5 1u 1n 1n 2u 4u)
*
YVLGa_nd1 q1 q1b clk d1 Vdff
YVLGa_nd2 q2 q2b clk q1 Vdff
.tran 1n 50u
*.probe all
.let v1=’v(q1)+6’
.let v2=’v(q2)+12’
.let v3=’v(q3)+18’
.let v4=’v(q4)+24’
.iplot v(clk) v1 v2 v3 v4
.end

Verilog-A Examples
15.1.7: 4bit Shift Register

Figure 15-15 4bit Shift_register is an example of using a DFF block This Shift Register is driven by
Clock rise edge.
Q1 Q2 Q3
Data D Q D Q D Q D Q
CLK Q CLK Q CLK Q CLK Q
H (s
Figure 15-15: 4bitShift Resistor
Spice Inputdeck(4bit_shift_reg.in):
*----LOGIC ( 4bit Shift Register ) Circuit-----*

*
.verilog "dff.va"
v02 d1 0 pwl(0 0 0.999u 0 1u 5 1.999u 5 2u 0 20u 0 R 0n)

*
YVLGa_nd1 q1 q1b clk d1 Vdff
.tran 1n 50u
*.probe all
.let v1=’v(q1)+6’
.let v2=’v(q2)+12’
.let v3=’v(q3)+18’
.let v4=’v(q4)+24’
.end

Figure 15-16: 4bit Shift Resistor Simulation Result
15.1.8: 4bit Down Counter

The next example is a 4bit down counter using a DFF VERILOG-A module. 4bit down Counter spice
netlist
Q1 Q2 Q3
D Q D Q D Q D Q
C
CL CLKQ CLKQ CLKQ CLK Q
Figure 15-17: 4bit Down Counter

4bit down counter netlist is shown as follows(4bit_counter.in).
Spice inputdeck(4bit_dcount.in):
*----LOGIC ( 4bit Down Counter ) Circuit-----*

*
.verilog "dff.va"
v01 d 0 pulse ( 0 5 5u 1n 1n 5u 10u)

*
YVLGa_nd1 q1 d1 clk d1 Vdff
YVLGa_nd2 q2 d2 q1 d2 Vdff
.tran 1n 50u

Verilog-A Examples
.let v1=’v(q1)+10’
.let v2=’v(q2)+20’
.let v3=’v(q3)+30’
.let v4=’v(q4)+40’
.probe all
.end
Figure 15-18: 4bit Down Counter Simulation Result
15.2: Analog Filter

Analog Filter is very important for analog Circuit design. In this section, we can learn basic filter
description for VERILOG-A using transfer function.
This section describes the following filters.
• LPF: first order Low pass filter
• HPF: first order High pass filter
• BPF: first order Band pass filter
15.2.1: LPF
LPF is called "differentialtor" (or differential circuit), as is shown as Figure 15-19.
Vin(t) Vout(t)
R
Figure 15-19: RC Filter

Transfer function for LPF is described in the following equation:
1
H ( s ) = ---------------------------------------------
1 + ( 1 ⁄ 2 Πfreq )S
We can write this equation for VERILOG-A using Laplace function.
Laplace_nd means "n: numerator" and "d: dominator". The numerator of above transfer function is
"1", and the dominator above transfer function are 1+(1/2pai*frq)*S
We can write:
laplace_nd(V(in), {1} , {1,1/(‘M_TWO_PI*freq_p1)} )
See Figure 15-20 LPF characteristics.

*Freq_p1 is Cut off frequency.
-3db
Freq(Hz)
Figure 15-20: LPF Characteristics
Verilog-A source file is the following (lpf.va):
‘include "Constants.h"
module lpf1(in,out);
input in;
output out;
voltage in,out;
parameter real freq_p1 = 1M from (0:inf);

analog
V(out) <+ laplace_nd(V(in), {1} , {1,1/(‘M_TWO_PI*freq_p1)} );
endmodule

Verilog-A Examples
Spice inputdeck (lpf.in):

*----- Low pass filter -----*
.verilog "lpf.va"
.option probe iplot_one
v01 in 0 2.5 ac 1
YVLG_lpf in out lpf
c01 out 0 1p
.options use degrees
.ac oct 10 1 1g
.let vdb=vdb(out)
.let vp=vp(out)
.iplot vdb
.end
Figure 15-21: LPF Simulation Results

15.2.2: HPF
HPF can be described as an Integrate(C-R) circuit (see Figure 15-22).
Vin(t)
Vout(t)
C
R
Fig Error! No text of specified style in document..0.

Figure 15-22: Integrator
HPF also can be expressed by transfer function as the following.
( 1 ⁄ 2 Πfreq )S
H ( s ) = ---------------------------------------------
1 + ( 1 ⁄ 2 Πfreq )S
We can write the above equation to VERILOG-A as follows:
laplace_nd(V(in), {0,1/(‘M_TWO_PI*freq_p1)} , {1,1/(‘M_TWO_PI*freq_p1)} )
Verilog-A source (hpf.va):
module hpf(in,out);
input in;
output out;
voltage in,out;
parameter real freq_p1 = 1M from (0:inf);
analog
V(out) <+ laplace_nd(V(in), {0,1/(‘M_TWO_PI*freq_p1)} , {1,1/
(‘M_TWO_PI*freq_p1)} );
endmodule
Spice inputdeck (hpf.in):
*----- high pass filter -----*

.verilog "hpf.va"

Verilog-A Examples
v01 in 0 2.5 ac 1
YVLG_lpf in out hpf
*c01 out 0 1p
.ac oct 10 1 1g
.let vdb=vdb(out)
.let vp=vp(out)
.iplot vdb
*.iplot vp
.end
Figure 15-23: HPF Simulation Result (freq v.s. gain)
15.2.3: BPF
BPF can be described using LPF and HPF.
BPF characteristics are shown in Figure 15-24.
-3db
Frq_p1 Frq_p2
Freq(Hz)
Figure 15-24: BPF Characteristics

If the input signal Frequency is "f", then BPF behavior is shown as:
• f <Freq_p1: input signal can't through
• Freq_p1 < f <Freq_p2: input signal can through
• Freq_p2 < f: input signal can't through
BPF is described in two ways:
1. One is to describe it by the transfer function
2. Or, description by LPF and HPF.
The later way can be described simply as the following
YVLG_LPF 2 IN LPF
YVLG_HPF OUT 2 HPF
The former way is difficult unless you can understand transfer function.
BPF transfer function shows the following equation:
( 1 ⁄ 2 Πfreq )S
H ( s ) = ------------------------------------------------------------------------------------------2
1 + ( 1 ⁄ 2 Πfreq )S + ( 1 ⁄ 2 Πfreq )S
We can describe transfer function like the following using laplace function of VERILOG-A:
laplace_nd(V(in), {0,1/(‘M_TWO_PI*freq_p1)} , {1,1/(‘M_TWO_PI*freq_p1),

pow(1/(‘M_TWO_PI*freq_p2),2)})
Verilog-A source (bpf.va):

module bpf(in,out);
input in;
output out;
voltage in,out;
parameter real freq_p1 = 100k from (0:inf),

freq_p2 = 1M from [freq_p1:inf);
analog
V(out) <+ laplace_nd(V(in), {0,1/(‘M_TWO_PI*freq_p1)} ,
{1,1/(‘M_TWO_PI*freq_p1),pow(1/(‘M_TWO_PI*freq_p2),2)} );
endmodule
Spice inputdeck (bpf.in):

*----- band pass filter -----*
.verilog "bpf.va"
.option probe iplot_one usedegrees=true
v01 in 0 2.5 ac 1
YVLG_lpf in out bpf
c01 out 0 1p

Verilog-A Examples
.ac oct 10 10 1g
.let vdb=vdb(out)
.let vp=vp(out)
.iplot vdb
.end
Figure 15-25: BPF Characteristics
15.3: Analog Circuit

This section has analog circuit examples using VERILOG-A, although describing analog circuit behavior
is difficult because the simple behavior is not the whole behavior of the analog circuit. If the user
wants to describe VERILOG-A code for an analog circuit, one must know the analog specification and
characteristics.
This section shows the following analog.
• Opamp
• Sample hold
• ADC
• DAC
• Delta-Sigma modulator
15.3.1: OPAMP (Operational Amplifier)

Figure 15-26 is an example of an inverted operational amplifier (opamp). This opamp can be described
in various ways. But, if the user wants to write this using VERILOG-A, the user must have a knowledge
of the characteristics for opamp. Figure 15-26 opamp input is Vin, the output voltage is Vout, and
Negative Feedback resistances are R1and R2.
This opamp gain shows the following equation:
R2
Gain = -------
R1
We can also describe the following for Vout:
R2
Vout – Vref = – ------- × ( Vin – Vref )
R1

Figure 15-26: Inverted Amplifier

In general, Vout is cramped by supply voltage, so we can describe this opamp using VERILOG-A.
Verilog-A source (amp.va):
// simple opamp
‘include "descipline.h"
module amp(in,out);
input in;
output out;
electrical in,out;
// parameter real gain=10;
parameter avcc=5;//Analog supply voltage soruce
parameter avss=0;//Analog ground reference
parameter vref=2.5;//input reference voltage
parameter real R1=1k;//initial resistance
parameter real R2=1k;//initial resistance
real A,gain,vout;
analog
begin
@(initial_step)
begin
gain=R2/R1;
A=-1*gain;//invert signal
end
vout=A*(V(in) - vref) + vref;
if( vout > avcc )
vout=avcc;
if( vout < avss )
vout=avss;
V(out) <+ vout;

end
endmodule

Verilog-A Examples
Spice inputdeck (opamp.in):

*---- ANALOG( OPAMP) Circuit-----*
*
.verilog "amp.va"
.options iplot_one
v01 in 0 sin(2.5 0.1 1meg)
YVLG_amp in out amp R2=10k

.tran 1n 10u
.iplot v(in) v(out)
.probe all
.end
As for the above Spice inputdeck, the amplitude of input signal is 0.1(V) and R2 is set to 10k, so
Gain=R2/R1=10k/1k=10. We can expect Vout as 10 times of the INPUT signal voltage.
Running spice simulation above inputdeck by these conditions, we get Figure 15-27.
Figure 15-27: OPAMP Simulation Result

15.3.2: Sample hold

As for analog circuits design, sample hold circuit is used for various analog blocks. For example, ADC
uses this to preserve input voltage (Vin).
A sample hold circuit is shown in Figure 15-28.
Figure 15-28: Sample Hold Circuit

Right Circuit behavior shows the following:
CLK: sampling clock signal
CLK=High, SW=ON
CLK=LOW, SW OFF
In other words, when CLK is high at t, Vout(t) is Vin(t). When CLK changes high to low at t+dt,
Vout(t+dt) is Vin(t)
We describe this using VERILOG-A:
Verilog-A source (sample_hold.va):
‘include "descipline.h"
module sample_hold(in,out,clk);
input in,clk;
output out;
voltage in,out,clk;
parameter real clk_vth = 2.5;
real v;
analog
begin
@(initial_step)
v=V(in);
if (analysis("static") || (V(clk) > clk_vth))
v = V(in); // passing phase
@(cross(V(clk)-clk_vth,0))
v = V(in); // sampling phase
V(out)<+v;
end
endmodule

Verilog-A Examples
Spice Inputdeck (shold.in):
*------ Sample Hold ----*

.verilog "sample_hold.va"
v01 in 0 sin(2.5 2.5 100k)
v02 clk 0 pulse(0 5 0.2u 1n 1n 0.3u 0.6u)
YVLG_sample_amp in out clk sample_hold
c01 out 0 1p
.probe all
.iplot v(in)
+v(clk)
+’v(out)+10’
.tran 1n 20u
.end
Figure 15-29: Sample Hold Simulation Result

15.3.3: ADC (Pipelined ADC and user defined resolution)

Analog to Digital Converter (ADC) is now used in various regions.
ADC behavior changes from analog signal to digital code with a resolution.
Analog signal input changes into 4bit digital code at the same time, and ADC is then called pipelined
ADC.
As for Pipelined ADC, it is useful for Flash ADC.
Figure 15-30: *bit ADC Block

The ADC block has a sample hold circuit and a comparator. The Comparator compares input voltage
with digital weighed (8bit).
Figure 15-31: ADC Simulation Result
Verilog-A source (adc.va)

//----- Pipelined ADC-----//
module adc (in,out,clk);

Verilog-A Examples
parameter integer bit=10; // ADC resolution

parameter real fullscale =5.0,//supply voltage
vth=2.5,//threshold
dly=10n, // transition delay
ttime=1n; // transition rising time
input in; // input analog voltage

input clk; // input clock
output [bit-1:0] out; // digital vector output
electrical in,clk;
electrical [bit-1:0] out;
real sample;
integer result[bit-1:0]; // integer array
integer i; // index loop
analog begin
@( cross(V(clk)-vth, +1) ) begin
sample = V(in);
for( i=bit-1;i>=0;i=i-1 ) begin
if( sample>vth )
begin
result[i] = 5.0;
sample = sample - vth;
end else begin
result[i] = 0.0;
end
sample = 2.0 * sample;
end
end
for(i=0;i<bit;i=i+1 ) begin
V(out[i]) <+ transition(result[i], dly, ttime);
end
end
endmodule
Spice inputdeck(adc.in):
*----- 8bit pipelined ADC -----*
.verilog "adc.va"
.options iplot_one
* voltage sources
vvin vin 0 sin (2.5 2.5 1meg 0 0 )
vvclk vclk 0 PULSE (0 5 10n 1n 1n 5n 20n)
* Verilog-A adc module instantiation

YVLGadc vin msb 7bit 6bit 5bit 4bit 3bit 2bit lsb vclk adc bit=8 fullScale=5
* analysis
.tran 1n 1000n
.let msb=’v(msb)/5+20’

.let7bit=’v(7bit)/5+18’
.letlsb=’v(lsb)/5+6’
.letclk=’v(vclk)/5’
* save all data
.iplot v(vin) clk msb 7bit 6bit 5bit 4bit 3bit 2bit lsb
.end
DAC (pipelined DAC and User defined resolution):

DAC is a Digital to Analog converter, whose function is to put input digital signal change into an
analog signal.
Figure 15-32 is an 8bit DAC, and the circuit behavior is ideal.
Figure 15-32: 8bit DAC

Simulation results show the following:

Verilog-A Examples
Figure 15-33: DAC Simulation Results
Verilog-A source (dac.va):
//----- DAC -----//

module dacn(in,out) ;
parameter real fullscale=5; //supply voltage
parameter integer maxbit=10,
bit=10; //Resolution
input [0:bit-1] in ;
output out;
electrical out ;
electrical [0:bit-1] in ;
real vlump[maxbit:1];
real vout[maxbit:1]; //voltage
real outv,vth;
integer i; //index loop
integer code[bit-1:0]; //digital code analog begin
analog begin
@(initial_step)
begin
vth=fullscale/2 ;
for( i=1;i <= maxbit; i=i+1) begin
vlump[i]=fullscale/pow(2,i) ;
end
end
for (i=1 ;i<= bit; i=i+1) begin
if( V(in[i-1])>vth ) begin

code[i-1]=1 ;
end else begin
code[i-1]=0 ;
end
vout[i]=vlump[i]*code[i-1] ;
end
if (bit<maxbit) begin
for( i=maxbit;i>bit;i=i-1 ) begin
vout[i]=0 ;
end
end
outv=vout[1]+vout[2]+vout[3]+vout[4]+vout[5]+vout[6]+vout[7]+vout[9]+vout[10
] ;
// V(out) <+ transition(outv,50n,50n,50n) ;

V(out)<+outv;
end
endmodule
Spice inputdeck:
*----- 8bit DAC -----*
.verilog "dac.va"
.verilog "dff.va"
.options iplot_one
v03 clk 0 pulse(0 5 0u 1n 1n 0.5u 1u)
*
YVLG_dff1 q1 d1 clk d1 dff
YVLG_dff2 q2 d2 q1 d2 dff
*
YVLG_DAC d8 d7 d6 d5 d4 d3 d2 d1 out dac bit=8
.tran 1n 500u
.let LSB=’v(d1)/5+6’
.let BIT2=’v(d2)/5+8’
.let BIT3=’v(d3)/5+10’
.let BIT4=’v(d4)/5+12’
.let BIT5=’v(d5)/5+14’
.let BIT6=’v(d6)/5+16’
.let BIT7=’v(d7)/5+18’
.let MSB=’v(d8)/5+20’
*.let BIT9=’v(d9)/5+22’
*.let MSB=’v(d10)/5+24’

Verilog-A Examples
.iplot v(out) LSB BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 MSB
.probe all
.end
15.3.4: ADC to DAC Example:

This section shows the previous example code (adc.va and dac.va). In this case, ADC resolution is set to
5bit, and DAC resolution is set to 5bit.
This circuit block is shown as:
Figure 15-34: 5bit ADC and 5bit DAC Block

The simulation result is shown in the Figure 15-35.
Figure 15-35: 5bit ADC/DAC Simulation Result

Spice inputdeck (adctodac.in):

*----- 5bit ADC to 5bit DAC -----*
.verilog "dac.va"
.verilog "adc.va"
*
.options post probe
+ iplot_one
vvin vin 0 sin (2.5 2.5 0.1meg 0 0 -90 )
vvclk vclk 0 PULSE (0 5 10n 1n 1n 100n 200n)
*
*YVLGdac msb 3 2 1 out dac
YVLGdac 5 4 3 2 1 out dac bit=5
YVLGadc vin 5 4 3 2 1 vclk adc bit=5
*
.tran 1n 20u
.probe all
.let MSB=’0.2*v(5)+4’
+ 4bit=’0.2*v(4)+6’
+ 3bit=’0.2*v(3)+8’
+ 2bit=’0.2*v(2)+10’
+ LSB=’0.2*v(1)+12’
.iplot v(vin)
+ v(out)
+ LSB 2bit 3bit 4bit MSB
.end
15.3.5: Delta-Sigma Modulator

Delta-Sigma consists of circuit blocks (see Figure 15-36). The first block is the summing block, and the
second block is the integrator, but these blocks presently consist of SCF (switched capacitor filter). The
"D" block is a quantizer in Feedback loop, and the final block is 1bit dac.
Figure 15-36: Delta-Sigma Modulator

All blocks are driven by sampling CLOCK (CLK).

Verilog-A Examples
Figure 15-37: Delta-Sigma Simulation Result
Verilog-A source(delta_sigma.va):
module delta_sigma(in,clk,out);
input in,clk;
output out;
voltage in,clk,out;
parameter real quantizer_vth=2.5;
parameter real clk_vth=0;
parameter real d2a_gain=1.0;
real vsum;
real vd;
real vint;
real vout;
real hi,lo;
analog
begin
@(initial_step)
begin
vd=0;vint=0;vout=0;
hi = 5; lo = 0;
end
@(cross(V(clk) - clk_vth,1))
begin
// summing junction
vsum = V(in) - vd ;
// integrator
vint = vint + vsum;
// quantizer
if (vint > quantizer_vth) vout = hi ;

else vout = lo ;
// D to A
vd = d2a_gain*vout ;
end
V(out) <+ vd ;
end
endmodule
Spice inpudeck ( sdelta.in):

**----- Analog (1st order Delta-Sigma modulator) circuit -----**
*
.verilog "firstorder_sigmadelta.va"
.options iplot_one
v01 vcc 0 dc 5
v02 clk 0 pulse(0 5 10n 0.1n 0.1n 10n 20n)
v03 in 0 SFFM (2.5 2.5 44.1k 1000 10 )
*
YVLG_sigmdelata in clk out delta_sigm
*
.tran 1n 20u
.let vin=’v(in)+6’
.let vout=’v(out)+6’
.let vclk=v(clk)
.iplot vout vin vclk
.end
15.4: Example 1: DFF with Spice Primitives

This example shows some techniques for creating an accurate VERILOG-A module of Data Flip-Flop cell.
An accurate module can be realized by introducing complex delay and rise/fall time models, which are
a function of the output load and ramp-time of the clock pulse. Another technique is the use of SPICE
primitives such as capacitor, resistor, diode, BJT and MOSFET. In this example, capacitors are
instantiated inside the module representing the load capacitance of module terminals.
A practical example of DFF module is shown below.
Example: DFF module description (dff_cl.va)
// D-FF with CLEAR

// Tpd, Tr and Tf are optimized based on the result of device simulation
// using BSIM3v3.2 default parameter set and nominal condition.
//
module dff_cl (d, clk, clr, q) ;

input d, clk, clr ;
output q ;
electrical d, clk, clr, q ;

Verilog-A Examples
parameter real VDD=3.3, THRESH=0.5, LO_THRESH=0.2, HI_THRESH=0.8,

FO=2.0, SLOPE_IN=0.09n ;
parameter real C_D=9.78e-15, C_CLK=9.98e-15, C_CLR=12.40e-15 ;
parameter real TR_CLK_0=38.7647p, TR_CLK_1=244.058p,
TF_CLK_0=259.585p, TF_CLK_1=128.525p,
TF_CLR_0=276.347p, TF_CLR_1=122.161p,
TD_L2H_0=937.706p, TD_L2H_1=-163.297p,
TD_H2L_0=831.739p, TD_H2L_1=-76.1828p,
TD_CLR_0=184.611p, TD_CLR_1=-67.1826p,
SLOPE_COEF=0.33033, SLOPE_NOM=0.09n ;
/* following parameters are calculated internally */

parameter real delta_thresh=HI_THRESH-LO_THRESH, vth=VDD*THRESH,
tr_clk = (TR_CLK_0+TR_CLK_1*FO)/delta_thresh,
tf_clk = (TF_CLK_0+TF_CLK_1*FO)/delta_thresh,
tf_clr = (TF_CLR_0+TF_CLR_1*FO)/delta_thresh,
td_l2h = TD_L2H_0+TD_L2H_1*FO+SLOPE_COEF*(SLOPE_IN-
SLOPE_NOM),
td_h2l = TD_H2L_0+TD_H2L_1*FO+SLOPE_COEF*(SLOPE_IN-
SLOPE_NOM),
td_clr = TD_CLR_0+TD_CLR_1*FO+SLOPE_COEF*(SLOPE_IN-
SLOPE_NOM) ;
real td, tr, tf ;

integer state ;
/* SPICE primitives as input capacitor */

capacitor #(.c(C_D)) cdata(d) ;
capacitor #(.c(C_CLK)) cclk(clk) ;
capacitor #(.c(C_CLR)) cclr(clr) ;
/* Behavioral description of DFF with CLEAR */

analog
begin
@(initial_step)
begin
state=0 ; tr=tr_clk ;
end
@(cross(V(clk)-vth,+1))
begin
if(V(clr) < vth) state=0 ;
else state=(V(d) > vth) ;
if(state) td=td_l2h ;
else begin
td=td_h2l ; tf=tf_clk ;
end
end
@(cross(V(clr)-vth,-1))
begin
state=0 ; td=td_clr ; tf=tf_clr ;
end

V(q) <+ transition(VDD*state, td, tr, tf) ;

end
endmodule
In the module description, three capacitors are introduced to represent input capacitance of module
ports; d, clk and clr. The capacitance values are derived from transistor level simulation, and should
match to the equivalent gate capacitance of MOSFET at each module port. For rough estimation, the
following capacitance equation can be used to calculate gate capacitance.
Cgate = EPSox*L*W/TOX
where EPXox is gate oxide permittivity = 3.453143e-11 [F/m]
L and W are channel length and width in meter
TOX is gate oxide thickness in meter
Another technique for achieving accurate model is the introduction of complex formula to model delay
time and rise/fall transition time of flip-flop. Generally, the delay time is the function of fanout and
ramp-time of clock pulse, and can be formulated as follows;
Tdelay = T0 + T1*FANOUT + T2*SLOPE

where FANOUT is number of fanout drived by DFF output
SLOPE is ramp-time of clk pulse
T0 is delay time at FANOUT=0 and SLOPE=0
T1 is coefficient of fanout dependency
T2 is coefficient of ramp-time dependency
In this example, the parameter SLOPE is replaced by (SLOPE - SLOPEnom), where SLOPEnom is the
nominal slope at which T0 and T1 are extracted.
The transition time is formulated in the same manner as delay time, except the fanout dependency
term is excluded, and is defined as following formula;
Ttrans = TT0 + TT1*FANOUT

where FANOUT is number of fanout drived by DFF output
TT0 is transition time at FANOUT=0
TT1 is coefficient of fanout dependency
Note that since the delay time of high data and low data are not identical, the different delay
parameters are introduced to calculate each delay formula of high and low data. In addition, the
different delay parameters are introduced to calculate the clear time. Likely, the different transition
parameters are introduced to calculate rise and fall time individually.

Verilog-A Examples
15.5: Simulation with SmartSpice

8-bit shift resister circuit and input deck are shown in Figure 15-38 and the following Example,
respectively.
Figure 15-38: 8 Bit Shift Resistor
Example: Input deck of 8-bit shift register
* 8-Bit Shift Register

*
*********************************** Netlist ********************************
VCLR CLR 0 PWL(0 0 1N 0 1.09N VDD 102N VDD 102.09N 0)
VCLK CLK 0 PULSE(0 VDD 5N SLOPE SLOPE 4.91N 10N)
VDATA DATA 0 PULSE(0 VDD 3N SLOPE SLOPE 9.91N 20N)
VDD VDD 0 DC 3.3
XCLK CLK CLKB INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5U
XCLKB CLKB CLK_VA INVERTER PARAMS: WP=’6.8U*4’ LP=0.5U WN=’4.8U*4’
LN=0.5U
XDATA DATA DATAB INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5U
XDATAB DATAB DATA_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5U
XCLR CLR CLRB INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5U

XCLRB CLRB CLR_VA INVERTER PARAMS: WP=’6.8U*4’ LP=0.5U WN=’4.8U*4’

LN=0.5U
YVLG0 DATA_VA CLK_VA CLR_VA Q0 DFF_CL FO=2.03085 SLOPE_IN=SLOPE_VAL
YVLG1 Q0 CLK_VA CLR_VA Q1 DFF_CL FO=2.03085 SLOPE_IN=SLOPE_VAL
XOUT0 Q0 O0_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5U
CL0 O0_VA 0 ’0.01PF*2’
CL1 O1_VA 0 ’0.01PF*2’
CL2 O2_VA 0 ’0.01PF*2’
CL3 O3_VA 0 ’0.01PF*2’
CL4 O4_VA 0 ’0.01PF*2’
CL5 O5_VA 0 ’0.01PF*2’
CL6 O6_VA 0 ’0.01PF*2’
CL7 O7_VA 0 ’0.01PF*2’
***** Subcircuit Definitions
.SUBCKT INVERTER IN OUT
MP1 OUT IN GND GND NM L=LN W=WN
MP2 OUT IN VDD VDD PM L=LP W=WP
.ENDS INVERTER
****************************** Control Deck ******************************
.MODEL PM PMOS LEVEL=8
.MODEL NM NMOS LEVEL=8
.VERILOG ’dff_cl.va’
.GLOBAL VDD GND
.PARAM VDD=3.3 SLOPE=0.09N SLOPE_VAL=308p
.SAVE V(CLK_VA) V(CLR_VA) V(DATA_VA)
+ V(O0_VA) V(O1_VA) V(O2_VA) V(O3_VA) V(O4_VA) V(O5_VA) V(O6_VA)
V(O7_VA)
.OPTIONS ACCT NOMOD
.TRAN 1P 120N
.END
Simulation Results:
Simulation results are shown in Figure 15-39 through Figure 15-41. These figures show that the
waveforms obtained from VERILOG-A simulation (solid lines) are well matched to those obtained from
transistor level simulation (dot lines).

Verilog-A Examples
Figure 15-39: CLK Signals Simulation Results
Figure 15-40: Output Signals (Rise) Simulation Results
Figure 15-41: Output Signals (Fall) Simulation Results
15.6: Example 2: PLL

The block diagram of PLL is shown in Figure 15-42. The PLL consists of digital blocks; Phase Detector
(PD) and clock Divider, and analog blocks; Voltage Controlled Oscillator (VCO), Charge Pump (CP) and
Loop Filter (LPF). Some of these blocks can be replaced by the VERILOG-A module for the purpose of
reducing the simulation time.
In this example, the PD, VCO and Divider blocks are replaced by the VERILOG-A module, and perform a
simulation to see the phase-lock characteristic of PLL.

Figure 15-42: PLL Block Diagram

The VERILOG-A module descriptions for each blocks are shown in List 2-1 through List2-3.
Example: Phase Detector module description (pll_pd.va)

// Phase Detector
//
module pll_pd (in_ref, in_fb, out_up, out_dn);

inout in_ref, in_fb, out_up, out_dn;
electrical in_ref ,in_fb ,out_up, out_dn;
parameter real vdd=3.3, ttol=10f, delay=1n, ttime=0.1n ;
integer state; // state=1 for down, -1 for up
analog begin
@(cross( V(in_ref) - vdd/2 , 1 , ttol )) state = state - 1;
@(cross( V(in_fb) - vdd/2 , 1 , ttol )) state = state + 1;
if ( state > 1 ) state = 1 ;
if ( state < -1 ) state = -1;
V(out_dn) <+ transition( (state + 1)/2*vdd , delay , ttime );
V(out_up) <+ transition( (state - 1)/2*vdd+vdd , delay , ttime );
end
endmodule
Example: VCO module description (pll_vco.va)

// VCO
//

Verilog-A Examples
module pll_vco ( in, out ) ;

inout in, out ;
electrical in, out ;
parameter real vdd=3.3 ;
parameter real amp = vdd/2, // amplitude of vout [V]
offset = vdd/2, // offset of vout [V]
gain = 464e6, // gain [Hz/V]
vnom = 1.270, // nominal vin [V]
fc = 400e6 ; // center frequency@vnom [Hz]
real freq ;
analog begin
freq = fc + gain * (V(in) - vnom) ;
V(out) <+ amp * sin( 2 * ‘M_PI * idt(freq) ) + offset ;
end
endmodule
Example: Divider module description (divider.va)

// CLOCK DIVIDER
//
module divider ( in, out ) ;

inout in, out ;
electrical in, out ;
parameter integer num_div = 4 ; // number of divide
parameter real vdd = 3.3 ,
delay = 2n ,
ttime = 0.1n ;
integer count, state ;
analog begin
@( cross( V(in) - vdd/2 , +1 ) ) begin
if ( count >= div_num/2 ) begin
state = !state ;
count = 0 ;
end
count = count + 1 ;
end
V(out) <+ transition( state * vdd, delay , ttime ) ;
end
endmodule
Note that the parameters gain and vnom used in VCO module, are derived from transistor level
simulation, therefore the phase-lock characteristic obtained from the VERILOG-A simulation would be
matched to that obtained from transistor level simulation.
The input deck is shown in the following Example.

Example: Input Deck of PLL simulation

* PLL ; SPICE/Verilog-A Mixed Simulation
*
*------------------ Verilog-A module file ------------------*
.verilog "pll_pd.va" ; Phase Detector
.verilog "pll_vco.va" ; VCO
.verilog "divider.va" ; Clock Divider
*------------------ SPICE Subcircuit file ------------------*
.include "pll_cp.net" ; Charge Pump
.include "pll_lpf.net" ; Loop Filter
*-------------------- PLL Main Circuit ---------------------*
YVLGpd ref fb up down pll_pd
Xcp up down lpf pll_cp
Xlpf lpf pll_lpf
YVLGvco lpf ckout pll_vco
YVLGdiv ckout fb divider
vref ref 0 pulse(0 3.3 22.4n 0.1n 0.1n 4.9n 10n)

vvdd vdd 0 3.3
.tran 1n 2u
.ic v(lpf)=1.1
.save v(ref) v(fb) v(up) v(down) v(lpf) v(ckout)
.end
Simulation Results:
Simulation results are shown in Figure 15-43 through Figure 15-45.
Figure 15-43 shows the phase-frequency difference between reference clock and feedback clock at
time=0s. After 1.5us of transient simulation, the feedback clock is locked to the reference clock as
shown in Figure 15-44. The VCO input voltage supplied from charge pump keeps constant value of
1.27v which is consistent with the given value of parameter vnom in VCO module.
Figure 15-45 shows the phase-lock characteristic of VERILOG-A mixed simulation and full transistor
level simulation.
Figure 15-43: V(vco_in) at time=0 s Simulation Results

Verilog-A Examples
Figure 15-44: V(vco_in) at time=1.5 us Simulation Results
Figure 15-45: Comparison with transistor level Simulation Results


Index
Symbols ac.................................................................................... 9-1

AEPI ............................................................................ 14-60
$abstime Function............................................................... 9-8
AEX ............................................................................. 14-60
$display .......................................................................... 9-19
AF ............................................................................... 14-60
$fdisplay ......................................................................... 9-23
AFN ........................................................................... 14-128
$fstrobe .......................................................................... 9-22
AJC ........................................................................... 14-126
$fwrite ............................................................................ 9-23
AJE ........................................................................... 14-126
$realtime Function .............................................................. 9-8
AJS ........................................................................... 14-126
$sit_get_ddv .................................................................... 9-16
Analog Conditional .............................................................. 5-5
$sit_get_prev ................................................................... 9-16
Analog Operators.............................................................. 6-11
$strobe ........................................................................... 9-17
Analog Procedural Block....................................................... 5-1
$write............................................................................. 9-19
Analog Signals ................................................................... 5-7
*AE.............................................................................. 14-60
Analysis............................................................................ 9-1
*AQB0.......................................................................... 14-60
Arithmetic Operators............................................................ 6-4
*AXI............................................................................. 14-59
Arrays .............................................................................. 4-5
*CBCO ......................................................................... 14-61
ART ........................................................................... 14-126
*CBEO ......................................................................... 14-61
AS ............................................................................... 14-61
*CTH ........................................................................... 14-61
Attributes HUGE, BLOWUP, MAXDELTA
*DEG ........................................................................... 14-60
(Cadence Comparibility).................................................. 13-3
*DVGBF ....................................................................... 14-60
Avalanche constant ......................................................... 14-64
*DVGBR ....................................................................... 14-60
AVC1 ......................................................................... 14-125
*DVGTE ....................................................................... 14-60
AVC2 ......................................................................... 14-125
*HRCF ....................................................................... 14-126
*IKF ........................................................................... 14-124
B
*IKP........................................................................... 14-124
Base Charge................................................................ 14-129
*IKR........................................................................... 14-124
Base Charge Equations.................................................... 14-41
*ITF ........................................................................... 14-127
Base Emitter Capacitance Equations................................... 14-42
*MLF............................................................................ 14-59
Base Nature ...................................................................... 4-7
*RTH ........................................................................... 14-61
base resistance model ..................................................... 14-42
*TAUB.......................................................................... 14-60
Base Width Modulation Parameters (Early Effect)................... 14-47
*TAUE.......................................................................... 14-60
Base-Collector Capacitance Equations ................................ 14-43
*TAUR.......................................................................... 14-60
Base-Collector Charge ................................................... 14-135
*TEPI ........................................................................... 14-60
Base-Collector Charge of the Parasitic Device..................... 14-136
*VAVL .......................................................................... 14-59
Base-Collector Current of the Parasitic Device..................... 14-133
*VBBE........................................................................ 14-128
Base-Collector Depletion Capacitance ................................. 14-43
*VEF............................................................... 14-59, 14-124
Base-Collector Diffusion Capacitance .................................. 14-43
*VER .............................................................. 14-59, 14-124
Base-Collector Weak Avalanche Current ............................ 14-132
*VO ........................................................................... 14-126
Base-Emitter Breakdown Current...................................... 14-132
*VRT.......................................................................... 14-126
Base-Emitter Charge ..................................................... 14-135
*VTF .......................................................................... 14-127
Base-Emitter Charge of the Parasitic Device ....................... 14-136
*WAVL ......................................................................... 14-59
Base-Emitter Current of the Parasitic Device ....................... 14-132
*XREC ......................................................................... 14-60
Base-Emitter Depletion Capacitance ................................... 14-43
A Base-Emitter Diffusion Capacitance .................................... 14-42
Base-Emitter Tunneling Parameters .................................. 14-128
AB............................................................................... 14-60
Basic DC Model Parameters.............................................. 14-45
Absolute Delay Operator .................................................... 6-14
BF ................................................................... 14-46, 14-59
AC............................................................................... 14-60
BFN ........................................................................... 14-128
SILVACO International Index-1

Binary Operators................................................................. 6-5 Depletion charge............................................................ 14-74

Binding Natures ................................................................ 4-10 Derived Nature .................................................................. 4-9
BJT Modeling ................................................................. 14-41 Description of charges..................................................... 14-72
Block Names...................................................................... 5-2 Differences between v1.1.5 and v1.2 ................................ 14-121
Block Statements ................................................................ 5-1 diffusion capacitance ...................................................... 14-42
Bounding the Time Step ....................................................... 9-7 Discipline of Wires and Undeclared Nets ............................... 4-14
BR............................................................................... 14-46 Disciplines ...................................................................... 4-10
Branches ........................................................................ 4-16 Discontinuity ..................................................................... 9-5
BRI .............................................................................. 14-59 Distributed High Frequency Effects
Built-in Potentials .......................................................... 14-138 In the Intrinsic Base..................................................... 14-77
BULK (NSUB) .............................................................. 14-123 DTA ............................................................................ 14-58
C E
Capacitance Equations..................................................... 14-42 EA ............................................................................ 14-127
Capacitance Temperature Equations................................... 14-45 EAIC ......................................................................... 14-127
Case ................................................................................ 5-5 EAIE ......................................................................... 14-127
CBCO ........................................................................ 14-125 EAIS ......................................................................... 14-127
CBEO......................................................................... 14-125 EANC ........................................................................ 14-127
CCSO ........................................................................ 14-125 EANE ........................................................................ 14-127
Charge and Capacitance Equations .................................. 14-133 EANS ........................................................................ 14-127
Chi-Square Distribution ...................................................... 9-14 EAP .......................................................................... 14-127
Circular Integrator Operator................................................. 6-13 Early Voltage Parameters .............................................. 14-124
CJC .................................................... 14-47, 14-60, 14-126 EKV MOSFET Model ...................................................... 14-29
CJCP ......................................................................... 14-126 Emission Coefficient Parameters ..................................... 14-123
CJE .................................................... 14-47, 14-59, 14-125 Emitter depletion charges................................................. 14-72
CJEP ......................................................................... 14-126 Empty Disciplines............................................................. 4-14
CJS ................................................................. 14-48, 14-61 Epilayer Parameters ........................................ 14-126, 14-139
Closing a File ................................................................... 9-24 Equivalent circuit.......................................................... 14-122
Collector Current Contributions ........................................ 14-129 Equivalent Circuit for Large Signal Analysis.......................... 14-58
Collector Resistance........................................................ 14-70 Equivalent Circuit of the VBIC
Compatibility of Disciplines.................................................. 4-11 Bipolar Model (large signal)......................................... 14-122
Compiler Directives ............................................................. 3-9 Erlang Distribution ............................................................ 9-15
Concatenations ................................................................ 6-10 Escaped........................................................................... 3-6
Conditional Statement .......................................................... 5-4 Event Detection ................................................................. 8-1
conservative system ............................................................ 1-3 Event OR Operator............................................................. 6-9
Control Flow .................................................................... 2-11 EXAVL......................................................................... 14-59
Converting Real Numbers to Integer Numbers ........................... 4-2 Excess Phase Network.................................................. 14-136
Correlated noise ................................................................. 9-4 exclude ............................................................................ 4-5
cross function..................................................................... 8-4 EXMOD ....................................................................... 14-58
current crowding ............................................................. 14-77 EXPHI ......................................................................... 14-59
Current Gain .................................................................. 14-63 Exponential Distribution ..................................................... 9-12
Currents and Voltages...................................................... 14-64 Extended Modeling of the Reverse
Current Gain EXMOD = 1 ............................................. 14-75
Currents in Modulated Resistors....................................... 14-130
External Base-Internal Collector
Junction Capacitance .................................................. 14-44
D Extrinsic collector depletion charges ................................... 14-73
dc.................................................................................... 9-1
DC Current Equations .................................................... 14-128 F
DC current Equations....................................................... 14-65
FC ................................................................. 14-47, 14-125
DEAR......................................................................... 14-127
flicker_noise...................................................................... 9-3
Declaring .......................................................................... 2-2
For.................................................................................. 5-6
Depletion Capacitances.................................................... 14-63
Index-2 SILVACO International

Index
Forward Base Currents .................................................... 14-66 ISE .............................................................................. 14-46

Forward mode (IC1C2 > 0)................................................ 14-70 ISP ............................................................................ 14-123
from................................................................................. 4-5 ISRR.......................................................................... 14-123
ISS .................................................................. 14-48, 14-60
G ITF .............................................................................. 14-48
GAMM........................................................................ 14-126
General Parameters ...................................................... 14-122 J
Genvars............................................................................ 4-5 Junction Capacitance Parameters..................................... 14-125
GEOM (SUBS)............................................................... 14-46 Junction Capacitor Parameters .......................................... 14-47
Geometry scaling............................................................ 14-65
Ground ........................................................................... 4-15 K
Gummel-Poon BJT Model Equations................................... 14-41 Keywords.......................................................................... 3-7
KF ............................................................................... 14-60
H KFN ............................................................... 14-60, 14-128
Heterojunction features ......................................... 14-65, 14-78 Kirchoff ’s Potential Law (KPL) ............................................... 1-3
High Current Beta Degradation Kirchoff’s Flow Law (KFL) ..................................................... 1-3
Effect Parameters .......................................... 14-47, 14-124
L
I Laplace Transform Filters ................................................... 6-22
IBBE .......................................................................... 14-128 laplace_nd....................................................................... 6-24
IBCI ........................................................................... 14-123 laplace_np....................................................................... 6-24
IBCIP ......................................................................... 14-123 laplace_zd....................................................................... 6-23
IBCN.......................................................................... 14-123 laplace_zp....................................................................... 6-23
IBCNP........................................................................ 14-123 LEVEL............................................................ 14-58, 14-122
IBEI ........................................................................... 14-123 LEVEL 3 Verilog-A Model Listing ........................................ 14-16
IBEIP ......................................................................... 14-123 Limited Exponential ........................................................... 6-27
IBEN.......................................................................... 14-123 Logical Operators................................................................ 6-7
IBENP........................................................................ 14-123 Looping ............................................................................ 5-6
IBF .............................................................................. 14-59 Low Current Beta Degradation Parameters ........................... 14-46
IBR.............................................................................. 14-59
ic..................................................................................... 9-1 M
Ideal forward and reverse current ....................................... 14-65 Main Current IN .............................................................. 14-65
Ideal Forward and Reverse Currents ................................. 14-129 MC ................................................................ 14-60, 14-126
Identifiers .......................................................................... 3-6 ME ............................................................................ 14-126
IHC.............................................................................. 14-59 MJC............................................................................. 14-47
IK ................................................................................ 14-59 MJE ............................................................................. 14-47
IKF .............................................................................. 14-47 MJS ............................................................................. 14-48
IKR.............................................................................. 14-47 Model constants ............................................................. 14-62
IKS .............................................................................. 14-61 Model Parameters........................................................... 14-58
Implicit............................................................................ 4-17 Modella Bipolar Transistor............................................... 14-159
Instantiating Analog Primitives that Use module ............................................................................. 2-1
Array Valued Parameters .............................................. 10-19
Modules.......................................................................... 10-1
Integer ............................................................................. 3-2 Creating and Naming ..................................................... 10-1
integer.............................................................................. 4-3 Instantiating Analog Primitives.......................................... 10-9
Integer Numbers................................................................. 4-1 Multilevel Hierarchal Designs ........................................... 10-5
Intrinsic and Extrinsic Base-Emitter Current ........................ 14-131 Overriding Parameter Values ........................................... 10-7
Intrinsic Base-Collector Current........................................ 14-132 Overriding Parameter Values in Instances........................... 10-7
Ports of Module Instances ............................................... 10-3
Intrinsic collector depletion charge ...................................... 14-72
Monitored Events ................................................................ 8-4
IRB.............................................................................. 14-47
MOSFET Model LEVEL=3 ................................................ 14-15
IS ....................................................... 14-46, 14-59, 14-123
MOSFET model LEVEL=3
ISC.............................................................................. 14-46
DC current equations ................................................... 14-11

model parameters........................................................ 14-15 Port Direction .................................................................... 2-4

MS ............................................................................ 14-126 Port Type ......................................................................... 2-4
MTAU........................................................................... 14-60 Ports ............................................................................... 2-3
MULT ........................................................................... 14-58 Probes............................................................................. 5-9
Probes and Sources ........................................................... 5-9
N PS ................................................................. 14-61, 14-126
Name ............................................................................... 2-3
Natures................................................................... 4-6, 4-15 Q
NBBE ......................................................................... 14-128 QBM ......................................................................... 14-123
NC............................................................................... 14-46 QCO ......................................................................... 14-126
NCI............................................................................ 14-123 QTF .......................................................................... 14-126
NCIP.......................................................................... 14-124
NCN .......................................................................... 14-124 R
NCNP......................................................................... 14-124 Random Numbers .............................................................. 9-9
NE............................................................................... 14-46 RB .............................................................................. 14-47
NEI ............................................................................ 14-123 RBC............................................................................ 14-59
NEN........................................................................... 14-123 RBI ........................................................................... 14-125
NF ................................................................. 14-46, 14-123 RBM ........................................................................... 14-47
NFP ........................................................................... 14-124 RBP .......................................................................... 14-125
NK (NKF) ...................................................................... 14-47 RBV ............................................................................ 14-59
NKF ........................................................................... 14-124 RBX .......................................................................... 14-125
Nodes ............................................................................ 2-14 RC.............................................................................. 14-47
nodeset ............................................................................ 9-1 RCC............................................................................ 14-59
Noise ............................................................................... 9-3 RCI ........................................................................... 14-125
noise .................................................................... 9-1, 14-78 RCV............................................................................ 14-59
Noise Model .................................................................. 14-78 RCX.......................................................................... 14-125
Noise Parameters ......................................................... 14-128 RE ...................................................... 14-47, 14-59, 14-125
noise_table........................................................................ 9-3 Real ................................................................................ 3-3
Non-Ideality Factors and Weak Avalanche real ................................................................................. 4-3
Model Parameters ..................................................... 14-138 Real Numbers ................................................................... 4-1
Normal (Gaussian) Distribution............................................. 9-12 Repeat and While............................................................... 5-6
Normalized Junction Depletion Charge .............................. 14-133 Resistance Parameters ................................................. 14-125
NR................................................................. 14-46, 14-123 Resistances .................................................................. 14-62
NS............................................................................... 14-48 Reverse Base Currents ................................................... 14-66
Numbers ........................................................................... 3-2 Reverse mode (IC1C2 ...................................................................14-71
REVISION (REV, VREV) ............................................... 14-122
O RS ............................................................................ 14-125
Operators.......................................................................... 3-2
Ordinary............................................................................ 3-6 S
Overlap Capacitance Parameters ..................................... 14-125 Saturation Current Parameters ........................................ 14-123
Saturation Currents ...................................................... 14-137
P Saturation Currents and Current Gain ................................. 14-44
Parameters................................................................ 2-5, 4-3 SCRCV........................................................................ 14-59
Parasitic Resistor Parameters ............................................ 14-47 Self-heating feature ........................................................ 14-80
Parasitic Resistors ........................................................ 14-137 Sequential ........................................................................ 5-3
Partioning Parameters.................................................... 14-124 Sequential Blocks............................................................... 5-1
PC................................................................. 14-60, 14-126 SFH ............................................................................ 14-59
PE ................................................................. 14-59, 14-125 Shift Operators .................................................................. 6-9
phase-shift .................................................................... 14-77 Signal Access Functions ...................................................... 5-7
Poisson Distribution........................................................... 9-13 Signal-flow systems ............................................................ 1-4
Port Declaration.................................................................. 2-4 Silvaco System Functions .................................................. 9-16

Index
Single piece model........................................................ 14-134 of the Parasitic Device ................................................ 14-130

Slew Filter ....................................................................... 6-20 TREF ........................................................................... 14-58
Sources ............................................................................ 5-9 Trigonometric and Hyperbolic Functions................................... 7-2
Special Characters.............................................................. 3-5 TVBBE1...................................................................... 14-128
Specified Distributions........................................................ 9-11 TVBBE2...................................................................... 14-128
Standard Gummel-Poon model ........................................ 14-133
Standard Mathematical Functions........................................... 7-1 U
static................................................................................ 9-1 Uniform Distribution ........................................................... 9-11
Stored base charges ....................................................... 14-74 User-Defined Functions...................................................... 9-24
Stored emitter charge ...................................................... 14-74
Stored epilayer charge ..................................................... 14-75 V
Stored extrinsic charges ................................................... 14-75 VAF ............................................................................. 14-47
Strings.............................................................................. 3-5 VAR............................................................................. 14-47
Student’s T Distribution ...................................................... 9-14 Variable Base Resistance ................................................. 14-69
Substrate Capacitance..................................................... 14-44 Variable Base Resistance Equations ................................... 14-41
substrate current............................................................. 14-41 VBIC Bipolar Transistor .................................................. 14-121
Substrate Current Equations ............................................. 14-41 Model Parameters ..................................................... 14-122
Substrate Current Parameters ........................................... 14-48 Temperature Scaling.................................................. 14-136
Survey of Modeled Effects ................................. 14-121, 14-159 VDC............................................................................. 14-60
Survey of modeled Effects ................................................ 14-57 VDE............................................................................. 14-59
VDS............................................................................. 14-61
T VERSION (VERS)......................................................... 14-122
TAVC......................................................................... 14-128 VGB............................................................................. 14-60
TD............................................................................. 14-127 VGC ............................................................................ 14-60
temperature................................................................... 14-44 VGJ ............................................................................. 14-60
Temperature conversions ................................................. 14-62 VGS............................................................................. 14-61
Temperature dependence of thermal resistance................... 14-136 VJC ............................................................................. 14-47
Temperature Effect Parameters ............................ 14-48, 14-127 VJE ............................................................................. 14-47
Temperature Effects Equations .......................................... 14-44 VJS ............................................................................. 14-48
Temperature scaling........................................................ 14-62 VLR ............................................................................. 14-59
Ternary Operator ................................................................ 6-9 VTF ............................................................................. 14-48
TF .................................................................. 14-48, 14-126
The Improved Mextram Transistor W
Model (LEVEL=504) .................................................... 14-57 WBE .......................................................................... 14-124
The power function Weak Avalanche Current .................................................. 14-67
$pwr........................................................................... 13-3 Weak Avalanche Parameters........................................... 14-125
Thermal Voltage ................................................................. 9-9 White Space ...................................................................... 3-1
Time Derivative Operator.................................................... 6-12 white_noise ....................................................................... 9-3
Time Integral Operator ....................................................... 6-12 Writing to a File ................................................................ 9-22
timer function ..................................................................... 8-5 WSP .......................................................................... 14-124
TNBBE....................................................................... 14-128
TNF ........................................................................... 14-128 X
TNOM ........................................................................ 14-127
X (Subcircuit Call) ........................................................... 10-18
Tokens ............................................................................. 3-1
XCJC ............................................................... 14-48, 14-60
TR.................................................................. 14-48, 14-127
XCJE ........................................................................... 14-60
tran.................................................................................. 9-1
XEXT ........................................................................... 14-59
Transit Time and Excess Phase Parameters ....................... 14-126
XIBI ............................................................................. 14-59
Transit Time Parameters .................................................. 14-48
XII ............................................................................. 14-128
Transit Times ................................................................. 14-64
XIKF .......................................................................... 14-128
Transition Filter ................................................................ 6-15
XIN ............................................................................ 14-128
Transport Current and Base Charge
XIS ............................................................................ 14-127

XISR .......................................................................... 14-128

XP ............................................................................... 14-60
XRB (XRBI) ................................................................. 14-127
XRBP ......................................................................... 14-127
XRBX ......................................................................... 14-127
XRC (XRCI)................................................................. 14-127
XRCX......................................................................... 14-127
XRE........................................................................... 14-127
XRS........................................................................... 14-127
XTF ............................................................... 14-48, 14-126
XVO........................................................................... 14-127
Z
Zero-Bias Capacitances ................................................. 14-139
zi_nd .............................................................................. 6-27
zi_np .............................................................................. 6-27
zi_zd .............................................................................. 6-26
zi_zp .............................................................................. 6-26
Z-Transform..................................................................... 6-25

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Verilog-A

User’s Manual Draft

SILVACO International January 2004

Phone: (408) 567-1000

The information contained in this document is subject to change without notice.

SILVACO International iii

SILVACO International TOC-vii

3.8: Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

TOC-viii SILVACO International

5.8.4: Behavioral Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

SILVACO International TOC-ix

TOC-x SILVACO International

SILVACO International TOC-xi

13.2.8: Usage of the command .ST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

TOC-xii SILVACO International

14.7.9: Source/Drain Diffusion Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-81

SILVACO International TOC-xiii

15.3.5: Delta-Sigma Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34

TOC-xiv SILVACO International

1.1: Modeling with the Verilog-A Language Overview

1.2: Representing a System

1.2.1: Nets and nodes

SILVACO International 1-1

Figure 1-1: Nets and Nodes

1.3: Verilog-A Systems

1-2 SILVACO International

1.4: Conservative Systems

Conservative Systems Electrical Systems

1.4.1: Kirchhoff’s Laws

SILVACO International 1-3

1.4.2: Reference Nodes

1.4.3: Reference Directions

1.5: Signal-Flow Systems

1.6: Mixed Conservative and Signal-Flow Systems

1-4 SILVACO International

module res(in, out);

endmodule // end module res

parameter real r=100 from (0:inf); | parameter declarations

SILVACO International 2-1

2.2: Declaring Modules

module_identifier: The name of the module being declared.

2-2 SILVACO International

2.3: Declaring the Module Interface

2.3.1: Module Name

SILVACO International 2-3

voltage P, N; // types of ports

m1 and1(out1, ina, inb); // module instantiation (section 2.4.1)

capacitor #(1u) C1(out, ref); // module instantiation (section 2.4.1)

Port Declaration Example

2-4 SILVACO International

parameter real gain = 8.0;

Optional type specifier Optional range specification

SILVACO International 2-5

module diode(p, n);

parameter real area=4;

real vd, id, qd; //Internal variables

2-6 SILVACO International

2.4: Structural Descriptions

2.4.1: Module Instantiations

The general format of module instantiation:

Positional (Ordered) Association and Assignment of Parameters

module a2d(d0, d1, d2, d3, in, clk);

/* This is /* an illegal / comment /