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Fig. 3. Four operation stages of the proposed S PFC converter during one switching period. (a) Mode 1 (T 0 T ). (b) Mode 2 (T 0 T ). (c) Mode 3 (T 0 T ).
(d) Mode 4 (T 0 0
T ). (d) Mode (T T ). (e) equivalent circuit at T T . 0
voltage source in series with a diode . Before the time A blocking voltage equal to is applied across
, switches S1 and S2 are turned off and no current is flowing in output diode , and is reversed biased. The output
the primary side (i.e., ). Meanwhile, voltage is sustained by . Note that only one voltage
diode is in conduction state and transformer T1 continues source (i.e., ) provides the current of two switches, which
delivering energy to output through current . equals .
Mode 1 : Both the switches S1 and S2 are closed. Mode 2 : Mode 2 is initiated by turning off S2 while
As the intermediate bus voltage is higher than the rectified S1 remains in on-state. The parallel capacitance of S2 is charged
input voltage at all times, the bridge diodes are reverse up so that the drain-to-source voltage of S2, , rises towards
biased. Therefore, inductor is not charging and is zero. until it is clamped by , as shown in Fig. 3(b). During this
Capacitor is discharged through , as shown period, the energy stored in T1 cannot be coupled to output as
in the equivalent circuit in Fig. 3(a). Energy is being stored in S1 is still closed. Because cannot sustain a sudden change of
the flyback transformer T1, and the current increases linearly current direction, is turned on to maintain the current flow
with a slope in T1. The voltage applied across primary winding of T1 is thus
zero (assume has zero forward voltage drop). Namely, T1 is
(1) free-wheeling within this interval and the rate of change of
LU et al.: SINGLE-STAGE AC/DC CONVERTER WITH HIGH POWER FACTOR 221
(5)
(6)
(7)
Fig. 4. Key switching waveforms of the proposed S PFC converter during two
successful switching period. After some time, S1 and S2 turns on again to begin the next
switching cycle, the operation described above will repeat.
is zero. Meanwhile, the rectified input voltage is applied on III. CONTROL
and is charged up linearly with a slope
The main objective of the control system is to find a simple
(2) and effective way to control the two switches S1 and S2 so that
PFC is achieved, the bus voltage and the output voltage
are regulated as line and load vary.
By the KCL, the current into node X (as shown in Fig. 2) equals
the current out of the node, we have the following relationship: A. PFC
(3) Given that the input voltage is a rectified sinusoidal wave, i.e.,
, where and are the angular frequency
Therefore, the current in is not a constant but is decreasing and the peak value of line input voltage. Assume the inductor
with the expression given by works in DCM, the instantaneous input current is obtained by
averaging the inductor current over a switching period, which is
(4) given by
(10)
where and are the boost inductor current and storage ca-
pacitor discharging current through T1, respectively. From (10),
apart from the individual conduction loss there is an extra loss
term . This explains why conventional S PFC
converters have higher power dissipation and lower total effi-
ciency than that of conventional two-stage PFC voltage regu-
lator when allowing two individual currents to flow through the
same switch simultaneously.
Reduction of switch current stress of the proposed converter is
achieved by separating the current injecting into S1 from the two
voltage sources (bus voltage and rectified input voltage ).
Since is always higher than , when S1 and S2 are turned
on only current from is flowing through the switches because
the bridge rectifier is reverse biased. When S2 is turned off but
S1 is kept on, the current from ceases so that input current
can flow through S1. By inspecting the waveforms in Fig. 4, the
switch current of S1 is equal to from to . And during pe-
riod to , the switch current is clamped to the peak current of
Fig. 6. Configuration of adopted dual-loop current mode PWM control in sim-
due to . Therefore, the conduction loss on S1 is reduced to
plified version.
(11)
and bus voltage regulation. The bus voltage is detected by the Due to the circuit operation, a conduction loss on equals
inverting input of the error amplifier E/A 2 with compensation (12)
network, and an error control voltage is generated. is
summed with the inductor current and compared to ground is observed at Mode 2, where is the voltage drop on . By
by comparator PWM 2 to produce desired off-duty cycle for putting a couple of diodes in parallel, the loss may be minimized
S1 through the D-type flip-flop (FF2). S1 will not go to low due to sharing of current. The lower the current in each diode
state until PWM1 commands S2 to turn off and current is then the lower the forward voltage drop. The current stress in S2 for
flowing through (in Fig. 2) to pull point B negative when both S PFC converter in Fig. 1 and proposed one is the same as
peak inductor current is reached. the two-transistor clamped flyback converter.
In the design of the controller, on one hand, the compensa- To compare the rms current of S1 of proposed converter
tion network by E/A2 is of slow response, which has around with that of Fig. 1 fairly, the circuits parameters mentioned in
10–20 Hz of cutoff frequency, to avoid the 100-Hz ac ripple Section III-A are used for both converters. Unlike the proposed
from bus capacitor being amplified and cause input current dis- converter, inductor and primary magnetizing currents in Fig. 1
tortion eventually. On the other hand, E/A1 is of fast response conduct simultaneously and are confined by the same duty cycle
to provide tight output regulation. ( in this case). Besides, to achieve the same output power at
100-V input, inductor is reduced to 26.5 H. The average
IV. CURRENT STRESS ON POWER SWITCHES values of S1 rms current over a half line period of proposed and
For conventional S PFC converter such as in Fig. 1, when conventional ones are, respectively, given by (13) and (14) at
both switches S1 and S2 are closed, currents from line input bottom of the page. In this example, the proposed converter re-
and storage capacitor inject into S1 simultaneously. duces the rms current of S1 by 3.3 times of the conventional one.
(13)
(14)
224 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008
Fig. 7. Experimental circuit showing practical devices values and placement of current sensing resistors.
V. STAND-BY MODE OPERATION boost and flyback parts as discussed in Section III. The experi-
mental power stage circuit with the current sensing resistors and
The proposed converter supports stand-by mode operation by
circuit parameters is shown in Fig. 7(a). Note that a link between
keeping S2 closed. As the bus voltage is always higher than
flyback primary and secondary grounds is inserted to simplify
the rectified line voltage , the input current ceases to flow
the sharing of common ground for control circuits. It has the
into the circuit. This standby mode is becoming a standard for
same results if an optocoupler is installed at output for isolated
the electronic system which is connected to this power con-
voltage feedback and without this link, as shown in Fig. 6(b). (A
verter. Power is saved by disconnecting the line voltage source
shunt regulator together with an optocoupler serves as an error
from the power converter and using solely the bus voltage to
amplifier. The optocoupler transmits the inverted error signal to
supply voltage to controller and maintain output regulated. This
the light-coupled transistor which controls the current source.
feature is hardly achieved in all S PFC converters.
The small current source at PWM is usually present in commer-
cial PWM IC chip.) An input filter capacitor of 0.15 F is added
VI. DESIGN EXAMPLE AND EXPERIMENTAL VERIFICATION to smooth out input current.
A S PFC converter using the proposed topology has been
built for verification. The converter has 24-V/100-W output with A. Power Semiconductors Selection
100–240 V ac input voltage range. The operation switching fre- The power semiconductor devices of the converter are se-
quency is at 50 kHz. Peak current mode is implemented both for lected by the criteria as follows. For and , the maximum
LU et al.: SINGLE-STAGE AC/DC CONVERTER WITH HIGH POWER FACTOR 225
voltage across the devices is when S1 and S2 are turned on C. Implementation of Control Circuit
during period and is equal to . In our example, The control circuit for the hardware prototype is shown in
V. For S1 and S2, the maximum voltage across the Fig. 7(b). A precision timer U1 is used to generate the clock
devices is when or is turned on and is clamped to as signals for the two flip-flops. Two operation amplifiers, U10 and
well. U11, are used to generate the error signals for peak current com-
parison of dc/dc and PFC stages, respectively. The signals from
B. Magnetics Selection
comparators U5A and U5B are used to control the off time of
In order to have transformer T1 operating without possible switches S2 and S1, respectively.
saturation, the following inequality from (5) needs to be satis- The stand-by mode is implemented by simply adding two
fied: comparators and a few logic gates to the control circuit. U6A
and U5B are used to monitor the output current and bus voltage,
(15) respectively. Once the output current is lower than the preset
Otherwise, T1 cannot be reset and will enter saturation. The threshold and bus voltage is lower than 350 V, the converter en-
maximum value of at maximum line input voltage is 338 ters standby mode. The gate signal of S1 is overrode by gate
V. Hence, the turns ratio is calculated as follows: signal of S2. Since and period is omitted,
input current ceases to flow. If either one of the conditions is
not fulfilled, the stand-by mode will be disabled. Notice that at
the present circuit we have used a 50-Hz transformer to get the
is taken. IC power, but we may also get power from the bus capacitor
To ensure works in DCM throughout the line and load through a linear regulator or a coupled winding from the main
ranges, the inequality must be satisfied. Here, we take transformer T1.
an approximation approach to obtain the inductance value of D. Experimental Results
and can be verified quickly through simulation or hardware
implementation. By inspecting inductor current in Fig. 4 and At low line input voltage the input current is the highest,
equivalent circuit in Fig. 3(e), we have is V. We have from (19). Putting
, , s, and V into (20),
(16) we work out that H.
Fig. 8 shows the critical switching waveforms of the con-
To ensure works in DCM, the following inequality must be verter. We can observe from Fig. 8(a) that when the inductor cur-
fulfilled: rent rises, the transformer primary current (same as the switch
current from to ) stays flat. It confirms the discussion in
(17) Section II. We can notice from Fig. 8(b) that represented by
is relatively constant apart from the noise spikes caused by
Besides, duty cycle can be approximated as
the switching at point B in Fig. 6(a).
(18) The input voltage and filtered input current of the converter
at 110, 180, and 240 V line voltages and at full load condition
Substitution of (17) and (18) into (16), one gets is shown in Figs. 9–11, respectively. These figures show close
agreement with the theoretical line current waveforms of DCM
(19) PFC operation in Fig. 5, except for the slightly reverse current
near the zero crossings of lower line voltages such as Figs. 9
and 10. The discrepency can be explained by Fig. 8(b). We can
In (19), the peak of input voltage is used because the dis-
observe that there appears negative inductor current near the
charging period of (i.e., ) is longest at this point. As
zero crossing of the line input voltage. This is because when
is roughly a constant and is obtained from the following
both S1 and S2 are turned on, will momentarily charge up
input–output integral of PFC part with assumption of lossless
the input filter capacitor, which is located in between the bridge
condition
rectifier and inductor, as shown in Fig. 7(a), and is for EMI re-
duction purposes. The inductor current then experiences a short
duration of reverse polarity. As shown in Fig. 12, power factor
is greater than 0.93 for entire input range and above 20% of
load. Fig. 13 shows that the converter attains low current har-
monics which complies with both Class A and D limits of IEC
61000-3-2, though the input current is not purely sinusoidal.
As the experimental input current is obtained with a nonideal
(20) sinusoidal voltage, the input current may be further distorted
when pure sinusoidal voltage is applied. However, as the present
As and are embedded in (20), solving (20) is an iterative input current harmonics, as shown in Fig. 13, are much below
process. Using (19), the limit of is obtained. Select within the limit, there is room for further adjustment as discussed in
the limit and one may work out from (20). Section III-A.
226 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008
Fig. 10. Waveforms for input voltage v and filtered input current I for input
voltage 180 V (rms) and line frequency 50 Hz. Scale: 100 V/Div; 0.5 A/Div.
Fig. 12. Power factor for entire line and load ranges.
Fig. 13. Input current harmonics for input voltage 240 V (rms) and full load Fig. 16. Conversion efficiency of the experimental circuit for entire line and
4 A. load ranges.
Fig. 14. Transient response between 40% and 100% of load. Upper: output are switching alternately. There is no current path for the boost
currentI (4 A/Div); lower: output voltage V
(0.5 V/Div). PFC part. For bus voltage regulation, S1 and S2 are switched
on simultaneously while S3 is turned off. When S1 and S2
are turned on, input current flows into the PFC front-end. This
period corresponds to shaping the input current to achieve
power factor correction. Meanwhile, due to the off-state of S3,
the net voltage across the transformer is zero. Therefore, we
have different time slots for corresponding independent control.
An additional advantage of this configuration is that at boost
operation mode (S3 off), S2 can turn on slightly earlier than
S1 and turn off slightly later than S1 to achieve soft-switching.
This especially favors CCM operation of boost section.
VIII. DISCUSSION
For the proposed converter, the boost inductor operates in
DCM. This operation requires a larger input filter; however, this
operation does save the power loss of reverse-recovery related
Fig. 15. Standby mode operation showing input current cutoff for power saving
feature. Input current resumes when V < 350 V. Upper: input voltage v loss of the output rectifier in this case, as compared to CCM
(100 V/Div); lower: input currentI (25 mA/Div). operation. This saving can reach up to 1%–2% of total effi-
ciency. Usually the input filter contributes to 2%–3% of total
efficiency. In this case, optimization of input filter in terms of
VII. TOPOLOGICAL EXTENSION core and copper losses can be employed to minimize the size of
The proposed single-stage construction concept can be input filter due to DCM operation. Operation of CCM PFC will
extended to derive other converter topologies such as forward, be investigated in future work.
half-bridge, full-bridge and push–pull converters which can From the current stress calculation, the efficiency of the
serve for medium power applications. Fig. 17 shows the inte- proposed converter is potentially better than the conventional
gration of boost PFC circuit with half-bridge converter. In order single-stage converter. Due to the current circulation period
to have independent control of bus voltage (PFC at the same , diode and switch S1 have addition conduction
time) and output voltage, S1 to S3 are programmed at different losses. As compared to two-stage design, the proposed con-
switching patterns. For output voltage regulation, S1 and S2 are verter may suffer more loss. However, the saving of one power
switched as normal half-bridge operation, i.e., S1 and S2/S3 switch and combining boost output rectifier and two-switch
228 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008
flyback free wheeling diode into one (i.e., ) justify the value [13] J. L. Lin, W. K. Yao, and S. P. Yang, “Analysis and design for a novel
of the proposed converter. The detailed comparison of effi- single-stage high power factor correction diagonal half-bridge forward
ac-dc converter,” IEEE Trans. Power Electron., vol. 53, no. 10, pp.
ciency between proposed converter, single-stage and two-stage 2274–2286, Oct. 2006.
converters will be discussed in a further paper. [14] H. Wei, I. Batarseh, G. Zhu, and P. Kornetzky, “A single-switch ac-dc
converter with power factor correction,” IEEE Trans. Power Electron.,
vol. 15, no. 3, pp. 421–430, May 2000.
IX. CONCLUSION [15] J. Y. Lee and M. J. Youn, “A single-stage power-factor-correction
converter with simple link voltage suppressing circuit (LVSC),” IEEE
This paper presents with verifications of experimental results Trans. Ind. Electron., vol. 48, no. 3, pp. 572–584, Jun. 2001.
[16] D. D. C. Lu, D. K. W. Cheng, and Y. S. Lee, “Single-stage ac–dc
the single stage PFC S PFC converter concept—PFC, regu- power-factor-corrected voltage regulator with reduced intermediate
lation of bus and output voltages at the same time. The key bus voltage stress,” Inst. Electron. Eng. Proc.-Electron. Power Appl.,
idea is to construct the power circuit so that current from two vol. 150, no. 5, pp. 506–514, Sep. 2003.
[17] C. F. Jin, Y. Ishihara, T. Totaka, T. Ninomiya, and S. Nakagawa, “High
input sources (ac main and bus capacitor) can be separately con- efficiency single stage ac-dc converter by hybrid parallel structure,” in
trolled. Therefore, though the two power stages share the same Proc. IEEE Power Electron. Specialists Conf., 2006, pp. 1–4.
[18] S. Luo, W. Qiu, W. Wu, and I. Batarseh, “Flyboost power factor cor-
power switches, only one of the two currents passes the switches rection cell and a new family of single-stage ac/dc converters,” IEEE
at a time within each switching period. Current stress on power Trans. Power Electron., vol. 20, no. 1, pp. 25–34, Jan. 2005.
switches is also reduced as a result. Moreover, by deliberately [19] Q. Zhao and F. C. Lee, “Single-switch parallel power factor correction
ac/dc converters with inherent load current feedback,” in Proc. IEEE
restricting the current from ac main, the converter can work at Appl. Power Electron. Conf., 2002, pp. 270–276.
standby mode with energy saving, which can hardly be imple- [20] P. L. Wong and F. C. Lee, “A novel concept in integrating PFC and
mented in existing S PFC converters. dc/dc converters,” in Proc. CPES Annu. Seminar, 2000, pp. 274–281.