218 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO.

1, JANUARY 2008

A Single-Stage AC/DC Converter With High Power

Factor, Regulated Bus Voltage, and Output Voltage
Dylan Dah-Chuan Lu, Member, IEEE, Herbert Ho-Ching Iu, Senior Member, IEEE, and Velibor Pjevalica

Abstract—Unlike existing single-stage ac/dc converters with un-

controlled intermediate bus voltage, a new single-stage ac/dc con-
verter achieving power factor correction (PFC), intermediate bus
voltage output regulation, and output voltage regulation is pro-
posed. The converter is formed by integrating a boost PFC con-
verter with a two-switch clamped flyback converter into a single
power stage circuit. The current stress of the main power switch is
reduced due to separated conduction period of the two source cur-
rents flowing through the power switch. A dual-loop current mode
controller is proposed to achieve PFC, and ensure independent bus
voltage and output voltage regulations. Experimental results on a
24-V/100-W hardware prototype are given to confirm the theoret-
ical analysis and performance of the proposed converter.
Fig. 1. Previous S PFC converter based on boost and two-transistor clamped
Index Terms—ac/dc converter, power factor correction, single- flyback converters [1]–[5].
stage.

I. INTRODUCTION in clamping the switch stresses to the input voltage as well as

S ERIES connection of a power factor correction (PFC) cir-
cuit such as boost converter with an isolated dc/dc converter
such as flyback and forward converters is a common practice to
implement both power factor correction and fast output regula-
tion of offline power supplies. In order to reduce the circuit and
control system complexity and to lower the total cost that suit-
able for low power applications, single-stage power-factor-cor-
rected S PFC ac/dc converters have been introduced [1]–[6].
The two power stages of the PFC circuit and the dc/dc con-
verter are simplified by sharing a common switch (or a pair
of switches). By allowing the boost inductor to operate in dis-
continuous conduction mode (DCM), PFC, and fast output reg-
ulation can be performed simultaneously using a single-loop
voltage feedback controller.
Among existing S PFC converters, the single-switch type
S PFC converter is found low cost and compact. However,
the voltage spike caused by the leakage energy of transformer
has to be dealt with to protect the switch from exceeding the
maximum tolerable voltage and to reduce switching loss. To
overcome this problem, various passive and active snubber cir-
cuits are proposed to suppress the voltage stress on the switch
and to dissipate or recycle the leakage energy the snubbers
stored. Two-transistor clamped isolated converters are useful
Manuscript received October 26, 2006; revised April 25, 2007. Recom-
mended for publication by Associate Editor S. Choi.
D. D.-C. Lu is with the School of Electrical and Information Engineering,
The University of Sydney, Sydney NSW 2006, Australia (e-mail: dylan.lu@ee.
usyd.edu.au).
H. H.-C. Iu is with the School of Electrical, Electronic and Computer Engi-
neering, The University of Western Australia, Perth WA 6000, Perth, Australia.
V. Pjevalica is with JP “Srbijagas,” 21000 Novi Sad, Serbia.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2007.911787
0885-8993/$25.00 © 2007 IEEE
recycling the leakage energy back to the source. Fig. 1 shows
a S PFC converter which integrated a boost converter into a
two-transistor clamped flyback converter and shared the same
switch S1 based on S PFC concept in [1]–[6]. S1 and S2 are
synchronized in action so that when they are turned on, the
inductors and are both charged up linearly by input
voltage and storage capacitor , respectively. When the
switches turn off, the energy stored in and are trans-
ferred to the storage capacitor and the load, respectively. The
leakage energy is transferred back to the storage capacitor, and
the switches are clamped to the intermediate bus voltage .
Owing to the input–output voltage characteristic of the boost
converter, the intermediate bus voltage is always higher than the
peak input voltage. For universal line input applications (i.e.,
90–264 V ) this voltage usually exceeds 450 V at high line
input condition, resulting in high-voltage stress on semicon-
ductor devices such as power transistors and diodes. It has been
shown that the intermediate bus voltage of the S PFC converter
where the dc/dc stage working in continuous conduction mode
(CCM) is inversely proportional to the load current [7]. This
voltage may even rise up higher (e.g., 1000 V) at high line light
load condition. It is more expensive for higher voltage rating
capacitor.
To suppress the voltage stress across the storage capacitor,
various approaches are introduced to reduce the energy feeding
the storage capacitor [8]–[20]. Variable switching frequency
(VSF) [8], [9] limits the input power pumped to the storage
capacitor by increasing the switching frequency at decreasing
load. However, large load variation results in wide variation
range in switching frequency. Even with ten times of switching
frequency range, the storage capacitor voltage is hardly sup-
pressed to below 450 V. The optimization of filtering is yet
another issue when using VSF to cope with the high-voltage
LU et al.: SINGLE-STAGE AC/DC CONVERTER WITH HIGH POWER FACTOR
stress problem. Bulk capacitor voltage feedback [10] can ef-
fectively reduce the voltage stress by curtailing the charging
current in the boost inductor when the load is decreasing.
However, a dead angle of input current occurs when the line
input voltage is lower than the feedback voltage, resulting in
poor power factor. By adding a parallel PFC converter with
the diode-capacitor filter, the bus voltage is clamped at the
peak input voltage and input current can design to comply with
IEC 61000-3-2 requirement [11]. However, the bus voltage
still varies with the input voltage. Therefore, the capacitance
has to be large enough for low-line operation. Operating both
stages in DCM may reduce the voltage stress but it may not
favor high output current/power applications [12], [13]. Direct
power transfer is introduced [15]–[18] to place an auxiliary
coupled winding in series with the charging path of boost
inductor, “stealing” energy to output directly after the first
power process. The voltage stress is reduced rapidly while
maintaining high power factor. Conversion efficiency is also
improved, but the bus voltage in all of these methods still varies
largely when input line voltage varies.
Another problem in S PFC converter is the extra current
stress on the switch (or a pair of switches) when compared
with the two-stage approach because it has to handle all the
input currents from the line input voltage and the bus voltage
simultaneously (e.g., switch S1 in Fig. 1). Conduction and
switching losses are therefore increased which deteriorate the
conversion efficiency. Besides reduction of voltage stress on
storage capacitor, the bulk capacitor voltage feedback is found
useful in reducing the switch current stress, but the reduction
of current stress also causes an increase in input current har-
monics. Recently, load current feedback technique is introduced
[19] in which the load information is brought forward to the
input stage, controlling the input current directly. And at any
time the switch handles current from one voltage source, either
the line input voltage or the storage capacitor. However, the
high input current harmonics problem still exists. The authors
in [5] and [20] attempted to control the bus voltage and output
voltage in S PFC converters but due to the integrated structure,
the currents from both input sources (ac mains and storage
capacitor) cannot be separated. Hence, the current stress issue
remains. Moreover, since the duty cycle varies largely for
universal input applications, an extra range switch is needed.
In this paper, a new S PFC converter derived from novel in-
tegration of boost converter and two-transistor clamped isolated
converter is proposed. In summary, the proposed converter has
the following advantages.
• The proposed S PFC converter gives simultaneous PFC,
bus voltage regulation, and fast output regulation, which
are not possible in existing S PFC converters.
• No additional switches, such as range switch, are needed
to implement universal input range applications.
• The current stress of the two power switches is lower than
that of the single-switch (or multiple-switch) S PFC con-
verter circuits.
• High power factor, as there is no deadband of input current
around the zero crossing of the line input voltage.
• Stand-by mode is possible that saves power and reduces
loss.
219
Fig. 2. Proposed S PFC converter based on new integration of boost and two-
transistor clamped flyback converters.
The principle of operation of the new boost-flyback S PFC
converter is described in Section II, whereas the controller de-
sign is depicted in Section III. Discussion on current stress and
stand-by mode operation are presented in Sections IV and V,
respectively. Experimental results obtained on a hardware pro-
totype is given in Section VI. Extension of the proposed concept
to various converter topologies is discussed in Secion VII, fol-
lowed by the conclusion in Section VIII.
II. PRINCIPLE OF OPERATION
A. Circuit Desciption
The proposed boost-flyback S PFC converter is shown in
Fig. 2. It consists of an input inductor , a two-transistor (S1 and
S2) clamped flyback converter with transformer T1 and a storage
capacitor . Inductor is used to shape the input current for
PFC function and to feed . Transformer T1 with turns ratio
is used to store energy from and couple the energy stored in
the magnetizing inductance to output load at transistor turn-
off period. Storage capacitor serves as a storage element for
absorption of power imbalance between input and output powers
as well as maintains output voltage constant. Diodes and
are used to recycle the leakage energy in T1 back to and to
clamp the drain-to-source voltages of S2 and S1 to bus voltage
simultaneously. is a bypass diode for charging of to
provide necessary housekeeping power at startup. Once rises
and becomes higher than input voltage, is reverse biased.
B. Circuit Operation
To simplify the analysis of operation, it is assumed that all
semiconductor devices are ideal. The capacitances of and
are so large that the ripple voltage on them are negligible;
and are constant dc voltage sources. The rectified input
voltage is essentially constant within each switching cycle
as the switching frequency is much higher than the
line frequency. Finally, the boost inductor works in DCM,
whereas the primary inductance of flyback transformer op-
erates in CCM.
To illustrate the principle of operation of the proposed boost-
flyback S PFC converter, Fig. 3 shows operation stages of the
circuit in Fig. 2 during a switching cycle, whereas Fig. 4 shows
the key theoretical waveforms within two switching cycles. In
the steady state, there are four modes of operation. Note that
the input voltage and bridge rectifier have been modeled as a
220 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008

Fig. 3. Four operation stages of the proposed S PFC converter during one switching period. (a) Mode 1 (T 0 T ). (b) Mode 2 (T 0 T ). (c) Mode 3 (T 0 T ).
(d) Mode 4 (T 0 0
T ). (d) Mode (T T ). (e) equivalent circuit at T T . 0

voltage source in series with a diode . Before the time A blocking voltage equal to is applied across
, switches S1 and S2 are turned off and no current is flowing in output diode , and is reversed biased. The output
the primary side (i.e., ). Meanwhile, voltage is sustained by . Note that only one voltage
diode is in conduction state and transformer T1 continues source (i.e., ) provides the current of two switches, which
delivering energy to output through current . equals .
Mode 1 : Both the switches S1 and S2 are closed. Mode 2 : Mode 2 is initiated by turning off S2 while
As the intermediate bus voltage is higher than the rectified S1 remains in on-state. The parallel capacitance of S2 is charged
input voltage at all times, the bridge diodes are reverse up so that the drain-to-source voltage of S2, , rises towards
biased. Therefore, inductor is not charging and is zero. until it is clamped by , as shown in Fig. 3(b). During this
Capacitor is discharged through , as shown period, the energy stored in T1 cannot be coupled to output as
in the equivalent circuit in Fig. 3(a). Energy is being stored in S1 is still closed. Because cannot sustain a sudden change of
the flyback transformer T1, and the current increases linearly current direction, is turned on to maintain the current flow
with a slope in T1. The voltage applied across primary winding of T1 is thus
zero (assume has zero forward voltage drop). Namely, T1 is
(1) free-wheeling within this interval and the rate of change of
LU et al.: SINGLE-STAGE AC/DC CONVERTER WITH HIGH POWER FACTOR 221

forward biased. is clamped at , and is reduced to

. Once again, inductor current cannot sustain a sudden
change of current direction, provides the path to maintain
the current of . The stored energy in is being transferred
to through and with a downslope equals

(5)

As point X reaches , a blocking voltage is set up on

and is reverse biased. As the dotted ends of T1 is positive
with respect to the non-dotted ends and voltage across primary
side rises and becomes slightly over , is forward biased,
and the energy stored in T1 is transferred to the load. con-
ducts with a rate of change of current equals

(6)

Mode 4 : This mode is started when has de-

creased to zero. Note that Mode 4 must exist, otherwise the
transfer of energy stored in to has not yet completed
and will enter CCM. A sudden rise in would occur that
causes high input current harmonics distortion. Transformer T1
continues to deliver the rest of energy to output through , as
shown in Fig. 3(d). The rate of change of current in is neg-
ative and equals

(7)
Fig. 4. Key switching waveforms of the proposed S PFC converter during two
successful switching period. After some time, S1 and S2 turns on again to begin the next
switching cycle, the operation described above will repeat.
is zero. Meanwhile, the rectified input voltage is applied on III. CONTROL
and is charged up linearly with a slope
The main objective of the control system is to find a simple
(2) and effective way to control the two switches S1 and S2 so that
PFC is achieved, the bus voltage and the output voltage
are regulated as line and load vary.
By the KCL, the current into node X (as shown in Fig. 2) equals
the current out of the node, we have the following relationship: A. PFC
(3) Given that the input voltage is a rectified sinusoidal wave, i.e.,
, where and are the angular frequency
Therefore, the current in is not a constant but is decreasing and the peak value of line input voltage. Assume the inductor
with the expression given by works in DCM, the instantaneous input current is obtained by
averaging the inductor current over a switching period, which is
(4) given by

where is the peak of at time equals . It should be (8)

noted that the current of power switch S1 during this mode
equals and is clamped at , without increasing current where
stress even is charging up. In some cases, the inductor cur-
rent may exceed the , diode stops conducting. , and (9)
are in series and charging up together. As , the
charging rate is small and so is the current stress on the switch, As long as works in DCM throughout the line cycle,
as shown in Fig. 4. flows into the converter for every switching period (i.e., in
Mode 3 : Mode 3 is begun when S1 is also Mode 2) and duty cycle keeps relatively constant, PFC is
turned off. The parallel capacitance of S1 is charged by . achieved automatically because functions as a boost in-
The drain-to-source voltage of S1, , rises towards , as ductor. At Mode 2, when S2 is turned off and S1 remains on, the
shown in Fig. 3(c). When rises slight above , is input current flows into the converter and charges linearly.
222
Fig. 5. Comparison of input current at different line input voltages.
As seen from (2), as soon as input voltage increases from
zero, there is always input current flowing through .
In order to obtain good power factor of the proposed con-
verter, all the parameters in (8) should be kept relatively con-
stant, except for the sine term which changes according to input
line voltage. The bus voltage contains twice the line fre-
quency voltage ripple because it serves as a buffer to balance the
difference of input and output powers. The control loop of PFC
should have a cutoff frequency far behind the line frequency
to avoid input current distortion, and therefore its response is
slower than that of the dc/dc counterpart. This implies duty cycle
is relatively constant throughout the line half period.
The converter operates in fixed frequency, the nonlinear factor
would be the function which will cause input current
distortion. From (9), it shows that the higher the bus voltage
and the smaller turns ratio and the output voltage ,
the smaller will be. Fig. 5 shows the input current and
duty cycle at different line input voltages over a half line
period. The plot is generated using H,
kHz, V, V, and W.
The input current is less distorted at low line than that of at
high line as the effect of nonlinearity of (9) is smaller. However,
such input current distortion still allows the converter to pass the
international standards such as IEC 61000-3-2, as will be proved
by the experimental results in Section VI.
B. Bus Voltage Regulation
At startup, the bus voltage is essentially zero, though a
residual charge may exist. When input voltage applies across
the converter input terminals, the storage capacitor is
charged up via . The presence of also prevents the
inductor from saturation at startup. The bus voltage rises to the
peak value of input voltage. The converter begins to deliver
energy to through , and rises gradually to the de-
signed reference value. The bus voltage is sensed and regulated
by controlling the duration of energy stored in during
Mode 2. At Mode 3, energy stored in will be delivered to
. Therefore, Modes 2 and 3 are dedicated for PFC and bus
voltage regulation.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008
C. Output Voltage Regulation
The bus voltage is used to provide regulation of output voltage
. This happens during Mode 1, when both switches S1 and S2
are turned on. At mean to full load, transformer T1 is working
in CCM. Even if there exists large load current variation, the
change of duty cycle in this mode is slight. It is due to the nega-
tive current feedback that the transformer regulates its primary
current according to the demand of secondary current. As seen
from (7), the rate of change of output diode current is propor-
tional to the output voltage . For example, if a decrease of
load (or a increase of load resistance ) occurs, the instanta-
neous output current is constant and causes to increase. This
steepens the downslope of output diode current. The primary
transformer current will be decreased so less current is drawn
from . When the load becomes light, T1 may work in DCM.
The duty cycle can vary freely in this mode to keep output con-
stant as there is no other current path. Therefore, Mode 1 is ded-
icated for output voltage regulation.
D. Current Mode Control
Even though voltage mode control is the simplest way to
achieve control purposes, current mode control monitors circuit
currents to provide fast response and protection from abnormal
operations such as over-current. Peak current mode control can be
achieved easily on the dc/dc part by sensing the current of switch
S1 directly through a resistor which is placed in series with
S1, as shown in Fig. 2. The PFC part is implemented also using
peak current mode control. One of the direct methods to sense the
inductor (or input) current is by placing a resistor in the return
path, as shown in Fig. 2. Although the PFC operates with constant
duty cycle and peak current limit, the average inductor current
indeed changes proportionally with input voltage to shape input
current, as seen from (5). For example, when increases, the
rate of change of decreases and the discharge period
extends. As input voltage is in series with the current path, more
current flows into the converter and increase as a result.
The controls on and on are independent due to the
circuit configuration that allows independent power processing
,
stages and independent currents paths for monitoring and reg-
ulating of and . It can be seen from Fig. 4 that during
Mode 1, only flyback dc/dc part is working. No current from
line input flows into the circuit. The current through equals
the bus capacitor discharging current. During Mode 2, flyback
transformer current is constant while boost inductor current
builds up. The current through is only.
E. Control Realization
Fig. 6(a) shows the simplified schematic of the proposed dual-
loop current mode control for the proposed converter. Both loops
are triggered by the same clock to have synchronized ON pulse.
When a clock pulse is generated, both S1 and S2 go to high state.
At startup, is charged up and able to couple energy to output
through T1. The first loop [upper circuit in Fig. 6(a)] is used for
output voltage regulation. The output voltage is sensed by the
inverting input of the error amplifier E/A 1 with compensation
network, and an error control voltage is generated. is
compared to the switch current of S1 by comparator PWM 1 to
produce desired off duty cycle for S2 through the D-type flip-flop
(FF1). The second loop [lower circuit in Fig. 6(a)] is used for PFC
LU et al.: SINGLE-STAGE AC/DC CONVERTER WITH HIGH POWER FACTOR
Fig. 6. Configuration of adopted dual-loop current mode PWM control in sim-
plified version.
and bus voltage regulation. The bus voltage is detected by the
inverting input of the error amplifier E/A 2 with compensation
network, and an error control voltage is generated. is
summed with the inductor current and compared to ground
by comparator PWM 2 to produce desired off-duty cycle for
S1 through the D-type flip-flop (FF2). S1 will not go to low
state until PWM1 commands S2 to turn off and current is then
flowing through (in Fig. 2) to pull point B negative when
peak inductor current is reached.
In the design of the controller, on one hand, the compensa-
tion network by E/A2 is of slow response, which has around
10–20 Hz of cutoff frequency, to avoid the 100-Hz ac ripple
from bus capacitor being amplified and cause input current dis-
tortion eventually. On the other hand, E/A1 is of fast response
to provide tight output regulation.
IV. CURRENT STRESS ON POWER SWITCHES
For conventional S PFC converter such as in Fig. 1, when
both switches S1 and S2 are closed, currents from line input
and storage capacitor inject into S1 simultaneously.
223
Suppose the on-state resistance of S1 is expressed as ,
the conduction loss of the switch S1 is given by
(10)
where and are the boost inductor current and storage ca-
pacitor discharging current through T1, respectively. From (10),
apart from the individual conduction loss there is an extra loss
term . This explains why conventional S PFC
converters have higher power dissipation and lower total effi-
ciency than that of conventional two-stage PFC voltage regu-
lator when allowing two individual currents to flow through the
same switch simultaneously.
Reduction of switch current stress of the proposed converter is
achieved by separating the current injecting into S1 from the two
voltage sources (bus voltage and rectified input voltage ).
Since is always higher than , when S1 and S2 are turned
on only current from is flowing through the switches because
the bridge rectifier is reverse biased. When S2 is turned off but
S1 is kept on, the current from ceases so that input current
can flow through S1. By inspecting the waveforms in Fig. 4, the
switch current of S1 is equal to from to . And during pe-
riod to , the switch current is clamped to the peak current of
due to . Therefore, the conduction loss on S1 is reduced to
(11)
Due to the circuit operation, a conduction loss on equals
(12)
is observed at Mode 2, where is the voltage drop on . By
putting a couple of diodes in parallel, the loss may be minimized
due to sharing of current. The lower the current in each diode
the lower the forward voltage drop. The current stress in S2 for
both S PFC converter in Fig. 1 and proposed one is the same as
the two-transistor clamped flyback converter.
To compare the rms current of S1 of proposed converter
with that of Fig. 1 fairly, the circuits parameters mentioned in
Section III-A are used for both converters. Unlike the proposed
converter, inductor and primary magnetizing currents in Fig. 1
conduct simultaneously and are confined by the same duty cycle
( in this case). Besides, to achieve the same output power at
100-V input, inductor is reduced to 26.5 H. The average
values of S1 rms current over a half line period of proposed and
conventional ones are, respectively, given by (13) and (14) at
bottom of the page. In this example, the proposed converter re-
duces the rms current of S1 by 3.3 times of the conventional one.
(13)
(14)
224
Fig. 7. Experimental circuit showing practical devices values and placement of current sensing resistors.
V. STAND-BY MODE OPERATION
The proposed converter supports stand-by mode operation by
keeping S2 closed. As the bus voltage is always higher than
the rectified line voltage , the input current ceases to flow
into the circuit. This standby mode is becoming a standard for
the electronic system which is connected to this power con-
verter. Power is saved by disconnecting the line voltage source
from the power converter and using solely the bus voltage to
supply voltage to controller and maintain output regulated. This
feature is hardly achieved in all S PFC converters.
VI. DESIGN EXAMPLE AND EXPERIMENTAL VERIFICATION
A S PFC converter using the proposed topology has been
built for verification. The converter has 24-V/100-W output with
100–240 V ac input voltage range. The operation switching fre-
quency is at 50 kHz. Peak current mode is implemented both for
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008
boost and flyback parts as discussed in Section III. The experi-
mental power stage circuit with the current sensing resistors and
circuit parameters is shown in Fig. 7(a). Note that a link between
flyback primary and secondary grounds is inserted to simplify
the sharing of common ground for control circuits. It has the
same results if an optocoupler is installed at output for isolated
voltage feedback and without this link, as shown in Fig. 6(b). (A
shunt regulator together with an optocoupler serves as an error
amplifier. The optocoupler transmits the inverted error signal to
the light-coupled transistor which controls the current source.
The small current source at PWM is usually present in commer-
cial PWM IC chip.) An input filter capacitor of 0.15 F is added
to smooth out input current.
A. Power Semiconductors Selection
The power semiconductor devices of the converter are se-
lected by the criteria as follows. For and , the maximum
LU et al.: SINGLE-STAGE AC/DC CONVERTER WITH HIGH POWER FACTOR 225

voltage across the devices is when S1 and S2 are turned on C. Implementation of Control Circuit
during period and is equal to . In our example, The control circuit for the hardware prototype is shown in
V. For S1 and S2, the maximum voltage across the Fig. 7(b). A precision timer U1 is used to generate the clock
devices is when or is turned on and is clamped to as signals for the two flip-flops. Two operation amplifiers, U10 and
well. U11, are used to generate the error signals for peak current com-
parison of dc/dc and PFC stages, respectively. The signals from
B. Magnetics Selection
comparators U5A and U5B are used to control the off time of
In order to have transformer T1 operating without possible switches S2 and S1, respectively.
saturation, the following inequality from (5) needs to be satis- The stand-by mode is implemented by simply adding two
fied: comparators and a few logic gates to the control circuit. U6A
and U5B are used to monitor the output current and bus voltage,
(15) respectively. Once the output current is lower than the preset
Otherwise, T1 cannot be reset and will enter saturation. The threshold and bus voltage is lower than 350 V, the converter en-
maximum value of at maximum line input voltage is 338 ters standby mode. The gate signal of S1 is overrode by gate
V. Hence, the turns ratio is calculated as follows: signal of S2. Since and period is omitted,
input current ceases to flow. If either one of the conditions is
not fulfilled, the stand-by mode will be disabled. Notice that at
the present circuit we have used a 50-Hz transformer to get the
is taken. IC power, but we may also get power from the bus capacitor
To ensure works in DCM throughout the line and load through a linear regulator or a coupled winding from the main
ranges, the inequality must be satisfied. Here, we take transformer T1.
an approximation approach to obtain the inductance value of D. Experimental Results
and can be verified quickly through simulation or hardware
implementation. By inspecting inductor current in Fig. 4 and At low line input voltage the input current is the highest,
equivalent circuit in Fig. 3(e), we have is V. We have from (19). Putting
, , s, and V into (20),
(16) we work out that H.
Fig. 8 shows the critical switching waveforms of the con-
To ensure works in DCM, the following inequality must be verter. We can observe from Fig. 8(a) that when the inductor cur-
fulfilled: rent rises, the transformer primary current (same as the switch
current from to ) stays flat. It confirms the discussion in
(17) Section II. We can notice from Fig. 8(b) that represented by
is relatively constant apart from the noise spikes caused by
Besides, duty cycle can be approximated as
the switching at point B in Fig. 6(a).
(18) The input voltage and filtered input current of the converter
at 110, 180, and 240 V line voltages and at full load condition
Substitution of (17) and (18) into (16), one gets is shown in Figs. 9–11, respectively. These figures show close
agreement with the theoretical line current waveforms of DCM
(19) PFC operation in Fig. 5, except for the slightly reverse current
near the zero crossings of lower line voltages such as Figs. 9
and 10. The discrepency can be explained by Fig. 8(b). We can
In (19), the peak of input voltage is used because the dis-
observe that there appears negative inductor current near the
charging period of (i.e., ) is longest at this point. As
zero crossing of the line input voltage. This is because when
is roughly a constant and is obtained from the following
both S1 and S2 are turned on, will momentarily charge up
input–output integral of PFC part with assumption of lossless
the input filter capacitor, which is located in between the bridge
condition
rectifier and inductor, as shown in Fig. 7(a), and is for EMI re-
duction purposes. The inductor current then experiences a short
duration of reverse polarity. As shown in Fig. 12, power factor
is greater than 0.93 for entire input range and above 20% of
load. Fig. 13 shows that the converter attains low current har-
monics which complies with both Class A and D limits of IEC
61000-3-2, though the input current is not purely sinusoidal.
As the experimental input current is obtained with a nonideal
(20) sinusoidal voltage, the input current may be further distorted
when pure sinusoidal voltage is applied. However, as the present
As and are embedded in (20), solving (20) is an iterative input current harmonics, as shown in Fig. 13, are much below
process. Using (19), the limit of is obtained. Select within the limit, there is room for further adjustment as discussed in
the limit and one may work out from (20). Section III-A.
226
Fig. 8. Switching waveforms (a) switch S1 drain-to-source current (upper
trace) and inductor current i (lower trace). Scale: 2 A/Div; 2 A/Div. (b) Error
signal from E/A2, v , in Fig. 6(a) (upper trace) and inductor current i
(lower trace).
Fig. 9. Waveforms for input voltage v and filtered input current I for input
voltage 110 V (rms) and line frequency 50 Hz. Scale: 50 V/Div; 2 A/Div.
The bus voltage is tightly regulated at 400 V throughout entire
line and load conditions due to the integrated but independent
converter structure and control, which make the simultaneous
control of bus and output voltages possible.
Apart from steady-state performance, the transient response
of the converter is tested under step change of load between
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008
Fig. 10. Waveforms for input voltage v and filtered input current I for input
voltage 180 V (rms) and line frequency 50 Hz. Scale: 100 V/Div; 0.5 A/Div.
Fig. 11. Waveforms for input voltage v and filtered input current I for input
voltage 240 V (rms) and line frequency 50 Hz. Scale: 100 V/Div; 0.25 A/Div.
Fig. 12. Power factor for entire line and load ranges.
40% to 100%, as shown in Fig. 14. The output voltage set-
tles after 2.5 ms with less than 1 V of overshoot/undershoot.
Fig. 15 shows the stand-by mode operation. Bus capacitor
sustains the output voltage while input current is zero. When
V, input current flows again to charge up for
a short duration. Fig. 16 shows that the conversion efficiency
reaches 80% or above at full load for entire line voltage range.
A comparison is made between the proposed converter with
the conventional two-stage boost and flyback in previous paper
[16], showing an improvement in efficiency (the dotted line
shows the predicted values).
LU et al.: SINGLE-STAGE AC/DC CONVERTER WITH HIGH POWER FACTOR
Fig. 13. Input current harmonics for input voltage 240 V (rms) and full load
4 A.
Fig. 14. Transient response between 40% and 100% of load. Upper: output
currentI (4 A/Div); lower: output voltage V
(0.5 V/Div).
Fig. 15. Standby mode operation showing input current cutoff for power saving
feature. Input current resumes when V < 350 V. Upper: input voltage
(100 V/Div); lower: input currentI (25 mA/Div).
VII. TOPOLOGICAL EXTENSION
The proposed single-stage construction concept can be
extended to derive other converter topologies such as forward,
half-bridge, full-bridge and push–pull converters which can
serve for medium power applications. Fig. 17 shows the inte-
gration of boost PFC circuit with half-bridge converter. In order
to have independent control of bus voltage (PFC at the same
time) and output voltage, S1 to S3 are programmed at different
switching patterns. For output voltage regulation, S1 and S2 are
switched as normal half-bridge operation, i.e., S1 and S2/S3
227
Fig. 16. Conversion efficiency of the experimental circuit for entire line and
load ranges.
Fig. 17. Extension of proposed concept to combining boost and half-bridge
converters.
are switching alternately. There is no current path for the boost
PFC part. For bus voltage regulation, S1 and S2 are switched
on simultaneously while S3 is turned off. When S1 and S2
are turned on, input current flows into the PFC front-end. This
period corresponds to shaping the input current to achieve
power factor correction. Meanwhile, due to the off-state of S3,
the net voltage across the transformer is zero. Therefore, we
have different time slots for corresponding independent control.
An additional advantage of this configuration is that at boost
operation mode (S3 off), S2 can turn on slightly earlier than
S1 and turn off slightly later than S1 to achieve soft-switching.
This especially favors CCM operation of boost section.
VIII. DISCUSSION
For the proposed converter, the boost inductor operates in
DCM. This operation requires a larger input filter; however, this
operation does save the power loss of reverse-recovery related
v loss of the output rectifier in this case, as compared to CCM
operation. This saving can reach up to 1%–2% of total effi-
ciency. Usually the input filter contributes to 2%–3% of total
efficiency. In this case, optimization of input filter in terms of
core and copper losses can be employed to minimize the size of
input filter due to DCM operation. Operation of CCM PFC will
be investigated in future work.
From the current stress calculation, the efficiency of the
proposed converter is potentially better than the conventional
single-stage converter. Due to the current circulation period
, diode and switch S1 have addition conduction
losses. As compared to two-stage design, the proposed con-
verter may suffer more loss. However, the saving of one power
switch and combining boost output rectifier and two-switch
228
flyback free wheeling diode into one (i.e., ) justify the value
of the proposed converter. The detailed comparison of effi-
ciency between proposed converter, single-stage and two-stage
converters will be discussed in a further paper.
IX. CONCLUSION
This paper presents with verifications of experimental results
the single stage PFC S PFC converter concept—PFC, regu-
lation of bus and output voltages at the same time. The key
idea is to construct the power circuit so that current from two
input sources (ac main and bus capacitor) can be separately con-
trolled. Therefore, though the two power stages share the same
power switches, only one of the two currents passes the switches
at a time within each switching period. Current stress on power
switches is also reduced as a result. Moreover, by deliberately
restricting the current from ac main, the converter can work at
standby mode with energy saving, which can hardly be imple-
mented in existing S PFC converters.
ACKNOWLEDGMENT
The authors would like to thank Prof. B. Nandor for his con-
structive comments on the hardware prototype development of
the converter.
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Dylan Dah-Chuan Lu (S’00–M’04) received the
B.Eng.(hons) and Ph.D. degrees in electronic and
information engineering from Hong Kong Poly-
technic University, Hong Kong, in 1999 and 2004,
respectively.
In 2003, he joined PowereLab Limited, a spin-off
company at the University of Hong Kong, as a
Senior Engineer. His major responsibilities include
project development and management, circuit de-
sign, and contribution of research in the area of
power electronics. Currently, he is a Lecturer in the
School of Electrical and Information Engineering, The University of Sydney,
Sydney, Australia. He has published a number of international conference
and journal papers on the analysis and design of power electronics circuits.
He holds one U.S. patent. His research interests include modeling, synthesis,
and computer-aided design of power converters, dc-dc converter for VRM
applications, electronic ballast, controls, power-factor-correction circuits,
soft-switching techniques, and renewable electrical energy systems.
Herbert Ho-Ching Iu (S’98–M’00–SM’06) re-
ceived the B.Eng. (hons) degree in electrical and
electronic engineering from the University of Hong
Kong, Hong Kong, in 1997 and the Ph.D. degree
from the Hong Kong Polytechnic University, Hong
Kong, in 2000.
In 2002, he joined the School of Electrical,
Electronic and Computer Engineering, University
of Western Australia, Perth, as a Lecturer. In 2007,
he became a Senior Lecturer. His research inter-
ests include power electronics, renewable energy,
nonlinear dynamics, applications of chaos, TCP dynamics, and computational
intelligence. He has published over 60 papers in these areas. He served as a
Visiting Lecturer at the University of Reims Champagne-Ardenne, France,
in 2004 and a Visiting Assistant Professor at the Hong Kong Polytechnic
University, Hong Kong, in 2006. He currently serves as Guest Editor for
Australian Journal of Electrical and Electronics Engineering and Circuits,
Systems and Signal Processing.
Velibor Pjevalica was born in Novi Sad, Serbia, in
1969. He received the M.Phil. degree from the Uni-
versity of Technical Sciences, Novi Sad, in 1999.
He was working with Prof. M. Tse at the Hong
Kong Polytechnic University. He is now with JP
“Srbijagas,” Novi Sad, Serbia. His research inter-
ests include power converters, control, chaos, and
bifurcations.