Analog and Mixed-Signal Center at Texas A&M University

C
S
M
A

Spring 2011

Edgar Sánchez-Sinencio
Office: 318-E WERC
e-mail: sanchez@ece.tamu.edu
When: TR 12:45- 2:00 PM
Where: 223A Zachry

1
 Advanced Analog Circuit Design
Required background:
Techniques
1. How to optimally bias your CMOS circuits
2. How to use MOS transistor models
3. Derive transfer functions from small signal circuits
- Use
U off nodal
d l admittance
d itt matrix
t i
1. Stability Criteria.
- How to determine pole and zeros.?
- Routh Hurtwitz Criteria
- Reduction of a higher-order system into a
2nd-order function
1. How to design:
1. Inverting Amplifiers
2. Current mirrors and current sources
3. Differential ppairs,, and low noise amplifiers
p
4. Simple Transconductor Amplifiers
5. Two Stage Conventional Operational Amplifiers 2
Analog and Mixed Signal Center, TAMU (ESS)
6. Basic common-mode feedback structures for Fully
Differential Operational
p Amplifiers
p

Required background (continues):

• Use CADENCE for

• Noise Analysis
y
• Monte Carlo Analysis
• S/N ratio determination
• Pole and zero determination
• Temperature effects

• Use of SIMULINK for systems analysis,

modeling and characterization

3
Analog and Mixed Signal Center, TAMU (ESS)
 Motivation
The knowledge and applications of analog circuits in
medical electronics, modern mixed-signal VLSI chips for
multimedia, perception, control, instrumentation and
telecommunication are vital .

• What are the challenges in designing low voltage circuits ?

- To pperform with technologies
g smaller than 65 nm
- To operate with power supplies smaller than 1 volt
- To design circuits with the same performance or better
than circuits designed for larger power supplies
-To
T come with
ith new ddesign
i alternatives
lt ti
4
Analog and Mixed Signal Center, TAMU (ESS)
Whyy Low-Voltage
g Analog
g Integrated
g Circuits?
• Modern CMOS feature size is continuing to be
scaled
l d down
d to have
h a high
hi h fT andd large
l component
density. In addition the maximum allowable power
supply
pp y voltage
g continuously y decreases.

• Therefore portable battery-

poweredd equipment
i t also
l
necessitates low-voltage low-
power circuit design.

5
 ( continues)
• Why are we concerned in designing low voltage circuits ?
- Designers could not use conventional cascode structures,
and other conventional design methodologies yielding high
signal
i l swing.
i
- Circuits must have the same performance or better than
circuits designed for larger power supplies
- Circuit performance with technologies smaller than 65 nm
must be better than circuits for larger technologies.
technologies
-Fourth-generation communication applications need circuits
( and systems) with improved dynamic range over a much
wider bandwidth.
- New buildingg blocks and systems
y must be designed
g to
satisfy the needs of portable, lighter, cheaper and faster
equipment 6
• When transistors operate in saturation, how deep in saturation
should they operate ?
Vds >Vgs-Vt ? By how much ? How can one answer this question?

• Can one model transistor with one equation valid for all regions of
operation?

• If LV circuits do not allow cascode circuits, what are the alternatives?

-Floating
Floating Gate
- Bulk Driven
- Nested Gm-C ( cascade plus optimal feedback compensation)
- Self Cascode Transistor
- NP Differential Pairs 7
Analog and Mixed Signal Center, TAMU (ESS)
 Global Microsystems Growth Forecasts*
Telecommunication & Communications Marker 13% (2005-2012)
Semiconductor Market 6% (2008-2013)
Embedded Technology Market 4.1% (2008-2013)
Intelligent Wireless Microsystems 56 4% (2008-2013)
56.4% (2008 2013)
Image Sensors 7.2% (2008-2013)
Biotechnology Market 12.3% (2005-2010)
Medical Devices Market 6.2% (2007-2012)
Biophotonics Chip
C Products 11%% ((2004-2014))
Biochips Market 12.7% (2006-2013)
BioMEMS 17% (2008-2012)
Microfluidics Technology Market 14% (2006-2011)
(2006 2011)
Semiconductors in Industrial/Medical Applications 8.8% (2007-2013)
Lab-on-Chip 36%(2004-2012)
Laser Transmitters 11% (2006-2011)
W ld id MEMS Systems
Worldwide S t 15% (2005
(2005-2010)
2010)
Optical Components 14% (2007-2012)

* From CMC Microsystems Annual Report 2009 (www.cmc.ca) AMSC-TAMU by Edgar Sanchez-Sinencio
8
 Technology Forecast (from http://www.itrs.net/ ITRS Roadmap 2009)
Year of
Production
2009 2011 2013 2015 2017 2019
Supply 1/2.5 0.93/1.8 0.87/1.8 0.81 0.76 0.71
Voltage(V)#
DRAM ½ Pitch 52 40 32 25 20 15.9
(nm) (contacted)
Gate length(nm) 37/250 28/180 22/180
Threshold 0 33
0.33 0 31
0.31 0 29
0.29 0 27
0.27 0 25
0.25 0 23
0.23
Voltage (V)
Gm/gds at 30(220) 30(160) 30(160)
5(10)Lmin
1/f noise 100/500 80/180 70/180
(uv2.um2/Hz)
NFmin(dB) 0.20 <0.2 <0.2
Peak Ft (GHz) 240/40 320/50 400/50
Peak Fmax 370/40 480/50 590/50
((GHz))

# one data is for Performance RF/Analog and the other for Precision Analog/RF Driver 9
Remarks.-

• Power supply reduction helps digital circuits for power

consumption but hurts analog voltage swing which should
not be reduced.
• Inherent transistor voltage gain decreases with reduced
size
i ttechnology,
h l thi
this iimplies
li llarger number
b off stages
t tto
compensate the overall voltage gain.
• Threshold voltages
g do not reduce linearly y with size of
technology, making the design with low VDD harder for
analog circuits

10
AMSC-TAMU by Edgar Sánchez-Sinencio
http://pradeepchakraborty.wordpress.com/category/global-semiconductor-market/page/2/

11
http://www.isuppli.com/Semiconductor-Value-Chain/News/Pages/Semiconductor-Industry-Set-For-Highest-Annual-Growth-
in-10-Years.aspx

12
 Concerns about low power supply voltage
Scaling
S li down
d size
i technology
h l andd
VTH supply voltage does not scale linearly
the “ VTH hat ”

VTH

Mister 3.3 volts IC Mister 0.6 volts IC

• Also VDSAT does not scale down linearly with power supply
nor with smaller size technologies. 13
Remarks on low power supply voltage integrated
circuits
Technology trends show that in every generation:

• Circuit delay is scaling down by 30%

• Supply voltages are also scaling by 30%

• Transistor’s threshold voltage

oltage is reduced
red ced by
b nearly
nearl 15%

• Transistor density and digital performance are double

approximately every two years.

• Higher power dissipation and temperature.

Reference . W. M. Elgharbawy and M. A. Bayoumi, “Leakage Sources and Possible Solutions in Nanometer

CMOS Technologies ” IEEE Circuits and Systems Magazine, pp. 6-15, Fourth Quarter 2005 14
 TRANSISTOR REGIONS OF OPERATION

• How to determine how much bias current is needed for

certain application ?

• When a designer operates transistors in saturation,

what does it mean VDS > VDS(SAT) ?

• Can a circuit have their transistors operating in the

((moderate inversion)) transition region
g ? What transistor
model equation can be employed ?

15
 One Equation-All Regions Transistor Model
• Features of ACM model:
– physics-based model,
– universal
i l andd continuous
i expression
i for
f any inversion
i i level
l l
– independent of technology, temperature, geometry and gate voltage,
– same model for analysis, characterization and design.
• M i design
Main d i equations:i (design
(d i parameters: I,I gm, if)
I 1+ 1+ if I ⎯ transistor drain current
= gm ⎯ transconductance in saturation
φtgmn 2
n ⎯ slope factor
2( 1 + i f − 1)
μφt
fT = φt ⎯ thermal voltage
2πL2
if ⎯ inversion level of the transistor defined as
i f = I I s , where I = μnC φ W is the
W gm 1 2
= t

L μCoxφt 1 + i f − 1
s ox
2 L
normalization current.
VDSAT
φt
≅ ( 1+ i f )
−1 + 4
if << 1 ⎯ weak inversion,
W
=
gm if >> 1 ⎯ strong inversion
inversion.
L ⎛ I ⎞
2μCoxφt ⎜⎜ − 1⎟⎟
⎝ φt g m n ⎠ 16
•Current-based MOSFET
model(drain current split into
a forward and a reversed term:
ID = IF − IR
W 1
(VGB − nVSB ( DB ) − VT 0 )
2
I F ( R ) = μ Cox
L 2n
V −V
VDB = GB T 0
n

•Forward saturation
I F >> I R and I D ≅ I F

•Normalized output characteristic:

VDS ⎛ 1 + if − 1 ⎞
= 1 + i f − 1 + i r + ln ⎜ ⎟
φt ⎜ 1+ i −1 ⎟
⎝ r ⎠
I F( R ) ⎛W⎞
if (r) = IS = ISQ ⎜ ⎟ ISQ =technological
g pparameter
IS ⎝L⎠ (slightly dependent on VG)
17
 The Saturation Voltage
gms
A= = gain in CG configuration
gmd

VDSSAT
φt
⎛ 1⎞
(
= ln (A ) + ⎜ 1 − ⎟ 1 + i f − 1)
⎝ A⎠
1

⎛ 1⎞ 10

⎜1 − ⎟ — saturation level
⎝ A⎠
0
10

•Strong inversion
VDSsat

VDSSAT ≅ φt it = (VG − VT ) / n -1
A = 100
10
A = 30
A = 10
•Weak inversion
l (A )
VDSSAT ≈ φt . ln 10
-2
-2 -1 0 1 2 3 4
10 10 10 10 10 10 10
Inversion level – if- 18
Drain Current and Aspect Ratio
2

g m = 2π ⋅ GBW ⋅ CL 10

1+ 1+ i f 10

I D = gm ⋅ n ⋅ φt
2 10
0

W gm ⎛ 1 + 1 + i f ⎞
= ⎜ ⎟ -1
I BIAS
L μ ⋅ Cox′ ⋅ϕt ⎜ id ⎟ 10 2 ⋅ g m ⋅ n ⋅ φt
⎝ ⎠ W L
g m (2 ⋅ μ ⋅ C′ox ⋅ φ t )
-2
10 -2 0 2 4
10 10 10 10
id
Normalized ID and W/L vs. if
WI (if<<1) MI (if=8) SI (if>>1)
ized IDID
normalized 1/2 1 if / 4
zed W/L
normalized W/L 4 / if 1 2/ if

19
 Correlation Between Area and Frequency Response

CL GBW
WL ≅ 2
′
Cox fT

Correlation Between Junction Capacitance (CJ) and Frequency Response

Parasitic capacitance α GBW/fT

CJ CJ′ L DIF GBW
CJ = CJ ′ ⋅ W ⋅ L DIF LDIF ≅2
CL C′ox L fT
W
CJ

20
 BIPOLAR MOS
IBIAS=IC IBIAS=IID

+
DC Circuit CL
VO
CL +
VO
+ +
VI - -
VI
- -

Transconductance ⎛ ⎞
gm 1 gm 1 ⎜ 2
-to-current-ratio = = ⎟
(gm/ID) IC φt ID ϕt ⎜ n 1+ 1+ i f
⎝ ( ) ⎟
⎠

⎛ ⎞
DC Gain VA VA ⎜ 2
(Avo) Avo = − Avo = −
(
φt ⎜ n 1+ 1+ i f )
⎟
⎟
φt ⎝ ⎠

1 IC ⎛ ⎞
Gain-Bandwidth GBW = GBW =
1 ID ⎜ 2 ⎟
Product (GBW) 2πCL φ t ⎝ (
2π CL φt ⎜ n 1 + 1 + i f ) ⎟
⎠

1
Intrinsic Cutoff
Frequency (fT)
fT ≅
2πτ
fT ≅
2πτ
1
2 ( 1 + i f −1 )
Minimum Output VCEsat
CE t ≅
6 to 8
VDSsat
DS

φt
= ( 1+ i f −1 + 4 )
Voltage (VO) φt
21
22
 Design Methodology
1+ 1+ if
I D = g m ⋅ n ⋅ ϕt
1 - Select the inversion level (if) 2
for 'optimal' design (ID, W/L). W
=
gm ⎛
⎜
1 ⎞
⎟
L μ ⋅ Cox′ ⋅ ϕt ⎜ 1 + i f − 1 ⎟
⎝ ⎠
VDSsat
φt
= ( )
1+ if −1 + 4

2 - Choose both W and L.L If

fT≅GBW, add the parasitic
capacitances (CJ, Cov) to CL. CJ + Cov
=2
1
(CJ′L DIF + CGDO ) GBW
CL LC′ox fT

3 - Verify if the spec for Avo is met. Otherwise, increase the channel
l
length
th and/or
d/ reduce
d id (cascode/cascade
( d / d ddesign
i can b be necessary).
)

4 - Take into account VDSsat and the parasitic capacitance of the

current source.
23
• Process technology to choose
• Cost
• Performance
• Compatibility
• Design approach and testing time
• Floating Gate
• Bulk-driven
Bulk driven
• LV techniques
g
• Region of operation
p
• Weak inversion
• Moderate inversion
• Ohmic region
• Saturation ( strong inversion) 24
 Small Size Technology
• The good news is that we will be able to run our
ICs faster i.e., circuit delay is scaling down by 30% every
generation.
ti
• The bad news is that leakage power dissipation
increases in a much faster rate than dynamic
power

Power (W)
100
20
Active Power L k
Leakage P
Power

0.01
.001
1970 1990 2000 25
E
Example:
l 9090nm

• sub-threshold leakage increases exponentially with

every 65mV
65 V ddecrease iin threshold
h h ld voltage
l

26
 LEAKAGE SOURCES IN CMOS CIRCUITS

1. Subthreshold leakage in the channel in an OFF

transistor between the source and drain
t
terminals
i l (Isub)
2. Reverse-bias source/drain junction leakage (IRB)

3. Gate leakage ( IGATE)

27
NMOS TRANSISTOR and ITS THREE MAIN LEAKAGE SOURCES

Isolation Oxide V DS V GS drain

source gate ID

source gate drain p n+ n+ p p n+ n+ p

n+ n+ n+ n+
p p p p

p p p p
substrate
p p p p p

Top view p- substrate

Well
VGS = 0, VDS = 0 (cutoff)

Drain
IRB
IGate
Well
Gate IRB
Source
Isub
28
 High Speed Amplifiers Remarks
• Op Amps usually have more than one high
impedance node, this slow significantly the speed
of amplifier. Recall that poles are inversely
proportional to time constants. Thus large
impedance node imply
impl poles near the origin.
origin
• Transconductance Amplifiers have ideally only
one high impedance node,
node all the internal nodes
are low impedance. This produces low voltage
ggains but the highest
g frequency
q y response.
p
29
C
Course Obj
Objectives:
ti

To understand at the macromodel level the circuit design

g
parameter tradeoffs.

To design optimal circuits,

circuits that is circuits that meet the
specifications with minimum area, design time and/or power.

To identify the effect of the non-idealities of actual circuits

and how to overcome these problems.
problems
30
Next we review the conventional Op Amp Design
frequency response compensation and also we
introduced a simple LV Current-Mode based Op
Amp using resistors as transconductors.
Difference Differential Amplifiers are also
introduced.

31
 UNCOMPENSATED CMOS OPERATIONAL AMPLIFIER
VDD
M3 M4 1
M6
C p1 2 v o1 Node 3 is a low impedance
Vin+ M1 M2 High M8
Vin− Cp2
Impedance 3 vo
M5 M7 CL
Vbs M9

VSS AV3 ~ 1
M1=M2; M3=M4

Ignoring zeros we can model this topology as:

Vin+ io1 io2

−
vo
V R o1 C p1 Ro 2 Cp2 Ro 3 CL
in

g m1 − gm6 g o 2 + g 04 go6 + go7

AV1 (0 ) ≅ ; AV2 (0 ) = ; ω p1 = ; ω p2 =
g o1 + g o 3 go6 + go7 C p1 C p2
AV 1 (0 ) AV 2 (0 ) AV 3 (0 ) g
AVT (s ) ≅ ; ω p3 ≅ m 8
(1 + s ω p1 )(1 + s ω p2 )(1 + s ω p3 ) CL
32
 UNCOMPENSATED CMOS OPERATIONAL
AMPLIFIER STABILITY ISSUES

• The low frequency voltage gain is high enough for a number of

applications.

• The open loop poles are far from the origin, this can cause stability
problems for closed loop applications.

• Closed loop poles might end very close to the jw axis and some in
the RHP.
RHP

• How to tackle this stability problem will be discussed next.

Two-Stage Uncompensated Amplifier
DD

3 4
6

Io I o
2 2
6
+ 1 2 −
vin vin g
i
out

o 7

7
5

SS
Uncompensated Operational Amplifier
gm2 g m6 Large
g voltage
g ggain
− A V = A V1A V 2 =
g 02 + g 04 g 06 + g 07
− Poles are close to the jω axis causing stability problems
34
 Employing a simple capacitor will split correctly the poles but will generate a
Zero in the RHP.
RHP

Using an RC compensation can eliminate the zero and split poles. The resistor
can be implemented with transistor in the ohmic region.
VDD

M3 M4 M8
A M6
M1
− M1 M2 0
Vout
v in CC M11 B
M9
M5 M7
v bias
bi

VSS

IImprovedd iinternally
t ll compensatedt d CMOS operational
ti l
amplifier. Better bias for the output stage (M8 and M9)
Analog and Mixed Signal Center, TAMU (ESS) 35
A variation at the output stage with class – AB is shown below.

−
vDS4 v GS6
+

Io I o
2 2 v GS 9
− +
vin v in

Vbias v GS 7
bi

CMOS op-amp with class-AB output stage and RC pole splitting.

36
“Pole Splitting” can be carried out with a compensation capacitor
feedback and a voltage
g buffer as shown below

+ −
vin vin

Two-Stage amplifier with source follower compensation scheme

• Without M12 and M11 a zero in the PRH

• With buffer (voltage follower), zero is eliminated and pole splitting

(due to CC ) is kept. 37
How about using a current follower instead
of a voltage
g follower?

38
Using a current buffer instead of a voltage follower for pole splitting.

M3 M4 M7 M8

Ibias M12
+ −
v in M1 M2 v in
M11 Vout
CC

M6 M9 M10
M5

Two-Stage amplifier with Current Buffer compensation scheme.

• Improve SR at the expense of power consumption.

39
 Summary for Two Stage Op Amp Architecture Designs
• Roots close to the jω axis for uncompensated
Q6
s p1 s p
Vin− Vin+ CL
2

I bias
↓ I ss • Potentially
o e a y unstable
u s ab e for
o some
so e values
va ues of
o CL
Vbias
Q5 Q7 Ibias = CLSR*2.5

Q6
Q9 • Improved output stage optimal bias of Q6 and Q7
Vin+
• No significant change of pole locations.
Vin− Vo
I bias Av (0) -> +
↓ I ss Q7
Vbias Q10
Av (ω)
( ) -> -
Q5

Q6
Q9 Vo
Pole splitting => one dominant pole
Vin− Vin+ CC ∫∫ s
s p1 p2
z1
I bias
↓ I ss Q7 z1 Phase
Ph ddeteriorates
i phase
h margin
i
Vbias Q10
Q5 The good and the bad news
Analog and Mixed Signal Center, TAMU (ESS)
Two possible solutions to cancel z1 and keeping sp2 > ωt =GBW and sp1 small

Vo Vo

Vin+ Vin− CC CL Q10

CC

I ss I ss
Q11
Vbias Vbias

Internally Compensated
Internally Compensated
with unity gain buffer
with RC CC
(Q10, Q11)
Operational Amplifier (conventional) Architectures.
Architectures

Reader.- See the internally

y Op
p Amp
p compensated
p with current gain
g
buffer in pages 36 and 37

Analog and Mixed Signal Center, TAMU (ESS)

This is an example of a Op Amp design using three
different frequency compensation techniques.

Technology used is 0.5 um CMOS Technology 42

Remarks.-
Remarks

We have studied three topologies of Op Amps

with internal frequency compensation.
Important variations are topologies with improved
Output stages such as Class A A-B.. Also the cascode
and folded cascode topologies are often used to
Increase the output impedance and thus the voltage
Gain These cascode topologies are possible if
Gain.
there is enough headroom to bias properly the
transistors and still allow sufficient output voltage
swing.

43
Examples of Techniques for Wideband Amplifiers
Focus the improvement in the load of the differential pair
R
Current Mirror Frequency Dependent
at the output load Current Mirror (FDCM)
CF >> Cgs
Conventional Wideband Alternative 0 1K < R < 1K
0.1K
CF

Ib
CF

Low Frequency
L F
Behavior
High Frequency
Behavior
T. Itakura and T. Iida, “A Feedforward Technique with Frequency-Dependent Current Mirrors for a Low-Voltage
Wideband Amplifier,” IEEE J. Solid-State Circuits, Vol. 31, No.6, pp. 847-849, June 1996.
An example of its use:

VDD
R3
M P3 Ib
M P4
M P1
vin− M P2 vin+ vo
CF1
CL
CF2
M P3 M n1 M n4
R1 M n2 R2
− VSS

Wideband Amplifier with Feedforward Technique

• CF1 by passes two current mirrors.

• CF2 is fed forward to the input of another FDCM and signal
i amplified.
is lifi d
Next,
N t we discuss
di a few
f different
diff t families
f ili off wideband
id b d reported
t d in
i the
th
literature.

RL RL
M n3 vo+ vo− M n4
• An alternative is to
connect CF instead
vin+ M n1 M n2 vin− to nodes B to nodes A
A A
B B
CF RSS CF

F. Centurelli et al, “A Bootstrap Technique for Wideband Amplifiers,” IEEE Trans. on Circuits
And Systesm – I, Vol. 49, No. 10, pp. 1474-1480, October 2002
FOLDED-CASCODE WIDEBAND AMPLIFIER ( See page 11 for cascode)

Vb4
Vb4
M P4 M P3

RF1
M P2 Vb1 Vb1 M P1 Vb1
Vb1 vin+ vin− Vout
vin+ −
vin
i
C F1 Vb2 CL
C LVOUT C F2
I tail M n5 I tail
Vb 2

M n3 M n4 M n3 M n4

Conventional Folded-Cascode (FC) FC with Capacitive Feedforward

V DD

R F1 R F2
Vb1 Vb1 V b1
I bias V o+ Vin−
V o− C F1 V o+
CL CL
C F2 Vb 2
Vb 2

− V SS
Differential Wideband Amplifier
F. Opt Eynde, W. Sansen, “A CMOS Wideband Amplifier with 800MHz Bandwidth,” IEEE Custom Integrated Circuits Conf., pp. 9.1.1-9.1.4, 1991
 VDD
io+
M12 M5 M6 M14 OP
Vbias v+ X Figure 1 io-
ON
IB IB IB IB

B OP
ib
M1 M3 M8 V- X Figure 1
ON

-
R ON OP
X
vin A
ix io - io+ Fig
g2
iR
Pseudo Differential Op Amp
M13 M2 M4 M9 M10 M11
VSS iR = Vin/R
iX = - iR
Fig. 1 Transconductance Amp
Basic Structure based on current-mode IB > iR
E.K.F. Lee, “ Low-Voltage Opamp Design and Differential Difference Amplifier Design Using Linear Transconductor with Resistor Input
, “ IEEE Trans. Circuits and Systems II,vol. 47, pp 776-778, Aug. 2000 48
 VDD
Transimpedance
amplifier
Vbias

CC
vo
io+
v+
Figure 2 io- R1
v-

R1

VSS

Fig 3 VCVS Amplifier: Op Amp

io1+
v1+
Transimpedance vo
Fi
Figure 2 io1-
amplifier
v1-
io2+
v2+
Figure 2 io2-
v2- DDA
49
 References

SS Rajput, SS Jamuar, Low voltage analog circuit design techniques, IEEECircuits and
Systems Magazine,,pp 24-42, 2002
S. Yan and E. Sánchez-Sinencio, Low Voltage Analog Circuit Design Techniques: A Tutorial,
IEICE Trans. Fundamentals, Vol. E83-A, No. 2, pp 179-196, February 2000
E. Sánchez-Sinencio and Andreas G. Andreou,, Eds. “ Low-Voltage/Low-Power
g Integrated
g
Circuits and Systems “, IEEE Press, Piscataway, NJ 1999
X. Xie, M.C. Schneider, E. Sanchez-Sinencio and S.H.K. Embabi, “ Sound Design of Low
Power Nested Transconductance-Capacitance
p Compensation
p Amplifiers”,
p , IEE
Electronics Letters, Vol. 35, pp.956-958, June 1999.
A. Rodriguez-Vazquez and E. Sánchez-Sinencio, Eds., Special Issue on Low-Voltage and
Low-Power Analog g and Mixed-Signal
g Circuits and Systems,
y IEEE Trans. on Circuits
and Systems I, vol. 42, No. 11, November 1995
J. Crols, J.; Steyaert, M.; Switched-opamp: an approach to realize full CMOS switched
capacitor circuits at very low power supply voltages Solid-State Circuits, IEEE Journal of
, Volume:
Vl 29 , Issue:
I 8 , Aug.
A 1994 P
Pages:936
936 - 942

50
Analog & Mixed-Signal Center (AMSC)
 References

CMOS Analog Design Using All-Region MOSFET Modeling. M. Schneider and C.

Galup-Montoro, New York, Cambridge University Press 2010
Low threshold CMOS circuits with low standby current
Stan, M.R. Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium
on , 10-12 Aug. 1998 Pages:97 - 99
Ad
dynamic
namic threshold voltage
oltage MOSFET (DTMOS) for ultra ltra low
lo voltage
oltage operation Assaderaghi,
A d hi F.;
F
Sinitsky, D.; Parke, S.; Bokor, J.; Ko, P.K.; Chenming Hu;
Electron Devices Meeting, 1994. Technical Digest., International , 11-14 Dec. 1994 Pages:809 -
812
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g ggain and high
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Analog & Mixed-Signal Center (AMSC)