Escolar Documentos
Profissional Documentos
Cultura Documentos
Email: navakant@ece.iisc.ernet.in
URL: http://ece.iisc.ernet.in/~navakant/Navakant_Bhat.html
August 2006
Dr. Navakanta Bhat 1
Logistics
• Instructor : Navakanta Bhat
• Lab session :
• Involves circuit design, simulation and analysis
using any circuit simulator (Spice3f5, WinSpice,
T-Spice, P-Spice, H-Spice, Spectre, Eldo…)
• Grading :
• Home work (lab assignments) : 20%
• Class tests : 20 %
• Course project : 20 %
• Final exam : 40%
Dr. Navakanta Bhat 2
List of Reference books
Due to the advent of mixed signal SOCs, numerous books
have been published on Analog Design. A partial list :
1. Analog CMOS Design
Razavi, McGraw Hill Publication
Input Output
Sensing Actuation
Blue tinge was created by a light shown on the chip. Actual size: 0.040 x 0.062 inches
First IC using planar process and photolithography was demonstrated by Robert Noyce at Fairchild semiconductors
Dr. Navakanta Bhat 11
Metal Oxide Semiconductor Field Effect
Transistor (MOSFET)
• Field effect transistor concept proposed in 1930s by Lilienfeld
PMOSFET NMOSFET
metal metal
oxide oxide
p+ n p+ n+ p n+
Silicon Silicon
CMOS Inverter
PMOS
IN OUT
NMOS
“Cramming more Components onto Integrated Circuits” “VLSI: some fundamental challenges”
Gordon E. Moore, Electronics 1965, p. 114. Moore, IEEE Spectrum 1970, p.30.
The bold extrapolation in 1965 by Moore was a challenge
to the industry to show the determination to lead a revolution
Moore proved his vision, by guiding INTEL
along his predicted trajectory
Moore who studied Chemistry in college is yet
another example to reiterate the fact that there
are no hard barriers between different fields
The implicit assumption behind Moore’s
“Moore’s law governs the Silicon revolution” law is the feature size scales continuously
Bandyopadhyay, Proc. of IEEE, 1998, p.78
Dr. Navakanta Bhat 15
Evolution from SSI to VLSI
• State of the art fab set-up costs more than US$2 billion
• Recovering the fab cost requires a modular process technology
approach capable of producing diverse products
metal
oxide
n+ n+ n+
p p p p
n-
Silicon
p
120
100
80
60 ft
ft
40
20
0
0 0.2 0.4 0.6 0.8 1 1.2
Channel length
G B
S
schematic switch model
gate
n+ n+
A A’
P-well
Si
lay out cross section
Tox Oxide
xj n+ source n+ drain
p substrate
Doping concentration = Na
µε oxW (Vgs − Vt )2
Ids =
Tox L 2
Vg3
Saturation
Vds=Vdd
Vds Vgs
•Ids is constant and independent of Vds in saturation
•Ids is zero in sub-threshold region
Both of these idealities are incorrect especially for
the sub-micron MOS transistor
Dr. Navakanta Bhat 25
Channel length modulation
Vg > Vt Vd > Vg - Vt Ids
∆Vds
Rout =
∆I ds
n+ source ∆L n+ drain
electron channel
p-substrate Vds=Vgs-Vt
Vds
Effective channel length is Leff = L - ∆L, where ∆L=f(Vds)
µε oxW (Vgs − Vt )2 µε oxW (Vgs − Vt )2
I ds = I ds = (1 + λVds )
Tox Leff 2 Tox L 2
Ids increases slightly in saturation region with increasing Vds
This limits the AC output resistance for analog applications
λ is channel length modulation parameter in SPICE
Dr. Navakanta Bhat 26
Body effect
Vg Vd
Vs
n+ n+
p-substrate
Vbs
Tox 4ε s qN aφb
Vt 0 = V fb + 2φb +
ε ox
Vt = Vt 0 + γ ( Vbs + 2φb − 2φb )
Tox 2qε s N a γ = body effect factor (γ = 0.3-0.7)
γ=
ε ox
• Vt increases due to body effect
• This results in a transconductance term
Dr. Navakanta Bhat 27
Summary
• Analog design is indispensable in a variety of applications
involving interaction with the physical world