PROFESSOR’S NOTES Vers 2.

20.1: CONCEPTS OF POWER ELECTRONICS

Most circuit electronics assumes a fairly casual attitude about power dissipation. For levels of power which are
small, on the order of mW and W, we obligingly ignore their impact on the circuit and concentrate instead on the
transfer characteristics Rin , Rout , and vo /vI . We assume that devices are ideal and they are able to handle levels of
any challenge, mV to kV and A to kA.

But when confronted by significant levels of power, our philosophy must change. High levels of power are accom-
panied by a certain degree of risk, and we must adopt caution if we are to ensure that the power is directed to the
application rather than to an innocent circuit component. We also have to be aware of the fact that large power
levels feature large voltage swings and large current swings, formidable situations for any circuit to handle, and
so small–signal analysis is inadequate. Our mission, should we choose to accept it, is to investigate the ways in
which we can design a circuit which is equal to conditions of large power and large amplitudes, and accommodate
the physical limitations of the devices and the ability of the environment to absorb our excesses.

Power electronic circuits usually take the form of:

(1) linear power amplifiers: – for signal drive of a large output transducer
(2) power converters: – to achieve levels of I,V required from the I,V that is available.

In these and other cases where large levels of power must be handled by electronic devices, several concepts be-
come of considerable importance. They are:

(1) Efficiency
(2) Thermal derating
(3) Distortion

The efficiency is the fraction of the supplied power that is actually delivered to the load. An efficiency of 100%
is desireable, but not very likely. Chances are that some power will be wasted along its route to the load and be
dissipated within the circuit. Power dissipated within the circuit manifests itself in the form of heat. Heat is an
unsavory companion, since it degrades the circuit capabilities and operational lifetime. In order to keep the transis-
tors out of trouble, their power–handling capability must always be derated by the ability of the cooling system
to cool the fevered brow of the junctions, and these constraints must be factored into the design. Since transistors
are not necessarily linear over their conduction region, and since the circuit itself has compliance limits, the signal
is subject to considerable distortion unless we use corrective designs.

Elementary heat transfer principles and common sense tell us that temperature difference is proportional to the
heat, – as is generated by dissipated power. Most of the dissipated power is released at the junction of a transistor or
diode, or in the channel if the component is a FET. Assuming that the junction temperature is of magnitude TJ and
the ambient temperature is TA , then we can make the identification


TJ

TA 
PD
JA (20.1–1)


where PD is the power dissipated in the device. The constant of proportionality, JA , is defined as the thermal resist-
ance between the junction and the ambient medium. Thermal resistance is given in terms of oC/W. The lower the
thermal resistance, the more heat can be conducted away from the junction. Cooler junctions are happier junctions.

200
Transistors have a maximum rated junction temperature TJ (max), on the order of 130 to 200 oC. It must not be
exceeded, or device meltdown, distortion of the space–time continuum, or something else equally undesireable
will take place. One of the design concerns of power electronics circuits is that TJ be kept less than TJ (max).

,.-  + / 

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Figure 20.1–1 Thermal resistances.

Temperatures can be kept within reasonable limits if the transistor has good thermal conduction from the junction,
where the power is dissipated, to the ambient medium. Since the ambient environment is usually air, the exterior
part of the thermal path will usually be in the form of a ’heatsink’ radiator, usually little more than a metal plate with
fins. As indicated by figure 20.1–1, the thermal resistance 0 JA between the junction and the ambient medium con-
sists of a series path of heat–conducting layers or elements, each of which have their own thermal resistance, so that
0 JA 1 0 JC 2 0 CS 2 0 SA

where 0 JC , 0 CS , and 0 SA are the thermal resistances of the various layers between the junction and the ambient.
They consist of the junction–to–case, the case–to–sink, and the sink–to–ambient, layers (or elements) respectively.

Junction–to–case thermal resistance, 0 JC , is defined by the power rating of the transistor. Transistor power ratings,
PD (max), are usually defined in terms of a standard reference case temperature TC = 25oC. If we then know the
maximum rated temperature of the junction, TJ (max), the junction–to–case thermal resistance is:
(T J(max) 3 25)
0 JC 1 (20.1–2)
P D(max rated)

The junction–to–case resistance, 0 JC , is typically on the order of 1 to 20 oC/W, depending on the power rating of the
transistor.

Thermal resistance 0 CS is the contact resistance between the case of the device and the heatsink, usually kept small
by a (modest) use of ’heatsink grease’. It is typically on the order of 0.2 to 0.5oC/W.

The sink–to–ambient or heatsink resistance, 0 SA , depends on construction and size of the heatsink. A heatsink with
radiative fins should have a reasonably low thermal resistance per length. Doubling of the size of the heatsink will
approximately half its thermal resistance.

Consider the following example:

**********************************************************************************
EXAMPLE 20.1–1: A pair of 25W transistors, used for a class–A amplifier, dissipate a total of 12W.
Assuming TJ (max) = 175 oC and heatsink grease such that 0 CS = 0.4 oC/W, (a) what thermal resistance of
heatsink for each transistor is needed to keep the junction temperature below TJ = 125 oC and (b) what size
heatsink is needed, assuming that a 2 cm length of heatsink has 0 SA = 16 oC/W?

201
 SOLUTION: Assuming that the transistors are rated at TC =25 oC, which is default, then the internal
thermal resistance JC is

JC
(175  25)  25
6 oC  W

Each transistor must dissipate 6W, and therefore, in order to meet junction requirement TJ  125 oC

JA
(125  25)  6
16.67 oC  W

Therefore (a) a heatsink of thermal resistance

SA
JA  ( JC  CS )
16.67  6.4
10.27 oC  W

is required for each transistor. (b) Using the heatsink stock cited, which is 16 oC/W for each 2 cm, each
heatsink must be of length

L 16 2 3.12cm



10.27 

For extra margin, we might cut off a 4 cm piece of stock for each transistor.
**********************************************************************************

In other cases, we might define a limit on the power that can be dissipated by a given transistor or device, in terms of
PD < PD (max). Note that, since

PD
I DV D

for which ID is the current through the device and VD is the voltage across the device, this relationship to PD repre-
sents a hyperbola in the I vs V domain. This behavior is represented by Figure 20.1–2, showing power hyperbolas
for both BJT and FET devices. We typically represent electrical properties of a BJT by a plot of IC vs VCE and an
FET by ID vs VDS , and often use these graphics to define load lines, etc. If we include a power limit, it represents a
limit as represented by the hyperbola PD (max) = ID  VD . This usually represents the derated power, since
PD (derated) must always be less than the PD (max) defined by optimum conditions. It should be noted that it is
usually not possible or practical to expect a 25W transistor to dissipate 25W, because of this thermal derating.


.


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202
20.2 LINEAR POWER AMPLIFIERS

In most applications involving signal amplification the final stage of the circuit is an output driver. This output
driver is usually dedicated to operation of a large transducer, usually electromechanical or radiative. The transduc-
er usually needs substantial levels of drive power, defined by (I,V) amplitudes. One of the more typical transducers
is the audio speaker, which is effectively an electromagnetic air piston. Load transducers, like the audio speaker,
come in various sizes ranging from little pipsqueaks to giants capable of defoliating trees along the roadway. So, in
like manner, our power circuits must be constructed in various sizes, matched to the demands of the output trans-
ducer. For simplicity, we will generalize the load transducer as merely a load resistance RL .

It should be noted that the power that an amplifier delivers to an output transducer is drawn directly from the power
supply rails. The ’amplifier’ circuit acts to channel power to the output load, and is little more than a pair of brute
transistors controlled by an input signal, situated between load and the power rails. Most of the time we assume that
the control signal is sinusoidal and that the transistors will therefore pass a sinusoidally varied current. In some
instances we let the transistors act as BIG switches, with an output that is a rail–to–rail square–wave.

Assuming sinusoidal signals, we find that the power delivered to a transducer of resistance RL by the drive transis-
tors cannot be any more than 2VS 2/RL , where rails of opposite polarity VS are assumed. Therefore, often the first
step in analyzing a linear power amplifier is to determine the power supply requirements needed to support the
output transducer at the desired load level.

For purposes of matching application to circuit form, power amplifiers are usually identified by a classification
system. Classification is defined by the duty cycle of the drive transistors. A circuit for which the drive transistors
are always conducting is called a class A amplifier. The transistors in the class A amplifier have a duty cycle of
100%. Class A amplifiers provide a nearly undistorted output signal, but do so at rotten efficiency. Most casual
circuits are of type class A, since they operate about an ”operating point” level. For the class A amplifier, efficiency
and the level of power dissipated in the transistors are at their worst when the amplitude of the input signal is zero,
since then all of the power must be dissipated in the circuit.

We improve the efficiency dramatically if we merely construct a circuit that is off when the signal level is zero. We
can accomplish this easily if we employ a pair of complementary transistors to drive the load. Ideally, each of the
drive transistors conducts only for half of the cycle and are off the other half cycle. This type circuit is called a class
B amplifier. The drive transistors in a class B amplifer have duty cycle of 50%. When the signal is at zero amplitude
no device is conducting and no power is consumed, a considerable improvement over the class A amplifier.

If the circuit is modified so that the drive transistors have a duty cycle slightly more than 50%, then the circuit is
called class AB. Class AB circuits have an efficiency slightly less than the class B amplifer. Class AB amplifiers
resolve a zero–crossing distortion problem that afflicts class B amplifiers.

Class C amplifiers have drive transistors biased below cutoff, and deliver large amounts of power for a small frac-
tion of a cycle. Class C amplifiers are defined as those whose duty cycle is less than 50%. They are usually used
only for tuned circuits. They have an efficiency greater than class B since the device conducts only when the signal
level is significant.

A type amplifier that does not quite fit the duty–cycle classification pattern is the class D amplifier. Class D ampli-
fiers are switching amplifiers, and their efficiency can approach 100%. For analog signal applications the class D
amplifier must include a modulator at the front–end to translate the waveform into high–frequency pulse widths,
and a filter network at the back end to remove the high–frequency pulses from the amplified output. Usually the
filter network is of a simple, lossless form such as R–L or R–C.

203
Table 20.2–1 summarizes the different types of common power amplifers and the way in which the signal is han-
dled.

Table 20.2–1. TYPES OF POWER AMPLIFIERS

TYPE DUTY CYCLE WAVEFORM

CLASS A D = 100%

CLASS B D = 50%

CLASS AB D > 50%

CLASS C D < 50%

CLASS D

204
20.3 POWER TRANSISTORS

Power transistors are the strong, big, slow members of the transistor kingdom. They usually live in their own sepa-
rate cases, with a tab or plate designed to have contact with a heatsink. They are not conceived in the same way as
their integrated–circuit cousins, but are formed in fierce, formidable environments. Therefore power transistors
are not usually included in an integrated circuit, since most IC fabrication technologies are dedicated to high–den-
sity, mild–temperature applications. This exclusive situation is not a law, and developments of new technologies
have allowed us to have some integrated circuits that have power transistors as a member. Whether in separate or
integrated form, we should think about power transistors and power diodes as the heavy lifters of the semiconductor
kingdom, designed to handle great power levels, and packaged to dissipate great levels of heat. In order for us to
design for these capabilities to best performance and operating lifetime, it behooves us to take a critical look at their
operating and performance characteristics.

In the first place, we expect power transistors to have relatively large cross–sectional area. Naturally, if all they had
to do was handle larger currents, we would just make a BIG (area) transistor of the usual type. But higher levels of
power also requires that we be able to control higher voltages without a breakdown disaster. So, in general, power
transistors are constructed with a different semiconductor layering, usually including one or more lightly–doped
regions, which are able to accommodate higher voltages.

So power transistors and diodes are characterized by:

(a) greater cross–sectional area

(b) a relatively thick, lightly–doped junction layer, for reduced level of E–field

There are other, more subtle things that we may do as well, such as heavy doping with gold or copper to speed–up
the recombination processes. For MOS devices, thicker oxide layers are necessary to protect the device from over-
voltages. The thicker layers cause FET device threshold, VTH , to be higher.

These modifications will compromise some of the other characteristics that we covet, such as low resistance and
fast response. Lightly doped regions have a significant intrinsic resistance, which lies directly in the current path.
Greater areas imply larger capacitances. Larger current levels imply higher levels of injected and stored charge.
These effects are all bad for switching speed and internal power dissipation.

Power transistors are, in general, characterized by the following performance limitations:

(c) higher VTH , lower F

(d) slower switching speeds
(e) greater VCE (sat), VDS (sat)
(f) greater intrinsic resistance in the conducting path

We will take a short look at each of the most common types of power transistors and components, and assess them as
candidates for our power electronics circuits.

P–I–N junctions

The p–i–n junction is a pn junction that includes a layer in the middle of the sandwich which is of intrinsic or near–
intrinsic semiconductor material. To the semiconductor world it probably looks like an ice–cream sandwich, with
the (vanilla) core being nearly ’clean’ of impurities. Actually, the core is always slightly doped, so we usually call
the junction a p– –n if the ”intrinsic” layer is slightly p–type, or a p– –n junction if the ”intrinsic” layer is slightly



n–type. Figure 20.3–1 shows a representative p–i–n junction and E–fields thereto.

205
 
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Figure 20.3–1 The p–i–n junction: (a) Cross–section (b) Potentials and E–fields in reverse–bias (c) In-
jected carrier levels in forward bias

The figure shows that, in reverse–bias, the E–field is relatively low, since the intrinsic layer can be made of thick-
ness much larger than the usual \ 1 ] m depletion depth of the typical pn junction. The E–field is approximately:
E \ V J^ W i (20.3–1)

where VJ is the junction reverse–bias and Wi is the thickness of the intrinsic layer For junction breakdown fields,
which are typically on the order of 20 to 40 V/ ] m, a reverse–bias of 100 V across an intrinsic layer thickness of 10
] m still has a comfortable safety margin, of another 100 V.
However in forward bias, we are faced with an intrinsic region across the main current path that has a miserable
conductivity, _ = q` Ni. Ni is the (low) doping density and ` is the carrier mobility. For cross–sectional area Ai and
layer thickness Wi , this leaves us with series resistance
Wi
Ri \ (20.3–2)
q` N iA i
**********************************************************************************
EXAMPLE 20.3–1: What is the intrinsic resistance for a silicon p–a –n junction of cross–sectional area
Ai = 1.0 cm2, doping of the intrinsic layer Ni = 2 b 1014 #/cm3 and layer thickness Wi = 30 ] m. Assume ` n
= 1250 cm2/Vs.

Ri \
Wi 30 b 10 d 4 75 me
SOLUTION:
q` N iA i c 1.6 b 10 d 19 b 1250 b (2 b 10 14) b 1.0 c

As resistances go, this doesn’t sound too bad, until you realize that this junction may be conducting 100 A
over a 50% duty cycle, in which case it must dissipate
PD 0.5 b 100 2 b 75me 375W
c c
At this level of internal power dissipation this had better be one tough junction.
**********************************************************************************
In forward bias we also have something of a speed problem, due to the fact that the intrinsic region is flooded with
charge carriers. And as a result of the low doping levels, we will not necessarily have a fast recombination time

206
constant R , since recombination time depends on the density of impurity sites. We usually add gold or copper to
enhance the recombination time, but this type of doping causes other complications. Therefore when we swing the
bias voltage from forward to reverse, current will continue to flow with time constant determined (approximately)
by the diffusion capacitance per area,
CD
JD R (20.3–3)

where JD is the forward current density and R is the recombination time constant, which is usually BAD (on the
order of  s). Adding to our grief, we also will usually have large–area (= large capacitance) junctions.

Power BJTs

The power BJT is little more than a conventional BJT with a collector junction which is of the form of a p–i–n
junction rather than the usual simple pn junction. We see this represented by figure 20.3–2. Sometimes we can get
away with a ’normal’ BJT construction and simply have a mildly–reduced doping level for the collector material.
As long as we don’t have any reverse junction biases in excess of 100 V, this will probably work OK, but we do have
to make the device with a larger than normal base–width (layer thickness) to avoid ’punch–through’ problems.
Transistors of this species will usually have a  F somewhat less than the traditional BJT, on the order of 25 to 50.

Higher–power BJT transistors, which must be able to withstand reverse junction biases in excess of 200 V, are typi-
cally of the form represented by figure 20.3–2. This figure shows a BJT with an n+–p– –n+ construction. The
lightly–doped region is usually called the drift–region since the carriers must ’drift’ across this region before they
get ’collected’ at the n+ collector. Transistors of this type are lucky to have a forward current gain  F as good as 25.
They are also characterized by a large ’quasi–saturation’ region of operation, corresponding to partial forward–bias
conditions in the lightly–doped drift region, as represented by figure 20.3–2(c)

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Figure 20.3–2 The high–voltage power BJT: (a) cross–sections (b) forward–bias characteristics (c) excess carrier
distributions for a power BJT in quasi–saturation.

207
High–power BJT transistors, as represented by figure 20.3–2(b), are therefore also characterized by a fairly poor
VCE (sat) because of this quasi–saturation region.

This effect is represented by figure 20.3–2(a) and (b). If we work through the semiconductor details of junction
work–functions and injected carrier levels, we will find, after all the mathematical and semiconductor dialogue is
completed, that the power BJT structure will have a VCE VCE (qsat) at the boundary of the quasi–saturation
region given by
N 
V CE(qsat)
V BE  2V T ln n i V i (20.3–4)
i

where Vi = Ri  IC is the resistive drop in the intrinsic region, VBE is the voltage across the forward–biased base–

emitter junction, and the term 2V T ln(N i n i) is a collective term due to the work function potential between base
region and intrinsic region and the charge carriers injected into the intrinsic region from the base. In this term, ni =
intrinsic carrier density for a pure semiconductor, which = 1.5  10 10 #/cm3 for the most likely semiconductor,
silicon, at nominal ambient temperature 300 K. The coefficient VT is the thermal voltage, and is approximately
.026 mV at 300~K

**********************************************************************************
EXAMPLE 20.3–2: Assume that a 400 V power BJT has a p–i–n collector junction of the same dimen-
sions and doping as given by example 20.3–1. For a VBE of 0.69 V, assume that current density J = 50
A/cm. Find the value of VCE at the boundary of quasi–saturation.

SOLUTION: This is a brute transistor, so don’t expect a small VCE . We see that at the boundary of quasi–
saturation,
 
2V T ln(N i n i)
2  .026  ln  (2  10 14) (1.5  10 10) 
0.494V
so that the complete VCE across the BJT, at the onset of the quasi–saturation condition will be

 
 

V CE(qsat) V BE 0.496 Ri  J  A i) 0.69 0.494 (.075  50) 3.95V
At the edge of hard saturation, the p–i–n junction is forward–biased and carriers flood the intrinsic region.
This high carrier level makes Ri = 0.0 and therefore

V CE(sat)
0.69  0.494
0.195V

In practice, VCE (sat) is seldom achieved in a high–power transistor, because the gain F of such a transis-
tor is so low it becomes difficult to provide the necessary base current. Even in the active region, F would
probably be no better than about 20 for a transistor of this power–handling capability.
**********************************************************************************

The Power MOSFET

The power MOSFET is a vertical structure, as represented by figure 20.3–3. In this case an nMOSFET is repre-
sented. Note that it is a double–diffused structure (sometimes called DMOS), which, in this case, is a p–well dif-
fused into a lightly–doped substrate layer, followed an n+ source diffused into the p–well. Although this structure
doesn’t look much like a MOSFET, the figure shows that the region of the p–diffusion at the surface can be sub-
jected to an E–field across the oxide at that point. Therefore field inversion can be accomplished at this narrow
region and conduction will occur. The drain node is at the bottom. High voltages at the drain node are isolated from
the gate and the implants at the upper surface by the ”thick” lightly–doped (n–) substrate layer.

208
 

   



  

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Figure 20.3–3 The power MOSFET: (a) cross–sections (b) ID vs VGS output characteristics,
(c) ID vs VDS output characteristics.

In reverse–bias the intrinsic layer provides the usual high–field protection as identified for p–i–n junctions. In
forward bias the intrinsic layer has a finite series resistance that will give us some undesireable effects, not unlike
those that we saw for the power diode and the power BJT. The MOSFET gate–channel voltage must be able to
withstand channel bias levels on the order of 10 to 20 V, and therefore requires oxide thickness on the order of 100 to
200 nm . The p–well must be at a healthy doping level to avoid a problem called ’punch–through’. These effects
combined imply that VTH will have a magnitude on the order of 4 to 5V.

Because the depletion region extends into the channel during forward operation, the value of L is very small. This
short–channel results in very strong field along the channel, and therefore drives the transistor in velocity–satura-
tion VDS when in the forward active mode. The result is a linear transfer characteristic for ID vs VGS , as represented
by figure 20.3–3(b), and is of the form:
ID 4 WC OX5 v C(V GS 6 V TH) (20.3–5)

For velocity saturation, vC is on the order of 107 cm/s for electrons in silicon. Cox is the oxide capacitance/area and
W is the channel width, which we make as large as possible by artful designs of the surface geometry. One of the
favorite suface designs is a hexagonal arrangement, and such structures are often called HEXFETS.

The resistance rDS is the channel resistance for a MOSFET at low VDS, given by
r DS 475 C OX W (V GS 6 V TH) (20.3–6)
L

This resistance represents the lower boundary of the velocity–saturated drain levels, as shown by figure 20.3–3(c).
It also represents the drain resistance of the MOSFET channel when it is operating in its most conductive state, a
fact which is often necessary for evaluating power dissipation in the device.

209
20.4 CLASS A AMPLIFIERS

A class A power amplifier is commonly of the form of a follower circuit, not unlike that shown by figure 20.4–1(a).
The follower circuit requires operation about a quiescent point, for which a finite operating current and voltage
drop across the transistor are necessary. Since the transistor is biased in the active regime, the drive transistor will
operate in a 100% duty cycle condition. In the voltage follower mode the drive transistor stays in the active mode
throughout the drive cycle. The output should therefore be almost undistorted, depending only on the linearity of
the drive transistor(s). The follower circuit has a fairly linear response over a wide output range, as indicated by
figure 20.4–1(b), and therefore the class A circuit is very ’linear’ in its response, with relatively little distortion of
the output. We might note theat the constant current source, which delivers fixed current, IS , will also require power
transistors and heat dissipation.







 


 




Figure 20.4–1 Class A circuit using BJT drivers.

The follower circuit does not necessarily have to make use of opposite polarity power rails, but for the sake of
simplicity in analysis and for comparison to other classes of power amplifiers where opposite–polarity power rails
are necessary, we will take this approach.

The voltage and current requirements of the circuit are defined in terms of the power to be delivered to load RL . For
a power amplifier with BJT drivers, and assuming that the output driver of the current source is a single BJT, then
the amplitude of the output waveform will be bounded by:
(V S V CE(sat))  V L  (V S V CE(sat))

where VS ( = VCC for BJT circuits) is the level of voltage on the power rails, and VCE (sat) is the saturation voltage of
the transistor. As indicated by section 20.3, VCE (sat)  0.3 V for the generic BJT device, and therefore is usually
treated as being negligible for all but lower voltage (Vo < 5V) levels. For the high–power, high–voltage BJTs, the
quasi–saturation limit may be as high as 5V, but this higher limit may be regarded as negligible if the drive voltage
levels are on the order Vo > 100V, which is a typical amplitude level for high–power transistors.

We therefore assume, as a slightly rougher approximation, that the upper and lower bounds of the output voltage are
VS  VL  VS

We can therefore identify the current level needed to drive the load, RL as:
VS
IS  (20.4–2)
RL

210
This current is also the quiescent point, corresponding to an input signal of zero amplitude. Since IS is a fixed level

of current, then the power supply will continuously deliver power at the level
V2
PS 2V S I S 2 S (20.4–3)
RL

whether we elect to use it or not. If the input signal level is zero, the drive transistor must dissipate
V 2S
P D(max) VS IS (20.4–4)
RL

  V sin 
Otherwise, assuming sinusoidal signals of output amplitude VO , power delivered to the load RL will be

 P  
2


2 2 2
PL 1 L
d 1 VL (20.4–5)
L
2 RL 2 RL
0

We see that this power, PL , is a maximum (= PL (max)) when VL = VS . The maximum efficiency that the class A
circuit can provide is therefore

(max) P L(max)
PS

V 2S (2R L)
PS
0.25 (or 25%)

If we analyze and design the system in terms of a given load requirement PL , we see that, at worst case, comparing
equations (20.4–5) and (20.4–4), the power dissipated in each of the drive transistors will be
P D(max) 2P L(max) (20.4–6)

Wups! Did we say ’each’ of the drive transistors? We should realize that one of the ”drive” transistors is hidden in
the current source. A class–A amplifier using a simple BJT current mirror and the output waveforms of the amplifi-
er is represented by figure 20.4–2.

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Figure 20.4–2 (a) Class A circuit using BJT driver and simple current mirror. (b) Waveforms for the class
A amplifier.

In the design process, specifications typically include values for RL and PL . We usually desire the circuit to work at
best efficiency, and so can define VS –> Vo in terms of equation (20.4–5). The design task is then a matter of identi-
fying power supply requirements VS and IS , drive and current source transistors having suitable power ratings, and
appropriate heatsinks.

211
Consider the following example:

**********************************************************************************
EXAMPLE 20.4–1: It has been determined that mosquitos appreciate certain audio frequencies, for
which they will fall out of the sky, lie on their backs, and wave their little legs in appreciation. The 63.2
kHz piezoelectric oscillator in the Donohoe mosquito–suppressor operates at maximum effectiveness
when PL = 4W. The equivalent load resistance of this transducer is 10 , and is to be driven by a class A
amplifier of the form of figure 20.4–2. Q3 is one–fifth the size of Q2. Determine (a) power supply require-
ments VS and IS needed to drive this load, and the total power PS that must be supplied by the voltage rails,
including that required of the current source; and (b) find the (total) efficiency of this circuit.

SOLUTION: For PL = 4W, and assuming that maximum power is delivered to the load, then, from equa-

 2P R  2  4 
tion (20.4–5), for Vo = VS ,
VS

L L 10
8.94 V

The current source must then deliver

IS
VS
RL

8.94
10
0.894 A

Therefore the biasing resistance R1 of the current source must be:

8.94 0.7 

R1
IS 5  46

The positive supply must provide power of magnitude I SV S
2  P
8W
P L S1

The negative supply must provide current of approximately (I  I  5)
1.07 A S S , ignoring the base
defect. Therefore the power that the negative supply must support is
P
(6  5)  I  V
9.6 W . The total efficiency is then

P
4
0.227 (or 22.7%)
S2 S S

P  P 8  9.6
L

S1 S2

Because there is no biasing source, the input and output signal of this amplifier are offset from each other
by approximately 0.7 V. For best performance this offset should be accommodated by a 0.7V level–shift
in the signal produced by the stage preceding the power amplifier.
**********************************************************************************

Note that we MUST design conservatively. For slowly–varying signals the power that will be dissipated in the
drive transistors is nearly on the order PD (max).

20.5 DISTORTION

One of the more common problems that we find with large–signal, high–power amplification is distortion of the
waveform. The techniques of analyzing the distortion content of a circuit are greatly simplified by use of our
friendly circuit simulation software, SPICE. The techniques of analyzing distortion in a power amplifier are also
applicable to power supplies (converters), where a small, undesirable content of ripple voltage may be present.

If we make a spectral assessment of the amplified waveform with distortion, we would find that it is made up of a
Fourier–series of harmonics:
V O(t)
V 1 cos(
 ) 
1 1 V 2 cos(
 ) 
2     2 V N cos(

N N )

212






 

where 1 is the input frequency and ( 2 = 2 1 , 3 = 3 1 ... N = N 1 ) are harmonics. Phase shifts ( 1 , 2 , ... ,
2N ) also occur. The rms output for a distorted wave, which is a simple means of assessing the distribution of power
in the harmonic spectrum, is

V rms  1 2 V  2
1 V 22  V 23   V 2N

The distortion content is defined in term of its ’THD’. This little alphabet soup acronym is our index of the ’total
harmonic distortion’ of the waveform. It is the ratio of the rms distortion content of the output signal to the undis-
torted part of the rms output. It is given by

V
THD  V rms(distortion)

2
2  V 23 V 2N
V 1rms V1

Example 20.5–1 shows an example SPICE distortion analysis for a large–signal output taken off a single–transistor
circuit. The circuit is shown by figure 20.5.1(a). For convenience, the results are given in table form as represented
by figure 20.5.1(b). The distorted output for the large–amplitude signal is shown by figure 20.5.2(c).

213
 *********************************************************************************
EXAMPLE 20.5–1: Single–transistor amplifer distortion analysis using SPICE.

**********************************************************************************

In assessing distortion, the THD is a figure of merit that we always determine. The usual means of determining
THD is by means of the .FOUR option of SPICE.

214
20.6 CLASS B AMPLIFIERS

For applications in which we cannot treat power casually, the class A amplifer is not particularly useful, since so
much of the power channelled to it from the supply is committed to signal management, and in the quiescent state it
continues to consume power. This profligate consumption is wasteful and inefficient. Therefore most linear power
amplifiers are designed using class B form, or its kissin’ cousin, class AB. The ideal class B operates the output
drive transistors at only a 50% duty cycle. This half–wave operation gives considerable advantages in efficiency
over the (100% duty cycle) class A configuration.

A representative class–B power amplifier using BJTs is shown by figure 20.6–1. Note that complementary output
drivers are required, in this case, NPN and PNP output transistors. Ideal class B circuits are sometimes called push–
pull amplifiers since the upper driver, QN , ’pushes’ the signal into RL , and the lower driver, QP , ’pulls’ the signal
through RL with opposite direction of current flow. With a little imagination, some similarity can be seen between
this circuit and the class A circuit shown by figure 20.4–2, except now the circuit is symmetric and the quiescent
state is at the operational minimum for the transistor(s). Zero input signal corresponds to approximately zero pow-
er consumption. Although there are a number of variants on the concept, the output drivers must generally be com-
plementary, usually follower–type circuits, for successful class B operation.

   

 



  




 >4?<@<>9A6B4C1?


 
"!# $ %&$ '( &)#*,+.-0/132&(45#%6'(7/189:(;/126'(<$ <2&$ /=

Figure 20.6–1 Class B circuit using BJT output drivers.

There is a little problem with this configuration. Since the transistors have a ”dead zone” for VI DFE 0.6 V, the
output will have a serious (zero–crossing) crossover distortion that will give us some grief, particularly at low sig-
nal amplitudes. This effect is represented by the output of figure 20.6–2. Some of the homework exercises invite
you to make a SPICE distortion analysis of this problem, should you care to accept.

215
 %'&
%'(
)
)


% (

5,6 7 8 9: 8 6 9;

%'&


%'( 4



 

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#$ $ # *,+-./+101 23$ +-$ +3

Figure 20.6–2 Crossover distortion in the simple BJT class B circuit

The crossover problem is aggravated even further when MOSFETs are used, particularly since power MOSFETs
have a relatively high VTH . For this reason, MOSFETs are usually used in the CS driver configuration, as indicated
by Figure 20.6–3(b).

However, in our usual flair for approximations, we assume that we can get away with neglecting crossover, or in
some way surmount it, as represented by figure 20.6–3. Then we can develop a concise analytical recipe for dealing
with amplifiers of class B (and class AB) form.

C ?D C ?D

FG I G

?A ?@
?BA ?@

<>= <>=

FH
I H

?D ?D
E E

JQ_L ?gfMf KPQ-RTS RPUVWXPhYMW[ YXUU [ [_Waikj1d R JKML ?BNON KMPQ-RTS RPUVWXPYZW[ YXUUZ[ [_Wa`cbedZR
E]\ \^ E]\ \^

Figure 20.6–3 Idealized schemes for correction of the crossover distortion problem using diode–con-
nected transistors at the input. These circuits are actually of class AB form rather than class B. Practical
design schemes will be developed in section 20.7.

Since the transistors are only conducting on a 50% duty cycle, the time–averaged current that is drawn from either
rail of the power supply will be:

216
 
1 V L sin  VL
I AV d (20.6–1)
2
RL

RL
0

assuming sinusoidal signals. Therefore the power drawn from the voltage rails is:
V
PS P S1  P S2 2V S
L (20.6–2)
RL

The power delivered to the load (assuming sinusoidal signal) is

2
PL 1 VL (20.6–3)
2 RL

so that the efficiency is

VL
 (20.6–4)
4 VS

Note that, at VL = VS , at which maximum power will be delivered to the load, the ideal class B circuit form has
efficiency  of as much as /4, or 78.5%. This level of efficiency is reasonably good. Higher efficiency means that
less power is dissipated in heating up the transistor junction, and the transistors will lead a happier and longer life-
span.

Also, we see that (virtually) no power is drained from the battery when VI = 0. In point of fact, some power budget
may need to be expended to address the crossover problem, which is what we do with class AB, so an efficiency of
75.8% is only a theoretical maximum. It is not something we can count on, but with careful circuit design we can
approach this theoretical maximum.

The power PD dissipated in the transistors will vary somewhat with output amplitude VO . We can analyze the pow-
er dissipation in a fairly straightforward manner, since the power dissipated in each drive transistor is just
2
PD PS PL 1 2V SV L 1 VL (20.6–5)

2 
RL

2 RL 

Taking derivative P D V L 0 to determine the condition for maximum dissipation, we find that
2V S
VL
(20.6–6)

Substituting (20.6–6) into (20.6–5) we see that the maximum power dissipated in each drive transistor will be
V 2S 2
P D(max)
2
2 P L(max) 0.203P L(max) (20.6–6)
R L

where PL (max) = VS 2 /(2 RL ) is the maximum power that can be delivered to the load, corresponding to VO = VS .
When operating at the level given by equation (20.6–6), we also see that the efficiency is only 50%. At this output
level PD = PL . For most designs we should keep in mind that we should design conservatively, accommodating the
possibility of maximum power level PD being dissipated in the transistors.

Table 20.6–1 summarizes design considerations of the class A and class B amplifiers. Usually power amplifier
design approaches analysis in terms of maximum load PL delivered to equivalent load resistance RL , and this is the
way in which the table is constructed.

217
 Table 20.6–1. SUMMARY: ANALYSIS OF POWER AMPLIFIERS

TYPE PL(max) VS(min) IS(max) PS(max) PD(max, ea trans)

V 2S VS
CLASS A 2P LR L 4P L(max) 2P L
2R L RL

V 2S VS 4 P (max) 2
CLASS B 2P LR L
L
2 P L(max)  0.203P L(max)
2R L RL

The next–to–last column recognizes that when PL = PL (max), the power rails will have to supply PS = PL /  (max).
Note that conservative design procedure demands that our heat dissipation must be defined in terms of PD (max).

20.7 CLASS AB AMPLIFIER ANALYSIS AND DESIGN

The class AB amplifier is of a form approximately the same as the class B, making use of minor circuit modifica-
tions to surmount the ”dead space” cross–over problem. Essentially, it elects to make a mild increase of duty cycle
for each transistor so that there is no output state for which both transistors are non–conducting. To good approxi-
mation, most of the analysis associated with class B can be applied to class AB. Distortion is minimal, and may be
less than that of the class A amplifier, due to the symmetry of the output drivers. The principles behind class AB
operation are represented by figure 20.7–1.

1+6
13254

1I
132'9
8

8
.7/

J 1+I .0/


   "!"#$&%'(&)#+*,"*-

: <;=>#?"@ ACBD=?E =??FGBD-"HG#G

Figure 20.7–1: Principles of operation of the class AB amplifier.

We might note that efficiency is mildly reduced, since a quiescent current IQ must flow in the transistors when input
VI is 0. Rather than use two current sources, as indicated by figure 20.7–1, it is adequate to use a single current

218
source and have the previous stage act as a current sink, which it is usually happy to do. This scheme is represented
by figure 20.7–2, which shows a BJT version of the class AB amplifier.

 

 



 
 








Figure 20.7–2: Diode–biased class AB configuration using BJTs.

The current source, Ibias, must provide sufficient base drive to meet the demands of the output transistors, i.e.,
I L(max)
I bias  I BN(max) 
( F  1)

In order for effective class AB operation, the offset bias VBB must be relatively fixed. Since the offset bias corre-
sponds to a state in which both transistor junctions are held at forward bias, the necessary VBB for class AB using
BJT drivers may be straightforwardly achieved by stacking a pair of diodes, maintained at forward bias, across the
input. We usually call this biasing scheme a ”diode–bias”.

It is important that the diodes be thermally linked to the drive transistors QN and QP, or we will run into a destructive
situation called thermal runaway. Thermal runaway occurs when we have a fixed bias across a junction. The cur-
rent will approximately double for every 10 oC increase in temperature when VJunction is fixed. In the circuit, the
situation is regenerative, since an increase in junction current produces an increase in temperature, which then pro-
duces an increase in junction current. Although this catastrophic condition can be created for any circuit in which
junction biases are externally set, it is a little more dramatic in power BJT transistors, since high levels of current
and heat will be generated (just before burnout) if the junction bias does not compensate. When the bias VBB is set
by thermally–linked junctions, such as indicated by figure 20.7–2, it will automatically compensate, decreasing by
( V = –2 mV/ oC) as the biasing diodes are heated up.

The offset bias VBB is on the order of 2  0.6 V. Fixed offset give us a straightforward relationship between emitter
current flow in the two drive transistors, since VBB = VBEN + VBEP. Therefore, taking inverses of the junction char-
acteristics I = Is e V / VT , we get
V BB  2  V T ln(I Q I S)  V T ln(I EN I S)  V T ln(I EP I S)

where Is = reverse saturation current of the output transistors, assumed to be matched. VT = kT /q = thermal voltage.
Therefore,
I 2Q  I ENI EP (20.7–1)
or we see that the load currents, IEN and IEP, in the two drive transistors are mutual inverses of each other.

219
 This scheme will work fine in most repects, but it has a slight problem which we can see when we assess the current
needed for biasing. In this case it is convenient to illustrate the problem by an example, given by example 20.7–1.

**********************************************************************************
EXAMPLE 20.7–1: A class AB amplifier configuration with biasing diodes 1/5 the size of the drive
transistor, is to be used to apply 8W to a RL = 4 load. Matched, complementary BJT drivers, with F = 50

are available. Determine Ibias and IQ , assuming that the current ID in the diodes is not allowed to vary by
more than a factor of 10. For simplicity, assume that IB (min) is negligible.

 

SOLUTION: Since V S 
2P L 
RL 
2 
8 
4 
8V then
I L(max) (8 4) 

I BN(max) 39.2 mA


( F 1)


51 
 

and, given the specification that IDmax  10 IDmin , and assuming IBN (min)

0.0, then
I bias 
I Dmax 
0.0 
10 
I Dmin 
I Dmin 
39.2 mA

Note that IDmax is also the approximate current that will flow through the diodes under quiescent (VI = 0.0)
conditions. Combining these two conditions, we get
I Dmin 
4.36mA I bias 
I Dmax 
43.6mA

Since the diodes are 1/5 the size of the drive transistors, and they have the same junction bias, then
IQ 
5 
I Dmax 
0.218 A

This level of IQ corresponds to a power consumption PQ = 2 VS IQ = 3.48 W at quiescent conditions.  

The power represents an additional dissipation term which must be included in the total PD .
**********************************************************************************

The example shows that extra expenditure of power, PQ is necessary for correction of crossover distortion. If the
power budget can accommodate this extra overhead then the simple diode bias is an adequate design option. We
might note that we can reduce the quiescent current IQ required if the base–bias diodes are more nearly the same
size as the output drivers, e.g. a size ratio of 1/3 instead of 1/5. But we do so at the expense of a more bulky circuit.

But if we examine the analytical process represented by example 20.7–1, we note that the F of the transistors is a

key factor in defining the quiescent overhead of the class AB circuit. If we should use drive transistors with a large

F, then the current levels for the base–bias network are considerably smaller. Since the quiescent current IQ is a
multiple of these current levels, then it would consequently be much smaller. For example, had we used transistors
with a F of 200 in example 20.7–1, then the quiescent current would be IQ = .055 A, and the power dissipated at

quiescent conditions would be PQ = 0.884 W.

Unfortunately, power BJTs, particularly the high–voltage types, are not usually able to have a large F due to larger

base thicknesses and extra layers (drift–regions). They commonly have an unimpressive forward current gain,
perhaps as low as F = 40. Weakening of current gain factor F is even more pronounced with the PNP power BJT

transistor, since carrier mobility is about a factor of 2.5 lower for holes than it is for electrons.

However, have no cause to worry. We can take advantage of a construct of linked transistors, the Darlington pair, as
represented by figure 20.7–3. As seen by the figure it consists of a pair of transistors Q1 and Q2 such the the base of
Q2 is supplied entirely by Q1. The Darlington pair has current gain

F 
(

1 
1)(

2 
1)
1 

1 2



1 

2 (20.7–2)

220
which can be on the order of F = 400 to 10,000, even for relatively weak transistors. These are usually incorpo-
rated in a single package and are sometimes called super–beta transistors. Their improved current gain is mildly
offset by the fact that they also have an equivalent VCE (sat) = VBE1 + VCE2 (sat) which will be on the order of 1.0V
(high–power, high–voltage transistors may have VCE (sat) = 5V). The Darlington pair will also require an input
offset biasing of VBE1 + VBE2 , which we expect to be on the order of 1.2 V.






 
    

Figure 20.7–3: The Darlington pair

When we use the class AB Darlington configuration, and even when we don’t, it is often convenient to use another
offset biasing scheme, the VBE multiplier circuit. This circuit is just a resistance ladder, made up of resistances R1 ,
R2 and transistor Q5, as shown by figure 20.7–4. This circuit uses the junction VBE5 of the bias transistor Q5 as a
voltage reference, and hangs it onto resistance ladder R1 and R2 to get necessary VBB bias. Transistor Q5 should be
in good thermal contact with the output drivers in order to assure good temperature compensation. A class AB
Darlington with VBE multiplier is shown by figure 20.7–5a.

!#"$ %'&

 +
 V BB +
R1 , R2
V BE5
R2
  –

(*)

Figure 20.7–4: The VBE multiplier

A modification of the class AB Darlington configuration, usually applied to the PNP driver, and known either as the
compound pnp or the Sziklai configuration, is shown by figure 20.7–5b. Since the principal pull–down transistor,
Q2, is of type npn, the compound–pnp driver will usually have a better forward current gain than the PNP Darling-
ton. It does represent a slight compromise in symmetry, since the output resistance is higher for the compound–pnp
than it would be for the pnp Darlington. This option may make the output slightly asymmetric, depending on size of
the load, RL . A SPICE distortion problem in the homework invites an assessment of these circuit options.

221
  

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0214365/7)14898;:=<?>@1A97 BDCFE+GIHFC 0IJK365/7L14898;:M<ONQPRBDST7)1B

Figure 20.7–5: Class AB Darlington configurations.

Analysis of the VBE multiplier is not much different from the process that we used in example 20.7–1, except that
we now need to identify the appropriate value of VBB in order to find the correct values for R1 and R2 . If we have
vanilla BJT form of the class AB output drivers, like that shown by figure 20.7–2, then VBB _ 1.2V. The analysis
process is illustrated by example 20.7–1. To good approximation, we can define values of R1 and R2 from VBB by
using
R1 a R2
V BB ` V BE5 (20.7–2)
R2

provided we can first identify the quiescent value of VBE5 and the current, IR , through the resistance ladder. Equa-
tion (20.7–2) assumes that Q5 has a large b F, for which its base current should be negligible. One of the homework
exercises calls for a test on the effect of b F on the VBE multiplier.

**********************************************************************************
EXAMPLE 20.7–2: The L59U cricket laser robot requires a linear amplifer for beam steering. At maxi-
mum (sinusoidal) modulation signal, a load power of PL = 32W must be applied to the focus coil, which
has an equivalent load resistance of RL = 4 c . Design a class AB Darlington using transistors all of which
have b F = 40. For convenience, we will choose IR = 1 mA and make specification that IC5 varies by no
more than a factor of 5. For typical power transistors we assume reverse saturation current Is1 = Is2 =
10–11 A and that Q3 and Q4 are 1/10 the size of Q1 and Q2, respectively, and Q5 is 1/50 the size of Q1. Find
the values of IL (max), VBB , and quiescent current IQ . Determine Ibias , R1 and R2 as needed for completion
of the design of the VBE multiplier.
f g
SOLUTION: The output voltage level must be V S d 2P L e RL d 2 e 32 e 4 d 16V . There-
fore the maximum load current is
IL d V S h R L d 16 h 4 d 4 A

Since the Darlington pair has equivalent b F of 40 e 40 + 40 + 40 = 1680 , then IB (max) is:
I B(max) d I L h 1681 d 2.38 mA

222


  
For minimum IC5 Imin , and assuming that IB 0 when in the quiescent state, then

  
I bias I C5(min) IR 2.38

I bias 5I min IR 0

 
Solving these two equations simultaneously, and using IR = 1 mA, as specified, gives
I min 0.595mA I bias 3.98mA

At quiescent, IC5 = IC5 (max) = 5 IC5 (min) = 2.975 mA

 
and therefore the quiescent current IQ through the power transistors is
IQ 50  I C5(max)
150 mA 0.15 A

since Q5 = 1/50 the size of Q1 .

 
     
11
Then V BE1 V BE2 V T ln(0.15 10 ) 0.607 V

and V BE3  V BE4  V T ln

  
0.15 ( 1 1)
0.570 V

1 10 10 11
since Q2 = 1/10 Q1 . We also have assumed T 300 K, so that VT = .0259 V.


  
The bias voltage VBB needed from the VBE multiplier is then
V BB
k 1
4
V BEk
 2 (V BE1 V BE2) 2.35V


    
and the voltage VBE5 provided by the reference transistor is
V T ln 2.975 10 3
V BE5 11
0.607 V
1 50 10

   
Using these values, we can determine the VBE multiplier ladder R1 and R2 , as follows:
R2
V BE5
IR
0.607 1.0 0.607 k
R1  V BB  IR
V BE5  1.743k
Note that the biases VBE1 , VBE2 , ..., VBE5 are all about 0.6V. Therefore it is not unreasonable, as an
approximation, to assume that (for quiescent operation), junction biases are a nominal 0.6 V. We may let
these values of VBE approximately define the VBE multiplier, given determination of the necessary IR,
then fine–tune the design by means of SPICE.
**********************************************************************************

223
20.8 OTHER AMPLIFIER CONSIDERATIONS

Instantaneous Power Dissipation

As emphasized, we always should design conservatively. So far we have taken for granted that the thermal time
constants are much much longer than the time constants of the signal and have determined PD based on time aver-
ages. The design reference table, table 20.6–1, is based on this assumption. However, nothing prohibits the drive
levels of current and voltage to have an instantaneous level of power consumption that exceeds the PD (max) of the
power dissipation hyperbolas. The time averaging process may be a very bad call if the the signal time constant is
very low. For example, a linear power amplifier intended to drive a servo motor control may have operation stop for
long periods of time at point A, and PD is then defined in terms of the ”long” instant. In such an application, the
transistor dissipation must be analyzed in terms of a worst–case instantaneous power dissipation scenario. For a
linear load line, as is represented by simple load resistance RL , the maximum instantaneous dissipation occurs at the
center of the load line, for which
VS
VS V 2S
PD 0.5P L
2R L 2 4R L

where we are assuming maximum (sinusoidal) output power PL = 0.5 VS 2/RL .



'

()
& VS


VS
2 VS


 



 !"#!%$

Figure 20.8–1: Load–line dissipation hyperbola for class AB configuration.

Power gain

It is essential that the power amplifier have a high intrinsic power gain. In most cases this represents a need for high
current gain, since the output drivers are of the form of either emitter–follower or source–follower circuits. There-
fore it is necessary that the power amplifier have a high input impedance. This requirement is no problem for the
FET amplifiers, assuming that we don’t go too high in frequency. It presents a little greater problem to BJT drivers,
since the input impedance depends on * F. Usually the ”super–beta” transistors, as represented by the Darlington
pair are sufficient to handle this requirement. Note that the input impedance of the emitter–follower circuit is
approximately
R in (+ F , 1)R L

For very high power, high–voltage transistors, even the Darlington configuration has some limitations, particularly
for PNP transistors for which * F may be as low as 5 to 10.

224
Inductive loads

Inductive loads such as motor circuits sometimes produce large voltage transients at the output node of the transis-
tor when output current changes too rapidly through the inductance. The effect of this induced emf is the induc-
tance’s attempt to keep the current flowing as represented by
V L dI (20.8–1)
dT

This induced emf can easily exceed the inverse breakdown voltage of the power transistor, usually with catastroph-
ic consequences. For this reason power amplifiers with inductive loads should be bridged by clamping diodes or
snubbers, as represented by figure 20.0–2. During normal operation these diodes are reverse–biased. During over-
voltages, they forward bias and allow the induced emf to harmlessly discharge onto the power rails.



    

 
 "!



 




Figure 20.8–2: Use of protective ’snubber’ diodes with an inductive load.

Short–circuit protection and fold–over current limiting

An accidental short–circuit to ground or an overload at the output, both of which are not uncommon, represents a
potentially disastrous situation. Assuming that the power supply has a comfortable margin of current that it can
provide, the power amplifier, in its ignorance, will attempt to let its drive transistors ’handle it’. The drive transis-
tors will comply, but only for a short interval before final expiration. To prevent these problems, short–circuit
protection is usually necessary. The circuit is shown by figure 20.8–3.

225
  

  

 



  




 
Figure 20.8–3: Short–circuit protection for class AB amplifier.

In figure 20.8–3, the transistors Q3 and Q4 are normally off for low current load, IL . They are turned on by sufficient
current through R3 and R4 to produce
I LR 3  0.5 V (20.8–2)

where we assume that 0.5 V is the approximate threshold for Q3 or Q4. When Q3 turns on, it steals base drive from
Q1, thereby limiting the collector current. Since the voltage drop 0.5V is relatively small compared to the output
drive, R3 and R4 will have negligible effect on the output drive. Because Q3 is not across the power rails, the power
it must dissipate is negligible. It is a base–drive shunt device, not some type of sacrificial transistor.

A somewhat similar problem is the possibility of the output load being positioned so that an accidental short or low
impedance path to one of the voltage rails is possible. Naturally, this situation will have effects which are equally as
disastrous as a short to ground. We can see from the plot given by figure 20.8–4(a) showing the dissipation hyper-
bolas (for the class AB) that one of the drive transistors would be well into catastrophic overload should VO be
shorted to +VS or –VS . Setting lower current short–circuit limits is not a good solution since this would seriously
restrict the maximum drive capability of the amplifier.

226
 

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Figure 20.8–4: Foldover protection circuit for class AB amplifier.

Figure 20.8–4(b) shows a modification of the circuit called a foldover circuit which gives an effective short–circuit
protection through the extra resistance ladder formed by R1 and R2 . When we use this arrangement
R2
V B3 u (V L v I LR 3)
R1 v R2

Since the voltage at VE3 = VL , then the voltage across the base–emitter junction of Q3 is then
w R1 R 2R 3
V BE3 u V B3 w V E3 u I
R1 v R2 v R1 v R2 L

If we assume a cut–in value VBE3 = 0.5V then

R1 R1 v R2
IL u V v 0.5
R 2R 3 L R 2R 3

Note that this is a current–voltage line which varies with respect to VO , and can be used to limit the current without
crossing over the PD hyperbola, as represented by figure 20.8–4(c). Therefore we have gained a wider range of
overload protection with minimum compromise of the load–handling capability of the circuit.

227
B20.9 POWER OPAMPS

At a higher level of abstraction and simplicity, we may take advantage of a technology and packaging shortcut. As a
consequence of advances in the semiconductor industry, amplifier circuits of moderate power need not be consid-
ered in terms of discrete transistors, but in terms of the integrated circuit option, as power opamps. The majority of
power opamps are constructed with moderate–voltage power transistors and therefore do not encounter the diffi-
culties of integrating high–voltage processing technology with lower–voltage technologies. Power opamps will
have such features such as short–circuit protection, current boosters, etc, integrated into the IC package. They are
optimized for class AB operation with minimum quiescent power budget, so that the circuit closely mimics ideal
class B operation.

Therefore with designs for which power opamps are included, we assume ideal class B characteristics, for which
the maximum power dissipated in the opamp, PD (max), is:

2
2
V 2S
1 2 V 2 
P D(max) S 0.405 P L(max) (20.9–1)
2R L 2R L

where PL (max) = VS 2/2RL is the maximum power that can be delivered to the load. We might note that PD (max) is
twice the power dissipation of a single drive transistor, consistent with that power dissipated by the (complementa-
ry) pair of drive transistors that are buried in the power opamp integrated circuit.

We see that the basic issues that we must identify for given power level PL delivered to a load are therefore:

(1) VS (min)
(2) the thermally derated limit PD (max)

For loads requiring greater levels of power than a single opamp will deliver, power opamps may be coupled in
parallel. Figure 20.9–1 shows two common options. It is necessary in these arrangements that a small equalization
resistance, on the order of 0.1  , be placed between each follower output node and the load to handle unequal off-
sets in the paralleled opamps.

 

 




  
    
  
  


 



 "!#%$'&)()+*,(+-"-/.0 1*23%1!546$+7 89&24;:<.;0

4=&>@?A&B

Figure 20.9–1: Circuits configurations using stacked power opamps.

228
Consider the following example:

**********************************************************************************
EXAMPLE 20.9–1: PL = 120W ( 1/5 Hp) of power is needed to drive the Halpin electromagnetic grip

used in the forearm of the markII cyborg. Equivalent load resistance of the artificial muscle is RL = 4 . A
power stage with good linearity and frequency response is needed in order to achieve the necessary dexter-
ity. Power opamps having ratings of 100W and thermal limit TJmax = 200oC are available. Heatsink
grease such that contact resistance CS = 0.2oC/W is available. Analyze for possible designs by (a) deter- 

mining minimum VS necessary and minimum heatsink resistance, assuming we desire to keep junction
temperature TJ 180oC to prolong device lifetime. Also find the case temperature TC . (b)If the system


can only accommodate a heatsink of SA = 5oC/W, what is the minimum number of opamps needed and 

their case temperature?

SOLUTION: (a) If we drive the 120 W load at maximum efficiency, then




VS 2 RL PL 2 4 120 31 V 
 


 

o
Assuming that the transistor is rated for 100 W at case temperature 25 C then
T Jmax T A 200 25
JC 1.75 oC W 

P Dmax 100


  

A conservative estimate of the power that the power opamp will need to dissipate is:

PD 0.405 P L 48.6 W 


for which we find that we need a heatsink of thermal resistance

SA 
(T J 
T A) P D


( 

JC

CS ) 
(180 
25) 48.6


(1.75

0.2) 
1.24 oC W

It is difficult to get a heatsink with such low thermal resistance. Case temperature is given by

TC 
TJ 


JC  PD 
180 
48.6  1.75 
94.9 oC

(b) Assuming heatsink resistance 

SA = 5oC/W, then the maximum power that can be dissipated per op-
amp, assuming TJ = 180 oC, is

PD (T J T A) ( JC




CS

SA ) 
(180 
25) (1.75

0.2

5) 
22.3 oC W

for which we will need

N OA 48.6 22.3 2.18 opamps 

Since opamps are not allocated in fractional quantities, we will need three opamps: NOA = 3.

The case temperature will then be

TC T A ( CS SA) PD 
25 (0.2

 

5)  48.6 3


109.2 oC
and the junction temperature will be: TJ = 137.6 oC

**********************************************************************************

Power opamps provide us other options for delivering power to a load. One of these is the power bridge configura-
tion, which makes use of a unity–gain follower and a unity–gain inverter to deliver a linear output of amplitude 2 

VS , and load power

(2V S) 2 2V 2S
PL (20.9–2)


2R L 

RL

229
 





= 


>

  
  



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.0/2143 5 67. $ #. 80,0/ :9<;

Figure 20.9–2: The power bridge: (a) the opamp pair (b) output transistor operation.

Figure 20.9–2(b) shows how the output transistors for the two opamps alternately conduct in the bridge configura-
tion. For maximum output power the peak current is approximately
V
IL ? 2 S (20.9–3)
RL

and the average current is

1 VO
I AV ? 2 @ A RL (20.9–4)

since each power rail draws current for both half cycles. The supply power will then be

4 V SV O
PS ? 2V SI AV ? A R L (20.9–5)

If we analyze the opamps to determine the maximum power that will be dissipated in each opamp,
B 2
1 A 4 V SV O 1 VO
P OA ? 2 RL C 2 RL D
(20.9–6)

Taking derivatives, we find that POA is a maximum when

? A VS
VO 4 (20.9–7)

Substituting equation (20.9–7) into equation (20.9–6) gives maximum power dissipated in each opamp of
B
2V 2S 2V 2
P OA(max) ?
1
2 A 42 @ RL D ? 0.203 R L ? 0.203P L(max)
S
(20.9–8)

We see that each opamp only has to dissipate half as much power as was required for the follower circuit. Of course
this should be no surprise, since now we are using two opamps instead of one, and we expect the dissipated power
PD to be equally distributed between the two packages. The advantage to the bridge configuration is that it only
needs half as much supply voltage VS as does the follower circuit, since it is a push–pull driver.

230
Let us reconsider example 20.9–1(a), but using a power bridge.

**********************************************************************************
EXAMPLE 20.9–2: For PL = 120 W, we find, using equation (20.9–2)


VS PL RL 2 15.5V

The maximum power that we expect to be dissipated in each opamp is then

P D(ea) 0.203 P L 24.3 W

for which we find that we need a heatsink of thermal resistance



4.42 oC W
 

(180 25) 24.3

SA   (1.75  0.2)
Case temperature is given by 

TC TJ PD 180 24.3 1.75 137.4 oC

JC 

The size of the heatsink, in this case, is not out of line. Note that the results are somewhat similar to exam-
ple 20.9.1(b). These results are not unexpected since we are making use of two opamps (as a power
bridge).
**********************************************************************************

We are also allowed to stack opamps in the power bridge configuration, if so desired.

20.10 CLASS D AMPLIFIERS

It might be interesting to note that the class B amplifier would have an efficiency approaching 100% if it amplified a
full voltage square–wave rather than a sinusoidal wave. This greater efficiency results because high current is
passed by a transistor in its most conductive state, i.e. I = large when VDS or VCE 0, and high voltage VCE or VDS


occurs when the transistor is in its least conductive state, for which I = 0. Since PD dissipated in the transistors is a
product of the current voltage, then PD is always small, since either the current is nearly zero at high voltage, and

voltage is small at high current. The class D amplifier is just a modification of this principle, chopping the signal
into square–wave pulses, as a high–frequency switch–mode that alternately connects load RL to the positive and
negative supplies. The class D amplifier has an efficiency approaching 100%.

But in order for the class D amplifier to function as a signal amplifier, the input must be of a pulse–width–modu-
lated (PWM) form, in order for the switch–mode process to work. The output is a time averaged result, needed in
order to define both signal profile and amplitudes. This requires that the class D amplifier include a pulse–width
modulator on the front end, and a filter circuit on the output. The switching frequency must be considerably higher
than the signal frequency in order to avoid aggravations such as distortion, aliasing, and others associated with
pulse–modulation schemes. Usually, a CMOS type of output circuit is used, as represented by figure 20.10–1(a), in
order to achieve the switching speed necessary.

231
 


   %&"'$

 !#"#$ 




 

Figure 20.10–1: The class D amplifier using CMOS output drive

The PWM system uses a high–speed comparator to generate the switch–level input, comparing signal input VI (t) to
a sawtooth with amplitude VP ( VI (max) running at switching frequency fs . The output of the comparator VA must
be of amplitude which is at least twice that sufficient to switch the drive transistors M1 and M2 ”on” and ”off”. A
representative modulator design is shown by figure 20.10–2. Note that the modulator is switched by a pulse train of
frequency fs , with switch Q1 discharging the capacitance C, and current source Io linearly charging the capacitance.
The amplitude VP of the sawtooth is
IO
VP ) (20.10–1)
f sC

/

0 
c
213
- .
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 /
4 56487:9;=<=>@?#AB? I E 5J;CKMLNKM E L
VPWTX@YZ\[.]BZN^B_`aXGb
?&KPO E:E RQS9TAU7HA.LNKM E L

Figure 20.10–2: Modulating circuit for front–end of class D amplifier.

232
 ('  *)+,-!#%./"102 345./

 
 

T > 1
fS

76  98;:<)="!,%$,!,
   "!#%$&!#


 

Assuming that a CMOS output drive is used similar to that of figure 20.10–1, the CMOS input node will be driven
by an input PWM pulse VI = VA /2 ? VM . This corresponds to input VGS = ? VM . to each transistor, since zero
signal (corresponding to VI = VA /2 input corresponds to gate voltage for each transistor being at the voltage rails.
The MOSFETs act as switched resistances, which in the ”on” state, are of the (usual) RDS magnitude:
1
R ON @ 2K(V M A V TH) (20.10–2)

For sinusoidal input, the power delivered to the load is time–averaged over the PWM output voltage amplitude VL
= RL / ( RL + RON ) B VS , so that
C 2
1 V OR L
PL @ 2 R L D R ON) E
(20.10–3)

where Vo is the time–averaged amplitude of the sinusoidal signal. The PWM output current has amplitude IL =
VL /RL = VS /( RL + RON ), which gives power drawn from the power supply of

1 I 2 (R 1 V 2O
PS @GF I 2L H (R L D R ON) @ 2 O L D R ON) @ 2 (R L D R ON)
(20.10–4)

Therefore the efficiency of the amplifier isI

PL RL
@ PS @ (R L D R ON) (20.10–5)

This equation, along with 20.10–2, also defines the lower limit of the input amplitude VM . Example 20.10–1 illus-
trate this analysis.

**********************************************************************************
EXAMPLE 20.10–1: A class D amplifier of the form shown by figure 20.10–1 uses a complementary,
matched pair of MOSFETs, with K = 0.4 A/V2 and | VTH | = 3.2 V. It is used to provide a maximum of

233
 60~W of power to a RL = 5 load. Determine power supply requirements VS and IS , and minimum input
drive level VM for operation at 80% efficiency.

 2P R  2 
SOLUTION: The maximum output voltage level Vo = VS is given by
VS

L L 60  5
24.5 V

and IS = VS / RL = 4.9 ~A

For efficiency of 80%, we have, from equation (20.10–5)

 
 5


(1 ) 0.2
R ON RL 1.25
0.8
From equation (20.10–2) we get
VM
V TH (2K 
1
R ON)
3.2 (2 
1
0.4  1.25)
4.2 V

**********************************************************************************

20.11 INTRODUCTION TO CONVERTERS

Converters are probably the most common form of power electronics. They take the power provided by a source
and convert it into the voltage and current appropriate to a given load. Converters can be as simple as a big fat
transformer, if all that is necessary is an AC–AC voltage conversion. But if we need to convert frequency as well as
amplitude, such as is required by a DC–to–AC converter, then a transformer is not enough. This little conversion
wrinkle is where transistor power electronics reigns supreme.

The most common converter is the AC–to–DC ”power supply”. It gets the name because it converts the commonly
available 110 VAC or 400 VAC to a fixed ”battery–level” VDC, at whatever current requirement is demanded by
the load. This type of converter is usually developed in connection with peak detectors and diode rectifier circuits,
and we can converse eloquently about half–wave and full–wave rectifiers, etc. that follow this approach. But this
technique has been largely supplanted by its more versatile cousin, the switching power supply, in which energy
conversion is achieved by means of high–speed switching power transistors. Switching power supplies can convert
from DC–to–AC, AC–to–DC, DC–to–DC, AC–to–AC of different frequencies, etc. Since the switching technique
is simple and straightforward, and offers advantages in adaptability, size, and efficiency, it is rapidly taking the lead
over the older linear technologies.

The generic form of the switching converter is DC to DC, transforming (quasi–steady) source level ( I1 ,V1 ) to
(quasi–steady) load level ( I2 , V2 ). Ideally, it is lossless, and therefore
I 1V 1
I 2V 2

DC–AC and AC–DC converters are just time–varied versions of the DC–DC converter.

The basic converter topology is represented by figure 20.11–1. In its most basic form it consists of a series element
and a shunt element. For the direct converter these are switches. Note that, for proper operation, the switches
MUST be complementary.

234
    
 

 

   

  
 ! 

"$#%
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(a) Basic topology (b) Series and shunt switches

Figure 20.11–1(a) and (b): Basic topology for a 12V – 9V direct converter

"
#+

.


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-,

(
' 3'
4 6537 '

"$#/

 
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(
"$#%

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(

Figure 20.11–1(c): (I,V) waveforms for the 12V – 9V converter

As indicated by the figure, the duty cycle D of SW1 defines voltage and current levels. D is defined as the fraction of
the cycle for which the switch is closed. Note that for the converter represented by figure 20.11–1, switch #1 has a
duty cycle D = 0.75. Switch #2 will therefore have complementary duty cycle (1 – D) = 0.25. Time averages for
these idealized waveforms give:

V 2 8:9 V SW2(t) ; 8 DV 1 (20.11–1a)

I 1 8<9 I SW1(t) ; 8 DI 2 (20.11–1b)

where = >? indicates time averaging. The ’roughness’ of the waveforms may readily be smoothed by use of capaci-
tances and inductances. Note that equation (20–11–1) reflects the behavior I1 V1 = I2 V2 , which assumes that we
have an approximately lossless converter.

235
The switching is usually done at a relatively high frequency so that energy storage elements of modest sizes can be
used to smooth out the waveforms. Capacitances are used to store voltage (in the form Q/C), and smooth out the
voltage waveform. Inductances are used to store current, and smooth out the current waveform. Effects of these
components in the circuit are realized by the definitions:

dV " 1 Idt (20.11–2a)

C
dI " 1 Vdt (20.11–2b)
L
The larger the value of C, and of L, the smaller the ”ripple”.

The second equation is also useful in that it shows that an emf (voltage) will be generated across the inductance
when the current changes:

# V " VL " # L dI (20.11–3)

dt
This effect is represented by figure 20.11–2. Note that the opening of a switch, for which $ I/$ t can be large, may
generate an emf of magnitude that can easily breakover the switch opening and create a massive arc when the switch
is in series with a large inductance that is carrying a significant DC current. In the early part of the century, when
many unwary experimenters would hook up a DC motor to a simple knife switch, a panicky yank on the switch to
shut off the motor would create an enormous, dangerous arc, usually sufficient to melt parts of the switch. In mod-
ern circuits, this effect merely annihilates the switching transistor as the overvoltage surges well beyond junction
breakdown. For this reason, many circuits containing an inductance add a ”snubber” to shunt destructive overvol-
tage spikes and arcs. Snubbers are even included in digital integrated circuits, since at high switching speeds, the
small inductances due to long interconnects may be sufficient to cause large overvoltages.

 
     


  

! !




Figure 20.11–2: Induced voltages in an inductance due to current interruption.

This effect is actually of advantage in converter circuits, because the opening of one switch will induce sufficient
reactive voltage to ’turn–on’ another switch. This action is illustrated by figure 20.11–3.

 
 
%
  

! ! !


Figure 20.11–3: Inductive complementary switching using a diode.

As indicated by the figure, the second switch is typically a diode, driven into forward bias by the emf induced across
an inductance. In combination with a controlled switch, which is usually a transistor, the diode will therefore serve
as the complementary switch that we need for efficient converter operation.

236
A complete converter circuit might then be represented by figure 20.11–4, which represents the topology which we
usually call a direct converter.


-.
01 2

 

  
-/





Figure 20.11–4: The direct converter topology (down converter).

For this topology, the energy is stored on capacitance C, so that the voltage supplied to the switches is V1 = VC .
The capacitance is discharged by current I2 – I1 flowing out of it during the interval in which SW1 is on, as repre-
sented by figure 20.11–5. The capacitance serves to keep change of voltage V1 to be
* DT
( ( 1 1 (I
V1 ) VC ) (I 2 + I 1)dt , + I 2)DT
C C 1
0

 

 


   "!$#%&
'

Figure 20.11–5: Discharge current

Therefore
( 1 I (1
VC , + D)T (20.11–4)
C 1
since, from equation (20.11–1b), I2 = I1 /D. Equation (20.11–4) represents the decrement of VC during discharge.

The ripple on the voltage across the capacitance will be of the form represented by figure 20.11–5.
57698":

5ACBD5FE

3 ;73 <>=? 4
;@ 3

G 5 A 5 E

5 A BD5 E

Figure 20.11–6. Ripple on V1 = VC .

237
The amplitude of this ripple can also be evaluated by evaluating change in voltage across C when SW1 is open (and
SW2 is closed), for which the capacitance is charged up by a flow of current I1 onto the capacitance. This current
causes an increment of voltage across C of value
 T
  1 1 I (1
V1  VC  I 1dt   D)T (20.11–5)
C C 1
DT

Note that this increment is exactly the same amplitude as the voltage decrement identified by equation (20.11–4).
That should be no surprise, since both represents the amplitude of the ripple Ideally, of course, V1 is a constant, but
since the source VS is non–ideal and has internal resistance R1 , then the ripple is inevitable. If we choose a larger
capacitance, then the ripple will be reduced, as is represented by either equation.

Similarly, a ripple in the current I2 will occur as the inductance discharges through the load while SW2 is closed, i.e.
 T
  1 1 V (1
 IL  I2  V 2dt   D)T
L L 2
DT

 1 V (1
| I L|   D)T (20.11–6)
L 2

The ripples in V1 and I2 will, of course, induce corresponding ripples in I1 and V2 , respectively.

**********************************************************************************
EXAMPLE 20.11–1: The circuit of figure 20.11–7 shows a direct converter which is supplied by a source
of value VS = 26 V and internal resistance R1 = 0.1  . R1 also acts as the resistive component of the RC
input filter. It is assumed that the load is resistive and has value R2 = 0.1  . It is switched by a clock at fs =
50 kHz. (a) What are the converter values I2 , V1 , and I1 . (b) What values of L and C are needed to keep the
current ripple at the output and the voltage ripple of the input to less than 2%?

 

 

   
 
 
   

Figure 20.11–7: 26V–to–5V direct converter operating at fs = 50 kHz

SOLUTION: For V2 = 5V, we have: I2 = V2 /R2 = 5/0.1 = 50 A.

Assuming V1  I1 = V2  I2 = 250 W, and I1 = ( 26 – V1 )/R1 , we get the quadratic:

10V 1(26  V 1)  250

which has solutions V1 = 25 and V1 = 1. Only the solution V1 = 25 V makes sense since the other solution
is less than V2 (= 5V). For this value, we then get:

I1 = (26 – V1 )/R1 = 10 A

The duty cycle D is then: D = V2 / V1 = 0.2

238
 The peak–peak ripple current at the output is, from equation (20.11–5),
 1 (5  (1  0.2))  20 s
I2 .02  50
L
from which we get lower limit on the inductance,
(5  0.8  20 )
L 80 H
0.02  50

Similarly, from equation (20.11–4),

 1 (10
V1 .02  25  (1  0.2))  20 s
C
from which we get capacitance lower limit,
0.8  20 ) (10 
320 F C
0.02  25
**********************************************************************************

If we had evaluated the topology of figure 20.11–4 in general, we would have the quadratic equation
V 1(V B  V 1) P 2R 1

which has solution


 
VB 4P 2R 1 (20.11–8)
V1 1  1 
2 V 2B

where only the positive root is valid, required in order that V1 > V2 .

The direct converter topology represented by figure 20.11–4 is also called the down converter or buck converter,
since it ”bucks” the voltage down to a lower output level. It has a sister that uses the same principles, called the
boost converter or up converter, represented by figure 20.11–8. This converter will take the energy stored in the
inductance during the first part of the duty cycle and ’dump’ it into the right–hand side of the circuit at a higher
voltage, as induced by the inductance. If D’ represents the duty cycle of the controlled switch, which is now the
shunt switch, then current through the diode results only when the controlled switch turns off. The fraction of the
interval for which the controlled switch is off corresponds to duty cycle (1–D’) for which the diode is toggled into a
conducting state. The conduction current through the diode is then
ID I2 (1  D  )I 1 (20.11–9)
Since we require that the circuit be lossless, for which I2 V2 = I1 V1 , then equation (20.11–9) requires that the voltage
at the output must be:
V1
V2 (20.11–10)
(1  D  )




  


  
 

Figure 20.11–8: The ”boost” direct converter topology.

Since (1 – D’) is always less than 1, then V2 > V1 , and the converter ’boosts’ the voltage.

239
The voltage V2 is the voltage that falls across capacitance C. In the buck converter, V1 was the voltage that fell
across acpacitance C. Therefore, if we designate D = the duty cycle of the series switch, which for the boost con-
verter is the same as 1 – D’, then equations (20.11–10) and (20.11–1a) are exactly the same:
VC V

D (20.11–11)
where V is the output voltage (= V2 ) for the down–converter (equation 20.11–1a) and V is the input voltage (= V1 )
for the up–converter (equation (20.11–10).

This is no coincidence, of course. The topologies are exactly the same, except that figure 20.11–8 is a right–to–left
version of figure 20.11–4. The only difference is in the arrangement of the controlled switch and the diode.



  


  
 

Figure 20.11–8: The ”boost” direct converter topology.

Analysis is entirely the same as for the down converter. Ripple equations for voltage across the capacitance and
current through the inductance are the same as (20.11–4) and (20.11–6), except that the subscripts may be inter-
changed if we adhere to subscript 1 as being at the input and subscript 2 as being at the output. Comparison is
represented by example 20.11–2.

**********************************************************************************
EXAMPLE 20.11–2: Warrior–brand combat underwear uses a muscle electrostimulation (ESM) unit
which requires 72V at 1A to operate in the superman mode. If it is supplied by a 9V battery belt capable of
supplying 50A of short–circuit current, determine (a) converter values V1 , and I1 and duty cycle D’ of the
controlled switch, (b) values of L and C needed to keep the voltage ripple at the output and the current
ripple of the input to less than 2%, assuming that the circuit is toggled at switching frequency fs = 50 kHz.

SOLUTION: (a) Assuming that the converter is approximately lossless, then I1 V1 = I2 V2 = 1  72 =

72W.

But V1 = VB – I1 R1 , where VB = battery voltage = 9V. Therefore

(V B  I 1R 1)I 1 P2 72

The internal resistance of the 9V battery belt is R1 = 9V  50A = 0.18  . Therefore

(V B  I 1R 1)I 1 (9  0.18I 1)I 1 72

which has solutions I1 = 10A and 40A. Although both solutions will work, I1 = 10A is the more reason-
able one, and will correspond to:
V1 = 7.2V and D = 1 – I2 /I1 = 0.9

(b) For ripple of less than 2%,  V2 = .02  72 = 1.44 V, for which the capacitance permits voltage ripple:
 V2 1 (1  (0.9  20 s))
1.44

C
where we have used T = 1/fs = 20  s, and that we evaluate ripple in terms of a discharge of the capacitance

240
 through the load, for which SW2 (= diode) is off, and  t = D’T = 0.9  20  s

Solving for capacitance we get: C = 12.5  F

Similarly, the current ripple at the input, which we evaluate for SW1 = ON for which  t = D’T = 0.9  20
 s

 I1 .02 1 (7.2  (0.9  20 s))

 10 0.2
  
L
for which the necessary inductance for 2% ripple is: L = 648  H
**********************************************************************************

Another topology is the indirect converter represented by figure 20.11–9. This topology can be either an ‘up‘ con-
verter or a ‘down’ converter. If we recognize that the time–average of voltage over the inductance must be zero,
then
V 1DT  V 2(1  D)T  0

so that
V2 D
V1 
(1  D) (20.11–12)

where D is the duty cycle of the controlled switch and T is the period of the cycle. Depending on the value of D, V2
can be either greater or less than V1 . We also note that the average capacitance current must be zero, in which case,
I 2DT  I 1(1  D)T

which is the same as

I2 (1  D)
I1 
D (20.11–13)

This result just confirms that the (ideal) net power going into the converter should be zero, assuming that the con-
verter is approximately lossless.





 
 
  


Figure 20.11–9: The indirect (buck–boost) converter topology.

But as is true for the power amplifiers, the converter is not lossless, since some power is dissipated in the switching
components. For the cases represented by figure 20.11–4 and its cousins, these are the transistor(s) and the diode(s).
Although considerably better than mechanical switches, these components will have finite turn–on and turn–off
times during which significant power levels are dissipated in the switches. The principle is represented by figure
20.11–10.

241
 V OFF vSW

V ON
 
tON tOFF

i SW
ION

 
tON tOFF

 
VI
4
V ONION
 
tON tOFF

Figure 20.11–100: Power dissipation in the switches.

Assuming that a switching transition can be represented by an approximately linear behavior over transition inter-
val (0 < t <  tON ), such as is represented by Figure 20.11–8, then:

I(t)  I ON t
 t ON
and

V(t) 
V ON) 1 t
(V OFF V ON
 t ON  
The power dissipated in the switch during transition is the time–average  P(t)  over the switching interval 0 –>
 tON . Taking this average over duty cycle interval T, we get:
P D    t 1 1 ON I ONV OFF
V
(20.11–14)
T  6  3 V OFF 

where  t is the transition time ( =  tON or  tOFF ), and T = 1/fs is the period associated with the switching frequen-
cy. Equation (20.11–14) is the same for either an (ON–OFF) as for the (OFF–ON) transition.

Note that the current ION that passes through either one of the switches is always the current driven by the induc-
tance. The voltage VOFF across a switch is always the voltage provided by the capacitance. These energy–storage
elements define the levels of voltage and current that are switched on/off by the two switching elements to yield
the desired I1 ,V1  I2 , V2 conversion.

The power dissipated when the switch is on is

DT  t ON (20.11–15a)
P D(on)  I ONV ON
T 
for the controlled switch, and

242

(1  D)T  t ON

P D(on) I ONV ON (20.11–15b)
T
for the complementary switch, respectively.

The turn–on and turn–off times are a function of the levels of current and voltage, since these switches must usually
be ”charged up” for minority–carrier injection or the depletion of a drift region. Turn–on and turn–off times tON

and tOFF are on the order of s. These response times represent a fundamental limit to the switching speed fs. Also
the switches themselves will have a finite voltage drop, which, as we noted in section 20.3, may on the order of 1–6
V for a power BJT in the ”ON” state. A power diode will have an ”ON” voltage drop on the order of 0.6V.

For low–voltage converters, as represented by examples 20.11–1, and 20.11–2, common off–the–shelf, large BJTs
and diodes may be used, for which the voltage drop across the devices is less severe.

**********************************************************************************
EXAMPLE 20.11–3: Assume that the controlled switch (= BJT) in example 20.11–1 has VCE (on) = 1.0
V, and that the diode has V(on) = 0.6 V. Assume that tON = 1 s = tOFF , both devices. Determine the 
power dissipated in the switches.

SOLUTION: From equation (20.11–8) the power dissipated during transitions (tON + tOFF ) is:

 


(1 1) 1 1

P D1 (50 25) 1 22.5W
20 6 3 25

P D2  (50  25)  (1 20 1)
16 13  0.6
25  21.8W

The power dissipated during ”ON” times is:

P D1(on) 50  1.0  0.2  20  1 7.5W

20
P D2(on) 50  0.6  0.8  20  1 22.5W
20

Therefore the power dissipated in the switches is

P D1 P D1  P D1(on) 30W

P D2 P D2  P D2(on) 44.3W

This loss represents a total PD of 74.3 W. Since the power applied to the load is on the order of 250W, it is
necessary to increase the duty cycle D slightly to compensate for the loss in the switches. The process is
iterative. If iterations are carried back and forth between examples 20.8.1 and 20.8.2, with the modifica-
tion
I 1V 1 I 2V 2 PD

where PD = PD1 + PD2 , we find that the duty cycle must be slightly increased, to D = 0.203. With this
change, we find also that V1 = 24.62 V
**********************************************************************************

In example 20.11–3, the change in the duty cycle D due to power dissipation in the switches is relatively minor. The
analysis tells us that we need to have a BJT and a diode capable of dissipating approximately 30W and 44.3W,
respectively. Allowing for safety margins and derating via the limitations of the heatsinks, this converter can prob-
ably be constructed using a 75 W power transistor and a 100 W diode.

243