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Abstract— Universal serial bus has supported a wide variety of devices from keyboard, mouse, flash memory device, game peripheral, imaging up to
high speed broad band devices. In addition, user applications demand a higher performance connection between the PC and other increasingly sophisticated
peripherals. USB 3.0 addresses this need by adding even faster transfer rates. It promises a data transfer rate of 4.8 Gbps as compared to its predecessor
interface USB 2.0 which has a raw data rate at 480Mbps. This implementation of synthesizable Media Access (MAC) layer of SuperSpeed USB Memory
Device, with a pipelining concept of processing the packets, is proposed to support high speed transfer rate and high throughputs. Alongside, the use of
efficient handshaking signals complies with optimum performance of the overall device. Master controller has also been implemented to have a command
over MAC Layer and the other layers that will be implemented in a future research. This implementation meets the required specifications and ensures the
data rate of atleast 4.0Gbps [1].
Index Terms— USB 3.0, MAC Layer, Physical Layer Controller, FPGA.
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1 INTRODUCTION
TABLE 1
MAC – LTSSM I/O INTERFACE SIGNALS
4.5 MAC – Link Layer Controller Interface Signals That data is read and send (to PHY chip) by the Read Buffer
The MAC-Link Layer Controller I/O signals are described Interface and Phy Encoder respectively (See Fig. 2). Similar-
in the Table 5. The signals described as inputs are received ly, the data coming from the PHY chip is received by Phy
by MAC and those described as outputs are driven by decoder, and
MAC. DPRF (for Encoder) is used by the Link Layer Con- then written into DPRF (for Decoder) through the Write
troller to write the data in dual port memory. Buffer Interface, which is then used by Link Layer Control-
ler (See Fig. 2).
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TABLE 2
MAC – MASTER CONTROLLER I/O INTERFACE SIGNALS
TABLE 3
MAC INTERNAL SIGNALS
5 MEDIA ACCESS (MAC) LAYER OR PHYSICAL When an encoding process is done by Link Layer con-
troller, it asserts “ll_enc_done” (section III-B), informing
LAYER CONTROLLER master controller that a valid data has been placed in du-
The main object of this research is the implementation of al-port-memory and must be fetched by Phy Encoder.
MAC Layer encoder and decoder that runs in parallel Master controller then asserts “start_en” (Fig. 3) signal to
and hence ensures the concurrent in-out transaction of initialize Phy encoder and waits for being acknowledged
USB 3.0 protocols. by Phy encoder.
Before discussing the developed algorithm of MAC LTSSM controls the power state of PHY chip through
Encoder and Decoder, it is good to have a look at the Phy Encoder. Phy chip remains idle in P1 and P3 power
standard USB 3.0 packet [1] first. It is also portrayed in states [1]. In P2 state, encoder waits for the instruction
Fig. 6. Refer [1] for detailed description of packet sym- from LTSSM either to force Phy Chip to transmit LFPS [1]
bols. or to do receiver detection operation (Fig. 7). When a val-
id data is present in the buffers, LTSSM instructs Phy
Encoder to take Phy chip into P0 state. Encoder starts the
process of fetching data, from buffer, only when a posi-
tive edge of “transmit” is seen asserted.
When LTSSM asserts “transmit” signal, encoder re-
quests the data and waits for the acknowledgment from
Read Buffer Interface. When transaction begins, encoder
obtains the data payload size from the packet size (given
by master controller, in terms of bytes) and puts into the
register, named “data_pld_size”. The purpose of calculat-
ing the data payload size is to find out how many num-
ber of transactions are required to send the complete
packet to Phy chip. Since each transaction can have 4
symbols of transmit data (32-bit bus) [refer 1 for detailed
description], therefore a packet size is divided by 4 to
obtain the correct number of transactions required. Refer-
ring [2], TxDataK bus indicates Control or Data byte in a
current transaction.
The RTL of encoder is efficient enough to locate which
byte is a control byte or data byte in a current transaction.
Fig. 6: Standard USB 3.0 packet with maximum of 1024 data bytes Fig.4 depicts that there are two such transactions (1st and
5.1 MAC Layer Encoder (Phy Encoder) 6th) which have complete control symbols (bytes) in it.
The last transaction should have all control bytes, but it
It is recommended to refer [2] first for PHY Chip encod-
depends on the data payload size. If data payload size is
ing signals, in order to understand Phy Encoding algo-
not a multiple of 4, then there must be an ambiguity
rithm. Algorithmic State Machine Description (ASMD) of
which symbol is a control or a data byte, in 2nd last trans-
PHY Encoder is shown in Fig. 7.
action. Two least significant bits of “data_pld_size” indi-
cates the position of data byte in 2nd last transaction
(Fig.6).
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5.2 MAC Layer Decoder (Phy Decoder) “PowerState” of Phy Decoder is again in a control of LTSSM.
Decoding process is pretty complicated and a challenging Phy Decoder remains idle in P1 & P2 states. In P3, LTSSM
task. It is recommended to refer [2] to grasp the PHY Chip asserts “receiver_DO” (See Fig. 2) signal when it requires “re-
decoding signals. ASMD of Phy Decoder is shown in Fig. 8. ceiver detection” operation to be performed.
Fig. 7: ASMD of Phy Encoder (see Fig. 2 for block level diagram)
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Phy Decoder in-turn asserts “TxDetectRx” signal [2], request- As soon as LTSSM instructs Phy decoder to take PHY Chip
ing PHY chip to begin “receiver detection” operation. This into the power state P0, decoder starts looking for
signal should remain high until “phy_status” signal [2] from “Rx_elec_idle” signal. Phy Decoder informs the LTSSM about
Phy Chip is seen asserted. When the receiver detection opera- LFPS on the basis of “Rx_elec_idle” signal. It then goes into
tion is completed, PHY chip asserts “phy_status” signal [2]. “idle” state until valid data is present at “RxData” bus. When
Phy decoder then deasserts “TxDetectRx”, meanwhile in- the valid data is present, decoder interrogates the “Write
forms LTSSM, the status of receiver through Buffer Interface” (Fig. 2) whether it is ready to accept the in-
“Rx_status_2LTSSM” bus. coming data, and jumps to the “ackldg” (acknowledge) state.
Fig. 8:ASMD of Phy Decoder (see Fig. 2 for block level diagram)
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of USB 3.0. It is designed in such a way that other layers integrated with this layer. The future objective could be
can be easily interfaced with it. complete USB 3.0 memory device whose top level
Link Layer, Protocol Layer and LTSSM will be diagram is shown in Fig. 9.
developed in future as an independent entity and