Objective: A versatile, analytical and hard-working Computer Engineering profes

sional with a practical hands-on approach, seeking an entry-level engineering po

sition to fully utilize my extensive knowledge and excellent abilities in ASIC/F
PGA
Computer Skills:
Programming Languages: VHDL, Verilog, Verilog-A, C language, Assembly
Operating System: Microsoft Windows (95/98/2000/XP/Vista/Win7) and UNIX (Redhat/
Fedora/Ubuntu)
Software: Cadence, NClaunch, SoC Encounter, RTL complier, Modelsim, HSipce, ISE,
Microsoft Office
Education:
Polytechnic Institute of New York University, Brooklyn, NY M.S. Computer Enginee
ring GPA: 3.8/4.0
a Winner of Graduate Center Merit-based Scholarship respectively in 2008 and 200
9
East China Normal University, Shanghai, China B.S. Microelectronics Class R
ank: 5/55
Projects:
Memristor thermal sensor design: Jan ~ May 2010
a Developed a new application of the fourth circuit element, Memristor, combined
with CMOS technology
a Design finalized as 1oC resolution in the range from -55oC to 150oC, with 5.4u
mx3.4um area (TSMC_90nm)
a Created a device model formulizing memristoras thermal property
a Performed full ASIC design flow and wrote Master thesis paper
Network-on-Chip VHDL design: Jan ~ Dec 2009
a Study high performance NoC structure supported by U.S. Army CERDEC
a As key VHDL designer, designed network interface (AMBA), switches and buffer c
ontrol (VoQ) modules
a Reduced latency of 4x4 NoC by 6 clock cycles, improved area/cost efficiency by
30%, handled 3 types of bursts
a Comparison study between 2D-Mesh and Clos-network, following ASIC/FPGA design
flow
Steganography SoC implementation: Jan ~ May 2009
a VLSI chip design carrying novel graphic encryption algorithm, which is verifie
d on software platform
a ASIC system level division and SoC architecture design, in a divide-and-conque
r manner
a Responsible for back-end process and research report writing as a team player
32-bit ALU ASIC implementation: Oct ~ Dec 2008
a Customized standard cells, schematics/layout design, Spice model simulation, D
RC and LVS
a Conducted compact layout manner, saving 50% area, chip is taped out with MOSIS
CMOS 0.25um
a Individually carried out ASIC flow (digital design)
Experiences:
Research Assistant, Polytechnic Institute of NYU, Brooklyn, NY Jan 2009 ~
Aug 2010
a Fulfilled ASIC/FPGA design frontend responsibilities, including source codes w
riting, algorithm verification
a Co-worked with ASIC backend, Schematic/layout design (Cadence Schematic Compos
er and Virtuoso)
a Wrote technical report, debugging and testing, and address presentation in gro
up meetings
a Reviewed papers for conferences, such as ISCAS 2010, ISLPED 2010, VLSI-SoC 201
0, IC-FPT 2010, etc.
Teaching Assistant, Polytechnic Institute of NYU, Brooklyn, NY Sep 2009 ~
May 2010
a Assisted professors during their lectures and lab sessions, prepared course wa
res and paper works
a Supervised the students in lab sessions, and guided seniors and juniors to lea
rn ASIC design flow
a Graded homework, lab reports and examinations, and solved specific problems
a Gave lectures on experiments and demonstrated the procedures on Xilinx