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RW3400

DIGITAL HOME ENTERTAINMENT SYSTEM


SERVICE MANUAL

A GENERAL DESCRIPTION
A.1 DMN8652
The DMN8652 accepts video from broadcast TV and other analog video sources, and compresses and formats the video for storage on DVD in industry-standard recordable formats (DVD-RAM, DVD-RW/R, DVD+RW/R).The DMN8652 highly integrated DVD Recorder Processor can control ATAPI disc loaders and read bitstreams using the various media. The device can decode bitstreams and process navigation data of the various formats. For DVD video recording applications, the DMN8652 supports video compression and decompression in compliance with the MPEG-1, MPEG-2, and DV-25 specifications. It also transcodes between DV25 and MPEG-2. The product supports corresponding audio compression and decompression in compliance with the Dolby Digital CE and MPEG-1 layer 2 specifications. For DVD playback applications, the DMN8652 supports the playback of DVD-Video disks with Dolby Digital 5.1 and DTS audio encoding, DVDAudio disks (MLP), VCD, and SVCD disks. DMN8652 also supports the play back of audio encoded in MP3 and WMA formats, and the display of pictures encoded in JPEG format.

General Features:

A/V Encode/Decode

Multiformat audio and video encode/decode Horizontal: 720, 704, 640, 544, 480, 352 Vertical: NTSC (480i, 480p) and PAL (576i) 240 and 288 (only at 352 horizontal resolution)

Resolutions

Digital Video

Formats Input

NTSC, PAL, ITUR BT.656/601, SMPTE 250M 8 or 10bit digital video from ITUR BT.656 (parallel D1) sources at 27MHz. Simultaneous 8-bit SMTPE 293M (ITU-R BT.1358) progressive video output and ITU-R BT.656 interlaced video output (for HDTV and VCR) of the same content. 16-bit YC b C r data (SMPTE 260M). Baseband composite (M) NTSC or (B,D,G,H,I) PAL analog video.

Output

Analog Video

Output

Separate analog Y/C outputs to support S-video. Separate analog component video RGB or SMPTE YPbPr outputs.

Inputs

Single stream input, supporting common audio formats, including I2S, with four input channels Dual stream outputs, supporting common audio formats, including I2S: Eight output channels on stream 1 Two output channels on stream 2 16 to 32 bits/sample 32, 44.1, 48, and 96 kHz output

Outputs Audio Resolutions Analog Audio Sampling Frequency Digital Audio Sampling Frequency

8 to 192 kHz over IEC958

Serial Parallel I/O USB1.1 Host System Graphics Encryption/decryption Memory Memory Controller Peak Bandwidth Input Voltages System Clock Physical Operating Power Package JTAG

IEEE1394 Link, IDC, SPI, two IR blaster, dual UARTs ATAPI/DVD&HDD Host low speed and full speed interface. A single port is available for down stream hub or device connection. 16/32 bit internal host 2D, 4 to 32bit RGB, OSD, flicker filter, and video scaler, supporting the following color modes: CLUT4, CLUT8, ARGB4444, ARGB 1555, ARGB 0565, ARGB 8888 CPRM, CPPM, CSS, 5C (via 1394), Watermark detection 16-256 Mbytes of SDRAM, SDR or DDR Onchip, 32 bit wide SDRAM interface, 148.5 Mhz. 1.2 Gbytes/s 3.3 V I/O; 1.8 V Core; 2.5 / 3.3 V SDRAM; 3.3 V Isolated Analog 13.5 or 27 MHz 3.4 W @ nominal Vdd , six VDACs enabled in Full Power Mode 388 Pin Ball Grid Array (BGA) IEEE 1149.1 compliance for boundary scan testing and board assembly testing

A.2 DIGITAL VIDEO DECODER


The TVP5146 or L2146 is a high quality, single-chip digital video decoder that digitizes and decodes all popular base-band analog video formats into digital component video. It supports the A/D conversion of component RGB and YPbPr signals, as well as the A/D conversion and decoding of NTSC, PAL and SECAM composite and S-Video into component YCbCr. Input terminals are properly configured to combination of RGB, YPbPr, CVBS, S-Video video inputs. The main blocks of the device include: Robust sync detection for weak and noisy signals as well as VCR Y/C separation by 2D 5-line (5H) adaptive comb or chroma trap filter Fast-switch input for instantaneous switching between CVBS and YCbCr/RGB component video inputs SCART support) Fast-switch input for synchronous switching between digital RGB overlay an any video inputs Four 10-bit, 30-MSPS A/D converters with analog pre-processors (Clamp/AGC) Luminance processor Chrominance processor Component processor Clock/Timing processor and power-down control Software controlled power saving stand-by modes Output formatter I2C host port interface VBI data processor Macrovision copy protection detection circuit (Type 1, 2 and 3) 3.3V tolerant digital I/O ports

A.3 MEMORY
Flash Memory: The system host interface controls access to external 16Mbit flash ROM which is used for RISC code. SDRAM Memory: The DMN8652 processor uses a 32-bit memory interface to access to up to 256 Mbytes of SDRAM. Two 16-bit wide 128Mbits(8Mx16) DDR-SDRAMs are used in this product. The interface can run up to 148.5 MHz, at signal levels of 2.5V and 3.3 V.

A.4 DRIVE INTERFACES The DMN8652 supports the AT Attachment Packet Interface (ATAPI), Integrated Drive Electronics (IDE), and other parallel and serial port interfaces used by many types of DVD loaders and harddiscs. These interfaces meet the specifications of many DVD loader and harddisc manufacturers. A.5 FRONT PANEL
The front panel is based around three interface chips. First of them is VFD and a front panel controller chip. The DMN8652 controls the front panel chip using several control signals, (clock, data, chip select). The infrared remote control signal is received by IR receiver IC an passed directly to the DMN8652 for decoding. Second is USB interface chip and third is MC interface chip. Outputs and Inputs at the RW3400 front panel: Left, Right audio outputs. CVBS-Video. Memory Card Reader. USB1.1

A.6 REAR PANEL


Outputs and Inputs at the RW3400 rear panel: Front Left, Front Right, Rear Left, Rear Right, Center and Subwoofer (active) audio outputs. Composite, S-Video, and SCART outputs. Input SCART Digital Audio Outputs (Optical and Coaxial) 220-240 V 50Hz AC Power input The video signals used to provide CVBS and S-Video are generated by the DMN8652s internal video DAC. Six channel or two channel audio output by the DMN8652 in the form of IDS data streams. The S/PDIF serial stream is also generated by the DMN8652 output by the rear panel. A six channel audio DAC (CS4360) are used for six channel audio output with DMN8652. A two channel audio DAC (CS4340) are used for two channel audio output with DMN8652.

B DESCRIPTIONS OF SYSTEM BLOCKS & DMN8652 PIN DESCRIPTION


B.1 DMN8652 PIN DESCRIPTION Ball No.
A1 A2 A3 A4 A5

Pin Name
CLKI CLKX DAC1_OUT DAC2_OUT DAC3_OUT

Type
Clk. In Out Out Out Out

Module
Misc. Misc. Video DAC Video DAC Video DAC

Description
Clock -- Used with CLKX for crystal input: Used to input LVTTL clock signal if crystal not used. Clock -- Used with CLKI for crystal input; Leave open if external clockapplied to CLKI Analog video DAC output Analog video DAC output Analog video DAC output

A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14

DAC4_OUT DAC5_OUT DAC6_OUT TDI VO_D[0] lvGPIOExt[0] VO_D[3] lvGPIOExt[3] VO_D[7] lvGPIOExt[7] VO_D[9] lvGPIOExt[9] VO_D[13] lvGPIOExt[13] VO_D[14] lvGPIOExt[14] VO_CLK VI_CLK[0] VI_CLK[1] VO2_D[8] VI_E[1] lvGPIOExt[29] 1 1 1 1 1 1 1

Out Out Out In 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O Clk. I/O Clk. In Clk. In 3state I/O 3state I/O In In Out Clk Out Clk Out In Power Power N/A Out Out Power Out Clk. In 3state I/O 1 1 1 1 1 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O

Video DAC Video DAC Video DAC JTAG Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Audio I/O Audio I/O Audio I/O Video I/O Pwr/Gnd Pwr/Gnd Pwr/Gnd Video DAC Video DAC Pwr/Gnd JTAG JTAG Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O

Analog video DAC output Analog video DAC output Analog video DAC output Test Data In Video Output Data Video Output Data Video Output Data Video Output Data Video Output Data Video Output Data Video Output Clock Video input Clock Video input Clock Video I/O Data Video Input Enable Video Input Vertical Sync Video Input Data IEC958 Interface Output Audio Master Input Clock output Audio Master Output Clock output Video Input Data Quiet Xtal Vdd Quiet Xtal Vss Analog Ground Current return path of the video DAC output Current return path of the video DAC output DAC ground Test Data Out Test Clock Video Output Horizontal Sync Video Output Data Video Output Data Video Output Data Video Output Data Video Output Data

VI_VSYNC[0] PEC VI_D[4] AO_IEC958 AI_MCLKO AO_MCLKO VI_D[9] XtalVdd XtalVss Agnd_1 DAC2_OUTB DAC4_OUTB DAC_DVSS_1 TDO TCK VO_HSYNC VO_D[1] lvGPIOExt[1] VO_D[2] lvGPIOExt[2] VO_D[6] lvGPIOExt[6] VO_D[8] lvGPIOExt[8] VO_D[12] lvGPIOExt[12]

B15 B16 B17 B18 B19 B20 B21 B22 B23 B24

VO_E lvGPIOExt[30] VO2_D[0] VO2_D[3] VO2_D[6] VI_D[1] VI_E[0] VI_D[5] VI_D[3] VI_D[2] AI_MCLKI GPIOExt[32] CS[8] AO_MCLKI GPIOExt[33] CS[9] VI_D[7] Vref RefVss Agnd_2 Agnd_3 Agnd_0 DAC_VDD_0 TRST VO_VSYNC RSTO VO_ACTIVE VO_D[4] lvGPIOExt[4] VO_D[5] lvGPIOExt[5] VO_D[10] lvGPIOExt[10] VO_D[11] lvGPIOExt[11] VO_D[15] lvGPIOExt[15] VO2_D[1] VO2_D[4] VO2_D[7] VI_D[0] VI_VSYNC[1] lvGPIOExt[45] GROUND

3state I/O 3state I/O In 3state I/O In 3state I/O In In In In In In Clk In

Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Audio I/O

Video Output Enable Video I/O Data Video I/O Data Video I/O Data Video Input Data Video Input Enable Video Input Data Video Input Data Video Input Data Audio Master Input Clock input

B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21

Clk. In In In Analog ground N/A N/A N/A Power In 3state I/O Out 3state I/O 1 1 1 1 1 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O In 1 3state I/O N/A

Audio I/O Video I/O Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd JTAG Video I/O Misc. Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Video I/O Pwr/Gnd

Audio Master Output Clock input Video Input Data Reference Resistor Reference ground Analog Ground Analog Ground Analog Ground DAC power Test Reset Video Output Vertical Sync Reset Out Video Output Active Video Output Data Video Output Data Video Output Data Video Output Data Video Output Data Video I/O Data Video I/O Data Video I/O Data Video Input Data Video Input Vertical Sync Circuit ground

C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E23 E24 E25 E26 F1

Vdd25_01 GROUND VI_D[8] VI_D[6] AI_FSYNC RefVdd Avdd_2 Avdd_1 Avdd_3 Avdd_0 DAC_VDD_3 DAC_DVDD TMS EPD Reserved, tie to Vdd Vdd_00 Vdd_01 Vdd_02 Vddp_01 Vddp_02 VO2_D[2] VO2_D[5] VO2_D[9] Vddp_03 Vddp_04 Bias_5V00 SDRAM_VREF Vdd25_00 AI__SCLK A2_FSYNC GPIOExt[34] AI_D[0] Dminus_0 Dplus_0 USB_Agnd_0 USB_Avdd_0 A2_SCLK GPIOExt[31] AI_D[1] GPIO[6] AO_FSYNC AI2_D GPIO[7] Dminus_1

N/A N/A In In I/O Analog Power N/A N/A N/A N/A Power Power In Out

Pwr/Gnd Pwr/Gnd Video I/O Video I/O Audio I/O Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd JTAG Misc.

Digital 2.5 V Power Circuit ground Video Input Data Video Input Data Start or end of the next stream 1 input sample or frame Reference Vdd Analog Vdd Analog Vdd Analog Vdd Analog Vdd DAC power DAC Digital Vdd Test Mode Select External Power Down

N/A N/A N/A N/A N/A 3state I/O 3state I/O 3state I/O N/A N/A

Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Video I/O Video I/O Video I/O Pwr/Gnd Pwr/Gnd Pwr/Gnd

Digital 3.3 V Power Digital 3.3 V Power Digital 3.3 V Power Digital 3.3 V Power Digital 3.3 V Power Video I/O Data Video I/O Data Video I/O Data Digital 3.3 V Power Digital 3.3 V Power

In N/A Clk. I/O 3state I/O In 3state I/O 3state I/O N/A N/A Clk. I/O 3state I/O 3state I/O Out 3state I/O 3state I/O

SDRAM Pwr/Gnd Audio I/O Audio I/O Audio I/O Analog Analog Analog Analog Audio I/O Audio I/O Audio I/O Audio I/O Analog

Reference voltage for SSTL Digital 2.5 V Power Serial audio bit clock for audio input stream 1 Start or end of the next stream 2 input and output sample or frame Audio Stream 1 Input Data USB transceiver D port 0 USB transceiver D+ port 0 USB Analog Ground USB Analog Power Serial audio bit clock for audio input and output stream 2 Audio Stream 1 Input Data Start or end of the next stream 1 output sample or frame Audio Stream 2 Input Data USB transceiver D port 1

F2 F3 F4 F23 F24 F25 F26 G1 G2 G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 H23 H24 H25 H26 J1 J2 J3 J4 J23 J24 J25 J26 K1 K2 K3 K4 K23 K24 K25 K26

Dplus_1 USB_Agnd_1 USB_Avdd_1 Vdd_03 AO_SCLK AO2_D[0] AO_D[2] Host PO_0 Host OC_0 Host PO_1 GPIOExt[43] Host OC_1 GPIOExt[44] AO_D[1] AO_D[0] AO_D[3] SDRAM_DQ[25] CLK0_DAC GPIOExt[35] USB_48MHZ GPIOExt[36] 1394_LINK_ON BYPASS_PLL SDRAM_DQ[24] SDRAM_DQ[27] SDRAM_DQ[26] SDRAM_DQS[3] 1394_PHY_DATA[5] 1394_PHY_DATA[4] 1394_PHY_DATA[0] 1394_PHY_CTL[0] SDRAM_DQ[30] SDRAM_DQ[28] SDRAM_DQ[29] SDRAM_DQ[31] 1394_PHY_CLK 1394_PHY_DATA[7] 1394_PHY_DATA[6] Vdd_08 SDRAM_DQM[3] SDRAM_DQ[23] SDRAM_DQ[22] SDRAM_DQ[21]

3state I/O N/A N/A N/A Clk. Out Out Out Out In 3state I/O 3state I/O Out Out Out I/O 3state I/O 3state I/O In In I/O I/O I/O I/O 3state I/O 3state I/O 3state I/O I/O I/O I/O I/O I/O Clk. In 3state I/O 3state I/O N/A Out I/O I/O I/O

Analog Analog Analog Pwr/Gnd Audio I/O Audio I/O Audio I/O Analog Analog Analog Analog Audio I/O Audio I/O Audio I/O SDRAM Misc. Misc. 1394 Misc. SDRAM SDRAM SDRAM SDRAM 1394 1394 1394 1394 SDRAM SDRAM SDRAM SDRAM 1394 1394 1394 Pwr/Gnd SDRAM SDRAM SDRAM SDRAM

USB transceiver D+ port 1 USB Analog Ground USB Analog Power Digital 3.3 V Power Serial audio bit clock for audio output stream 1 Audio Stream 2 Output Data Audio Stream 1 Output Data Power enable for the external USB power management chips Over current status pins from the external USB power management chips Power enable for the external USB power management chips Over current status pins from the external USB power management chips Audio Stream 1 Output Data Audio Stream 1 Output Data Audio Stream 1 Output Data SDRAM Read / Write Data Output of the internal 13.5 MHz crystal oscillator External USB 48 MHz Clock Occurrence of a linkon event Bypasses the PLL used to generate the internal processing clock SDRAM Read / Write Data SDRAM Read / Write Data SDRAM Read / Write Data SDRAM Data Strobe Phylink data bus Phylink data bus Phylink data bus Phylink control bus SDRAM Read / Write Data SDRAM Read / Write Data SDRAM Read / Write Data SDRAM Read / Write Data 49.152 MHz clock supplied by the PHY device Phylink data bus Phylink data bus Digital 3.3 V Power SDRAM Data Mask (Byte Enables) SDRAM Read / Write Data SDRAM Read / Write Data SDRAM Read / Write Data

L1 L2 L3 L4 L11 L12 L13 L14 L15 L16 L23 L24 L25 L26 M1 M2 M3 M4 M11 M12 M13 M14 M15 M16 M23 M24 M25 M26 N1 N2 N3 N4 N11 N12 N13 N14 N15 N16 N23 N24 N25 N26 P1 P2

1394_LPS 1394_LREQ 1394_PHY_CTL[1] 1394_PHY_DATA[1] GROUND GROUND GROUND GROUND GROUND GROUND SDRAM_DQ[20] SDRAM_DQS[2] SDRAM_DQ[19] SDRAM_DQ[18] ATAPI_DATA[8] ATAPI_DATA[7] 1394_PHY_DATA[3] 1394_PHY_DATA[2] GROUND GROUND GROUND GROUND GROUND GROUND Vdd25_02 SDRAM_DQ[17] SDRAM_DQ[16] SDRAM_DQM[2] ATAPI_DATA[9] ATAPI_DATA[6] ATAPI_DATA[5] Vdd_09 GROUND GROUND GROUND GROUND GROUND GROUND SDRAM_CLK[0] Vdd25_03 SDRAM_DQ[15] SDRAM_DQM[1] ATAPI_ADDR[4] ATAPI_DATA[10]

Out Out I/O 3state I/O N/A N/A N/A N/A N/A N/A I/O I/O I/O I/O 3state I/O I/O 3state I/O 3state I/O N/A N/A N/A N/A N/A N/A N/A I/O I/O Out 3state I/O I/O I/O N/A N/A N/A N/A N/A N/A N/A DInff. Out N/A I/O Out Out 3state I/O

1394 1394 1394 1394 Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd SDRAM SDRAM SDRAM SDRAM ATAPI ATAPI 1394 1394 Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd SDRAM SDRAM SDRAM ATAPI ATAPI ATAPI Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd SDRAM Pwr/Gnd SDRAM SDRAM ATAPI ATAPI

Link Power Status Link Request Phylink control bus Phylink data bus Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground SDRAM Read / Write Data SDRAM Data Strobe SDRAM Read / Write Data SDRAM Read / Write Data Bidirectional ATAPI data bus Bidirectional ATAPI data bus Phylink data bus Phylink data bus Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground Digital 2.5 V Power SDRAM Read / Write Data SDRAM Read / Write Data SDRAM Data Mask (Byte Enables) Bidirectional ATAPI data bus Bidirectional ATAPI data bus Bidirectional ATAPI data bus Digital 3.3 V Power Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground SDRAM CLock -- buffered versions of the internal DMN8652 clock Digital 2.5 V Power SDRAM Read / Write Data SDRAM Data Mask (Byte Enables) ATAPI device register address Bidirectional ATAPI data bus

P3 P4 P11 P12 P13 P14 P15 P16 P23 P24 P25 P26 R1 R2 R3 R4 R11 R12 R13 R14 R15 R16 R23 R24 R25 R26 T1 T2 T3 T4 T11 T12 T13 T14 T15 T16 T23 T24 T25 T26 U1 U2

ATAPI_DATA[4] Vddp_08A GROUND GROUND GROUND GROUND GROUND GROUND SDRAM_CLK[0] Vdd25_04 SDRAM_DQ[13] SDRAM_DQ[14] ATAPI_IORDY ATAPI_DATA[3] ATAPI_DATA[11] Vddp_09 GROUND GROUND GROUND GROUND GROUND GROUND SDRAM_CLK[1] Vdd25_05 SDRAM_DQS[1] SDRAM_DQ[12] ATAPI_DATA[2] ATAPI_DATA[12] ATAPI_DIOW Vddp_10 GROUND GROUND GROUND GROUND GROUND GROUND SDRAM_CLK[1] Vdd25_06 SDRAM_DQ[10] SDRAM_DQ[11] ATAPI_DATA[1] ATAPI_DATA[13]

I/O N/A N/A N/A N/A N/A N/A N/A DInff. Out N/A I/O I/O In I/O 3state I/O N/A N/A N/A N/A N/A N/A N/A Diff. Out N/A I/O I/O I/O 3state I/O Out N/A N/A N/A N/A N/A N/A N/A Diff. Out N/A I/O I/O I/O 3state I/O

ATAPI Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd SDRAM Pwr/Gnd SDRAM SDRAM ATAPI ATAPI ATAPI Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd SDRAM Pwr/Gnd SDRAM SDRAM ATAPI ATAPI ATAPI Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd SDRAM Pwr/Gnd SDRAM SDRAM ATAPI ATAPI

Bidirectional ATAPI data bus Digital 3.3 V Power Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground SDRAM CLock -- buffered versions of the internal DMN8652 clock Digital 2.5 V Power SDRAM Read / Write Data SDRAM Read / Write Data ATAPI device IO ready Bidirectional ATAPI data bus Bidirectional ATAPI data bus Digital 3.3 V Power Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground SDRAM CLock -- buffered versions of the internal DMN8652 clock Digital 2.5 V Power SDRAM Data Strobe SDRAM Read / Write Data Bidirectional ATAPI data bus Bidirectional ATAPI data bus ATAPI I/O write request Digital 3.3 V Power Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground Circuit ground SDRAM CLock -- buffered versions of the internal DMN8652 clock Digital 2.5 V Power SDRAM Read / Write Data SDRAM Read / Write Data Bidirectional ATAPI data bus Bidirectional ATAPI data bus

10

U3 U4 U23 U24 U25 U26 V1 V2 V3 V4 V23 V24 V25 V26 W1 W2 W3 W4 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB23 AB24 AB25

ATAPI_DATA[0] ATAPI_ADDR[3] Vdd25_08 SDRAM_DQM[0] SDRAM_DQ[8] SDRAM_DQ[9] ATAPI_DMAACK ATAPI_DATA[14] ATAPI_ADDR[2] ATAPI_DMARQ SDRAM_DQ[0] SDRAM_DQ[4] SDRAM_DQ[6] SDRAM_DQ[7] ATAPI_ADDR[1] ATAPI_INTRQ ATAPI_DIOR ATAPI_DATA[15] SDRAM_CKE SDRAM_DQ[1] SDRAM_DQS[0] SDRAM_DQ[5] ATAPI_RESET ATAPI_ADDR[0] ATAPI2_DATA[0] ATAPI2_DATA[2] SDRAM_A[16] SDRAM_RAS SDRAM_DQ[2] SDRAM_DQ[3] ATAPI2_DATA[1] ATAPI2_DATA[3] ATAPI2_DATA[5] Vdd_14 Vdd_30 SDRAM_A[2] SDRAM_CAS SDRAM_WE ATAPI2_DATA[4] ATAPI2_DATA[6] ATAPI2_DATA[8] ATAPI2_DATA[11] SDRAM_A[1] SDRAM_A[4] SDRAM_A[15] 3 3

I/O Out N/A Out I/O I/O Out 3state I/O Out In I/O I/O I/O I/O Out In Out 3state I/O Out I/O I/O I/O Out Out I/O I/O Out Out I/O I/O I/O I/O I/O N/A N/A Out Out Out I/O I/O 3state I/O 3state I/O Out Out Out

ATAPI ATAPI Pwr/Gnd SDRAM SDRAM SDRAM ATAPI ATAPI ATAPI ATAPI SDRAM SDRAM SDRAM SDRAM ATAPI ATAPI ATAPI ATAPI SDRAM SDRAM SDRAM SDRAM ATAPI ATAPI ATAPI ATAPI SDRAM SDRAM SDRAM SDRAM ATAPI ATAPI ATAPI Pwr/Gnd Pwr/Gnd SDRAM SDRAM SDRAM ATAPI ATAPI ATAPI ATAPI SDRAM SDRAM SDRAM

Bidirectional ATAPI data bus ATAPI device register address Digital 2.5 V Power SDRAM Data Mask (Byte Enables) SDRAM Read / Write Data SDRAM Read / Write Data ATAPI DMA acknowledgement Bidirectional ATAPI data bus ATAPI 2 device register address ATAPI Device DMA request SDRAM Read / Write Data SDRAM Read / Write Data SDRAM Read / Write Data SDRAM Read / Write Data ATAPI device register address ATAPI Device interrupt request ATAPI I/O read request Bidirectional ATAPI data bus SDRAM Clock Enable SDRAM Read / Write Data SDRAM Data Strobe SDRAM Read / Write Data Reset out to connected ATAPI devices ATAPI device register address Bidirectional ATAPI 2 data bus Bidirectional ATAPI 2 data bus SDRAM Address, Bank Select, or Chip Select SDRAM Row Address Strobe SDRAM Read / Write Data SDRAM Read / Write Data Bidirectional ATAPI 2 data bus Bidirectional ATAPI 2 data bus Bidirectional ATAPI 2 data bus Digital 3.3 V Power Digital 3.3 V Power SDRAM Address SDRAM Column Address Strobe SDRAM Write Enable Bidirectional ATAPI 2 data bus Bidirectional ATAPI 2 data bus Bidirectional ATAPI 2 data bus Bidirectional ATAPI 2 data bus SDRAM Address SDRAM Address SDRAM Address, Bank Select, or Chip Select

11

AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16

SDRAM_A[17] ATAPI2_DATA[7] ATAPI2_DATA[9] ATAPI2_DATA[12] ATAPI2_ADDR[2] ATAPI2_DMARQ Vdd_15 Bias_5V01 HMST_ADDRHI[3] MAddress[25] HMST_ADDRLO[2] MAddress[3] HMST_WAIT

Out I/O 3state I/O 3state I/O Out In N/A Pwr/Gnd Out Out Out 3state I/O 3state I/O N/A N/A N/A N/A 3state I/O 3state I/O Out Out

SDRAM ATAPI ATAPI ATAPI ATAPI ATAPI Pwr/Gnd

SDRAM Address, Bank Select, or Chip Select Bidirectional ATAPI 2 data bus Bidirectional ATAPI 2 data bus Bidirectional ATAPI 2 data bus ATAPI 2 device register address ATAPI 2 Device DMA request Digital 3.3 V Power

Host Infc Host Infc Host Infc Host Infc Pwr/Gnd Pwr/Gnd Pwr/Gnd Pwr/Gnd Host Infc

Upper five Maddress bits [26:22] Lower five Maddress bits [5:1] Host Wait Host MAddress [21:6] during address cycles; Host MData [15:0]during data cycles Digital 3.3 V Power Digital 3.3 V Power Digital 3.3 V Power Digital 3.3 V Power Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Host Upper Data Strobe SPI chip select IDC Data UART1 receive Digital 3.3 V Power UART2 clear to send SDRAM Address SDRAM Address SDRAM Address SDRAM Address Bidirectional ATAPI 2 data bus Bidirectional ATAPI 2 data bus ATAPI 2 device register address ATAPI 2 I/O write request ATAPI 2 I/O read request Reset out to connected ATAPI 2 devices Upper five Maddress bits [26:22]

HMST_AddrData[12] MAddress[18] MData[12] Vddp_19A Vddp_19 Vddp_20 Vddp_21 HMST_AddrData[4] MAddress[10] MData[4] HMST_UDS HMST_UWE

AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10

Host Infc Serial I/O Serial I/O Serial I/O Pwr/Gnd Serial I/O SDRAM SDRAM SDRAM SDRAM ATAPI ATAPI ATAPI ATAPI ATAPI ATAPI Host Infc Host Infc Host Infc Host Infc

SIO_SPI_CS[2] CS[10] Out SIO_SDA SIO_UART1_RX Vdd_23 SIO_UART2_CTS SDRAM_A[8] SDRAM_A[12] SDRAM_A[0] SDRAM_A[3] ATAPI2_DATA[10] ATAPI2_DATA[13] ATAPI2_ADDR[1] ATAPI2_DIOW ATAPI2_DIOR ATAPI2_RESET HMST_ADDRHI[1] MAddress[23] HMST_GPIO[0] HMST_ADDRLO[3] MAddress[4] HSMT_DTACK I/O In N/A In Out Out Out Out 3state I/O 3state I/O Out Out Out Out Out I/O Out Out

Lower five Maddress bits [5:1] Data Transfer Acknowledge

12

AD11 AD12 AD13

HMST_AddrData[15] MAddress[21] MData[15] HMST_CS0_8BIT HMST_AddrData[6] MAddress[12] MData[6] HMST_AddrData[8] MAddress[14] MData[8] HMST_AddrData[2] MAddress[8] MData[2] HMST_AddrData[5] MAddress[11] MData[5] HMST_AddrData[0] MAddress[6] MData[0] SIO_SPI_CLK SIO_IRTX1 GPIOExt[40] CS7 SPI_CS[3] CS[11] SIO_SCL SIO_SPI_MISO SDRAM_A[14] SDRAM_A[10] SDRAM_A[5] SDRAM_A[6] ATAPI2_DATA[14] ATAPI2_ADDR[0] ATAPI2_ADDR[4] ATAPI2_IORDY HMST_CS[4] HMST_ADDRHI[4] MAddress[26] HMST_ADDRHI[0] MAddress[22] HMST_ADDRLO[1] MAddress[2] HMST_GPIO[3] HMST_GPIO[2] HMST_AddrData[9] MAddress[15] MData[9] HMST_AddrData[14] MAddress[20] MData[14] 3

3state I/O In 3state I/O

Host Infc Host Infc Host Infc

Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Slave Chip Select / Master 8bit transfer chip select Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles SPI clock IR transmit 1 SPI chip select IDC Clock SPI master in slave out. SDRAM Address, Bank Select, or Chip Select SDRAM Address SDRAM Address SDRAM Address Bidirectional ATAPI 2 data bus ATAPI 2 device register address ATAPI 2 device register address ATAPI 2 device IO ready Master Chip Select 4 Upper five Maddress bits [26:22] Upper five Maddress bits [26:22] Lower five Maddress bits [5:1] Slave address bus Slave address bus Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles

AD14

3state I/O

Host Infc

AD15

3state I/O

Host Infc

AD16

3state I/O

Host Infc

AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11

3state I/O Out 3state I/O Out I/O In Out Out Out Out 3state I/O Out Out In 3state I/O Out Out Out 3state I/O 3state I/O 3state I/O

Host Infc Serial I/O Serial I/O Serial I/O Serial I/O Serial I/O SDRAM SDRAM SDRAM SDRAM ATAPI ATAPI ATAPI ATAPI Host Infc Host Infc Host Infc Host Infc Host Infc Host Infc Host Infc

AE12

3state I/O

Host Infc

13

AE13 AE14 AE15

HMST_AddrData[10] MAddress[16] MData[10] HMST_GPIO[1] HMST_AddrData[7] MAddress[13] MData[7] HMST_AddrData[1] MAddress[7] MData[1] HMST_AddrData[3] MAddress[9] MData[3] HMST_RST SIO_IRRX GPIOExt[39] CS6 SIO_UART1_CTS GPIOExt[42] SIO_SPI_CS[1] GPIOExt[25] SIO_SPI_MOSI SIO_UART2_TX GPIOExt[38] SIO_UART2_RTS SDRAM_A[7] SDRAM_A[11] ATAPI2_DATA[15] ATAPI2_ADDR[3] ATAPI2_DMAACK ATAPI2_INTRQ HMST_CS[5] HMST_ADDRHI[2] MAddress[24] HMST_ADDRLO[4] MAddress[5] HMST_ADDRLO[0] MAddress[1] PCMCIA_IOW GPIO[4] PCMCIA_IOR GPIO[5] HMST_AddrData[13] MAddress[19] MData[13] HMST_AddrData[11] MAddress[17] MData[11] HMST_LDS HMST_OE

3state I/O 3state I/O 3state I/O

Host Infc Host Infc Host Infc

Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Slave address bus Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Host Reset IR receive input UART1 clear to send SPI chip select SPI master out slave in UART2 transmit UART2 request to send. SDRAM Address SDRAM Address Bidirectional ATAPI 2 data bus ATAPI 2 device register address ATAPI 2 DMA acknowledgement ATAPI 2 Device interrupt request Master Chip Select 5 Upper five Maddress bits [26:22] Lower five Maddress bits [5:1] Lower five Maddress bits [5:1] PCMCIA I/O Write PCMCIA I/O Read Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles Host MAddress [21:6] during address cycles; Host MData [15:0]during data cycles Lower data strobe

AE16

3state I/O

Host Infc

AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10

3state I/O In 3state I/O 3state I/O 3state I/O Out 3state I/O Out Out Out 3state I/O Out Out In 3state I/O Out Out Out 3state I/O 3state I/O

Host Infc Host Infc Serial I/O Serial I/O Serial I/O Serial I/O Serial I/O Serial I/O SDRAM SDRAM ATAPI ATAPI ATAPI ATAPI Host Infc Host Infc Host Infc Host Infc Host Infc Host Infc

AF11

3state I/O

Host Infc

AF12

3state I/O 3state I/O In Out

Host Infc

AF13

Host Infc

14

AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26

HMST_WR LWE HMST_ALE HMST_CS[0] HMST_CS[1] HMST_CS[2] HMST_CS[3] SIO_IRTX2 SIO_SPI_CS[0] GPIOExt[24] SIO_UART2_RX GPIOExt[37] SIO_UART1_RTS GPIOExt[41] SIO_UART1_TX SDRAM_A[9] SDRAM_A[13]

In Out Out 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O 3state I/O Out Out Out

Host Infc Host Infc Host Infc Host Infc Host Infc Host Infc Serial I/O Serial I/O Serial I/O Serial I/O Serial I/O SDRAM SDRAM

Write enable Master address latch enable Master Chip Select 0 Master Chip Select 1 Master Chip Select 2 Master Chip Select 3 IR transmit 2 SPI chip select UART2 receive UART1 request to send UART1 transmit SDRAM Address SDRAM Address

1. lvGPIO are GPIO that are 3.3 volt tolerance only. 2. ATAPI_DATA[4]] can be used as a IEC958 bypass input (bypassed and sent out to AO_IEC958) 3. For a one slot SDRAM system, SDRAM_A[17] should be connected to the SDRAM chip select. For a two slot system, both SDRAM_A[17] and SDRAM_A[16] are used as chip selects. The SDRAM address pins should be mapped to SDRAM chip as follows: SDRAM_A[17] = CS0 SDRAM_A[16] = CS1 SDRAM_A[15] = B1 SDRAM_A[14] = B0

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B.2 SYSTEM BLOCK DIAGRAM


The block diagram of digital board is shown in the following figure:

16

The block diagram of analog board is shown in the following figure:

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B.3 AUDIO OUTPUT


The DMN-8652 can receive and transmit two separate streams of 16- to 32-bit audio data via the serial audio interface. Common audio formats, including inter-device serial (IDS), are supported. Four channels of audio input and eight channels of audio output are supported on stream 1. Two channels of audio input and two channels of audio output are supported on stream 2. Each stream has separate input and output clocking. An IEC-958 encoded audio output, synchronized to output stream 1, is also provided. Internal input and output audio clocks can be generated from the internal system clock. Four channels of serial audio data are clocked in by the two AI_D pins, and up to eight channels of serial audio data are clocked out of the four AO_D pins by the clock on the AO_SCLK pin. With two samples/frame, channel 2n and 2n + 1 use AudioIn/Out[n]. With one sample/frame, channel n uses AudioIn/Out[n]. AI_FSYNC determines the start or end of the next stream input sample or frame as specified by the stream frame format. The interface carries either PCM audio samples (mono or stereo) or compressed audio bitstreams (AC3 or MPEG). The sample rate of audio samples carried by this interface can be 32, 44.1, 48 or 96 kHz. The width of audio samples can be up to 24 bits. The DMN8652 also provides digital output in S/PDIF format. The board supports both optical and coaxial S/PDIF outputs.

B.4 AUDIO DACS The IDS data and clock lines can be connected directly to one or more audio DAC to generate analog audio output. The six-channel DAC is an CS4360. The two-channel DAC is CS4340. The outputs of the DAC are differential, not single ended so a buffering circuit is required. The buffer circuits use opamps to perform the low-pass filtering and the buffering. B.5 AUDIO ADC
The CS5340 ADC converts analog audio signals to digital and passes trough IS interface to DMN8652. It performs sampling, analog to digital conversion, and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 200 kHz per channel. The CS5340 uses a 5th-order, multi-bit Delta-Sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter.

B.6 VIDEO INTERFACE


Video Output The video output channel supports a separate PIP video layer and a separate OSD/graphics overlay with 4-bit, 8-bit, 16-bit or 32-bit pixel formats and optional two-tap flicker filter. Two programmable OSD windows are output for each field, without software intervention. For DMN-8652 processor, the maximum output rate is 74.25 MHz (SMPTE 250M). The maximum OSD pixel rate with flicker filtering and 32-bit pixels is 37.125 MHz. The DMN-8652 processor output values are optionally passed through an interpolating 4-tap, 8-phase horizontal filter. Video Input The video input channel captures 8- or 10-bit digital video from ITU-R BT.656 (parallel D1) or video decoder chips such as the TVP5146.Two programmable rectangular windows are captured from each field without software intervention. This allows for VITC and closed-caption capture. Additional windows can be captured by loading a new capture window into the input channel at the completion of each window. In the DMN8652, 10-bit input values are dithered down to 8-bit values and are optionally passed through an 8-tap, 8-phase horizontal filter for resampling and noise reduction. Double buffered luma and chroma buffers hold the filtered values. The DMA transfer captures up to one entire field between video interrupts. Luma information and chroma information are stored separately in SDRAM. Video Interface Pins The functions of the various Video I/O signal pins depend on the specific configuration of the DMN8652 Video Channels. The frequency of VO_CLK and VI_CLK varies from 27MHz to 74.25 MHz.

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B.7 DDR SDRAM MEMORY The DMN8652 device utilizes Synchronous DRAM (SDRAM) for the external memory bank due to SDRAMs flexibility and high sustainable bandwidth. The interface supports Double Data Rate (DDR) SDRAM for high performance applications. The SDRAM clock frequency for SDR and DDR devices ranges from 108 to 148.5 MHz. The address and control I/O signals can drive up to four loads, while the data (DQ, DQS, DQM, and the clock) signal can drive up to two loads. All I/Os are PVT compensated to minimize output delay variations. RAS and CAS latency and cycle time are programmable, so that designers can use SDRAMs from different vendors at different speeds. The SDRAM devices are DDR SDRAM 16M x 16b which are used in the system. Since DDRs use a Stub-Series Terminated Logic (SSTL) interface to easily allow stacking, they are quite power-hungry and should be used only for high-performance, non-power critical applications. For DDRs, all control signals change only at the rising edge of the clock, but data and data mask can change on both rising and falling edges of the clock.

B.8 FLASH MEMORY


32MBits Flash size is required for DMN8652.

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B.9 ATA/IDE LOADER&HDD INTERFACE


The primary and secondary AT Attachment Packet Interface (ATAPI) is a standard interface with a 16-bit data bus, which is used to connect devices such as hard disks, CD/DVD ROMs, and DVD RAMs. All

operations are initiated by reading/writing a set of ATAPI device registers through programmed input/output (PIO) data transfer. ATAPI has DMA commands for transferring long data. The peripheral I/O supports these transfers with the DVDctl (ATAPI control register). The ATAP interface supports the following operations: Register read Register write DMA read DMA write The Register read and write operations are used to configure a set of ATAPI device registers. The DMA read and write operations are needed for transferring long sector data. The ATAPI register address is defined by the output pins CS0, CS1, DA2, DA1, and DA0, where CS0 is the most significant bit. The ATAPI read cycle starts when the ATAPI Interface receives the ATAPI_RD command from the host. The ATAPI Interface subsequently puts the register address on the address bus and asserts the ATAPI_DIOR signal t1 time later. The 16-bit data (AtapiIOCS16 signal is always low) from the ATAPI device is latched by the ATAPI Interface during the rising edge of the ATAPI_DIOR signal. The wait cycle can be generated by the ATAPI device driving the ATAPI_IORDY signal low during the read cycle. The ATAPI device must drive the ATAPI_IORDY signal low before time tA to initiate a wait cycle. During the wait cycle, the ATAPI Interface keeps the register address and the ATAPI_DIOR signal asserted until the ATAPI_IORDY signal becomes high. The ATAPI write cycle starts when the ATAPI Interface receives the ATAPI_WR command from the host. The ATAPI Interface follows by placing the register address on the address bus and asserting the ATAPI_DIOW signal time t1 later. The ATAPI device can also initiate the wait cycle by driving the ATAPI_IORDY signal low before time tA. During the wait cycle, the ATAPI Interface keeps the register address, write the data, and the ATAPI_DIOW signal asserted until the ATAPI_IORDY signal becomes high. Note: The decoder board supports the standard ATAPI electrical connections, but the software protocol within the drive is not always supported according to ATAPI specifications. Custom software may need to be developed and tested to support ATAPI drives from different manufacturers.

B.11 FRONT PANEL


The VFD controller is a PTC PT6315. This controller is not a processor, but does include a simple state machine which scans the VFD and reads the front panel button matrix. The 6315 also includes RAM so it can store the current state of all the VFD icons and segments. Therefore, the 6315 need only be accessed when the VFD status changes and when the button status is read. The DMN8652 can control this chip directly using PIO pins or can allow the front panel PIC to control the VFD. There are video& audio connectors, USB&MC sockets on the user interface board. AU9368 is the electrical interface chip for USB1.1.

B.12 MISCELLANEOUS FUNCTIONS Reset Circuitry A reset ic is used to provide the power-on-reset. Vth should be smaller than 4.65. B.13 CONNECTORS
ATAPI Drive Standard Connector The I/O connector is a 40-pin connector as shown in figure A.1, with pin assignments as shown in table A.1. The connector shall be keyed to prevent the possibility of installing it upside down. A key is provided by the removal of pin 20. The corresponding pin on the cable connector shall be plugged.

20

The cable plug, not the receptacle, governs the pin locations. The way in which the receptacle is mounted on the printed circuit board affects the pin positions, and pin 1 shall remain in the same relative position. This means the pin numbers of the receptacle may not reflect the conductor number of the plug. The header receptacle is not polarized, and all the signals are relative to pin 20, which is keyed. By using the plug positions as primary, a straight cable can connect devices. As shown in figure A.1, conductor 1 on pin 1 of the plug shall be in the same relative position no matter what the receptacle numbering looks like. If receptacle numbering was followed, the cable would have to twist 180 degrees between a device with top-mounted receptacles, and a device with bottom mounted receptacles.

Recommended part numbers for the mating connector and cable are shown below, but equivalent parts may be used. Connector (40 pin) 3M 3417-7000 or equivalent Strain relief 3M 3448-2040 or equivalent Flat cable (stranded 28 AWG) 3M 3365-40 or equivalent Flat cable (stranded 28 AWG) 3M 3517-40 (shielded) or equivalent

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SCART Connectors Pinout of the scart connectors: SCART1 1 Audio Right Out 2 Audio Right In 3 Audio Left / Mono Out 4 Audio Gnd 5 Blue Gnd 6 Audio Left / Mono In 7 Blue Out 8 Control Voltage 9 Green Gnd 10 Comms Data 2(TVLINK) 11 Green Out 12 Comms Data 1(Not connected) 13 Red Gnd 14 Comms Data Gnd 15 Red Out 16 Fast Blanking 17 Video Gnd 18 Fast Blanking Gnd 19 Composite Video Out 20 Composite Video In 21 Shield SCART2 1 Audio Right Out 2 Audio Right In 3 Audio Left / Mono Out 4 Audio Gnd 5 Blue Gnd 6 Audio Left / Mono In 7 Blue In 8 Control Voltage 9 Green Gnd 10 Comms Data 2(Not connected) 11 Green In 12 Comms Data 1(Not connected) 13 Red Gnd 14 Comms Data Gnd 15 Red In 16 Fast Blanking 17 Video Gnd 18 Fast Blanking Gnd 19 Composite Video Out 20 Composite Video In 21 Shield

Some cheaper SCART cables use unshielded wires, which is just about acceptable for short cable lengths. For longer lengths, shielded coaxial cable become essential. Scart Signals: Audio signals 0.5V RMS, <1K output impedance, >10K input impedance. Red, Green, Blue 0.7Vpp 2dB, 75R input and output impedance. Note that the Red connection (pin 20) can alternatively carry the S-VHS Chrominance signal, which is 0.3V. Composite Video / CSync 1Vpp including sync, 2dB, 75R input and output impedance.Bandwidth = 25Hz to 4.8MHz for normal TV Video de-emphasis to CCIR 405.1 (625-line TV) Fast Blanking 75R input and output impedance. This control voltage allows devices to over-ride the composite video input with RGB inputs, for example when inserting closed caption text. It is called fast because this can be done at the same speeds as other video signals, which is why it requires the same 75R impedances. 0 to 0.4V: TV is driven by the composite video input signal (pin 19). Left unconnected, it is pulled to 0V by its 75R termination. 1V to 3V: the TV is driven by the signals Red, Green, Blue and composite sync. The latter is sent to the TV on pin 19. This signal is useful when using a TV to display the RGB output of devices such as home computers with TV-compatible frame rates. Tying the signal to 5V via 100R forms a potential divider with the 75R termination, holding the signal at around 2V. Alternatively, if a TTL level (0 to 5V) negative sync pulse is available, this will be high during the display periods, so this can drive the blanking signal via a suitable resistor. Control Voltage 0 to 2V = TV, Normal. 5 to 8V = TV wide screen 9.5 to 12V = AV mode

C CIRCUIT DESCRIPTION
C.1 POWER SUPPLY & ANALOG BOARD
Socket PL100 is the 220VAC input. 3.15A fuse F100 is used to protect the device against short circuit and unexpected overloads.

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Line filter and capacitors L100, L101, L102, C100 and C101 are used to block the parasitic coming from the mains. They also prevent the noise, produced in the circuit, from being injected to the line. Voltage is rectified by diodes D100, D101, D102 and D103. Using capacitor C105 (47f) a DC voltage is produced. (310-320VDC). The current in the primary side of the transformer TR100 comes to the SMPS IC (IC304 ICE2A165). The SMPS IC has a eight-pin DIP-8 package and an external MOSFET with a cooler is mounted on it. It has a built-in oscillator, overcurrent and overvoltage protection circuitry and runs at 100kHz. It starts with the current from the primary side of the transformer and follows the current from the feedback winding. Feedback current is deteceted by optocoupler IC101. Depending on the control current coming from the secondary side, SMPS IC keeps the output voltage constant by controlling the duty cycle of the ~30kHz signal (PWM) at the primary side of the transformer. Voltages on the secondary side of the transformer are as follows: +33V, +5V, +8V, +15V and -22V. Using the output of the D323, a photo diode inside of the IC101 generates feedback signal by using optocoupler's phototransistor. This phototransistor adjusts the control voltage at the IC304 pin2. The voltage at this pin effects the PWM output frequency on the IC304 pin4 and pin5. And finally output voltages reach their correct values by this way. 22 Volts is used to feed the VFD (Vacuum Fluorescent Display) driver IC on the front panel. Socket PL108 is connector of cooler fan which is under the HDD. The cooler fan is controlled by IC211(MCU) on the analog board. Analog board is the interface between the digital board and the input/output signals. On the analog board, there is a IF-PLL demodulator (IC204 TDA9885), a multi-standard sound processor (IC110 MSP3417), a video switch (IC206 STV6412) and an audio DAC (IC104 CS4360 for 6ch, IC107 CS4340 for 2ch). There are three op-amp ICs IC101, IC102 and IC103 for Front Left, Front Right, Rear Left, Rear Right, Center and Subwoofer outputs after DAC IC.

C.2 FRONT PANEL


All the functions on the front panel are controlled by DMN8652 on the mainboard. Key scanning and IR checking operations on the standby mode are controlled by IC211 MSP430F1101A on the analog board. It also controls audio switching. DMN8652 IC sends the commands to IC101 PT6315 via socket PL101 (pins 4, 5 and 6). Pin 5 is the oscillator pin and is connected via R169 100K. LED D1(blue colour) is on in stand-by mode and off when the device is on. Vacuum fluorescent display MD1 is specially designed for RW3400. IR remote control receiver module IC102 (TSOP1836) sends the commands from the remote control directly to DMN8652 and MSP430F1101A analog board controller. Socket PL102 is the power connector of board and it carries the operating power(5V), VFD filament voltage and 22 Volts. Also there are connectors for Left&Right audio inputs and CVBS and S-Video Video inputs. U1(TPS2041) is USB electrical interface chip which DMN8652 communicates with USB devices via U1. U2(AU9368) is multistandard memory card reader chip. DMN8652 communicates with U2 by USB port.

C.3 I/OS & BACK PANEL


JK605 RCA audio jack on the analog board gives out analog audio that come from audio opamps in the form of Front Left, Front Right, Rear Left, Rear Right, Center and Subwoofer. There are two SCART connectors SCART1 and SCART2 (Scart2 is for input on Scart mode and Scart1 is for TV output), 1 RCA connector for CVBS out, 1 Connector for SVHS output. There are RF input and TV output connections on the tuner. There are two SPDIF outputs on the power board, optical (MD100) and coaxial (JK100).

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D SERVICE MENU IN THE SOFTWARE


When you power on the RW3400 DVD-Recorder, you can access to a hidden menu with useful information about the system by the following procedure: Be sure that tray is closed Press SETUP key Press 3, 2,1 and CLEAR keys consecutively. Hidden menu content: Software Version Number / Download Date Loader FW Version Number Macrovision FW Version Number MPEG Chip ID Audio DAC Region Number Development Team

Region information may be between 0-6. 0 means the unit is multi-region, ie, it can play all discs independent of discs own region information. If player is set for a specific region and you try to play a dvd disc with another region information, disc will not be played.

E SW UPDATE PROCEDURE
Burn the given files to the CD according to the rules below. 1) Update file name must be DMN8600.CUB 2) No multi session and finalize CD options must be selected before burning Update procedure: 1) Insert the disc. 2) Select yes in the CD update confirmation screen. 3) The unit first loads the software into the memory then ejects the disc automatically. 4) Take the disc out and press close. 5) Wait until the player resets itself. (The flash update may take several minutes.) 6) After reset the update process is done.

!!! Don't power off the unit after the disc has been ejected. !!!

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